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Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.11.3 Concept
Data Memory Space
XRAM (2MB)
0x800000
EPG
EPG FLASH (512k)
Lower 32k of EPG flash
0x400000
OTC DRAM and SRAM
0x000000
Figure 9-32 Memory diagram (initial situation)
The architecture of the OTC microprocessor does not allow the
execution of code from the external RAM. It is also impossible
to write data in the code memory space (there is no instruction
to write data to those memory locations).
The OTC normally boots from its internal ROM (IROM) but
modification of the internal ROM software would be too
expensive. Fortunately, the chip architecture allows also the
booting from external ROM (XROM).
The IROM is mapped on the first 32 kB of the ROM address
space. The XROM is mapped starting at the same address.
Therefore, the lower 32 kB of XROM overlaps the IROM
memory space.
Via an external pin (EA), it is possible to reveal the XROM
memory below the IROM and so boot using this hidden
software. This is the first trick used by the software upgrade
procedure.
To be able to write to the CODE flash, it is required to address
the device via the RAM address space. Today all RAM but also
the EPG flash is mapped on the RAM address space.
Devices are mapped to the right address space via a few
control lines (kind of chip select). By exchanging the control
lines between the EPG and the CODE flash, it is possible to
map the CODE flash in the RAM address space and at the
same time use the EPG flash to execute software. This is the
second trick used by the procedure.
The main idea is to use the EPG flash to boot up the software
upgrade procedure.
Therefore, the complete procedure relies on the presence of
that one. The upgrade procedure is so prescribed for Europe
but a small flash of 32 kB could still be used for US and AP
(currently investigated).
Code Memory Space
Bootstrap
SW image (32k)
0x3F8000
XROM-FLASH (4MB)
0x000000
CL 36532008_117.eps
130503
EM6E AB
Data Memory Space
XRAM (2MB)
0x800000
XROM-FLASH (4MB)
Exchange
0x400000
OTC DRAM and SRAM
0x000000
Figure 9-33 Memory diagram (after bus exchange)
In order to be able to write new software code to the set, we
therefore must copy the bootstrap code to a free memory area
(e.g. the EPG flash-RAM) in order to be able to execute
"externally" the upgrade procedure code.
Solution: swap the software code to the data memory space
(via placing a jumper on 1402) and boot from the EPG FLASH.
After the zip-file uploading and (internally) software unpacking,
the old situation must be restored.
7007
7012
RAM
CONTROL
7001
2MB
0.5MB
2
TXT
EPG
I
C
DRAM
FLASHRAM
Figure 9-34 Software upgrade set-up
A jumper on the SSP will swap the devices and boot
"externally" via the EPG flash. Then, via ComPair, the
download command is given. The new (ZIP) image will be first
downloaded to the OTC's external RAM (TXT DRAM). Then a
checksum on the ZIP image will be computed on both sides
and compared.
If everything is correct, the CODE flash will be erased and the
new image will be transferred and unzipped (= decompressed)
into the flash. This is done via the bootstrap code. A second
checksum will be computed on the decompressed image.
After the upgrade, the EPG flash will be cleared again.
9.
EN 169
Code Memory Space
EPG FLASH (512k)
Lower 32k of EPG flash
(bootstrap)
0x000000
CL 36532008_118.eps
130503
7006
SWITCH
7018/7019
ROM
CONTROL
4MB
ARTISTIC
(OTC)
EA
I ROM
JUMPER
ROM/
1402
FLASH-RAM
CL 36532008_116.eps
060503
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