Drive Stop State; Dsi_Phy_Register1; Dsi_Phy_Register2 - Texas Instruments OMAP36 Series Technical Reference Manual

Display Subsystem Use Cases and Tips
• Length of the line in video mode in Nb of byte clock cycles (TxByteClkHS):
TL = FHSB/FVPP × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP)
TL1f = (BPP/(8 × NDL)) × (DISPC_HSA + DISPC_HFP + PPL +DISPC_HBP)
• Blanking periods (HBP + HFP) in DSI are calculated based on the following formula:
(DISPC_HSA + DISPC_HBP + PPL + DISPC_HFP) × Fppi = (HS + HBP + ((WC + 6)/NDL) +HFP) ×
Fvp
HBP + HFP = (TVPP/THSB) × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP – (HS + (WC +
6)/NDL))
HBPplusHFP = (FHSB/FVPP) × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP) – (HS + WC +
6)/NDL)
HBPplusHFPf = ((FHSB/FVPP) × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP)) – ((HS + WC +
6)/NDL)
HFP = (DISCP_HFP × BPP)/(NDL × 8) – (2/NDL)
HBP = HBPplusHFP – HFP
7.6.4.2.5 Configure DSI_PHY
Calculate the timing in the functions of DDR_CLK_P (see
1000/DSI_DDR_CLK. See
Steps
Refer to Section 7.4.3.2
NOTE: Keep Reserved bits at reset value in the

DSI_PHY_REGISTER2

7.6.4.2.6 Drive Stop State

Table 7-92 lists the steps to Drive Stop State.
Steps
Force TX stop mode
Wait until FORCE_TX_STOP_MODE_IO = 0
7.6.4.3 Initialization of the External MIPI Display Controller
1. Wait for the external MIPI display controller initialization after power up.
In this example, the external MIPI display controller is reset using GPIO 87.
2. Configure the external MIPI display controller.
1800
Display Subsystem
Public Version
Section 7.4.3.2, Clock Requirements, for details on timing calculation.
Table 7-91. Calculate DSI_PHY Timing
Registers
DSI_PHY_REGISTER0[31:24] REG_THSPREPARE
DSI_PHY_REGISTER0[23:16]
REG_THSPRPR_THSZERO
DSI_PHY_REGISTER0[7:0] REG_THSEXIT
DSI_PHY_REGISTER0[15:8] REG_THSTRAIL
DSI_PHY_REGISTER2[7:0] REG_TCLKPREPARE
DSI_PHY_REGISTER1[7:0] REG_TCLKZERO
DSI_PHY_REGISTER1[15:8] REG_TCLKTRAIL
DSI_PHY_REGISTER1[20:16] REG_TLPXBY2

DSI_PHY_REGISTER1

registers.
Table 7-92. Drive Stop State
DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO
DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO
Copyright © 2009–2010, Texas Instruments Incorporated
Table 7-91). In the example, DDR_CLK_P =
CEIL(70 ns/DDR clock period) + 2
ceil(175 ns/DDR clock period) + 2
ceil(145 ns/DDR clock period)
ceil(60 ns/DDR clock period) + 5
ceil(65 ns/DDR clock period)
ceil(265 ns/DDR clock period)
ceil(60 ns/DDR clock period) + 2
ceil(25ns/DDR clock period)
and
Registers
SWPU177N – December 2009 – Revised November 2010
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(29)
(30)
Value
Value
0x1
Read 0x0