Freescale Semiconductor MPC561 Reference Manual

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MPC561/MPC563 Reference Manual

Additional Devices Supported:

MPC562

MPC564

MPC561RM

REV 1.2

08/2005

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Page 1 MPC561/MPC563 Reference Manual Additional Devices Supported: MPC562 MPC564 MPC561RM REV 1.2 08/2005...
Page 2 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor Hong Kong Ltd.
Page 3: Table Of Contents
Queued Serial Multi-Channel Module (QSMCM) ..........1-8 1.3.3.6 Peripheral Pin Multiplexing (PPM) ................ 1-8 MPC561/MPC563 Optional Features ................1-9 Comparison of MPC561/MPC563 and MPC555 ............1-9 Additional MPC561/MPC563 Differences ..............1-10 SRAM Keep-Alive Power Behavior ................1-11 MPC561/MPC563 Address Map .................. 1-11 MPC561/MPC563 Reference Manual, Rev.
Page 4: Paragraph Number
2.2.2 READI Port Signal Sharing ..................2-21 Pad Module Configuration Register (PDMCR) ............2-22 Pad Module Configuration Register (PDMCR2) ............2-23 MPC561/MPC563 Development Support Signal Sharing ..........2-28 2.5.1 JTAG Mode Selection ....................2-29 2.5.2 BDM Mode Selection ....................2-30 2.5.3...
Page 5 Precise Exceptions ....................3-36 3.11.5 Exception Vector Table .................... 3-36 3.12 Instruction Timing ......................3-37 3.13 User Instruction Set Architecture (UISA) ..............3-39 3.13.1 Computation Modes ....................3-39 3.13.2 Reserved Fields ......................3-39 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 6 System Reset Exception and NMI (0x0100) ............3-45 3.15.4.2 Machine Check Exception (0x0200) ..............3-46 3.15.4.3 Data Storage Exception (0x0300) ................. 3-48 3.15.4.4 Instruction Storage Exception (0x0400) ............... 3-48 3.15.4.5 External Interrupt (0x0500) .................. 3-48 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 7 Enhanced External Interrupt Relocation (EEIR) ............4-10 Decompressor RAM (DECRAM) Functionality ............4-12 4.4.1 General-Purpose Memory Operation ................ 4-13 4.4.1.1 Memory Protection Violations ................4-14 4.4.1.2 DECRAM Standby Operation Mode ..............4-14 Branch Target Buffer ....................4-14 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 8 Interrupt Configuration ................... 6-8 6.1.4.3 Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10 6.1.4.4 Enhanced Interrupt Controller Operation ............. 6-11 6.1.4.4.1 Lower Priority Request Masking ..............6-14 6.1.4.4.2 Backward Compatibility with MPC555/MPC556 ..........6-14 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor viii...
Page 9 Real-Time Clock Alarm Register (RTCAL) ............ 6-44 6.2.2.4.8 Periodic Interrupt Status and Control Register (PISCR) ........6-44 6.2.2.4.9 Periodic Interrupt Timer Count Register (PITC) ..........6-45 6.2.2.4.10 Periodic Interrupt Timer Register (PITR) ............6-45 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 10 8.2.2 Skew Elimination ......................8-4 8.2.3 Pre-Divider ........................8-4 8.2.4 PLL Block Diagram ....................8-4 8.2.5 PLL Pins ........................8-5 System Clock During PLL Loss of Lock ................ 8-6 Low-Power Divider ......................8-6 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 11 8.11.1 System Clock Control Register (SCCR) ..............8-29 8.11.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) ........8-33 8.11.3 Change of Lock Interrupt Register (COLIR) ............8-36 8.11.4 IRAMSTBY Control Register (VSRMCR) .............. 8-37 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 12 Transfer Error Acknowledge ................9-40 9.5.9.4 Termination Signals Protocol ................9-40 9.5.10 Storage Reservation ....................9-42 9.5.11 Bus Exception Control Cycles .................. 9-45 9.5.11.1 Retrying a Bus Cycle .................... 9-45 9.5.11.2 Termination Signals Protocol Summary ............... 9-49 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 13 Memory Controller Status Registers (MSTAT) ............. 10-32 10.9.3 Memory Controller Base Registers (BR0–BR3) ............ 10-32 10.9.4 Memory Controller Option Registers (OR0–OR3) ..........10-34 10.9.5 Dual-Mapping Base Register (DMBR) ..............10-36 10.9.6 Dual-Mapping Option Register (DMOR) ............... 10-37 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xiii...
Page 14 Global Region Attribute Register (L2U_GRA) ............11-16 Chapter 12 U-Bus to IMB3 Bus Interface (UIMB) 12.1 Features ......................... 12-1 12.2 UIMB Block Diagram ....................12-2 12.3 Clock Module ....................... 12-2 12.4 Interrupt Operation ....................... 12-3 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 15 Conversion Cycle Times ..................13-35 13.4.1.2 Amplifier Bypass Mode Conversion Timing ............. 13-35 13.4.2 Channel Decode and Multiplexer ................13-36 13.4.3 Sample Buffer Amplifier ..................13-36 13.4.4 Digital-to-Analog Converter (DAC) Array ............13-36 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 16 Analog Input Signals ....................13-71 13.7.5.1 Analog Input Considerations ................13-73 13.7.5.2 Settling Time for the External Circuit ..............13-75 13.7.5.3 Error Resulting from Leakage ................13-75 13.7.5.4 Accommodating Positive/Negative Stress Conditions ........13-76 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 17 14.4 Digital Subsystem ....................... 14-38 14.4.1 Queue Priority ......................14-39 14.4.2 Sub-Queues That are Paused .................. 14-39 14.4.3 Boundary Conditions ....................14-41 14.4.4 Scan Modes ......................14-42 14.4.4.1 Disabled Mode ....................14-42 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xvii...
Page 18 Chapter 15 Queued Serial Multi-Channel Module 15.1 Block Diagram ......................15-1 15.2 Key Features ......................... 15-2 15.2.1 MPC561/MPC563 QSMCM Details ................ 15-3 15.3 Memory Maps ....................... 15-4 15.4 QSMCM Global Registers .................... 15-6 15.4.1 Low-Power Stop Operation ..................15-6 15.4.2 Freeze Operation .......................
Page 19 Slave Mode ......................15-39 15.6.6.1 Description of Slave Operation ................15-40 15.6.7 Slave Wraparound Mode ..................15-41 15.6.8 Mode Fault ......................15-42 15.7 Serial Communication Interface ................. 15-42 15.7.1 SCI Registers ......................15-45 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 20 Chapter 16 CAN 2.0B Controller Module 16.1 Features ......................... 16-1 16.2 External Signals ......................16-2 16.2.1 TouCAN Signal Sharing ................... 16-3 16.3 TouCAN Architecture ....................16-3 16.3.1 Tx/Rx Message Buffer Structure ................16-4 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 21 Receive Buffer 14 Mask Registers (RX14MSKHI, RX14MSKLO) ...... 16-32 16.7.11 Receive Buffer 15 Mask Registers (RX15MSKHI, RX15MSKLO) ...... 16-33 16.7.12 Error and Status Register (ESTAT) ................ 16-33 16.7.13 Interrupt Mask Register (IMASK) ................16-35 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 22 17.8.1.1 MMCSM Signal Functions ................. 17-21 17.8.2 MMCSM Prescaler ....................17-21 17.8.3 Modular I/O Bus (MIOB) Interface ................ 17-21 17.8.4 Effect of RESET on MMCSM ................17-22 17.8.5 MMCSM Registers ....................17-22 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxii...
Page 23 Duty Cycles (0% and 100%) ................17-51 17.10.3.6 Pulse/Frequency Range Table ................17-52 17.10.3.7 MPWMSM Status and Control Register (SCR) ..........17-53 17.10.3.8 MPWMSM Interrupt ..................17-53 17.10.3.9 MPWMSM Port Functions ................. 17-54 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxiii...
Page 24 MIOS14 Function Examples ..................17-70 17.13.1 MIOS14 Input Double Edge Pulse Width Measurement ........17-70 17.13.2 MIOS14 Input Double Edge Period Measurement ..........17-71 17.13.3 MIOS14 Double Edge Single Output Pulse Generation ......... 17-72 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxiv...
Page 25 Short Channels Register (SHORT_CH_REG) ............18-22 18.4.12 Scale Transmit Clock Register (SCALE_TCLK_REG) ........18-24 Chapter 19 Time Processor Unit 3 19.1 Overview ........................19-2 19.2 TPU3 Components ......................19-2 19.2.1 Time Bases ........................ 19-2 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 26 Dual-Port TPU3 RAM (DPTRAM) 20.1 Features ......................... 20-1 20.2 DPTRAM Configuration Block Diagram ..............20-2 20.3 Programming Model ..................... 20-2 20.3.1 DPTRAM Module Configuration Register (DPTMCR) ......... 20-3 20.3.2 DPTRAM Test Register (DPTTCR) ................. 20-4 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxvi...
Page 27 High Voltage Operations ..................21-21 21.3.6.1 Overview of Program/Erase Operation .............. 21-21 21.3.7 Programming ......................21-21 21.3.7.1 Program Sequence ....................21-22 21.3.7.2 Program Shadow Information ................21-24 21.3.7.3 Program Suspend ....................21-25 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxvii...
Page 28 CALRAM Module Configuration Register (CRAMMCR) ........22-13 22.5.2 CALRAM Region Base Address Registers (CRAM_RBAx) ........ 22-15 22.5.3 CALRAM Overlay Configuration Register (CRAM_OVLCR) ......22-17 22.5.4 CALRAM Ownership Trace Register (CRAM_OTR) ........... 22-17 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxviii...
Page 29 Running in Debug Mode ..................23-27 23.3.1.6 Exiting Debug Mode ................... 23-28 23.4 Development Port ....................... 23-28 23.4.1 Development Port Pins ................... 23-28 23.4.2 Development Serial Clock ..................23-29 23.4.3 Development Serial Data In ..................23-29 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxix...
Page 30 Development Port Data Register (DPDR) .............. 23-53 Chapter 24 READI Module 24.1 Features Summary ......................24-1 24.1.1 Functional Block Diagram ..................24-2 24.2 Modes of Operation ...................... 24-3 24.2.1 Reset Configuration ....................24-3 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 31 Non-Temporal Ordering of Transmitted Messages ..........24-33 24.7.6 READI Reset Configuration ................... 24-34 24.7.7 READI Signals ....................... 24-36 24.7.7.1 Reset Configuration for Debug Mode ..............24-36 24.7.7.2 Reset Configuration for Non-Debug Mode ............24-37 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxxi...
Page 32 Queue Overflow Data Trace Error Message ............24-54 24.9.4 Data Trace Operation ....................24-54 24.9.5 Data Trace Windowing ................... 24-56 24.9.6 Special L-Bus Cases ....................24-56 24.9.7 Data Trace Queuing ....................24-56 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxxii...
Page 33 Ownership Trace ......................24-74 24.13.1 Ownership Trace Messaging .................. 24-75 24.13.2 Queue Overflow Ownership Trace Error Message ..........24-75 24.13.2.1 OTM Flow ......................24-75 24.13.2.2 OTM Queueing ....................24-76 24.13.3 OTM Timing Diagrams ..................24-76 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxxiii...
Page 34 25.2 MPC561/MPC563 Restrictions .................. 25-32 25.2.1 Non-Scan Chain Operation ..................25-32 25.2.2 BSDL Description ....................25-33 Appendix A MPC562/MPC564 Compression Features ICDU Key Features ......................A-1 Class-Based Compression Model Main Principles............A-1 MPC561/MPC563 Reference Manual, Rev. 1.2 xxxiv Freescale Semiconductor...
Page 35 Show Cycles in Decompression On Mode ............A-15 A.3.2 Vocabulary Table Storage Operation ................ A-16 A.3.3 READI Compression ....................A-16 A.3.3.1 I-Bus Support Control Register (ICTRL) ............. A-16 Decompressor Class Configuration Registers (DCCR0-15) ........A-18 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxxv...
Page 36 Pulse-Width Modulation (PWM).................. D-44 D.17 Discrete Input/Output (DIO)..................D-46 D.18 Synchronized Pulse-Width Modulation (SPWM)............D-48 D.19 Read/Write Timers and Pin TPU3 Function (RWTPIN) ..........D-51 D.20 Serial Input/Output Port (SIOP) ................... D-53 D.20.1 Parameters......................... D-53 MPC561/MPC563 Reference Manual, Rev. 1.2 xxxvi Freescale Semiconductor...
Page 37 Application of PORESET or HRESET ..............F-17 F.9.2 Keep-Alive RAM....................... F-18 F.10 AC Timing ........................F-18 F.10.1 Debug Port Timing ....................F-43 F.11 READI Electrical Characteristics .................. F-45 F.12 RESET Timing....................... F-47 F.13 IEEE 1149.1 Electrical Characteristics................F-50 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxxvii...
Page 38 F.21 MPIOSM Timing Characteristics .................. F-71 F.22 Pin Summary ......................... F-73 F.22.1 Package Diagrams...................... F-83 F.22.1.1 MPC561/MPC563 Ball Map ................. F-86 Appendix G 66-MHz Electrical Characteristics 66-MHz Feature Limitations ..................G-1 Package ........................... G-3 EMI Characteristics ......................G-3 G.3.1 Reference Documents ....................G-3 G.3.2...
Page 39 G.21.2 MMCSM Timing Characteristics ................G-62 G.21.3 MDASM Timing Characteristics................G-64 G.22 MPIOSM Timing Characteristics ................. G-67 G.23 Pin Summary ........................ G-68 G.23.1 Package Diagrams..................... G-78 G.23.1.1 MPC561/MPC563 Ball Map ................G-81 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xxxix...
Page 40 Contents Paragraph Page Title Number Number MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 41 MPC561/MPC563 Block Diagram ................... 1-3 Recommended Connection Diagram for IRAMSTBY............1-11 MPC561/MPC563 Memory Map ................... 1-12 MPC561/MPC563 Internal Memory Map ................1-14 MPC561/MPC563 Signal Groupings ..................2-2 Pads Module Configuration Register (PDMCR) ..............2-22 Pads Module Configuration Register 2 (PDMCR2) ............... 2-23 Debug Mode Selection (JTAG) ....................
Page 42 Circuit Paths of Reading and Writing to SGPIO ..............6-7 MPC561/MPC563 Interrupt Structure..................6-9 Lower Priority Request Masking—One Bit Diagram ............6-14 MPC561/MPC563 Interrupt Controller Block Diagram ............6-15 Typical Interrupt Handler Routine..................6-17 RTC Block Diagram ....................... 6-20 PIT Block Diagram ......................... 6-21 SWT State Diagram ........................
Page 43 8-19 IRAMSTBY Control Register (VSRMCR) ................8-37 Input Sample Window ......................9-2 MPC561/MPC563 Bus Signals ....................9-3 Basic Transfer Protocol ......................9-8 Basic Flow Diagram of a Single Beat Read Cycle ..............9-9 Single Beat Read Cycle – Basic Timing – Zero Wait States..........9-10 Single Beat Read Cycle –...
Page 44 Basic Flow of an External Master Read Access ..............9-50 9-36 Basic Flow of an External Master Write Access ..............9-51 9-37 Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States) ..9-52 9-38 Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States).... 9-53 9-39 Flow of Retry of External Master Read Access ..............
Page 45 12-6 Interrupt Synchronizer Block Diagram................... 12-6 12-7 UIMB Module Configuration Register (UMCR) ..............12-7 12-8 Pending Interrupt Request Register (UIPEND)..............12-9 13-1 QADC64E Block Diagram ..................... 13-1 13-2 QADC64E Conversion Queue Operation................13-5 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 46 CCW Freeze Situation 12 ..................... 13-61 13-39 CCW Freeze Situation 13 ..................... 13-62 13-40 CCW Freeze Situation 14 ..................... 13-62 13-41 CCW Freeze Situation 15 ..................... 13-62 13-42 CCW Freeze Situation 16 ..................... 13-62 MPC561/MPC563 Reference Manual, Rev. 1.2 xlvi Freescale Semiconductor...
Page 47 QADC64E Queue Operation With Pause ................14-40 14-23 QADC64E Clock Subsystem Functions ................14-49 14-24 Bus Cycle Accesses ......................14-52 14-25 CCW Priority Situation 1...................... 14-55 14-26 CCW Priority Situation 2...................... 14-55 14-27 CCW Priority Situation 3...................... 14-56 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xlvii...
Page 48 QSPI Control Register 0 (SPCR0)..................15-17 15-12 SPCR1 — QSPI Control Register ..................15-19 15-13 SPCR2 — QSPI Control Register 2 ..................15-20 15-14 SPCR3 — QSPI Control Register 3 ..................15-21 MPC561/MPC563 Reference Manual, Rev. 1.2 xlviii Freescale Semiconductor...
Page 49 TouCAN Module Configuration Register (CANMCR) ............16-25 16-10 TouCAN Interrupt Configuration Register (CANICR) ............16-27 16-11 Control Register 0 (CANCTRL0)..................16-27 16-12 Control Register 1 (CANCTRL1)..................16-28 16-13 Prescaler Divide Register...................... 16-29 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor xlix...
Page 50 Interrupt Mask Register (IMASK)..................16-35 16-21 Interrupt Flag Register (IFLAG)................... 16-36 16-22 Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR)......16-36 17-1 MPC561/MPC563 MIOS14 Block Diagram ................17-2 17-2 MIOS14 Memory Map ......................17-13 17-3 MBISM Registers ......................... 17-13 17-4 Test and Signal Control Register (MIOS14TPCR) ..............
Page 51 General Purpose Data Out Register (GPDO) ............... 18-19 18-22 General Purpose Data In Register (GPDI)................18-19 18-23 Short Register (SHORT_REG)..................... 18-19 18-24 Example of TouCAN Internal Short with SH_TCAN = 0b110..........18-21 18-25 Short Between TPU Channels ....................18-22 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 52 UC3F EEPROM High Voltage Control Register (UC3FCTL) ..........21-11 21-5 PEGOOD Valid Time ......................21-14 21-6 Shadow Information ......................21-16 21-7 Hard Reset Configuration Word (UC3FCFIG) ..............21-16 21-8 512-Kbyte Array Configuration.................... 21-19 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 53 Erase State Diagram......................21-27 21-11 Censorship States and Transitions ..................21-33 22-1 System Block Diagram ......................22-2 22-2 MPC561/MPC563 Memory Map with CALRAM Address Ranges ........22-3 22-3 Standby Power Supply Configuration for CALRAM Array ..........22-4 22-4 CALRAM Array ........................22-7 22-5 CALRAM Module Overlay Map of Flash (CLPS = 0) ............
Page 54 Code (PTSM - 0)........................24-45 24-31 Indirect Branch Synchronization Message Format with Compressed Code (PTSM = 1)........................24-45 24-32 Program Trace Full Message Format..................24-46 24-33 Relative Address Generation and Re-Creation ..............24-47 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 55 Download Request Message ....................24-71 24-68 Upload/Download Information Message................24-72 24-69 Error Message (Invalid Access Opcode) ................24-72 24-70 Watchpoint Message Format ....................24-73 24-71 Error Message (Watchpoint Overrun) Format..............24-73 24-72 Watchpoint Message......................24-74 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 56 I-Bus Support Control Register (ICTRL) ................A-16 A-14 Decompressor Class Configuration Registers1 (DCCR ) ............. A-19 MPC561/MPC563 Power Distribution Diagram — 2.6 V ............C-3 Power Distribution Diagram — 5 V and Analog ..............C-3 Crystal Oscillator Circuit ......................C-4 RC Filter Example ........................C-5 MPC561/MPC563 Reference Manual, Rev.
Page 57 RWTPIN Parameters ......................D-52 D-31 Two Possible SIOP Configurations ..................D-53 D-32 SIOP Parameters ........................D-55 D-33 SIOP Function Data Transition Example ................D-59 Option A Power-Up Sequence Without Keep-Alive Supply..........F-14 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lvii...
Page 58 JTAG Test Clock Input Timing ....................F-51 F-38 JTAG Test Access Port Timing Diagram ................F-52 F-39 Boundary Scan (JTAG) Timing Diagram................F-53 F-40 QSPI Timing – Master, CPHA = 0 ..................F-58 MPC561/MPC563 Reference Manual, Rev. 1.2 lviii Freescale Semiconductor...
Page 59 MPC561/MPC563 Package Footprint (2 of 2) ............... F-85 F-66 MPC561/MPC563 Ball Map ....................F-86 F-67 MPC561/MPC563 Ball Map (Black and White, page 1) ............F-87 F-68 MPC561/MPC563 Ball Map (Black and White, page 2) ............F-88 F-69 MPC561/MPC563 Ball Map (Black and White, page 3) ............F-89 F-70 MPC561/MPC563 Ball Map (Black and White, page 4) ............
Page 60 MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ......G-61 G-49 MPWMSM Enable To MPWMO Output Pin Rising Edge Timing Diagram ....... G-62 G-50 MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram..... G-62 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 61 MPC561/MPC563 Package Footprint (2 of 2) ..............G-80 G-65 MPC561/MPC563 Ball Map ....................G-81 G-66 MPC561/MPC563 Ball Map (Black and White, page 1) ............G-82 G-67 MPC561/MPC563 Ball Map (Black and White, page 2) ............G-83 G-68 MPC561/MPC563 Ball Map (Black and White, page 3) ............G-84 G-69 MPC561/MPC563 Ball Map (Black and White, page 4) ............
Page 62 Figures Figure Page Title Number Number MPC561/MPC563 Reference Manual, Rev. 1.2 lxii Freescale Semiconductor...
Page 63 Enhanced PCS 4 & 5 Pad Function ..................2-26 2-11 Enhanced PCS 6 & 7 Pad Function ..................2-28 2-12 MPC561/MPC563 Development Support Shared Signals ............. 2-28 2-13 MPC561/MPC563 Mode Selection Options................2-29 2-14 MPC561/MPC563 Signal Reset State ..................2-34 RCPU Execution Units ......................
Page 64 Interrupt Latency Estimation for Three Typical Cases............6-16 Decrementer Time-Out Periods ....................6-18 SIUMCR Bit Descriptions ..................... 6-25 Debug Pins Configuration ...................... 6-27 General Pins Configuration ....................6-27 6-10 Single-Chip Select Field Pin Configuration ................6-27 MPC561/MPC563 Reference Manual, Rev. 1.2 lxiv Freescale Semiconductor...
Page 65 Data Bus Requirements For Read Cycles................9-31 Data Bus Contents for Write Cycles..................9-32 Priority Between Internal and External Masters over External Bus ........9-36 4 Word Burst Length and Order ..................... 9-38 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 66 QADC64E_A Address Map ....................13-3 13-2 QADC64E_B Address Map....................13-4 13-3 Multiplexed Analog Input Channels..................13-7 13-4 Analog Input Channels ......................13-7 13-5 QADCMCR Bit Descriptions ....................13-8 13-6 QADC64E Bus Error Response.................... 13-11 MPC561/MPC563 Reference Manual, Rev. 1.2 lxvi Freescale Semiconductor...
Page 67 QASR0 Bit Descriptions....................... 14-22 14-16 Pause Response........................14-26 14-17 Queue Status ......................... 14-26 14-18 QASR1 Bit Descriptions....................... 14-28 14-19 CCW Bit Descriptions ......................14-31 14-20 QADC64E_A Multiplexed Channel Assignments and Signal Designations ....... 14-32 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxvii...
Page 68 Serial Frame Formats......................15-52 15-30 Examples of SCIx Baud Rates....................15-53 15-31 Effect of Parity Checking on Data Size ................15-53 15-32 QSCI1CR Bit Descriptions ....................15-60 15-33 QSCI1SR Bit Descriptions ....................15-61 MPC561/MPC563 Reference Manual, Rev. 1.2 lxviii Freescale Semiconductor...
Page 69 MCPSM Register Address Map ................... 17-17 17-7 MCPSMSCR Bit Descriptions .................... 17-18 17-8 Clock Prescaler Setting ......................17-18 17-9 MMCSM Address Map ......................17-22 17-10 MMCSMCNT Bit Descriptions.................... 17-23 17-11 MMCSMML Bit Descriptions....................17-24 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxix...
Page 70 PPMPCR Bit Descriptions....................18-12 18-4 SAMP[0:2] Bit Settings ......................18-13 18-5 PPMPCR[CM] and PPMPCR[STR] Bit Operation.............. 18-15 18-6 Configuration Register (TX and RX) Channel Settings ............18-17 18-7 SHORT_REG Bit Descriptions .................... 18-20 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 71 UC3F External Interface Signals .................... 21-4 21-2 UC3F Register Programming Model ..................21-5 21-3 UC3FMCR Bit Descriptions....................21-6 21-4 UC3FMCRE Bit Descriptions ....................21-9 21-5 UC3FCTL Bit Descriptions ....................21-11 21-6 RCW Bit Descriptions ......................21-17 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxxi...
Page 72 CMPG-CMPH Bit Descriptions ................... 23-47 23-24 LCTRL1 Bit Descriptions..................... 23-47 23-25 LCTRL2 Bit Descriptions..................... 23-49 23-26 ICTRL Bit Descriptions......................23-51 23-27 ISCT_SER Bit Descriptions ....................23-52 23-28 BAR Bit Descriptions ......................23-53 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxxii...
Page 73 Development Port Access: DSDI Field ................24-84 24-34 Development Port Access: DSDO Field................24-84 24-35 Power Management Mechanism Overview ................24-86 25-1 MPC561 Boundary Scan Bit Definition ................. 25-5 25-2 MPC563 Boundary Scan Bit Definition ................25-17 25-3 Instruction Decoding......................25-30 ICTRL Bit Descriptions......................A-17 MPC561/MPC563 Reference Manual, Rev.
Page 74 Oscillator and PLL........................F-11 Array Program and Erase Characteristics ................F-12 CENSOR Cell Program and Erase Characteristics..............F-12 Flash Module Life........................F-12 Power Supply Pin Groups....................... F-13 F-10 Bus Operation Timing ......................F-20 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxxiv...
Page 75 F-26 MDASM Timing Characteristics.................... F-69 F-27 MPIOSM Timing Characteristics ................... F-71 F-28 MPC561/MPC563 Signal Names and Pin Names ..............F-73 Absolute Maximum Ratings (VSS = 0V) ................G-1 Thermal Characteristics ......................G-3 ESD Protection ........................G-6 DC Electrical Characteristics....................G-7 Oscillator and PLL.........................
Page 76 G-24 MPWMSM Timing Characteristics ..................G-60 G-25 MMCSM Timing Characteristics ..................G-62 G-26 MDASM Timing Characteristics................... G-64 G-27 MPIOSM Timing Characteristics ..................G-67 G-28 MPC561/MPC563 Signal Names and Pin Names ..............G-68 MPC561/MPC563 Reference Manual, Rev. 1.2 lxxvi Freescale Semiconductor...
Page 77: About This Book Lxxvii
Suggested Reading for further information. Unless otherwise noted, references to the MPC561 and MPC563 also apply to their code compressed counterparts, the MPC562 and MPC564, respectively. Any functional differences between the MPC561/MPC563 and MPC562/MPC564 are noted. MPC562/MPC564-specific information is located in Appendix A, “MPC562/MPC564 Compression...
Page 78 Chapter 14, “QADC64E Enhanced Mode Operation.” The two queued analog-to-digital converter (QADC) modules on the MPC561/MPC563 devices are 10-bit, unipolar, successive approximation converters. The modules can be configured to operate in one of two modes, legacy mode (for MPC555 compatibility) and enhanced mode. This chapter describes how the module operates in enhanced mode.
Page 79 MPC561/MPC563 to an external device; and shorts internal signals to increase access to multiple functions multiplexed on the same external signal. • Chapter 19, “Time Processor Unit 3,” describes an enhanced version of the original TPU, an intelligent, semi-autonomous microcontroller designed for timing control.
Page 80: Suggested Reading
This document uses the following notational conventions: cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of one, it is said to be set. MPC561/MPC563 Reference Manual, Rev. 1.2 lxxx Freescale Semiconductor...
Page 81: Notational Conventions
Notational Conventions Table i contains notational conventions that are used in this document. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxxxi...
Page 82: Acronyms And Abbreviations
Built-in self test Bus interface unit Branch processing unit BSDL Boundary-scan description language CMOS Complementary metal-oxide semiconductor Effective address External access register FIFO First-in-first-out Floating-point register FPSCR Floating-point status and control register MPC561/MPC563 Reference Manual, Rev. 1.2 lxxxii Freescale Semiconductor...
Page 83: References
Register used for indicating conditions such as carries and overflows for integer operations References The Sematech Official Dictionary and the Reference Guide to Letter Symbols for Semiconductor Devices by the JEDEC Council/Electronics Industries Association are recommended as references for terminology and symbology. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor lxxxiii...
Page 84 MPC561/MPC563 Reference Manual, Rev. 1.2 lxxxiv Freescale Semiconductor...
Page 85: Introduction
Chapter 1 Overview This chapter provides an overview of the MPC561/MPC563 microcontrollers, including a block diagram showing the major modular components and sections that list the major features, and differences between the MPC561/MPC563 and the MPC555. The MPC561, MPC562, MPC563, and MPC564 devices are members of the Freescale MPC500 RISC Microcontroller family.
Page 86: Block Diagram
— 2.6 ± 0.1-V external bus with a 5-V tolerant I/O system — 2.6 ± 0.1-V internal logic — <150µA on-chip voltage shunt regulator for RAM standby operation Block Diagram Figure 1-1 is a block diagram of the MPC561/MPC563. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 87: Key Features
8-Kbyte MIOS14 TPU3 TPU3 DPTRAM Figure 1-1. MPC561/MPC563 Block Diagram Key Features The MPC561/MPC563 key features are explained in the following sections. 1.3.1 High-Performance CPU System • Fully static design • Four major power saving modes — On, doze, sleep, deep-sleep, and power-down MPC561/MPC563 Reference Manual, Rev.
Page 88: Risc Mcu Central Processing Unit (Rcpu)
Support for enhanced exception table relocation feature • Branch target buffer • Contains 2 Kbytes of decompression RAM (DECRAM) for code compression. This RAM may also be used as general-purpose RAM when the code compression feature is not used. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 89: Flexible Memory Protection Unit
External 4.75- to 5.25-V VFLASH power supply for program, erase, and read operations • Security modes for software protection • Typical endurance of 100,000 write/erase cycles @ 25ºC • Typical data retention of 100 years @ 25ºC MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 90: 32-Kbyte Static Ram (Calram)
8 Kbytes of dual port TPU RAM (DPTRAM) shared by two TPU3 modules for TPU micro-code 1.3.3.2 22-Channel Modular I/O System (MIOS14) • Six modulus counter sub-modules (MCSM) • 10 double-action sub-modules (DASM) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 91: Two Enhanced Queued Analog-To-Digital Converter Modules (Qadc64E)
— Open network architecture, multi-master concept — High immunity to EMI — Short latency time for high-priority messages — Low-power sleep mode, with programmable wake-up on bus activity — TouCAN_C pins are shared with MIOS14 GPIO or QSMCM MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 92: Queued Serial Multi-Channel Module (Qsmcm)
Software configurable clock (TCLK) based on system clock • Software selectable clock modes (SPI mode and TDM mode) • Software selectable operation modes — Continuous mode — Start-transmit-receive (STR) mode • Software configurable internal modules interconnect (shorting) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 93: Mpc561/Mpc563 Optional Features
Overview MPC561/MPC563 Optional Features The following features of the MPC561/MPC563 are optional features and may not appear in certain configurations: • 56- or 66-MHz operation (40 MHz is default) • Code compression (available on MPC562 and MPC564 only) • 512 Kbytes Flash (available on MPC563 and MPC564 only)
Page 94: Additional Mpc561/Mpc563 Differences
— New Module Additional MPC561/MPC563 Differences • The MPC561/MPC563 devices are very similar to the MPC555 with the following differences: — Up to 66 MHz operating frequency (Refer to the applicable electrical characteristics document for more information.) — CDR3 technology —...
Page 95: Sram Keep-Alive Power Behavior
The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming a register in the USIU (IMMR[ISB]). The eight possible locations are the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 96 0x0140 0000 0x017F FFFF 0x0180 0000 0x01BF FFFF 0x01C0 0000 0x01FF FFFF 0xFFFF FFFF Figure 1-3. MPC561/MPC563 Memory Map The internal memory space is divided into the following sections. Refer to Figure 1-4. • Flash memory (512-Kbytes) • CALRAM static RAM memory (32-Kbytes) •...
Page 97 TouCAN_B (1 Kbyte) 4-Kbyte Overlay Section 0x30 7800 0x3F FFFF TouCAN_C (1 Kbyte) 0x30 7900 Reserved (896 bytes) 0x30 7F80 Note: Flash is available only on the UIMB Registers MPC563/MPC564. (128 bytes) 0x30 7FFF MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 1-13...
Page 98 Overview Figure 1-4. MPC561/MPC563 Internal Memory Map Supporting Documentation List This list contains references to currently available and planned documentation. • MPC555 User’s Manual (MPC555UM/AD) • RCPU Reference Manual (RCPURM/AD) • Nexus Standard Specification (non-Freescale document) available at: http://www.nexus5001.org/ •...
Page 99 Chapter 2 Signal Descriptions This chapter describes the MPC561/MPC563 microcontroller’s external signals. It contains a description of individual signals, shows their behavior, shows whether the signal is an input or an output, and indicates signal multiplexing. NOTE A bar over a signal name indicates that the signal is active-low—for example, TA (transfer acknowledge).
Page 100 Note: In cases where one multiplexed signal QVDDL is an input and another is an output, together KAPWR they are shown as I/O. VDDH NVDDL Global Power Supply The MPC561 has no Flash EEPROM Figure 2-1. MPC561/MPC563 Signal Groupings MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 101 Signal Descriptions Signal Summary Table 2-1 describes individual MPC561/MPC563 signals, grouped by functional module. Table 2-1. MPC561/MPC563 Signal Descriptions No. of Function after Signal Name Type Description Signals Reset Bus Interface Address Bus [8:31]. Specifies the physical address of the Controlled by bus transaction.
Page 102 MPC561/MPC563. Output Enable. This output line is asserted when a read access is initiated by the MPC561/MPC563 to an external slave controlled by the memory controller’s GPCM. Reset Configuration. This input line is sampled by the MPC561/MPC563 during the assertion of the HRESET signal in order to sample the reset configuration.
Page 103 Port SGPIOC2. Allows the signal to be used as a general-purpose input/output. Memory Transfer Start. This is the transfer start signal from the MPC561’s memory controller that allows external memory access by an external bus master. Interrupt Request 3. One of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the RCPU.
Page 104 Write Enable[0:3]/Byte Enable[0:3]. This output signal is asserted when a write access to an external slave controlled by the memory controller is initiated by the MPC561/MPC563. It can be optionally asserted on all read and write accesses. See WEBS bit definition in Table 10-8.
Page 105 Hard Reset. The reset controller can detect an external assertion of HRESET only if it occurs while the MPC561/MPC563 is not asserting reset. After negation of HRESET or SRESET is detected, a 16-cycle period is taken before testing the presence of an external reset.
Page 106 Visible Instruction Queue Flush Status 0. This output signal RCW[DBGC]. together with VF1 and VF2 is output by the Table 6-8. MPC561/MPC563 when program instruction flow tracking is required. VFs report the number of instructions flushed from the instruction queue in the internal core. See Chapter 23, “Development Support,”...
Page 107 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset JTAG/BDM/READI TMS unless the Test Mode Select. This input controls test mode operations Nexus (READI) for on-board test logic (JTAG). TMS / EVTI port is enabled, EVTI.
Page 108 ENGCLK / BUCLK ENGCLK (2.6 EECLK[0:1] bits in the SCCR register in the SIU. BUCLK. When the MPC561/MPC563 is in limp mode, it is operating from a less precise on-chip ring oscillator to allow the system to continue minimum functionality until the system clock is fixed.
Page 109 MPC561. VSSF VSSF VSSF. Flash core ground reference. Available in the MPC563 only. This signal is not connected on the MPC561. QADC64E_A and QADC64E_B ETRIG[1:2]. These are the external trigger inputs to the QADC64E_A and QADC64E_B modules. ETRIG1 can be...
Page 110 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset Analog Channel 2. Internally multiplexed input-only analog channel. The input is passed on as a separate signal to the QADC64E. Multiplexed Analog Input (A_ANy). Externally multiplexed...
Page 111 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset Analog Channel 1. Internally multiplexed input-only analog channel. Passed on as a separate signal to the QADC64E. Multiplexed Analog Input (B_ANx). Externally multiplexed...
Page 112 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset ALTREF ALTREF ALTREF. Input signal for alternate reference voltage for the QADC64E_A and QADC64E_B modules. VDDA VDDA VDDA. Power supply input to analog subsystems of the QADC64E_A and QADC64E_B modules.
Page 113 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset Transmit Data 2. This is the serial data output from the SCI2 Port QGPO 2. When this signal is not needed for SCI applications it can be configured as general-purpose output.
Page 114 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset MPWM1 unless Pulse Width Modulation 1. This signal provides a variable the Nexus pulse width output signal at a wide range of frequencies.
Page 115 MIOS14 GPIO 0. Allows the signals to be used as general-purpose inputs/outputs. Visible Instruction Queue Flush Status 0. These signals MPIO32B0 output by the MPC561/MPC563 when program instruction unless the flow tracking is required. VF reports the number of MPIO32B0 / VF0 / MDO1...
Page 116 MIOS14 GPIO 3. Allows the signal to be used as a general-purpose input/output. Visible History Buffer Flush Status 0. This signal is output by MPIO32B3 the MPC561/MPC563 to allow program instruction flow unless the tracking. It reports the number of instructions flushed from Nexus (READI) the history buffer in the RCPU.
Page 117 Signal Descriptions Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Function after Signal Name Type Description Signals Reset MIOS14 GPIO 12. This function allows the signals to be MPIO32B12 / C_CNTX0 MPIO32B12 used as general-purpose inputs/outputs. TouCAN_C Transmit Data. This is the serial data output signal for the TouCAN_C module.
Page 118 SRAM), BBC DECRAM (2-Kbyte vocabulary SRAM). This is the function after PORESET/TRST and HRESET. This signal also included the MDO5 function on the K27S mask set of the MPC561. This signal was ECK on K27S mask set of MPC561. Only the MCP563/MPC564 have Flash memory.
Page 119 Signal Descriptions Table 2-2. MPC561/MPC563 Signal Sharing (continued) Signal Name Module Sharing MPWM0/MDI1, READI submodule shared with MIOS14 PWM submodule MPWM1/MDO2, MPWM17/MDO3, MPWM[18:19]/MDO[6:7] B_T2CLK/PCS4 TPU3 modules shared with QSMCM module. A_T2CLK/PCS5 ETRIG1/PCS6 QADC64E modules shared with QSMCM module. ETRIG2/PCS7 2.2.2...
Page 120 1 Not slew rate controlled SLRC5 controls the slew rate of the MIOS14 MPWM3 signal. For the slew rate refer to Appendix F, “Electrical Characteristics.” 0 Slew rate controlled 1 Not slew rate controlled MPC561/MPC563 Reference Manual, Rev. 1.2 2-22 Freescale Semiconductor...
Page 121 15-31 — Reserved This bit was RESERVED on the K27S mask set of MPC561. Pad Module Configuration Register (PDMCR2) The PDMCR2 controls alternate functionality of signals shared between different modules, as well as the pre-discharge circuitry to allow 5V friendliness on the data bus.
Page 122 This bit will be disabled if full port mode is enabled in the READI module, and MDO6 bit is logic ‘0’. 22:24 — Reserved PCSV Selects the polarity of QSMCM module QSPI PCS signals in the PCS expanded mode. 0 Selects Active High. 1 Selects Active Low. MPC561/MPC563 Reference Manual, Rev. 1.2 2-24 Freescale Semiconductor...
Page 123 PPM_RX1 MPWM2 PPM_TSYNC PPM_TCLK PPM_RX0 PPM_TX0 PPM_RX1 PPM_TX1 PPM_TSYNC PPM_TCLK Table 2-9. Enhanced PCS Functionality PCS_IN[3:0] PCS_OUT[7:0] IF PCSV = 0 PCS_OUT[7:0] IF PCSV = 1 0000 00000001 11111110 0001 00000010 11111101 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 2-25...
Page 124 PDMCR2 PDMCR2 SHORT_REG A_T2CLK/PCS5 B_T2CLK/PCS4 TPU_A TPU_B [PCS5EN] [PCS4EN] [SH_T2CLK] PAD Function PAD Function Connection Connection A_T2CLK B_T2CLK A_T2CLK/PCS5 B_T2CLK/PCS4 A_T2CLK B_T2CLK A_T2CLK/PCS5 A_T2CLK/PCS5 A_T2CLK PCS4 A_T2CLK/PCS5 B_T2CLK Signal driven HI internally MPC561/MPC563 Reference Manual, Rev. 1.2 2-26 Freescale Semiconductor...
Page 125 ETRIG1/PCS6 and ETRIG2/PCS7 pads dependent on the values of PDMCR2[PCS6EN], PDMCR2[PCS7EN], SHORT_REG [SH_ET1] and SHORT_REG [SH_ET2]. Also shown in this table is the internal connection of the ETRIG signals when the enhanced chip select function is used. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 2-27...
Page 126 PCS6 PCS7 Disabled A_TPUCH15 B_TPUCH15 On the MPC561/MPC563, the JTAG, BDM, and READI (Nexus interface) signals are all shared. Only one set of signals can be active at a time. Table 2-12 shows the shared functions in the different modes.
Page 127 2.5.1 JTAG Mode Selection The MPC561/MPC563 has five JTAG signals. The test data input (TDI) and test data output (TDO) scan ports are used to scan instructions as well as data into the various scan registers for JTAG operations. The scan operation is controlled by the test access port (TAP) controller, which in turn is controlled by the test mode select (TMS) input sequence.
Page 128 JTAG On JTAG Disabled Figure 2-4. Debug Mode Selection (JTAG) 2.5.2 BDM Mode Selection The MPC561/MPC563 has a 10 pin BDM port. See Figure 2-5 for BDM mode selection. The BDM mode is entered by the following sequence of events: •...
Page 129 This is especially true if the reset configuration word (RCW) comes from the Flash, because the Flash does not drive the RCW until 256 clocks after the start of MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 130 For the signals that support debug, opcode tracking, and bus control functionality, the pull resistors will be controlled by the SPRDS bit in the PDMCR register. During reset this signal will be synchronously used MPC561/MPC563 Reference Manual, Rev. 1.2 2-32...
Page 131 Table 2-14 summarizes the reset states of all signals on the MPC561/MPC563. Note that PD refers to a weak pull-down, PU2.6 refers to a weak pull-up to 2.6 V, and PU5 refers to a weak pull-up to 5 V. All...
Page 132 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? USIU ADDR[8:31] 2.6 V 50 ; 25 PD until reset Controlled by SC bit in the negates reset config word.
Page 133 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? IRQ4 / 2.6 V PD until reset IRQ4 6, 8 negates AT2 / 2.6 V...
Page 134 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? 7, 12 2.6 V 50 ; 25 PU2.6 when driver not enabled or until...
Page 135 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? SGPIOC6 50 ; 50 PD until PRDS is set FRZ / 2.6 V 50 ;...
Page 136 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? 2.6 V 50 ; 25 PU2.6 until reset DSDO unless the Nexus negates or the...
Page 137 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? TXD2 / 50 ; 50 PU5 until QGPO2 PULL_DIS1 is QGPO2 / 50 ; 50 C_CNTX0 50 ;...
Page 138 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? MPWM[18:19] 50 ; 50 Pull device MPWM[18:19] enabled until PULL_DIS0 is MDO[6:7] 2.6 V 50 ;...
Page 139 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? MPIO32B12 / 50 ; 50 PU5 until MPIO32B12 PULL_DIS0 is C_CNTX0 50 ; 50 MPIO32B13 50 ;...
Page 140 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? A_AN1 / PU5 when driver A_AN1 not enabled or A_ANx / until PULL_DIS2 is A_PQB1 50 ;...
Page 141 Signal Descriptions Table 2-14. MPC561/MPC563 Signal Reset State (continued) Slew Rate Drive Hysteresi Function After HRESET, Signal List Voltage Controlled Load Reset State PORESET/TRST Option? (pF) Enabled? B_AN3 / PU5 when driver B_AN3 not enabled or B_ANz / until PULL_DIS2 is B_PQB3 50 ;...
Page 142 This pin requires a pull-up to 2.6 V if interrupts are ever enabled for this IRQ input. This signal also includes the MDO5 function on the K27S mask set of the MPC561. The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used as interrupts, the interrupt source should be removed during PORESET/TRST to insure the MODCK pins are in the correct state on the rising edge of PORESET/TRST.
Page 143 An external pull-up is required in order to negate the signal in the appropriate time. This pin is 5-V tolerant. This signal was PD only until SPRDS is set on mask set K27S of the MPC561. These values represent full drive, half drive and quarter drive.
Page 144 Signal Descriptions MPC561/MPC563 Reference Manual, Rev. 1.2 2-46 Freescale Semiconductor...
Page 145 This section provides an overview of the RCPU. For a detailed description of this processor, refer to the RCPU Reference Manual. The following sections describe each block and sub-block. RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 146 Address Instruction Sequencer ALU/ Instruction Pre-fetch IMUL/ Queue IDIV I-DATA History Branch Processor Unit (32 X 32) I-ADDR Next Address Control Generation Regs Write Back Bus 2 slots/clock Figure 3-1. RCPU Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 147 Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 148 Branch processing unit (BPU) Includes the implementation of all branch instructions. Load/store unit (LSU) Includes implementation of all load and store instructions, whether defined as part of the integer processor or the floating-point processor. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 149 IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require multiple clock cycles to execute. IMUL–IDIV is pipelined for multiply instructions, so that consecutive multiply instructions can be issued MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 150 Virtual environment architecture (VEA) — describes the memory model for a multiprocessor environment, and describes other aspects of virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may not necessarily adhere to the OEA. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 151 Registers can be accessed explicitly through specific instructions such as move to special-purpose register (mtspr) or move from special-purpose register (mftspr), or implicitly as part of an instruction’s execution. Some registers are accessed both explicitly and implicitly. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 152 Integer Exception Register (XER) Link Register (LR) Count Register (CTR) USER MODEL VEA Time Base Facility (for Reading) Time Base Lower – Read (TBL) Time Base Upper – Read (TBU) Figure 3-3. RCPU Programming Model MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 153 Central Processing Unit Table 3-2 lists the MPC561/MPC563 supervisor-level registers; refer also to Chapter 6, “System Configuration and Protection,” Chapter 11, “L-Bus to U-Bus Interface (L2U),” and Chapter 4, “Burst Buffer Controller 2 Module,” for more information. Table 3-2. Supervisor-Level SPRs...
Page 154 L2U Region Attribute Register 0 (L2U_RA0) Table 11-9 for bit descriptions. L2U Region Attribute Register 1 (L2U_RA1) Table 11-9 for bit descriptions. L2U Region Attribute Register 2 (L2U_RA2) Table 11-9 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 3-10 Freescale Semiconductor...
Page 155 Comparator H Value Register (CMPH) Table 23-23 for bit descriptions. L-bus Support Comparators Control 1 (LCTRL1) Table 23-24 for bit descriptions. L-bus Support Comparators Control 2 (LCTRL2) Table 23-25 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-11...
Page 156 The PowerPC ISA architecture provides 32 64-bit FPRs. These registers are accessed as source and destination registers through operands in floating-point instructions. Each FPR supports the double-precision, floating-point format. Every instruction that interprets the contents of an FPR as a MPC561/MPC563 Reference Manual, Rev. 1.2 3-12 Freescale Semiconductor...
Page 157 Status, not sticky [24:31] Control FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not listed among the FPSCR bits directly affected by the various instructions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-13...
Page 158 VXISI Sticky bit Floating-point invalid operation exception for ∞/∞. VXIDI Sticky bit VXZDZ Floating-point invalid operation exception for 0/0. Sticky bit Floating-point invalid operation exception for ∞ x 0. VXIMZ Sticky bit MPC561/MPC563 Reference Manual, Rev. 1.2 3-14 Freescale Semiconductor...
Page 159 Floating-point underflow exception enable. This bit should not be used to — determine whether denormalization should be performed on floating-point stores. Floating-point zero divide exception enable. — Floating-point inexact exception enable. — MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-15...
Page 160 A specified field of the CR can be set by an instruction (mcrxr) to move to the CR from the XER. • Condition register logical instructions can be used to perform logical operations on specified bits in the condition register. • CR0 can be the implicit result of an integer operation. MPC561/MPC563 Reference Manual, Rev. 1.2 3-16 Freescale Semiconductor...
Page 161 When a specified CR field is set by a compare instruction, the bits of the specified field are interpreted as shown in Table 3-9. A condition register field can also be accessed by the mfcr, mcrf, and mtcrf instructions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-17...
Page 162 Integer and subtract instructions having OE=1 set OV if the carry out of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by compare instructions or other instructions that cannot overflow. MPC561/MPC563 Reference Manual, Rev. 1.2 3-18 Freescale Semiconductor...
Page 163 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Field Loop Count Reset Unchanged Addr SPR 9 Figure 3-10. Count Register (CTR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-19...
Page 164 SRESET 0000_0 Figure 3-11. Machine State Register (MSR) This bit is available only on code compression-enabled options of the MPC561/MPC563. The reset value is a reset configuration word value extracted from the internal bus line. Refer to Section 7.5.2, “Hard Reset Configuration Word (RCW).”...
Page 165 Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select the endian mode for the context established by the exception. Little-endian mode is not supported on the MPC561/MPC563. This bit should be cleared to 0 at all times. 0 The processor runs in big-endian mode during exception processing.
Page 166 0 Machine state is not recoverable. 1 Machine state is recoverable. Little-endian mode. This mode is not supported on MPC561/MPC563. This bit should be cleared to 0 at all times. 0 The processor operates in big-endian mode during normal processing.
Page 167 Machine Status Save/Restore Register 1 (SRR1) The machine status save/restore register 1 (SRR1), SPR 27, saves the machine status on exceptions and restores the machine status when an rfi instruction is executed. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-23...
Page 168 GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory. SPRG2 This register may be used by the operating system as needed. SPRG3 This register may be used by the operating system as needed. MPC561/MPC563 Reference Manual, Rev. 1.2 3-24 Freescale Semiconductor...
Page 169 A 16-bit number that distinguishes between various releases of a particular version. The RCPU value is 0x0020. 3.9.10 Implementation-Specific SPRs The MPC561/MPC563 includes several implementation-specific SPRs that are not defined by the PowerPC ISA architecture. These registers, listed in Table 3-2 Table 3-3, can be accessed by supervisor-level instructions only.
Page 170 0 Source operand A is not denormalized 1 Source operand A is denormalized Floating-point tiny result. 0 Floating-point result is not tiny 1 Floating-point result is tiny NOTE Software must insert a sync instruction before reading the FPECR. MPC561/MPC563 Reference Manual, Rev. 1.2 3-26 Freescale Semiconductor...
Page 171 — Branch and trap instructions — Condition register logical instructions • Processor control instructions, which are used for synchronizing memory accesses. — Move to/from SPR instructions — Move to/from MSR MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-27...
Page 172 (addze. addzeo addzeo.) rD,rA Add to Zero Extended and (and.) rA,rS,rB andc (andc.) rA,rS,rB AND with Complement andi. rA,rS,UIMM AND Immediate andis. rA,rS,UIMM AND Immediate Shifted b (ba bl bla) target_addr Branch MPC561/MPC563 Reference Manual, Rev. 1.2 3-28 Freescale Semiconductor...
Page 173 Floating Convert to Integer Word fctiwz (fctiwz.) frD,frB Floating Convert to Integer Word with Round Toward Zero fdiv (fdiv.) frD,frA,frB Floating Divide (Double-Precision) fdivs (fdivs.) frD,frA,frB Floating Divide Single fmadd (fmadd.) frD,frA,frC,frB Floating Multiply-Add (Double-Precision) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-29...
Page 174 Load Floating-Point Single with Update Indexed lfsx frD,rA,rB Load Floating-Point Single Indexed rD,d(rA) Load Half-Word Algebraic lhau rD,d(rA) Load Half-Word Algebraic with Update lhaux rD,rA,rB Load Half-Word Algebraic with Update Indexed MPC561/MPC563 Reference Manual, Rev. 1.2 3-30 Freescale Semiconductor...
Page 175 Move to FPSCR Field Immediate mtmsr Move to Machine State Register mtspr SPR,rS Move to Special Purpose Register mulhw (mulhw.) rD,rA,rB Multiply High Word mulhwu (mulhwu.) rD,rA,rB Multiply High Word Unsigned mulli rD,rA,SIMM Multiply Low Immediate MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-31...
Page 176 Store Floating-Point as Integer Word Indexed stfs frS,d(rA) Store Floating-Point Single stfsu frS,d(rA) Store Floating-Point Single with Update stfsux frS,rB Store Floating-Point Single with Update Indexed stfsx frS,r B Store Floating-Point Single Indexed rS,d(rA) Store Half-Word MPC561/MPC563 Reference Manual, Rev. 1.2 3-32 Freescale Semiconductor...
Page 177 Recommended Simplified Mnemonics To simplify assembly language coding, a set of alternative mnemonics is provided for some frequently used operations (such as no-op, load immediate, load address, move register, and complement register). MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-33...
Page 178 Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until all instructions currently in the execute stage successfully complete execution and report their results. MPC561/MPC563 Reference Manual, Rev. 1.2 3-34 Freescale Semiconductor...
Page 179 To determine whether the machine state is recoverable, the RI (recoverable exception) bit in SRR1 can be read. During exception processing, the RI bit in the MSR is copied to SRR1 and then cleared. The MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 180 NOTE In the MPC561/MPC563, the exception table can additionally be relocated by the BBC module to internal memory and reduce the total size required by the exception table (see Section 4.3, “Exception Table Relocation...
Page 181 This exception will not be generated by hardware. 3.12 Instruction Timing The RCPU processor is pipelined. Because the processing of an instruction is broken into a series of stages, an instruction does not require the processor’s full resources. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-37...
Page 182 Central Processing Unit The instruction pipeline in the MPC561/MPC563 has four stages: 1. The dispatch stage is implemented using a distributed mechanism. The central dispatch unit broadcasts the instruction to all units. In addition, scoreboard information (regarding data dependencies) is broadcast to each execution unit. Each execution unit decodes the instruction. If the instruction is not implemented, a program exception is taken.
Page 183 In most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any control register implemented by the MPC561/MPC563. Exception to this rule are bits [16:23] of the fixed-point exception cause register (XER) and the reserved bits of the machine state register (MSR), which are set by the source value on write and return the value last set for it on read.
Page 184 3.13.7.1 Invalid Branch Instruction Forms Bits marked with z in the BO encoding definition are discarded by the MPC561/MPC563 decoding. Thus, these types of invalid form instructions yield results of the defined instructions with the z-bit zero. If the decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address of the branch is the new value of the CTR.
Page 185 Optional Instructions The only optional instruction implemented by RCPU hardware is store floating-point as integer word indexed (stfiwx). An attempt to execute any other optional instruction causes an implementation dependent software emulation exception. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-41...
Page 186 When the operand is between the range of single denormalized and double denormalized it is considered a programming error. The hardware will handle this case as if the operand was single denormalized. MPC561/MPC563 Reference Manual, Rev. 1.2 3-42 Freescale Semiconductor...
Page 187 The MPC561/MPC563 does not provide support for snooping an external bus activity outside the chip. The provision is made to cancel the reservation inside the MPC561/MPC563 by using the CR and KR input signals. Internal buses are snooped for RCPU accesses, and the reservation mechanism can be used for multitask single master applications.
Page 188 3.15 Operating Environment Architecture (OEA) The MPC561/MPC563 has an internal memory space that includes memory-mapped control registers and internal memory used by various modules on the chip. This memory is part of the main memory as seen by the RCPU and can be accessed by an external system master.
Page 189 Cleared to 0 10:15 Cleared to 0 Other Loaded from bits [16:31] of MSR. In the current implementation, bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR[RI] MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-45...
Page 190 A machine-check exception is assumed to be caused by one of the following conditions: • The accessed address does not exist. • A data error was detected. • A storage protection violation was detected by chip-select logic. MPC561/MPC563 Reference Manual, Rev. 1.2 3-46 Freescale Semiconductor...
Page 191 MSR[5:9] 10:15 Cleared to 0 16:31 Loaded from bits [16:31] of MSR. In the current implementation, bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR[RI] MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-47...
Page 192 The interrupt may be caused by the assertion of an external IRQ signal, by a USIU timer, or by an internal chip peripheral. Refer to Section 6.1.4, “Enhanced Interrupt Controller,” for more information on the interrupt controller. MPC561/MPC563 Reference Manual, Rev. 1.2 3-48 Freescale Semiconductor...
Page 193 The enhanced interrupt controller mode is available for interrupt-driven applications on MPC561/MPC563. It allows the single external interrupt exception vector 0x500 to be split into up to 48 different vectors corresponding to 48 interrupt sources to speed up interrupt processing. It also supports a low priority source masking feature in hardware to handle nested interrupts more easily.
Page 194 Otherwise undefined. If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a compressed address. MPC561/MPC563 Reference Manual, Rev. 1.2 3-50 Freescale Semiconductor...
Page 195 Trap — A trap type program exception is generated when any of the conditions specified in a trap instruction is met. The register settings for program exceptions are shown in Table 3-28. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-51...
Page 196 Register Bits Setting Description Save/Restore Register 0 (SRR0) Set to the effective address of the instruction that caused the exception. Save/Restore Register 1 (SRR1) [0:15] Cleared to 0 [16:31] Loaded from MSR[16:31] MPC561/MPC563 Reference Manual, Rev. 1.2 3-52 Freescale Semiconductor...
Page 197 Machine State Register (MSR) No change No change Set to value of ILE bit prior to the exception DCMPEN This bit is set according to (BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]) Other Cleared to 0 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-53...
Page 198 MSR[BE]= 1 and a branch is completed. Notice that the trace interrupt does not occur after an instruction that caused an interrupt (for instance, sc). Monitor/debugger software must change the vectors of other MPC561/MPC563 Reference Manual, Rev. 1.2 3-54 Freescale Semiconductor...
Page 199 The register settings for floating-point assist exceptions are shown in Table 3-33. Table 3-33. Register Settings following Floating-Point Assist Exceptions Register Name Bits Description Save/Restore Register 0 (SRR0) Set to the effective address of the instruction that caused the interrupt MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-55...
Page 200 Cleared to 0 10:15 Cleared to 0 Other Loaded from bits [16:31] of MSR. In the current implementation, bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR[RI]. MPC561/MPC563 Reference Manual, Rev. 1.2 3-56 Freescale Semiconductor...
Page 201 MSR[IR] Machine State Register (MSR) No change No change Bit is copied from ILE DCMPEN This bit is set according to (BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]) Other Cleared to 0 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-57...
Page 202 3.15.4.15 Implementation-Specific Data Protection Error Exception (0x1400) The implementation-specific data protection error exception occurs in the following case: • The data access violates the storage protection and MSR[DR]=1. See Chapter 11, “L-Bus to U-Bus Interface (L2U).” MPC561/MPC563 Reference Manual, Rev. 1.2 3-58 Freescale Semiconductor...
Page 203 When the development port request is asserted to the RCPU. Refer to Chapter 23, “Development Support,” for details on how to generate the development port-interrupt request. Table 3-37 for debug-exception register settings. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-59...
Page 204 In general, the architecture permits instructions to be partially executed when an alignment or data storage interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is MPC561/MPC563 Reference Manual, Rev. 1.2 3-60 Freescale Semiconductor...
Page 205 Any other OEA optional facilities and instructions (except those that are discussed here) are not implemented by the RCPU hardware. Attempting to execute any of these instructions causes an implementation dependent software emulation interrupt to be taken. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 3-61...
Page 206 Central Processing Unit MPC561/MPC563 Reference Manual, Rev. 1.2 3-62 Freescale Semiconductor...
Page 207 The IMPU is able to relocate the RCPU exception vectors. The IMPU always maps the exception vectors into the internal memory space of the MPC561/MPC563. This feature is important for a multi-MPC561/MPC563 system, where, although the internal memories of some controllers are not shifted to the lower 4 Mbytes, they can still have their own internal exception vector tables with the same exception addresses issued by their RCPU cores.
Page 208 Figure 4-1. BBC Module Block Diagram Key Features 4.1.1 BIU Key Features • Supports pipelined and burstable and single accesses to internal and external memories • Supports the decoupled interface with the RCPU instruction unit MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 209 No need for address translation between compressed and non-compressed address spaces — ICDU provides “next instruction address” to the RCPU • In most cases, instruction decompression takes one clock • Code decompression is pipelined: MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 210 BIU. The IMPU compares the address of the access to its region programming. The BIU checks if the access can be immediately transferred to the U-bus, otherwise it requests the U-bus for the next clock. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 211 4 data beats on the internal U-bus. NOTE The burst operation in the MPC561/MPC563 is useful if a user system implements burstable memory devices on the external bus. Otherwise the mode will cause performance degradation when running code from external memory.
Page 212 Hard reset sets some of the fields and bits in the BBC configuration registers to their default reset state. Some bits in the BBCMCR register get their values from the reset configuration word. All the registers are reset using HRESET; SRESET alone has no effect on them. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 213 4.2.6 Debug Operation Mode When the MPC561/MPC563 RCPU core is in debug mode, the BBC initiates non-burstable access to the debug port and ICDU is bypassed (i.e., instructions transmitted to the debug port must be non-compressed regardless of RCPU MSR[DCMPEN] bit state).
Page 214 If the exception table relocation is disabled by the ETRE bit in the BBCMCR register, the BBC transfers the exception fetch address to the U-bus of the MPC561/MPC563 with no interference. In this case, normal PowerPC ISA exception addressing is implemented.
Page 215 NOTE The 8 Kbytes allocated for the original PowerPC ISA exception table can be almost fully utilized. This is possible if the MPC561/MPC563 system memory is not mapped to the exception address space, (i.e., the addresses 0xFFF0 0000 to 0xFFF0 1FFF are not used).
Page 216 4.3.2 Enhanced External Interrupt Relocation (EEIR) The BBC also supports the enhanced external interrupt model of the MPC561/MPC563 which allows the removal of the interrupt requesting a source detection stage from the interrupt routine. The interrupt controller provides the interrupt vector to the BBC together with an interrupt request to the RCPU. When the RCPU acknowledges an interrupt request, it issues an external interrupt vector to the BBC.
Page 217 EEIR mechanism. When the EEIR function is activated, any branch instruction execution with the 0xFFF0 0500 target address may cause unpredictable program execution. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 4-11...
Page 218 It is mapped both in the ICDU internal address space and in the chip memory address space. It is a single port memory and may not be accessed simultaneously from the ICDU and U-bus. MPC561/MPC563 Reference Manual, Rev. 1.2 4-12...
Page 219 4-6. The proper access rights to the DECRAM array may be defined by programming the R, D, and S bits of the BBCMCR register: • Read/write or read only • Instruction/data or data only • Supervisor/user or supervisor only MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 4-13...
Page 220 When the RCPU generates a change of flow (COF) address for instruction fetch, the BTB control logic compares it to the tag values currently stored in the tag register file where the following events can happen: MPC561/MPC563 Reference Manual, Rev. 1.2 4-14...
Page 221 BTB entry were delivered. In case of a BTB hit, the impact of instruction decompression latency (in compressed mode) is eliminated as well as a latency of instruction storage memory device. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 4-15...
Page 222 The BTB operation may be inhibited regarding some memory regions. The BTB caching is inhibited for a region if the BTBINH bit is set in the region attribute register (or global region attribute register). See MPC561/MPC563 Reference Manual, Rev. 1.2 4-16...
Page 223 RCPU mtspr/mfspr instructions. 2. Decompressor vocabulary RAM (DECRAM). The DECRAM array occupies the 2-Kbyte physical memory (8 Kbytes of the MPC561/MPC563 address space is allocated for DECRAM). 3. Decompressor class configuration registers (DCCR) block. It consists of 15 decompression class configuration registers.
Page 224 The DECRAM occupies addresses from 0x2F 8000 to 0x2F 87FF. The DCCR block occupies addresses from 0x2F A000 to 0x2F A03F. The address for non-implemented memory blocks is not acknowledged, and causes an error condition. MPC561/MPC563 Reference Manual, Rev. 1.2 4-18 Freescale Semiconductor...
Page 225 These bits can be set in Factory test mode only. The User should treat these bits as reserved and always write as zeros. 8:17 — Reserved Burst Enable 0 Burst access is disabled. 1 Burst access is enabled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 4-19...
Page 226 Enable Compression. This bit enables the operation of the MPC562/MPC564 in compression on mode. NOTE: For Rev A and later versions of the MPC563 and rev B and later of the MPC561, the default state is defined by bit 21 of the reset configuration word, and is writable. In earlier versions, the bit can only be set by the reset configuration word.
Page 227 Reserved for BBC Test Operations. BE and BTEE should not both be set at the same time, setting the BE bit disables the BTB. This bit is available on the MPC562/MPC564 only, software should write "0" to this bit for MPC561/MPC563. NOTE...
Page 228 G and PP attributes perform similar protection activities on a region. The more protective attribute will be implied on the region if the attributes programming oppose each other. This field is available only on the MPC562/MPC564. MPC561/MPC563 Reference Manual, Rev. 1.2 4-22 Freescale Semiconductor...
Page 229 MI_RB[0:3]/MI_RBA[0:3] registers. It also contains protection regions 0-3 enable bits. Field ENR 0 ENR1 ENR2 ENR3 — HRESET 0000_0000_0000_0000 Field — — CMPR BTBINH — HRESET 0000_0000_0000_0000 Addr SPR 528 Figure 4-10. Global Region Attribute Register (MI_GRA) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 4-23...
Page 230 1 BTB operation is prohibited for current memory region. 29:31 — Reserved This field is available only on the MPC562/MPC564. NOTE The MI_GRA register should be programmed to enable fetch access (PP and G bits) before RCPU MSR[IR] is set. MPC561/MPC563 Reference Manual, Rev. 1.2 4-24 Freescale Semiconductor...
Page 231 External Interrupt Relocation Table Base Address bits [0:20] 21:31 — Reserved. EIBADR must be set on a 4K page boundary. 4.6.3 Decompressor Class Configuration Registers Section A.4, “Decompressor Class Configuration Registers (DCCR0-15)” for the registers of the ICDU. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 4-25...
Page 232 Burst Buffer Controller 2 Module MPC561/MPC563 Reference Manual, Rev. 1.2 4-26 Freescale Semiconductor...
Page 233 The EBI handles the transfer of information between the internal busses and the memory or peripherals in the external address space. The MPC561/MPC563 is designed to allow external bus masters to request and obtain mastership of the system bus, and if required access the on-chip memory and registers. Refer to Chapter 9, “External Bus...
Page 234 EEPROM.” It is not possible to operate the MPC561/MPC563 from the external world while the Flash is in censorship mode and in a censorship state. The internal Flash array will be either locked or accessible only after the entire array contents have been erased.
Page 235 (SIMASK3),” for details. 0x2F C050 Interrupt In-Service2 Register (SISR2) Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and SISR3),” for details. 0x2F C054 Interrupt In-Service3 Register (SISR3) Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and SISR3),” for details. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 236 Section 6.2.2.4.3, “Time Base Reference Registers (TBREF0 and TBREF1),” for bit descriptions. 0x2F C208 Time Base Reference 1 (TBREF1) Section 6.2.2.4.3, “Time Base Reference Registers (TBREF0 and TBREF1),” for bit descriptions. 0x2F C20C–0x2F Reserved C21C MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 237 0x2F C308 Time Base Reference 1 Key (TBREF1K) Table 8-8 for bit descriptions. 0x2F C30C Time Base and Decrementor Key (TBK) Table 8-8 for bit descriptions. 0x2F C310–0x2F C31C Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 238 USIU Special-Purpose Registers Table 5-2 lists the MPC561/MPC563 special purpose registers (SPR) used by the USIU. These registers reside in an alternate internal memory space that can only be accessed with the mtspr and mfspr instructions, or from an external master (refer to Section 6.1.2, “External Master...
Page 239 Bits [0:17] and [28:31] are all 0. Table 5-3 shows the MPC561/MPC563 address format for special purpose register access. For an external master, accessing an MPC500 SPR, address bits [0:17] and [28:31] are compared to zeros to confirm that an SPR access is valid. See Section 6.1.2.1, “Operation in External Master...
Page 240 Unified System Interface Unit (USIU) Overview MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 241 MPC500 architecture to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base (also defined by the MPC561/MPC563 architecture). The period for the DEC when driven by a 4-MHz oscillator can be up to 4295 seconds, which is approximately 71.6 minutes.
Page 242 Low Power Stop (Section 6.1.12, “Low Power Stop Operation”)—In low power modes, specific timers are frozen but others are not. Figure 6-1 shows a block diagram of the system configuration and protection logic. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 243 System configuration registers include the SIU module configuration register (SIUMCR), and the internal memory mapping register (IMMR). Refer to Section 6.2.2, “System Configuration and Protection Registers,” for register diagrams and bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 244 Peripheral mode (enabled by setting PRPM in the external master control (EMCR) register) uses a special slave mechanism that shuts down the RCPU and an alternative master on the external bus can perform accesses to any internal bus slave. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 245 The MPC561/MPC563 does not support burst accesses from an external master; only single accesses of 8, 16, or 32 bits can be performed. The MPC561/MPC563 asserts burst inhibit (BI) on any attempt to initiate a burst access to internal memory.
Page 246 During an external master access, the USIU compares the external address with the internal address block to determine if MPC561/MPC563 operation is required. Since only 24 of the 32 internal address bits are available on the external bus, the USIU assigns zeros to the most significant address bits (ADDR[0:7]).
Page 247 Read Register GPIO Write Register Read Write Write Path Clock Write SGPIO Read Path of Write Operation Path of Read Operation SGPIO Circuitry Figure 6-2. Circuit Paths of Reading and Writing to SGPIO MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 248 Full backward compatibility with MPC555/MPC556 (enhanced mode is software programmable.) 6.1.4.2 Interrupt Configuration An overview of the MPC561/MPC563 interrupt structure is shown in Figure 6-3. The interrupt controller receives interrupts from USIU internal sources, such as PIT, RTC, from the UIMB module (which has its own interrupt controller) or from the IMB3 bus (directly from IMB modules) and from external pins IRQ[0:7].
Page 249 Levels[0:7] Sequencer ilbs[0:1] USIU Figure 6-3. MPC561/MPC563 Interrupt Structure If programmed to generate an interrupt, the SWT and external pin IRQ0 always generate an NMI, non-maskable interrupt to the RCPU. NOTE The RCPU takes the system reset exception when an NMI is asserted, the external interrupt exception for any other asserted interrupt request, and the decrementer exception when the decrementer MSB changes from 0 to 1.
Page 250 — Level 0 0x0008 00000100 — EXT_IRQ1 0x0010 00001000 — Level 1 0x0018 00001100 — EXT_IRQ2 0x0020 00010000 — Level 2 0x0028 00010100 — EXT_IRQ3 0x0030 00011000 — Level 3 0x0038 00011100 MPC561/MPC563 Reference Manual, Rev. 1.2 6-10 Freescale Semiconductor...
Page 251 MSR[EE] bit (EE = 1). This time should take longer than the time needed for a load of the same register that was just cleared. To guarantee enough time, include this load instruction before the instruction that sets MSR[EE]. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-11...
Page 252 Level 4 0x00C8 01100100 — IMB_IRQ 16 0x00D0 01101000 — IMB_IRQ 17 0x00D8 01101100 — IMB_IRQ 18 0x00E0 01110000 — IMB_IRQ 19 0x00E8 01110100 — EXT_IRQ5 0x00F0 01111000 — Level 5 0x00F8 01111100 MPC561/MPC563 Reference Manual, Rev. 1.2 6-12 Freescale Semiconductor...
Page 253 NOTE When the enhanced interrupt controller is enabled the SIPEND and SIMASK registers are not used. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-13...
Page 254 Section 6.1.4.3, “Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode).” The regular operation is fully compatible with the interrupt controller already implemented in MPC555/MPC556. Figure 6-5 illustrates the interrupt controller functionality in the MPC561/MPC563. MPC561/MPC563 Reference Manual, Rev. 1.2 6-14 Freescale Semiconductor...
Page 255 Priority IRQ[0:7] Encoder (6 from 48) (Enables branch to the highest priority interrupt routine) Enhanced Interrupt Controller Enabled Interrupt Request (to RCPU and IRQOUT pad) Figure 6-5. MPC561/MPC563 Interrupt Controller Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-15...
Page 256 Total: At Least 70-80 Clocks At Least 50-60 Clocks 20 Clocks NOTE Compiler and bus collision overhead are not included in the calculations. MPC561/MPC563 Reference Manual, Rev. 1.2 6-16 Freescale Semiconductor...
Page 257 The monitor counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge within bursts. If the monitor times out, transfer error acknowledge (TEA) is asserted internally by the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-17...
Page 258 System Configuration and Protection MPC561/MPC563, and RCPU access is terminated with a data error, causing a machine check state or exception. The bus monitor timing bit in the system protection control register (SYPCR[BMT]) defines the bus monitor time-out period. The programmability of the time-out allows for variation in system peripheral response time.
Page 259 TB are restricted to special instructions. Separate special-purpose registers are defined in the MPC500 architecture for reading and writing the TB. For the MPC561/MPC563 implementation, it is not possible to read or write the entire TB in a single instruction. Therefore, the mttb and mftb instructions are used to move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the upper half (TBU).
Page 260 Any write to the PITC stops the current countdown, and the count resumes with the new value in PITC. If the PISCR[PTE] bit is not set, the PIT is unable to count and retains the old count value. Reads of the PIT have no effect on the counter value. MPC561/MPC563 Reference Manual, Rev. 1.2 6-20 Freescale Semiconductor...
Page 261 The service sequence clears the watchdog timer and the timing process begins again. If any value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-21...
Page 262 SWSR. If the SWE is loaded with the value zero, the modulus counter does not count (i.e. SWTC is disabled). MPC561/MPC563 Reference Manual, Rev. 1.2 6-22...
Page 263 These timers are capable of generating an interrupt to bring the MCU out of these low-power modes. Memory Map and Register Definitions This section provides the MPC561/MPC563 memory map, register diagrams and bit descriptions of the system configuration and protection registers. 6.2.1 Memory Map The MPC561/MPC563 internal memory space can be assigned to one of eight locations.
Page 264 0xFFFF FFFF Figure 6-11. MPC561/MPC563 Memory Map 6.2.2 System Configuration and Protection Registers This section describes the MPC561/MPC563 registers. 6.2.2.1 System Configuration Registers System configuration registers include the SIUMCR, the IMMR, and the EMCR registers. MPC561/MPC563 Reference Manual, Rev. 1.2...
Page 265 Address write type enable configuration. This bit configures the pins to function as byte write enables or address types for debugging purposes. 0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3] 1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3] MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-25...
Page 266 SIUMCR[BURST_EN] = 1. Do not place code at the last 8 words of a memory controller region while SIUMCR[BURST_EN] = 1. 29:31 — Reserved WE/BE is selected per memory region by WEBS in the appropriate BR register in the memory controller. MPC561/MPC563 Reference Manual, Rev. 1.2 6-26 Freescale Semiconductor...
Page 267 00 (multiple chip, 32-bit port size) DATA[0:15] DATA[16:31] ADDR[8:31] 01 (multiple chip, 16-bit port size DATA[0:15] SPGIOD[16:31] ADDR[8:31] 10 (single-chip with address show SPGIOD[0:15] SPGIOD[16:31] ADDR[8:31] cycles for debugging) 11 (single-chip) SPGIOD[0:15] SPGIOD[16:31] SPGIOA[8:31] MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-27...
Page 268 6.2.2.1.2 Internal Memory Map Register (IMMR) The internal memory map register (IMMR) is a register located within the MPC561/MPC563 special register space. The IMMR contains identification of a specific device as well as the base for the internal memory map. Based on the value read from this register, software can deduce availability and location of any on-chip system resources.
Page 269 It would not change if the part is changed to fix a bug in an existing module. The MPC561 has an ID of 0x35. The MPC563 has an ID of 0x36.
Page 270 Instruction attribute. INST controls the internal bus instruction attribute as follows: 0 Instruction fetch 1 Operand or non-CPU access 23:24 — Reserved RESV Reservation attribute. RESV controls the internal bus reservation attribute as follows: 0 Storage reservation cycle 1 Not a reservation MPC561/MPC563 Reference Manual, Rev. 1.2 6-30 Freescale Semiconductor...
Page 271 Bits Name Description CONT Control attribute. CONT drives the internal bus control bit attribute as follows: 0 Access to MPC561/MPC563 control register, or control cycle access 1 Access to global address map — Reserved TRAC Trace attribute. TRAC controls the internal bus program trace attribute as follows:...
Page 272 SRESET 0000_0000_0000_0000 Addr 0x2F C040 Field IRQ3 LVL3 IRQ4 LVL4 IRQ5 LVL5 IRQ10 IRQ1 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 SRESET 0000_0000_0000_0000 Figure 6-16. SIU Interrupt Pending Register 2 (SIPEND2) MPC561/MPC563 Reference Manual, Rev. 1.2 6-32 Freescale Semiconductor...
Page 273 (SIMASK, SIPEND, SIEL, or SISR). Refer to MSR[EE] bit description in Table 3-11 and the note regarding special handling of the EIC in Section 6.1.4.4, “Enhanced Interrupt Controller Operation.” MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-33...
Page 274 IRQ0 of the SIPEND2 register is not affected by the setting or clearing of the IRQ0 bit of the SIMASK2 register. IRQ0 is a non-maskable interrupt Figure 6-19. SIU Interrupt Mask Register 2 (SIMASK2) MPC561/MPC563 Reference Manual, Rev. 1.2 6-34 Freescale Semiconductor...
Page 275 The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line causes the MPC561/MPC563 to exit low-power mode. Field ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7...
Page 276 Routine4 • • • BASE +1000 • BASE +10 • • • BASE + n • BASE + n • • Figure 6-23. Example of SIVEC Register Usage for Interrupt Table Handling MPC561/MPC563 Reference Manual, Rev. 1.2 6-36 Freescale Semiconductor...
Page 277 The system protection control register (SYPCR) controls the system monitors, the software watchdog period, and the bus monitor timing. This register can be read at any time, but can be written only once after system reset. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-37...
Page 278 The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT time-out, a 0x556C followed by 0xAA39 should be written to this register. The SWSR can be written at any time but returns all zeros when read. MPC561/MPC563 Reference Manual, Rev. 1.2 6-38 Freescale Semiconductor...
Page 279 TEA signal when an instruction fetch was initiated. IBMT Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-out when an instruction fetch was initiated. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-39...
Page 280 The TB is a 64-bit register containing a 64-bit integer that is incremented periodically. There is no automatic initialization of the TB; the system software must perform this initialization. The contents of the MPC561/MPC563 Reference Manual, Rev. 1.2 6-40 Freescale Semiconductor...
Page 281 Field TBREF0 Reset Unaffected Addr 0x2F C204 Figure 6-32. Time Base Reference Register 0 (TBREF0) Field TBREF1 Reset Unaffected Addr 0x2F C208 Figure 6-33. Time Base Reference Register 1 (TBREF1) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-41...
Page 282 More than one status bit can be cleared at a time. This register is locked after reset by default. Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See Section 8.8.3.2, “Keep-Alive Power Registers Lock Mechanism.” MPC561/MPC563 Reference Manual, Rev. 1.2 6-42 Freescale Semiconductor...
Page 283 Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See Section 8.8.3.2, “Keep-Alive Power Registers Lock Mechanism.” Field Reset Unaffected Addr 0x2F C224 Figure 6-36. Real-Time Clock Register (RTC) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-43...
Page 284 PITF PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted. Periodic timer enable 0 PIT stops counting and maintains current value 1 PIT continues to decrement MPC561/MPC563 Reference Manual, Rev. 1.2 6-44 Freescale Semiconductor...
Page 285 Table 6-22. PIT Bit Descriptions Bits Name Description 0:15 Periodic interrupt timing count—This field contains the current count remaining for the periodic timer. Writes have no effect on this field. 16:31 — Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-45...
Page 286 SIU general-purpose I/O Group D[24:31]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOD[24:31]. The direction of SGPIOD[24:31] is controlled by eight dedicated direction control signals SDDRD[24:31]. Each pin in this group can be configured separately as general-purpose input or output. MPC561/MPC563 Reference Manual, Rev. 1.2 6-46 Freescale Semiconductor...
Page 287 SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the [24:31] general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register configures these pins as a group as general-purpose input or output. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 6-47...
Page 288 [24:31] of the corresponding SGPIOD pin [24:31]. Table 6-26 describes the bit values for data direction control. Table 6-26. Data Direction Control SDDR/GDDR Operation SGPIO configured as input SGPIO configured as output MPC561/MPC563 Reference Manual, Rev. 1.2 6-48 Freescale Semiconductor...
Page 289 The PORESET pin should be asserted for a minimum time of 100,000 of clock oscillator cycles after a valid level has been reached on the KAPWR supply. After detecting the assertion of PORESET, the MPC561/MPC563 remains in the power-on reset state until the last of the following two events occurs: MPC561/MPC563 Reference Manual, Rev. 1.2...
Page 290 HRESET only if it occurs while the MPC561/MPC563 is not asserting HRESET. When the MPC561/MPC563 detects assertion of the external HRESET pin or a cause to assert the internal HRESET line is detected, the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer expires (after 512 cycles) the configuration is sampled from data pins (refer to Section 7.5.1, “Hard Reset...
Page 291 Reset use the MPC561/MPC563 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE bit in the PLL, low-power, and reset control register (PLPRCR) is set. The enabled PLL loss of lock event generates an internal hard reset sequence. Refer to Chapter 8, “Clocks and Power...
Page 292 • JTAG Reset Data Coherency During Reset The MPC561/MPC563 supports data coherency and avoids data corruption during reset. If a cycle is executing when any SRESET or HRESET source is detected, then the cycle will either complete or will not start before generating the corresponding reset control signal. There are reset sources, however, when the MPC561/MPC563 generates an internal reset due to special internal situations where this protection is not supported.
Page 293 0 No external soft reset has occurred 1 An external soft reset has occurred LLRS Loss of lock reset status 0 No enabled loss-of-lock reset has occurred 1 An enabled loss-of-lock reset has occurred MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 294 0 No on-chip clock switch reset has occurred 1 An on-chip clock switch reset has occurred ILBC Illegal bit change. This bit is set when the MPC561/MPC563 changes any of the following bits when they are locked: LPM[0:1], locked by the LPML bit...
Page 295 If the PRDS control bit in the PDMCR register is cleared and HRESET and RSTCONF are asserted, the MPC561/MPC563 pulls the data bus low with a weak resistor. The user can overwrite this default by driving the appropriate bit high. See Figure 7-2 for the basic reset configuration scheme.
Page 296 TEXP output function are both required, RSTCONF should be asserted until SRESET is negated. Figure 7-3 Figure 7-6 provide sample reset configuration timings. NOTE Timing diagrams in the following figures are not to scale. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 297 Figure 7-3. Reset Configuration Sampling Scheme for “Short” PORESET Assertion, Limp Mode Disabled CLKOUT (Backup Clock) PORESET Internal PORESET 512 clocks HRESET Tsup RSTCONF Internal data(0:31) Default RSTCONF Controlled Figure 7-4. Reset Configuration Timing for “Short” PORESET Assertion, Limp Mode Enabled MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 298 (maximum rise time - up to 6 clocks) RSTCONF Reset Configuration Word DATA Internal Tsup = Minimum Setup time of reset recognition = 15 clocks reset Sample Data Configuration Sample Data Configuration Figure 7-6. Reset Configuration Sampling Timing Requirements MPC561/MPC563 Reference Manual, Rev. 1.2 7-10 Freescale Semiconductor...
Page 299 OERC — COMP COMP HRESET 0000_0000_0000_0000 Figure 7-7. Reset Configuration Word (RCW) Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563. Table 7-5. RCW Bit Descriptions Bits Name Description EARB External Arbitration — Refer to Section 9.5.7, “Arbitration...
Page 300 The default indicates the exceptions are all non-compressed. See Table 4-4 and <XrefBlue>Appendix A, “MPC562/MPC564 Compression Features." — Reserved. This bit must not be high in the reset configuration word. MPC561/MPC563 Reference Manual, Rev. 1.2 7-12 Freescale Semiconductor...
Page 301 This bit is HC if read from the internal Flash Reset Configuration Word. See Section 21.2.3.1, “Reset Configuration Word (UC3FCFIG)." Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563. 7.5.3 Soft Reset Configuration When a soft reset event occurs, the MPC561/MPC563 reconfigures the development port. Refer to Chapter 23, “Development...
Page 302 Reset MPC561/MPC563 Reference Manual, Rev. 1.2 7-14 Freescale Semiconductor...
Page 303 KAPWR is powered to the same voltage value as the voltage of the I/O buffers and logic. The MPC561/MPC563 clock module consists of the main crystal oscillator, the SPLL, the low-power divider, the clock generator, the system low-power control block, and the limp mode control block. The clock module receives control bits from the system clock control register (SCCR), change of lock interrupt register (COLIR), the PLL low-power and reset-control register (PLPRCR), and the PLL.
Page 304 RCPU and BBC CLKOUT Drivers ENGCLK TMBCLK TMBCLK Driver Backup Clock Oscillator Loss Detector RTC / PIT Clock PITRTCLK and Driver /4 or /256 XTAL Main Clock Oscillator EXTAL Figure 8-1. Clock Unit Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 305 The backup clock on-chip ring oscillator allows the MPC561/MPC563 to function with a less precise clock. When operating from the backup clock, the MPC561/MPC563 is in limp mode. This enables the system to continue minimum functionality until the system is fixed. The BUCLK frequency is approximately 11 MHz for the MPC561/MPC563 (see Appendix F, “Electrical...
Page 306 (PORESET). Once KAPWR is valid, PORESET must be asserted long enough to allow the external oscillator to start up and stabilize for the device to come out of reset in normal (non limp) mode. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 307 PLL circuits. The pin should be provided with an extremely low impedance path to ground. VSSSYN should be bypassed to VDDSYN by a 0.1 µF capacitor located as close as possible to the chip package. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 308 PLL loss of lock. Software can use these timers to measure the loss-of-lock period. If the timer reaches the user-preset software criterion, the MPC561/MPC563 can switch to the backup clock by setting the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode enable (LME) bit in the SCCR is set.
Page 309 The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source and is twice the MPC561/MPC563 system clock. MPC561/MPC563 Reference Manual, Rev. 1.2...
Page 310 With other values of DFNH or DFNL, the duty cycle is less than 50%. Refer to Figure 8-7. GCLK1_50 rises simultaneously with GCLK1. When the MPC561/MPC563 is not in gear mode, the falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines the division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
Page 311 Limp mode disabled. Normal operation, PLL enabled. Main timing reference is crystal osc (4 MHz). Limp mode enabled. Normal operation, PLL enabled. Main timing reference is crystal osc (20 MHz). Limp mode enabled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 312 The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50) are the basic clock supplied to all modules and sub-modules on the MPC561/MPC563. GCLK1C and GCLK2C are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C are stopped when the chip enters the doze-low power mode.
Page 313 Interrupt routines, for example, may require more performance than the low frequency operation provides, but must consume less power than in maximum frequency operation. The MPC561/MPC563 provides a method to automatically switch between low and high frequency operation whenever one of the following conditions exists: •...
Page 314 FREQsysmax = VCOOUT/2 Therefore, the complete equation for determining the system clock frequency is: (MF + 1) OSCCLK System Frequency= DIVF + 1 (2 DNFH ) or (2 DFNL + 1) MPC561/MPC563 Reference Manual, Rev. 1.2 8-12 Freescale Semiconductor...
Page 315 (SCCR)”). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and electromagnetic interference on the printed circuit board. When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low state (provided that BUCS = 0). MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-13...
Page 316 If the chip is in limp mode, clearing the LME bit switches the system to normal operation and asserts hard reset to the chip. Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the status and control for each state. MPC561/MPC563 Reference Manual, Rev. 1.2 8-14 Freescale Semiconductor...
Page 317 When buclk_enable is changed, the chip asserts HRESET to switch the system clock to BUCLK or PLL. At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit (LOCSS) is asserted, and the chip should operate with BUCLK. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-15...
Page 318 NOTE Higher than desired currents during low-power mode can be avoided by executing a mullw instruction before entering the low-power mode, i.e., anytime after reset and prior to entering the low-power mode. MPC561/MPC563 Reference Manual, Rev. 1.2 8-16 Freescale Semiconductor...
Page 319 Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt generated by the interrupt controller. Any enabled asynchronous interrupt clears the LPM bits but does not change the PLPRCR[CSRC] bit. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-17...
Page 320 The MSR[POW] bit is cleared (power management is disabled). When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asynchronous interrupt status bits are reset, the system returns to normal-low mode. MPC561/MPC563 Reference Manual, Rev. 1.2 8-18 Freescale Semiconductor...
Page 321 (and the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be asserted, and causes an exit from power-down low-power mode. Refer to Section 8.8.3, “Keep-Alive Power” for more information. 8.7.3.5 Low-Power Modes Flow Figure 8-9 shows the flow among the different power modes. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-19...
Page 322 TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS. The switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared. Figure 8-9. Low-Power Modes Flow Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 8-20 Freescale Semiconductor...
Page 323 The power supply inputs VDDH and VFLASH should be connected to the same 5.0-V supply. VDDA can be isolated from VDDH, but should be the same approximate voltage. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-21...
Page 324 VDDF, VSSF VDDF provides internal core voltage to the UC3F Flash module; it should be a nominal 2.6V. VSSF provides an isolated ground for the UC3F Flash module. The MPC561 has no VDDF or VSSF signal. MPC561/MPC563 Reference Manual, Rev. 1.2...
Page 325 SUPPLYMIN SUPPLYMAX See note in the VSRMCR[ZOREG] bit description. SUPPLY SUPPLY IRAMSTBY SUPPLY Figure 8-10. IRAMSTBY Regulator Circuit 8.8.2.11 VSS provides the ground reference for the MPC561/MPC563. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-23...
Page 326 SW1 and SW2 can be unified in only one switch if VDDSYN and VDD/NVDDL/QVDDL are supplied by the same source. MPC561/MPC563 Reference Manual, Rev. 1.2 8-24 Freescale Semiconductor...
Page 327 If power-down mode is not entered before power disconnect, there is a chance of data loss in these registers. To minimize the possibility of data loss, the MPC561/MPC563 includes a key mechanism that ensures data retention as long as a register is locked. While a register is locked, writes to this register are ignored.
Page 328 System Clock Control Key (SCCRK) Table 8-9 for bit descriptions. 0x2F C284 PLL Low-Power and Reset-Control 0x2F C384 PLL Low-Power and Reset-Control Register (PLPRCR) Register Key (PLPRCRK) Table 8-11 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 8-26 Freescale Semiconductor...
Page 329 Figure 8-14 Figure 8-15 detail the power-up sequencing for MPC561/MPC563 during normal operation. Note that for each of the conditions detailing the voltage relationships the absolute bounds of the minimum and maximum voltage supply cannot be violated; that is, the value of VDDL cannot fall below 2.5 V or exceed 2.7 V, and the value of VDDH cannot fall below 4.75 V or exceed 5.25 V for normal...
Page 330 If the turn-off voltage of the power supply chip is greater than 0.74 V for the 2.6-V supply and greater than 0.8 V for the 5-V supply, then the circuitry inside the MPC561/MPC563 will act as a load to the respective supply and will discharge the supply line down to these values.
Page 331 VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561. Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
Page 332 CLKOUT pin is not connected to external circuits, set both bits (disabling CLKOUT) to minimize noise and power dissipation. The default value for COM[1] is determined by the BDRV bit in the reset configuration word. See Table 7-5. For CLKOUT control see Table 8-10. MPC561/MPC563 Reference Manual, Rev. 1.2 8-30 Freescale Semiconductor...
Page 333 1 Switches to high frequency (defined by DFNH) when the power management bit in the MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt controller MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-31...
Page 334 111111). These bits can be read and written at any time. They are not affected by hard reset but are cleared during power-on reset. NOTE: If the engineering clock division factor is not a power of two, synchronization between the system and ENGCLK is not guaranteed. MPC561/MPC563 Reference Manual, Rev. 1.2 8-32 Freescale Semiconductor...
Page 335 Clock Output Disabled, Bus pins full drive Clock Output Disabled, Bus pins reduced drive 8.11.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep-alive power supply. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-33...
Page 336 0 No loss of oscillator has been detected 1 Loss of oscillator has been detected SPLS System PLL lock status bit 0 SPLL is currently not locked 1 SPLL is currently locked MPC561/MPC563 Reference Manual, Rev. 1.2 8-34 Freescale Semiconductor...
Page 337 This bit is writable once after soft reset. 0 No reset will occur when checkstop is asserted 1 Reset will occur when checkstop is asserted MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-35...
Page 338 It contains the interrupt request level and the interrupt status bit. This register is readable and writable at any time. A status bit is cleared by writing a one (writing a zero does not affect a status bit’s value). The COLIR is mapped into the MPC561/MPC563 USIU register map. Field...
Page 339 1 Internal IRAMSTBY zener regulator has gone out of regulation. Note: ZOREG may get set inadvertently if IRAMSTBY is not supplied with at least 150µA. 8:15 — Reserved Removed on all parts that have the ZOREG bit. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 8-37...
Page 340 Clocks and Power Control ZOREG is not in Rev 0 of the MPC561 but is in all later revisions. It is not in Rev 0 or 0A of the MPC563, but is in Rev A and later revisions. MPC561/MPC563 Reference Manual, Rev. 1.2...
Page 341 • Bus is synchronous (all signals are referenced to rising edge of bus clock) • Bus can operate at the same frequency as the internal RCPU core of MPC561/MPC563 or half the frequency. Bus Transfer Signals The bus transfers information between the MPC561/MPC563 and external memory of a peripheral device.
Page 342 Bus cycles can be completed in two clock cycles. For all inputs, the MPC561/MPC563 latches the level of the input during a sample window around the rising edge of the clock signal. This window is illustrated in...
Page 343 Cycle Termination Arbitration RETRY Figure 9-2. MPC561/MPC563 Bus Signals Bus Interface Signal Descriptions Table 9-1 describes each signal in the bus interface unit. More detailed descriptions can be found in subsequent subsections. The buses are described in big endian manner, which means that bit 0 is the most significant bit in a bus (MSB), and bit 31 is the least significant bit (LSB).
Page 344 Driven low indicates that a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. The MPC561/MPC563 does not support burst accesses to internal slaves. Driven by the MPC561/MPC563 along with the address when it owns the external bus.
Page 345 Pins Active Description Driven by the MPC561/MPC563 when it owns the external bus. It is part of the burst protocol. When BDIP is asserted, the second beat in front of the current one is requested by the master. This signal is...
Page 346 Byte Lane DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31] Driven by the MPC561/MPC563 when it owns the external bus and it initiated a write transaction to a slave device. For single beat transactions, the byte DATA[0:31] High lanes not selected for the transfer by ADDR[30:31] and TSIZ[0:1] do not supply valid data.
Page 347 When the internal arbiter is enabled, the MPC561/MPC563 asserts this signal to indicate that it is the current owner of the bus. When the internal arbiter is disabled, the...
Page 348 CLKOUT output signal. All signals for the MPC561/MPC563 bus interface are specified with respect to the rising edge of the external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge.
Page 349 3. Assert bus busy (BB) if no other master is driving bus 4. Assert transfer start (TS) 5. Drive address and attributes 1. Receive address 2. Return data 3. Assert transfer acknowledge (TA) Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 350 Receive bus grant and bus busy negated Assert BB, drive address and assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST, BDIP Data Data is valid Figure 9-5. Single Beat Read Cycle – Basic Timing – Zero Wait States MPC561/MPC563 Reference Manual, Rev. 1.2 9-10 Freescale Semiconductor...
Page 351 The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-11...
Page 352 4. Assert transfer start (TS) 5. Drive address and attributes 1. Drive data 1. Assert transfer acknowledge (TA) 1. Interrupt data driving Figure 9-7. Basic Flow Diagram of a Single Beat Write Cycle MPC561/MPC563 Reference Manual, Rev. 1.2 9-12 Freescale Semiconductor...
Page 353 Receive bus grant and bus busy negated Assert BB, drive address and assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST, BDIP Data Data is sampled by slave Figure 9-8. Single Beat Basic Write Cycle Timing – Zero Wait States MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-13...
Page 354 In this case, the MPC561/MPC563 attempts to initiate a transfer as in the normal case. If the bus interface receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through the internal memory controller), the MCU initiates successive transactions until the completion of the data transfer.
Page 355 Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories while the MPC561/MPC563 data bus pads are optimized to 2.6-V memories, and cannot tolerate more than 3.1 V. When connecting 3.3-V devices to the E-bus, and performing read and write operations, this mode should be invoked in order to avoid long term reliability issues of the data pads.
Page 356 When external devices can charge the data bus to a higher voltage level than 3.1 volts • And when one or more of the following occurs: — The MPC561/MPC563 uses write accesses to any external memory — Data show cycles are enabled — Instruction show cycles are enabled in code compression mode (MPC562/MPC564 only)
Page 357 9.5.4 Burst Transfer The MPC561/MPC563 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight words). A non-wrapping burst access stops accessing the external device when the word address is modulo four/eight. Burst configuration is determined by the value of BURST_EN in the SIUMCR register. See Chapter 5, “Unified System Interface Unit (USIU)
Page 358 In this case, the MPC561/MPC563 attempts to initiate a burst transfer as in the normal case. If the memory controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words.
Page 359 BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the rising edge of the clock. Burst inputs (reads) in the MPC561/MPC563 are used only for instruction cycles. Data load cycles are not supported.
Page 360 Receive Data Drive Last Data BDIP Asserted & Assert TA Return Data Negate Burst Data in Progress (BDIP) Assert Transfer Acknowledge (TA) Drive Last Data BDIP Asserted & Assert TA Receive Data MPC561/MPC563 Reference Manual, Rev. 1.2 9-20 Freescale Semiconductor...
Page 361 Expects Another Data BDIP Data No Data Expected Data Data Data Data is Valid is Valid is Valid is Valid Figure 9-13. Burst-Read Cycle – 32-Bit Port Size – Zero Wait State MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-21...
Page 362 No Data Normal Late Expected Data Data Data Data Data Wait State is Valid is Valid is Valid is Valid Figure 9-14. Burst-Read Cycle – 32-Bit Port Size – One Wait State MPC561/MPC563 Reference Manual, Rev. 1.2 9-22 Freescale Semiconductor...
Page 363 No Data BDIP Expected Data Data Data Data Data is Valid is Valid is Valid is Valid Wait State Figure 9-15. Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-23...
Page 364 External Bus Interface CLKOUT ADDR[8:31] ADDR[28:31] = 0000 RD/WR TSIZ[0:1] BURST BDIP Data[0:15] Figure 9-16. Burst-Read Cycle – 16-Bit Port Size MPC561/MPC563 Reference Manual, Rev. 1.2 9-24 Freescale Semiconductor...
Page 365 Assert Transfer Acknowledge (TA) Drive Data Don’t Sample BDIP Asserted Next Data Sample Data Negate Burst Data in Progress (BDIP) Assert Transfer Acknowledge (TA) Don’t Sample BDIP Asserted Next Data Stop Driving Data MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-25...
Page 366 Data Data Data is Sampled is Sampled is Sampled is Sampled From external master Figure 9-18. Burst-Write Cycle, 32-Bit Port Size, Zero Wait States (Only for External Master Memory Controller Service Support) MPC561/MPC563 Reference Manual, Rev. 1.2 9-26 Freescale Semiconductor...
Page 367 BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a sequence of normal cycles. Figure 9-19. Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-27...
Page 368 External Bus Interface CLKOUT ADDR(0:29) n (n modulo 4 = 1) ADDR[30:31] RD/WR TSIZ[0:1] BURST Expects Another Data BDIP Data Figure 9-20. Non-Wrap Burst with Three Beats MPC561/MPC563 Reference Manual, Rev. 1.2 9-28 Freescale Semiconductor...
Page 369 Sampled Figure 9-21. Non-Wrap Burst with One Data Beat 9.5.6 Alignment and Packaging of Transfers The MPC561/MPC563 external bus requires natural address alignment: • Byte accesses allow any address alignment • Half-word accesses require address bit 31 to equal zero MPC561/MPC563 Reference Manual, Rev.
Page 370 A 32-bit port resides on DATA[0:31], a 16-bit port must reside on DATA[0:15], and an 8-bit port must reside on DATA[0:7]. The MPC561/MPC563 always tries to transfer the maximum amount of data on all bus cycles. For a word operation, it always assumes that the port is 32 bits wide when beginning the bus cycle.
Page 371 — — — — — — — — — — — — — — — Half-word — — — — Word Note: “—” denotes a byte not required during that read cycle. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-31...
Page 372 Arbitration Phase The external bus design provides for a single bus master at any one time, either the MPC561/MPC563 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus.
Page 373 BR or kept asserted for the current master to park the bus. When configured for external central arbitration, BG is an input signal to the MPC561/MPC563 from the external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master.
Page 374 BB line negated, regardless of how many cycles have passed since the previous master relinquished the bus. Refer to Figure 9-25. Master External Bus MPC500 Device (Slave 1) Slave 2 Figure 9-25. Master Signals Basic Connection MPC561/MPC563 Reference Manual, Rev. 1.2 9-34 Freescale Semiconductor...
Page 375 9.5.7.4 Internal Bus Arbiter The MPC561/MPC563 can be configured at system reset to use the internal bus arbiter. In this case, the MPC561/MPC563 will be parked on the bus. The parking feature allows the MPC561/MPC563 to skip the bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from the arbiter.
Page 376 BG = 1 BB = 0 External Device With Higher MPC500 Device Priority than the Current Internal Still Needs Bus Master Requests the Bus the Bus Figure 9-27. Internal Bus Arbitration State Machine MPC561/MPC563 Reference Manual, Rev. 1.2 9-36 Freescale Semiconductor...
Page 377 The address bus consists of 32 bits, with ADDR0 the most significant bit and ADDR31 the least significant bit. Only 24 bits (ADDR[8:31]) are available external to the MPC561/MPC563. The bus is byte-addressable, so each address can address one or more bytes. The address and its attributes are driven on the bus with the transfer start signal and kept valid until the bus master receives the transfer acknowledge signal from the slave.
Page 378 Section 9.5.14, “Show Cycle Transactions” for information on show cycles. Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the definitions achieved by combining these pins. MPC561/MPC563 Reference Manual, Rev. 1.2 9-38 Freescale Semiconductor...
Page 379 External Bus Interface Table 9-7. Address Type Pins Function 0 Special transfer 1 Normal transfer 0 Start of transfer 1 No transfer Must equal zero on MPC561/MPC563 0 Supervisor mode 1 User mode 0 Instruction 1 Data Reservation/Program Trace 0 Program trace...
Page 380 Refer to Figure 9-28 Figure 9-29. MPC561/MPC563 Reference Manual, Rev. 1.2 9-40 Freescale Semiconductor...
Page 381 Slave 1 Slave 2 negates acknowledge allowed to drive negates acknowledge allowed to drive acknowledge signals signals and turns off acknowledge signals signals and turns off Figure 9-29. Termination Signals Protocol Timing Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-41...
Page 382 Reservation occurs when a master loads data from memory. The memory location must not be overwritten until the master finishes processing the data and writing the results back to the reserved location. The MPC561/MPC563 storage reservation protocol supports a multi-level bus structure. For each local bus, storage reservation is handled by the local reservation logic.
Page 383 CLKOUT Figure 9-30. Reservation on Local Bus The MPC561/MPC563 samples the CR line at the rising edge of CLKOUT. When this signal is asserted, the reservation flag is reset (negated). The external bus interface (EBI) samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the RCPU stwcx instruction.
Page 384 The flag is reset (negated) when an alternative master on the remote bus accesses the same location in a write cycle. If the MPC561/MPC563 begins a memory cycle to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the following two cases can occur: •...
Page 385 In the next clock cycle, a normal arbitration procedure occurs again. As shown in the figure, the external master did not use the bus, so the MPC561/MPC563 initiates a new transfer with the same address and attributes as before.
Page 386 External Bus Interface CLKOUT BG (output) Allow External Master to Gain the Bus ADDR[8:31] ADDR ADDR RD/WR TSIZ[0:1] BURST Data RETRY (input) Figure 9-32. Retry Transfer Timing – Internal Arbiter MPC561/MPC563 Reference Manual, Rev. 1.2 9-46 Freescale Semiconductor...
Page 387 Figure 9-33. Retry Transfer Timing – External Arbiter When the MPC561/MPC563 initiates a burst access, the bus interface recognizes the RETRY assertion as a retry termination only if it detects it before the first data beat was acknowledged by the slave device.
Page 388 RETRY signal assertion as a transfer error acknowledge. In the case in which a small port size causes the MPC561/MPC563 to break a bus transaction into several small transactions, terminating any transaction with RETRY causes a transfer error acknowledge. See Section 9.5.2.3, “Single Beat Flow with Small Port...
Page 389: Bus Operation In External Master Modes
MPC561/MPC563 asserts TA, and the external master can proceed with another external master access or relinquish the bus. If an address or data error is detected internally, the MPC561/MPC563 asserts TEA for one clock. TEA should be negated before the second rising edge after it is sampled asserted in order to avoid the detection of an error for the next bus cycle initiated.
Page 390 Address in Internal Memory Map Memory Controller 1. Returns Data Asserts CSx If In Range 1. Asserts Transfer Acknowledge (TA) 1. Receives Data Figure 9-35. Basic Flow of an External Master Read Access MPC561/MPC563 Reference Manual, Rev. 1.2 9-50 Freescale Semiconductor...
Page 391 9-38, and Figure 9-39 describe read and write cycles from an external master accessing internal space in the MPC561/MPC563. NOTE The minimum number of wait states for such access is two clocks. The accesses in these figures are valid for both peripheral mode and slave mode.
Page 392 Assert BB, Drive Address and Assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST BDIP TS (input) Data TA (output) Minimum 2 Wait States Data is valid Figure 9-37. Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States) MPC561/MPC563 Reference Manual, Rev. 1.2 9-52 Freescale Semiconductor...
Page 393: Contention Resolution On External Bus
9.5.13 Contention Resolution on External Bus When the MPC561/MPC563 is in slave mode, external master access to the MPC561/MPC563 internal bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to be executed. The RETRY signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock.
Page 394 Address in Internal Memory Map Memory Controller 1. Returns Data Asserts CSx If In Range 1. Asserts Transfer Acknowledge (TA) 1. Receives Data Figure 9-39. Flow of Retry of External Master Read Access MPC561/MPC563 Reference Manual, Rev. 1.2 9-54 Freescale Semiconductor...
Page 395: Show Cycle Transactions
9.5.14 Show Cycle Transactions Show cycles are representations of RCPU accesses to internal devices of the MPC561/MPC563. These accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have one address phase and one data phase, or just an address phase in the case of instruction show cycles. The cycle can be a write or a read access.
Page 396 — 0 = decompression off mode; — 1 = decompression on mode; • DATA[1:4] = bit pointer Chapter 4, “Burst Buffer Controller 2 Module” and Appendix A, “MPC562/MPC564 Compression Features” for more details about decompression mode. MPC561/MPC563 Reference Manual, Rev. 1.2 9-56 Freescale Semiconductor...
Page 397 • Two clock cycle duration • Address valid for two clock cycles • Data is valid only in the second clock cycle • STS signal only is asserted (no TA or TS) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 9-57...
Page 398 CLKOUT BR (in) BG (out) ADDR[8:31] ADDR1 ADDR2 RD/WR TSIZ[0:1] BURST Data DATA1 DATA2 Read Data Show Cycle Bus Transaction Write Data Show Cycle Bus Transaction Figure 9-42. Data Show Cycle Transaction MPC561/MPC563 Reference Manual, Rev. 1.2 9-58 Freescale Semiconductor...
Page 399: Memory Controller
CS3. CS0 also functions as the global (boot) chip-select for accessing the boot Flash EEPROM. The chip select allows zero to 30 wait states. Figure 10-2 is a block diagram of the MPC561/MPC563 memory controller. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 400 A memory transfer start (MTS) strobe permits one master on a bus to access external memory through the chip selects on another. The memory controller functionality allows MPC561/MPC563-based systems to be built with little or no glue logic. A minimal system using no glue logic is shown in Figure 10-3.
Page 401: Memory Controller Architecture
WE/BE[0:3] WE/BE[0:3] Data [0:31] SRAM Figure 10-3. MPC561/MPC563 Simple System Configuration 10.2 Memory Controller Architecture The memory controller consists of a basic machine that handles the memory access cycle: the general-purpose chip-select machine (GPCM). When any of the internal masters request a new access to external memory, the address of the transfer (with 17 bits having a mask) and the address type (with three bits having a mask) are compared to each one of the valid banks defined in the memory controller.
Page 402: Associated Registers
Defined 32-bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words, or words on word boundaries. The port size is specified by the PS bits in the base register. MPC561/MPC563 Reference Manual, Rev. 1.2 10-4...
Page 403: Write-Protect Configuration
If the memory controller is used to support an external master accessing an external device with bursts, the BDIP input signal is used to indicate to the memory controller when the burst is terminated. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 404: Reduced Data Setup Time
Burst access time of memory Data setup time of CPU Delays 20ns The number of clocks required therefore 2 clocks are required. --------- - 1.11 17.9 This case is illustrated in Figure 10-5. MPC561/MPC563 Reference Manual, Rev. 1.2 10-6 Freescale Semiconductor...
Page 405: Case 2: Short Setup Time
Enabling short setup time requires one clock cycle: Initial access time of memory Data setup time of CPU Delays 53ns --------- - 2.96 1(SST Enable Clock) 3.96 The number of clocks required therefore 4 clocks are 17.9 required. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-7...
Page 406: Summary Of Short Setup Time
Short setup time creates a saving of three clock cycles with a 4-beat burst and can result in even better performance with an 8-beat burst, saving seven clock cycles. MPC561/MPC563 Reference Manual, Rev. 1.2 10-8...
Page 407 No Data Expected Data 1st Data 2nd Data 3rd Data 4th Data Is Valid Is Valid Is Valid Is Valid Figure 10-5. A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-9...
Page 408: Chip-Select Timing
An extra clock cycle is required to enable short set-up time, resulting in a 4-1-1-1 cycle. 10.3 Chip-Select Timing The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface between the MPC561/MPC563 and external SRAM, EPROM, EEPROM, ROM peripherals. When an address and MPC561/MPC563 Reference Manual, Rev. 1.2 10-10 Freescale Semiconductor...
Page 409 TA signal is asserted externally at least two clock cycles before the wait states counter has expired, this assertion terminates the memory cycle. When SETA is cleared, it is forbidden to assert external TA less than two clocks before the wait states counter expires. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-11...
Page 410: Memory Devices Interface Example
Memory Devices Interface Example Figure 10-7 describes the basic connection between the MPC561/MPC563 and a static memory device. In this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines are connected to the respective WE in the memory device where each WE/BE line corresponds to a different data byte.
Page 411: Peripheral Devices Interface Example
Peripheral Devices Interface Example Figure 10-9 illustrates the basic connection between the MPC561/MPC563 and an external peripheral device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W line is connected to the R/W in the peripheral device. The CSx line is the strobe output for the memory access.
Page 412: Relaxed Timing Examples
Strobes (OE and CS) assertion time is delayed one clock relative to address (TRLX bit set effect). • Strobe (CS) is further delayed (half-clock) relative to address due to ACS field being set to 11. MPC561/MPC563 Reference Manual, Rev. 1.2 10-14 Freescale Semiconductor...
Page 413 The total cycle length = three clock cycles, determined as follows: — The basic memory cycle requires two clock cycles. — An extra clock cycle is required due to the effect of TRLX on the strobes. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-15...
Page 414 — The basic memory cycle requires two clock cycles. — Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of the CS and WE strobes. MPC561/MPC563 Reference Manual, Rev. 1.2 10-16 Freescale Semiconductor...
Page 415 The total cycle length is three clock cycles, determined as follows: — The basic memory cycle requires two clock cycles. — One extra clock cycle is required due to the effect of TRLX on the negation of the WE/BE strobes. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-17...
Page 416: Extended Hold Time On Read Accesses
For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the corresponding OR register can be set. In this case any MPC561/MPC563 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access to the same bank.
Page 417 EHTR = 1. An extra clock is inserted between the cycles. For a write cycle following a read, this is true regardless of whether both accesses are to the same region. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-19...
Page 418 Figure 10-16. Consecutive Accesses (Write After Read, EHTR = 1) Figure 10-17 shows consecutive accesses from different banks. Because EHTR = 1 (and the accesses are to different banks), an extra clock cycle is inserted. MPC561/MPC563 Reference Manual, Rev. 1.2 10-20 Freescale Semiconductor...
Page 419 Even though EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case of two consecutive read cycles to the same region, data contention is not a concern.) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-21...
Page 420: Summary Of Gpcm Timing Options
2 + SCY write 1/4 * clock 3/4 * clock 1/2 * clock 2 + SCY write 1/4 * clock 1/2 * clock 3/4 * clock 1/2 * clock 2 + SCY MPC561/MPC563 Reference Manual, Rev. 1.2 10-22 Freescale Semiconductor...
Page 421 The LBDIP/TBDIP function can operate only when the cycle termination is internal, using the number of wait states programmed in one of the ORx registers. The LBDIP/TBDIP function cannot be activated at the same time—results are unknown. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-23...
Page 422: Write And Byte Enable Signals
(as programmed in the DMBR) with the cycle type matching the AT/ATM field in DMBR/DMOR registers, the following occurs: • The internal Flash memory does not respond to that address • The memory controller takes control of the external access MPC561/MPC563 Reference Manual, Rev. 1.2 10-24 Freescale Semiconductor...
Page 423 Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped code or data. One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped region (DMBR[DME] = 1, but BRx[V] = 0). Figure 10-19 illustrates the phenomenon. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-25...
Page 424: Dual Mapping Of An External Flash Region
Dual mapping is not supported for an external master when the memory controller serves the access; in such a case, the MPC561/MPC563 terminates the cycle by asserting TEA. 10.6 Dual Mapping of an External Flash Region The dual mapping feature also enables mapping of external memory to alternative memory regions controlled by the memory controller.
Page 425: Global (Boot) Chip-Select Operation
The global chip select feature is disabled by driving only the BDIS line of the RCW (FLEN, BDIS, DME = 0b010). This is shown in case 3 of Table 10-6. Table 10-5 shows the initial values of the “boot bank” in the memory controller. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-27...
Page 426: Memory Controller External Master Support
If the address of any master is mapped within the internal MPC561/MPC563 address space, the access will be directed to the internal device, and will be ignored by the memory controller. If the address is not mapped internally, but rather mapped to one of the memory...
Page 427 Memory Address Address WE/BE BDIP BDIP Data Data BURST BURST NOTE: The memory controller’s BDIP line is used as a burst_in_progress signal. Figure 10-20. Synchronous External Master Configuration for GPCM-Handled Memory Devices MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-29...
Page 428 Data Figure 10-21. Synchronous External Master Basic Access (GPCM Controlled) NOTE Because the MPC561/MPC563 has only 24 address signals, the eight most significant internal address lines are driven as 0b0000_0000, and so compared in the memory controller’s regions. MPC561/MPC563 Reference Manual, Rev. 1.2...
Page 429: Programming Model
10.9.1 General Memory Controller Programming Notes 1. In the case of an external master that accesses an internal MPC561/MPC563 module (in slave or peripheral mode), if that slave device address also matches one of the memory controller’s regions, the memory controller will not issue any CS for this access, nor will it terminate the cycle. Thus, this practice should be avoided.
Page 430: Memory Controller Status Registers (Mstat)
HRESET(BR[1:3]) Unchanged The reset value is determined by the value on the internal data bus during reset (reset-configuration word). Table 10-9 for reset value. Figure 10-23. Memory Controller Base Registers 0–3 (BR0–BR3) MPC561/MPC563 Reference Manual, Rev. 1.2 10-32 Freescale Semiconductor...
Page 431 External transfer acknowledge 0 TA generated internally by memory controller 1 TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may have no meaning when this bit is set MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-33...
Page 432: Memory Controller Option Registers (Or0-Or3)
1111 It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2 - 1 = 7 [0b111]). Figure 10-24. Memory Controller Option Registers 1–3 (OR0–OR3) MPC561/MPC563 Reference Manual, Rev. 1.2 10-34 Freescale Semiconductor...
Page 433 EHTR Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a read access from the current bank and any MPC561/MPC563 write accesses or read accesses to a different bank. 0 Memory controller generates normal timing 1 Memory controller generates extended hold timing Following a system reset, the EHTR bits are cleared in OR0.
Page 434: Dual-Mapping Base Register (Dmbr)
(along with the address type field) to the address of the address bus to determine whether an address should be dual-mapped by one of the memory banks controlled by the memory controller. These bits are used in conjunction with the AM[11:16] bits in the DMOR. MPC561/MPC563 Reference Manual, Rev. 1.2 10-36 Freescale Semiconductor...
Page 435: Dual-Mapping Option Register (Dmor)
— HRESET 0000_0000_0000_0000 It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2 - 1 = 7 [0b111]). Figure 10-26. Dual-Mapping Option Register (DMOR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 10-37...
Page 436 NOTE: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This means that only data accesses are dual mapped. Refer to the address types definition in Table 9-8. 13:31 — Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 10-38 Freescale Semiconductor...
Page 437: L-Bus To U-Bus Interface (L2U)
Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and 16 Mybtes — Region must start on the specified region size boundary (modulo addressing) — Overlap between regions is allowed • Each of the four regions supports the following attributes: MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-1...
Page 438: L2U Block Diagram
No protection for accesses to the CALRAM module on the L-bus (CALRAM has its own protection options) 11.3 L2U Block Diagram Figure 11-1 shows a block diagram of the L-bus to U-bus interface as implemented in the overall MPC561/MPC563 bus architecture. MPC561/MPC563 Reference Manual, Rev. 1.2 11-2 Freescale Semiconductor...
Page 439: Modes Of Operation
The L2U transfers load/store accesses from the RCPU to the U-bus and the read/write accesses by the U-bus master to the L-bus. In addition to the bus protocol translation, the L2U supports other functions such as show cycles, data memory protection, and MPC500 reservation protocol. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-3...
Page 440: Reset Operation
When it detects an access violation, the L2U generates an exception request to the CPU. A functional diagram of the DMPU is shown in Figure 11-2. MPC561/MPC563 Reference Manual, Rev. 1.2 11-4 Freescale Semiconductor...
Page 441: Functional Description
If the attributes match, the access is permitted. When the access is permitted, a U-bus access may be generated according to the specific attribute of the effective region. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-5...
Page 442: Associated Registers
Region Base Address Register 2 L2U_RBA3 Region Base Address Register 3 L2U_RA0 Region Attribute Register 0 L2U_RA1 Region Attribute Register 1 L2U_RA2 Region Attribute Register 2 L2U_RA3 Region Attribute Register 3 L2U_GRA Global Region Attribute MPC561/MPC563 Reference Manual, Rev. 1.2 11-6 Freescale Semiconductor...
Page 443: L-Bus Memory Access Violations
MPC500 processor (RCPU) is notified of storage reservation loss on a remote bus (U-bus, IMB or external bus) only when it has issued a stwcx cycle to that address. That is, the reservation loss indication comes as part of the stwcx cycle. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-7...
Page 444: Reservation Protocol
Storage reservation is set regardless of the termination status (address or data phase) of the lwarx access. Storage reservation is cleared regardless of the data phase termination status of the stwcx access if the address phase is terminated normally. MPC561/MPC563 Reference Manual, Rev. 1.2 11-8 Freescale Semiconductor...
Page 445: Reserved Location (Bus) And Possible Actions
The L2U module provides support for L-bus show cycles. L-bus show cycles are external visibility cycles that reflect activity on the L-bus that would otherwise not be visible to the external bus. L-bus show cycles are software controlled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-9...
Page 446: Programming Show Cycles
11.7.4 L-Bus Write Show Cycle Flow The L2U performs the following sequence of actions for an L-bus-write show cycle. 1. Arbitrates for the L-bus to prevent any other L-bus cycles from starting MPC561/MPC563 Reference Manual, Rev. 1.2 11-10 Freescale Semiconductor...
Page 447: L-Bus Read Show Cycle Flow
The L2U module does not show cycle any L-bus activity that is aborted. • The L2U module does not access the U-bus if the USIU inhibits show cycle activity on the U-bus. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-11...
Page 448: L2U Programming Model
Region Base Address Register 2 L2U_RBA3 11000 11011 0x0000_3780 SUPR Region Base Address Register 3 L2U_RA0 11001 11000 0x0000_3190 SUPR Region Attribute Register 0 L2U_RA1 11001 11001 0x0000_3390 SUPR Region Attribute Register 1 MPC561/MPC563 Reference Manual, Rev. 1.2 11-12 Freescale Semiconductor...
Page 449: U-Bus Access
All L2U registers are only word accessible (read and write) in peripheral mode. A half-word or byte access in peripheral mode will result in a word transaction. 11.8.3 L2U Module Configuration Register (L2U_MCR) The L2U module configuration register (L2U_MCR) is used to control the L2U module operation. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-13...
Page 450: Region Base Address Registers (L2U_Rbax)
There are four registers (x = 0...3), one for each supported region. Field Reset Undefined Field — Reset Undefined 0000_0000_0000 Addr SPR 792–795 Figure 11-5. L2U Region x Base Address Register (L2U_RBAx) MPC561/MPC563 Reference Manual, Rev. 1.2 11-14 Freescale Semiconductor...
Page 451: Region Attribute Registers (L2U_Rax)
0000_0001_1111 = 128 Kbytes 0000_0011_1111 = 256 Kbytes 0000_0111_1111 = 512 Kbytes 0000_1111_1111 = 1 Mbyte 0001_1111_1111 = 2 Mbytes 0011_1111_1111 = 4 Mbytes 0111_1111_1111 = 8 Mbytes 1111_1111_1111 = 16 Mbytes MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-15...
Page 452: Global Region Attribute Register (L2U_Gra)
ENR1 Enable attribute for region 1 0 Region attribute is off 1 Region attribute is on ENR2 Enable attribute for region 2 0 Region attribute is off 1 Region attribute is on MPC561/MPC563 Reference Manual, Rev. 1.2 11-16 Freescale Semiconductor...
Page 453 10 Supervisor read/write access, user read-only access 11 Supervisor read/write access, user read/write access 22:24 — Reserved Guarded attribute 0 Not guarded from speculative accesses 1 Guarded from speculative accesses 26:31 — Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 11-17...
Page 454 L-Bus to U-Bus Interface (L2U) MPC561/MPC563 Reference Manual, Rev. 1.2 11-18 Freescale Semiconductor...
Page 455: U-Bus To Imb3 Bus Interface (Uimb)
Supports scan control for modules on the IMB3 and on the U-bus NOTE Modules on the IMB3 bus can only be reset by SRESET. Some modules may have a module reset, as well. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 12-1...
Page 456: Uimb Block Diagram
Table 12-1. STOP and HSPEED Bit Functionality STOP HSPEED Functionality IMB3 bus frequency is the same as U-bus frequency. IMB3 bus frequency is half that of the U-bus frequency. IMB3 clock is not generated. MPC561/MPC563 Reference Manual, Rev. 1.2 12-2 Freescale Semiconductor...
Page 457: Interrupt Operation
(one for QSCI1/QSCI2 and another for QSPI). In this case, the QSMCM has two interrupt sources. Each of these two sources can assert the interrupt on any of the 32 levels. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 458 The timing for the scheme and the values of ILBS and the interrupt levels driven onto the IMB3 IRQ lines are shown in Figure 12-5. This scheme causes a maximum latency of four clocks and an average latency of two clocks before the interrupt request can reach the interrupt synchronizer. MPC561/MPC563 Reference Manual, Rev. 1.2 12-4 Freescale Semiconductor...
Page 459 If IMB3 modules drive interrupts on any of the 24 levels (levels eight through 31), they will be latched in UIPEND in the UIMB. If any of the register bits 7 to 31 are set, then bit 7 will be set as well. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 460 UIMB registers. As shown in Figure 1-2, this block begins at offset 0x30 7F80 from the start of the MPC561/MPC563 internal memory map (the last 128-byte sub-block of the UIMB interface memory map). Table 12-5. UIMB Interface Register Map...
Page 461 The UIMB module configuration register (UMCR) is accessible in supervisor mode only. Field STOP IRQMUX HSPEED — HRESET 0000_0000_0000 Addr 0x30 7F80 Field — HRESET 0000_0000_0000_0000 Figure 12-7. UIMB Module Configuration Register (UMCR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 12-7...
Page 462 The UIPEND register is a read-only status register which reflects the state of the 32 interrupt levels. The state of IRQ0 is shown in bit 0, the state of IRQ1 is shown in bit 1 and so on. This register is accessible only in supervisor mode. MPC561/MPC563 Reference Manual, Rev. 1.2 12-8 Freescale Semiconductor...
Page 463 Table 12-7. UIPEND Bit Descriptions Bits Name Description 0:31 LVLx Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt source as UIMB LVLx, where x is the interrupt number. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 12-9...
Page 464 U-Bus to IMB3 Bus Interface (UIMB) MPC561/MPC563 Reference Manual, Rev. 1.2 12-10 Freescale Semiconductor...
Page 465 Chapter 13 QADC64E Legacy Mode Operation The two queued analog-to-digital converter (QADC) modules on MPC561/MPC563 devices are 10-bit, unipolar, successive approximation converters. The modules can be configured to operate in one of two modes, legacy mode (MPC555 compatible) and enhanced mode. This chapter describes how the modules operate in legacy mode, which is the default mode of operation.
Page 466 Key Features and Quick Reference Diagrams This section gives an overview of the implementation of the two QADC64E modules on MPC561/MPC563. It can also be used as a quick reference guide while programming the modules. 13.2.1 Features of the QADC64E Legacy Mode Operation •...
Page 467 64 16-bit entries are the CCW table, and 64 16-bit entries are the result table, and occupy 192 16-bit address locations because the result data is readable in three data alignment formats. Each QADC64E module on the MPC561/MPC563 has its own memory space. Table 13-1 shows the memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF.
Page 468 Legacy and Enhanced Modes of Operation The QADC64E modules can be configured to operate in legacy or enhanced mode. Legacy mode is the default state out of reset. Configuring bits in the QADC64E module configuration register enables MPC561/MPC563 Reference Manual, Rev. 1.2 13-4 Freescale Semiconductor...
Page 469 The QADC can use from one to four 8-input external multiplexer chips to expand the number of analog signals that may be converted. The externally multiplexed channels are automatically selected from the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-5...
Page 470 Figure 13-3. Example of External Multiplexing In the external multiplexed mode, four of the port B signals are redefined to each represent eight input channels. Refer to Table 13-3 for more information. MPC561/MPC563 Reference Manual, Rev. 1.2 13-6 Freescale Semiconductor...
Page 471 • Control register 1 (QACR1) is associated with queue 1 (Section 13.3.6, “Control Register 1 (QACR1)”) • Control register 2 (QACR2) is associated with queue 2 (Section 13.3.7, “Control Register 2 (QACR2)”) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-7...
Page 472 (default) or enhanced mode. This bit can only be written when the LOCK is set (unlocked). Refer to Section 13.3.1.3, “Switching Between Legacy and Enhanced Modes of Operation,” for more information. 0 = Legacy mode enabled 1 = Enhanced mode enabled MPC561/MPC563 Reference Manual, Rev. 1.2 13-8 Freescale Semiconductor...
Page 473 Depending on when the FREEZE signal is asserted, there are three possible queue "freeze" scenarios: • When a queue is not executing, the QADC64E freezes immediately • When a queue is executing, the QADC64E completes the conversion in progress and then freezes MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-9...
Page 474 Supervisor/Unrestricted Address Space The QADC64E memory map is divided into two segments: supervisor-only data space and assignable data space. Access to supervisor-only data space is permitted only when the software is operating in supervisor MPC561/MPC563 Reference Manual, Rev. 1.2 13-10 Freescale Semiconductor...
Page 475 The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the IMB3. For privilege violations, refer to the Chapter 9, “External Bus Interface” to determine the consequence of a bus error cycle termination. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-11...
Page 476 Figure 13-6 displays the interrupt levels on IRQ with ILBS. Refer to Chapter 12, “U-Bus to IMB3 Bus Interface (UIMB),” for more information. MPC561/MPC563 Reference Manual, Rev. 1.2 13-12 Freescale Semiconductor...
Page 477 Unaffected Addr (PORTQA) 0x30 4806 ; 0x30 4C06 (PORTQB) 0x30 4807, 0x30 4C07 ANALOG CHANNEL: AN2 AN1 MULTIPLEXED ADDRESS OUTPUTS: MA2 MA1 MA0 Figure 13-7. Port x Data Register (PORTQA and PORTQB) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-13...
Page 478 Control Register 0 is used to define whether external multiplexing is enabled, assign external triggers to the conversion queues and to sets up the QCLK prescaler parameter field. All of the implemented control MPC561/MPC563 Reference Manual, Rev. 1.2 13-14 Freescale Semiconductor...
Page 479 1 represents the high time in IMB3 clocks Note that this bit location is maintained for software compatibility with previous versions of the QADC64E. It serves no functional benefit in the MPC561/MPC563 and is not operational. 13:15 Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value...
Page 480 Interval timer single-scan mode: time = QCLK period x 2 00110 Interval timer single-scan mode: time = QCLK period x 2 00111 Interval timer single-scan mode: time = QCLK period x 2 MPC561/MPC563 Reference Manual, Rev. 1.2 13-16 Freescale Semiconductor...
Page 481 SSE2 bit, which is readable only when the test mode is enabled. Most of the bits are typically written once when the software initializes the QADC64E, and not changed afterwards. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-17...
Page 482 RESUME 0 After suspension, begin executing with the first CCW in queue 2 or the current sub-queue 1 After suspension, begin executing with the aborted CCW in queue 2 MPC561/MPC563 Reference Manual, Rev. 1.2 13-18 Freescale Semiconductor...
Page 483 Interval timer single-scan mode: time = QCLK period x 2 01001 Interval timer single-scan mode: time = QCLK period x 2 01010 Interval timer single-scan mode: time = QCLK period x 2 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-19...
Page 484 The status registers contains information about the state of each queue and the current A/D conversion. Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger overrun bits (TOR1 and TOR2), MPC561/MPC563 Reference Manual, Rev. 1.2 13-20...
Page 485 QADC64E is finished with a queue 1 scan. The software acknowledges that it has detected the completion flag being set by writing a zero to the completion flag after the bit was read as a one. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-21...
Page 486 QADC64E is finished with a queue 2 scan. The software acknowledges that it has detected the completion flag being set by writing a zero to the completion flag after the bit was read as a one. MPC561/MPC563 Reference Manual, Rev. 1.2 13-22 Freescale Semiconductor...
Page 487 0 No unexpected queue 1 trigger events have occurred 1 At least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an end-of-queue condition for the second time in gated mode) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-23...
Page 488 During the stop mode, the CWP is reset to zero, since the control registers and the analog logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the last executed CCW. MPC561/MPC563 Reference Manual, Rev. 1.2 13-24 Freescale Semiconductor...
Page 489 The idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in a valid queue operating mode awaiting a trigger event to initiate queue execution. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 490 The queue status field is affected by the stop mode. Because all of the analog logic and control registers are reset, the queue status field is reset to queue 1 idle, queue 2 idle. MPC561/MPC563 Reference Manual, Rev. 1.2 13-26...
Page 491 CCW word are read/write data, where they may be written when the software initializes the QADC64E. The remaining 6-bits are unimplemented so these read as zeros, and write MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-27...
Page 492 A “trigger event” is used to refer to any of the ways to cause the QADC64E to begin executing the CCWs in a queue or sub-queue. An “external trigger” is only one of the possible “trigger events.” MPC561/MPC563 Reference Manual, Rev. 1.2 13-28 Freescale Semiconductor...
Page 493 2 CCW entry. The RESUME bit in QACR2 allows the software to select where queue 2 begins after suspension. By choosing to re-execute all of the suspended queue 2 queue and MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-29...
Page 494 Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and subsequently changes the timing. Refer to Section 13.4.1.2, “Amplifier Bypass Mode Conversion Timing,” for more information. 0 Amplifier bypass mode disabled. 1 Amplifier bypass mode enabled. MPC561/MPC563 Reference Manual, Rev. 1.2 13-30 Freescale Semiconductor...
Page 495 PQB6 AN50 — 110010 PQB7 AN51 — 110011 PQA0 AN52 — 110100 PQA1 AN53 — 110101 PQA2 AN54 — 110110 PQA3 AN55 — 110111 PQA4 AN56 — 111000 PQA5 AN57 — 111001 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-31...
Page 496 The result word table is a RAM, 64 words long and 10 bits wide. An entry is written by the QADC64E after completing an analog conversion specified by the corresponding CCW table entry. Software can read MPC561/MPC563 Reference Manual, Rev. 1.2 13-32...
Page 497 Write operations to the table may occur during test or debug breakpoint operation. When locations in the CCW table are not used by an application, software could use the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 498 (4 BIT) RDAC (7 BIT) 4 (one is offset) CHAN State Mach, SAR and SAR Buffer CCW Buffer Result WCCW EOS/EOC Data Bus Standard Converter Interface Figure 13-20. QADC64E Analog Subsystem Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 13-34 Freescale Semiconductor...
Page 499 QADC64E need to be considered, since the benefits of the sample amplifier are not present. NOTE Because of internal RC time constants, a sample time of two QCLKs in bypass mode for high frequency operation is not recommended. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-35...
Page 500 Resolution begins with the most significant bit (MSB) and works down to the least significant bit (LSB). The switching sequence is controlled by the comparator and successive-approximation register (SAR) logic. • Sample capacitor — The sample capacitor is employed to sample and hold the voltage to be converted. MPC561/MPC563 Reference Manual, Rev. 1.2 13-36 Freescale Semiconductor...
Page 501 (control registers 1 and 2). Once a queue has been started by a trigger event (any of the ways to cause the QADC64E to begin executing the CCWs in a queue or sub-queue), the QADC64E performs a sequence of conversions and places the results in the result word table. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-37...
Page 502 CCW format and an example of using pause to create sub-queues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue. MPC561/MPC563 Reference Manual, Rev. 1.2 13-38 Freescale Semiconductor...
Page 503 Trigger events which occur during the execution of a sub-queue are ignored, except that the trigger overrun flag is set. When a continuous-scan mode is selected, a trigger event occurring after the completion of the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 504 Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW MPC561/MPC563 Reference Manual, Rev. 1.2 13-40 Freescale Semiconductor...
Page 505 Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not active. It functions the same as disabled mode. CAUTION Do not use a reserved mode. Unspecified operations may result. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-41...
Page 506 Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is MPC561/MPC563 Reference Manual, Rev. 1.2 13-42...
Page 507 If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set. Software can read the CWPQ1 to MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 508 By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, the following software initiated modes can be selected: • Software initiated continuous-scan mode MPC561/MPC563 Reference Manual, Rev. 1.2 13-44 Freescale Semiconductor...
Page 509 The software initiated continuous-scan mode may be chosen for either queue, but is normally used only with queue 2. When the software initiated continuous-scan mode is chosen for queue 1, that queue operates MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 510 The queue will continue to execute until the gate closes or the mode is disabled. MPC561/MPC563 Reference Manual, Rev. 1.2 13-46 Freescale Semiconductor...
Page 511 For software compatibility with earlier versions of QADC64E, the definition of PSL, PSH, and PSA have been maintained. However, the requirements on minimum time and minimum low time no longer exist. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-47...
Page 512 QACR0, and selects the basic low phase of QCLK with the prescaler clock low time (PSL) field. The combination of the PSH and PSL parameters establishes the frequency of the QCLK. MPC561/MPC563 Reference Manual, Rev. 1.2 13-48...
Page 513 Table 13-21 also show the conversion time calculated for a single conversion in a queue. For other MCU IMB3 clock frequencies and other input sample times, the same calculations can be made. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-49...
Page 514 PSH = 11, QCLK is high for 12 IMB3 clock cycles and with PSL = 7, QCLK is low for 8 IMB3 clock cycles. Finally, example 3 shows that with PSH = 7 and PSL = 7, QCLK alternates between high and low every 8 IMB3 cycles. MPC561/MPC563 Reference Manual, Rev. 1.2 13-50 Freescale Semiconductor...
Page 515 The BIU is designed to act as a slave device on the IMB3. The BIU has the following functions: • Respond with the appropriate bus cycle termination • Supply IMB3 interface timing to all internal module signals MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-51...
Page 516 32-bit accesses. Figure 13-26 shows the three bus cycles which are implemented by the QADC64E. The following paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit accesses. MPC561/MPC563 Reference Manual, Rev. 1.2 13-52 Freescale Semiconductor...
Page 517 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides the lower half of one QADC64E location, and the upper half of the following QADC64E location. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 518 Events that trigger queue 2 execution (external trigger, software initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) MPC561/MPC563 Reference Manual, Rev. 1.2 13-54 Freescale Semiconductor...
Page 519 The trigger overrun error status bit is set, and otherwise, the premature trigger event is ignored. A trigger event that occurs before the servicing of the previous trigger event is completed does not disturb the queue execution in progress. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-55...
Page 520 Figure 13-28. CCW Priority Situation 2 Situation S3 (Figure 13-28) shows that when the pause feature is in use, the trigger overrun error status bit is set the same way, and that queue execution continues unchanged. MPC561/MPC563 Reference Manual, Rev. 1.2 13-56 Freescale Semiconductor...
Page 521 1 execution is not disturbed. Situation S5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in use in either queue. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-57...
Page 522 RESUME=0 IDLE ACTIVE IDLE ACTIVE PAUSE ACTIVE IDLE ACTIVE ACTIVE IDLE SUSPEND 0000 1000 0100 0110 1010 0010 0000 QADC S6 Figure 13-32. CCW Priority Situation 6 MPC561/MPC563 Reference Manual, Rev. 1.2 13-58 Freescale Semiconductor...
Page 523 CCW, not the first CCW in the queue. RESUME=1 PAUSE IDLE ACTIVE ACTIVE ACTIVE IDLE IDLE IDLE ACTIVE SUSPEND ACTIVE 0000 1000 0100 0110 1010 0010 0000 QADC S8 Figure 13-34. CCW Priority Situation 8 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-59...
Page 524 TOR2 TOR2 IDLE IDLE ACTIVE ACTIVE PAUSE SUSPEND IDLE ACTIVE ACTIVE PAUS SUSPEND ACTIVE IDLE 0000 0010 1010 0110 0101 0110 1010 0010 0000 QADC S10 Figure 13-36. CCW Priority Situation 10 MPC561/MPC563 Reference Manual, Rev. 1.2 13-60 Freescale Semiconductor...
Page 525 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished. Situations 12 through 19 (Figure 13-38 Figure 13-45) show examples of all of the freeze situations. FREEZE QADC S12 Figure 13-38. CCW Freeze Situation 12 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-61...
Page 526 Figure 13-40. CCW Freeze Situation 14 (Triggers Ignored) FREEZE T2 T2 T1 T1 QADC S15 Figure 13-41. CCW Freeze Situation 15 (Triggers Ignored) FREEZE QADC S16 Figure 13-42. CCW Freeze Situation 16 MPC561/MPC563 Reference Manual, Rev. 1.2 13-62 Freescale Semiconductor...
Page 527 Q1 begins with CCW0 and ends with CCW3 • CCW0 has pause bit set • CCW1 does not have pause bit set • External trigger rise-edge for Q1 • CCW4 = BQ2 and Q2 is disabled MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-63...
Page 528 When the gate closes and opens again the conversions start with the first CCW in Q1. When the gate closes the active conversion completes before the queue goes idle. When Q1 completes both the CF1 bit sets and the SSE bit clears. MPC561/MPC563 Reference Manual, Rev. 1.2 13-64 Freescale Semiconductor...
Page 529 NOTE At the end of Q1,the completion flag CF1 sets and the queue restarts. Also, note that if the queue starts a second time and completes, the trigger overrun flag TOR1 sets. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-65...
Page 530 Port A and B signals are connected to a digital input synchronizer during reads and may be used as general purpose digital inputs when the applied voltages meet high voltage input (V ) and low voltage input (V requirements. Refer to Appendix F, “Electrical Characteristics,” for more information on voltage requirements. MPC561/MPC563 Reference Manual, Rev. 1.2 13-66 Freescale Semiconductor...
Page 531 QACR0 register by the TRG bit. When TRG=0, ETRIG[1] triggers queue 1 and ETRIG[2] triggers queue 2. When TRG=1, ETRIG[1] triggers queue 2 and ETRIG[2] triggers queue 1. NOTE The ETRIG[2:1] pins on the MPC561/MPC563 are multiplexed with the PCS[7:6] pins. 13.7.3...
Page 532 . This results in a maximum obtainable 10-bit conversion value of 0x3FE. At the bottom of the signal range, V is 15 mV higher than V , resulting in a minimum obtainable 10-bit conversion value of three. MPC561/MPC563 Reference Manual, Rev. 1.2 13-68 Freescale Semiconductor...
Page 533 Care must be taken to not introduce additional sources of noise into the analog circuitry. Common sources of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-69...
Page 534 • Non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground/power points. • Distance for trace runs should be minimized where possible MPC561/MPC563 Reference Manual, Rev. 1.2 13-70 Freescale Semiconductor...
Page 535 (within the practical range of capacitors that still have good high frequency characteristics). This capacitor has two effects: • It helps attenuate any noise that may exist on the input. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-71...
Page 536 The external capacitor is perfect (no leakage, no significant dielectric absorption characteristics, etc.) • All parasitic capacitance associated with the input signal is included in the value of the external capacitor • Inductance is ignored MPC561/MPC563 Reference Manual, Rev. 1.2 13-72 Freescale Semiconductor...
Page 537 QADC64E analog input signal through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC64E analog input channel is displayed. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-73...
Page 538 R FILTER R SOURCE 0.01 µF SOURCE C FILTER C SAMP C PCB QADC64E EXT MUX EX 1 Typical Value 2 RFILTER typically 10KW–20KW Figure 13-53. External Multiplexing of Analog Signal Sources MPC561/MPC563 Reference Manual, Rev. 1.2 13-74 Freescale Semiconductor...
Page 539 A typical input leakage of 200 nA acting through 10 kΩ of external series resistance results in an error of 0.4 count (2.0 mV). If the source impedance is 100 kΩ and a typical leakage of 100 nA is present, an error of two counts (10 mV) is introduced. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-75...
Page 540 Figure 13-55 shows positive stress conditions can activate a similar PNP transistor. STRESS INJN Signal Under STRESS Stress Parasitic Device SELECTED Adjacent signal QADC64E PAR Figure 13-54. Input Signal Subjected to Negative Stress MPC561/MPC563 Reference Manual, Rev. 1.2 13-76 Freescale Semiconductor...
Page 541 QADC64E inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 13-77...
Page 542 QADC64E Legacy Mode Operation MPC561/MPC563 Reference Manual, Rev. 1.2 13-78 Freescale Semiconductor...
Page 543 Chapter 14 QADC64E Enhanced Mode Operation The two queued analog-to-digital converter (QADC) modules on the MPC561/MPC563 devices are 10-bit, unipolar, successive approximation converters. The modules can be configured to operate in one of two modes, legacy mode (for MPC555 compatibility) and enhanced mode. This chapter describes how the module operates in enhanced mode.
Page 544 Key Features and Quick Reference Diagrams This section gives an overview of the implementation of the two QADC64E modules on the MPC561/MPC563. It can also be used for a quick reference while programming the modules. 14.2.1 Features of the QADC64E Enhanced Mode Operation •...
Page 545 64 16-bit entries are the CCW table, and 64 16-bit entries are the result table, and occupy 192 16-bit address locations because the result data is readable in three data alignment formats. Each QADC64E module on MPC561/MPC563 has its own memory space. Table 14-1 shows the memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF.
Page 546 The QADC64E modules can be configured to operate in Legacy or Enhanced mode. Legacy mode is the default state out of reset. The QADC64E modules are configured for Enhanced mode by a series of writes MPC561/MPC563 Reference Manual, Rev. 1.2 14-4...
Page 547 The QADC can use from one to four 8-input external multiplexer chips to expand the number of analog signals that may be converted. The externally multiplexed channels are automatically selected from the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-5...
Page 548 Figure 14-3. Example of External Multiplexing Table 14-3. Multiplexed Analog Input Channels Multiplexed Analog Input Channels ANw (AN44) 0 through 7 ANx (AN45) 8 through 15 ANy (AN46) 16 through 23 ANz (AN47) 24 through 31 MPC561/MPC563 Reference Manual, Rev. 1.2 14-6 Freescale Semiconductor...
Page 549 Each CCW table entry is a 16-bit entry, though only 10 bits are used. The final block of address space belongs to the result word table, which appears in three places in the memory map. Each result word table location holds one 10-bit conversion value. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-7...
Page 550 QADC64E requires some recovery time (T in Appendix F: Electricl Characteristics) to stabilize the analog circuits after the stop enable bit is cleared. MPC561/MPC563 Reference Manual, Rev. 1.2 14-8...
Page 551 The LOCK and FLIP bits of the QADCMCR register control the operating mode of the QADC64E modules. Out of reset, the QADC64E modules are in legacy mode (FLIP = 0) and the LOCK bit is clear, MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 552 Attempts to write unimplemented data space in the unrestricted access mode and SUPV= 1, causes the bus master to assert a bus error condition and no data is written. In all other MPC561/MPC563 Reference Manual, Rev. 1.2 14-10 Freescale Semiconductor...
Page 553 They are typically written once when the software initializes the QADC64E, and not changed afterwards. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-11...
Page 554 IMB3 IRQ [7:0] 31:24 15:8 23:16 Figure 14-6. Interrupt Levels on IRQ with ILBS 14.3.3 Port Data Register QADC64E ports A and B are accessed through two 8-bit port data registers, PORTQA and PORTQB. MPC561/MPC563 Reference Manual, Rev. 1.2 14-12 Freescale Semiconductor...
Page 555 I/O signals. Refer to Appendix F, “Electrical Characteristics,” for more information. Any bit set to one in this register configures the corresponding signal as an output. Any bit cleared to zero in this register MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-13...
Page 556 Typically, they are written once when software initializes the QADC64E and are not changed afterwards. EMUX PRESCALER Field — — SRESET Addr 0x30 480A (QACR0_A); 0x30 4C0A (QACR0_B) Figure 14-9. Control Register 0 (QACR0) MPC561/MPC563 Reference Manual, Rev. 1.2 14-14 Freescale Semiconductor...
Page 557 0000111 0100111 1000111 1100111 0001000 0101000 1001000 1101000 0001001 0101001 1001001 1101001 0001010 0101010 1001010 1101010 0001011 0101011 1001011 1101011 0001100 0101100 1001100 1101100 0001101 0101101 1001101 1101101 0001110 0101110 1001110 1101110 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-15...
Page 558 Most of the bits are typically written once when the software initializes the QADC64E, and not changed afterwards. Field CIE1 PIE1 SSE1 — SRESET 0000_0000_0000_0000 Addr 0x30 480C (QACR1_A); 0x30 4C0C (QACR1_B) Figure 14-10. Control Register 1 (QACR1) MPC561/MPC563 Reference Manual, Rev. 1.2 14-16 Freescale Semiconductor...
Page 559 Interval timer single-scan mode: time = QCLK period x 2 01011 Interval timer single-scan mode: time = QCLK period x 2 01100 Interval timer single-scan mode: time = QCLK period x 2 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-17...
Page 560 QADC64E, and not changed afterwards. Field CIE2 PIE2 SSE2 RESUME SRESET 0_0000 111_1111 Addr 0x30 480E (QACR2_A), 0x30 4C0E (QACR2_B) Figure 14-11. Control Register 2 (QACR2) MPC561/MPC563 Reference Manual, Rev. 1.2 14-18 Freescale Semiconductor...
Page 561 RESUME 0 After suspension, begin executing with the first CCW in queue 2 or the current sub-queue 1 After suspension, begin executing with the aborted CCW in queue 2 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-19...
Page 562 Interval timer single-scan mode: time = QCLK period x 2 01000 Interval timer single-scan mode: time = QCLK period x 2 01001 Interval timer single-scan mode: time = QCLK period x 2 MPC561/MPC563 Reference Manual, Rev. 1.2 14-20 Freescale Semiconductor...
Page 563 CCW1 while queue 1 is converting CCW2, the QADC64E would not recognize a BQ2 end-of-queue condition until queue 1 execution reached CCW1 again, presumably on the next pass through the queue. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-21...
Page 564 QADC64E is finished with a queue 1 scan. The software acknowledges that it has detected the completion flag being set by writing a zero to the completion flag after the bit was read as a one. MPC561/MPC563 Reference Manual, Rev. 1.2 14-22 Freescale Semiconductor...
Page 565 QADC64E is finished with a queue 2 scan. The software acknowledges that it has detected the completion flag being set by writing a zero to the completion flag after the bit was read as a one. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-23...
Page 566 0 No unexpected queue 1 trigger events have occurred 1 At least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an end-of-queue condition for the second time in gated mode) MPC561/MPC563 Reference Manual, Rev. 1.2 14-24 Freescale Semiconductor...
Page 567 During the stop mode, the CWP is reset to zero, since the control registers and the analog logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the last executed CCW. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-25...
Page 568 The idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in a valid queue operating mode awaiting a trigger event to initiate queue execution. MPC561/MPC563 Reference Manual, Rev. 1.2 14-26...
Page 569 The queue status field is affected by the stop mode. Since all of the analog logic and control registers are reset, the queue status field is reset to queue 1 idle, queue 2 idle. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 570 CCW. The ten implemented bits of the CCW word are read/write data, where they may be written when the software MPC561/MPC563 Reference Manual, Rev. 1.2 14-28...
Page 571 The queue operating mode determines what type of trigger event causes queue execution to begin. A “trigger event” is used to refer to any of the ways to cause the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 572 2 execution, the execution of queue 2 is suspended by aborting the execution of the CCW in progress, and the queue 1 execution begins. When queue 1 execution is completed, queue 2 MPC561/MPC563 Reference Manual, Rev. 1.2 14-30 Freescale Semiconductor...
Page 573 Alternate Reference Enabled. Setting REF high in the CCW enables the use of an alternate reference. 0 VRH is used as high reference 1 AltRef signal is used as the high reference MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-31...
Page 574 A_PQB1 AN45 Input/Output 0101101 A_PQB2 AN46 Input/Output 0101110 A_PQB3 AN47 Input/Output 0101111 A_PQB4 AN48 — Input/Output 0110000 A_PQB5 AN47 — Input/Output 0110001 A_PQB6 AN50 — Input/Output 0110010 A_PQB7 AN51 — Input/Output 0110011 MPC561/MPC563 Reference Manual, Rev. 1.2 14-32 Freescale Semiconductor...
Page 575 0100000 to 32 to 41 0101001 — RESERVED — — 0101010 — RESERVED — — 0101011 B_PQB0 AN44 Input/Output 0101100 B_PQB1 AN45 Input/Output 0101101 B_PQB2 AN46 Input/Output 0101110 B_PQB3 AN47 Input/Output 0101111 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-33...
Page 576 Left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower order bits • Left justified, with zeros in the lower order unused bits MPC561/MPC563 Reference Manual, Rev. 1.2 14-34 Freescale Semiconductor...
Page 577 NOTE Some write operations, like bit manipulation, may not operate as expected because the hardware cannot access a true 16-bit value. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-35...
Page 578 Initial sample time is fixed at two QCLK cycles. Final sample time can be two or eight QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles. MPC561/MPC563 Reference Manual, Rev. 1.2 14-36...
Page 579 DAC also converts the following three internal channels: • — Reference voltage high • — Reference voltage low • – V )/2 — Reference voltage The DAC array serves to provide a mechanism for the successive approximation A/D conversion. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-37...
Page 580 (control registers 1 and 2). Once a queue has been started by a trigger event (any of the ways to cause the QADC64E to begin executing the CCWs in a queue or sub-queue), the QADC64E performs a sequence of conversions and places the results in the result word table. MPC561/MPC563 Reference Manual, Rev. 1.2 14-38 Freescale Semiconductor...
Page 581 CCW format and an example of using pause to create sub-queues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-39...
Page 582 A sub-queue cannot be executed a second time before the overall queue execution has been completed. Refer to Section 14.3.7, “Control Register 2” for more information. MPC561/MPC563 Reference Manual, Rev. 1.2 14-40 Freescale Semiconductor...
Page 583 The pause bit is set in CCW5 and the EOQ code is in CCW6 • The pause is set in CCW63 • During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-41...
Page 584 Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not active. It functions the same as disabled mode. WARNING Do not use a reserved mode. Unspecified operations may result. MPC561/MPC563 Reference Manual, Rev. 1.2 14-42 Freescale Semiconductor...
Page 585 Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 586 If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set. Software can read the CWPQ1 to MPC561/MPC563 Reference Manual, Rev. 1.2 14-44...
Page 587 By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, the following software initiated modes can be selected: • Software initiated continuous-scan mode • External trigger continuous-scan mode MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-45...
Page 588 The software initiated continuous-scan mode may be chosen for either queue, but is normally used only with queue 2. When the software initiated continuous-scan mode is chosen for queue 1, that queue operates MPC561/MPC563 Reference Manual, Rev. 1.2 14-46 Freescale Semiconductor...
Page 589 The queue will continue to execute until the gate closes or the mode is disabled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-47...
Page 590 Before using the QADC64E, the software must initialize the prescaler with values that put the QCLK within the specified range. Though most software applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. MPC561/MPC563 Reference Manual, Rev. 1.2 14-48 Freescale Semiconductor...
Page 591 The QADC64E requires that f be at least twice f . Therefore if the value in the PRESCALER SYSCLK QCLK field is set to Zero, the resulting QCLK frequency is calculated to be: QCLK SYSCLK MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-49...
Page 592 When the internal FREEZE line is negated, the timer counter starts counting from the beginning. Refer to Section 14.4.7, “Configuration and Control Using the IMB3 Interface” for more information. MPC561/MPC563 Reference Manual, Rev. 1.2 14-50 Freescale Semiconductor...
Page 593 32-bit accesses. Figure 14-24 shows the three bus cycles which are implemented by the QADC64E. The following paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit accesses. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-51...
Page 594 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides the lower half of one QADC64E location, and the upper half of the following QADC64E location. MPC561/MPC563 Reference Manual, Rev. 1.2 14-52...
Page 595 Events that trigger queue 2 execution (external trigger, software initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-53...
Page 596 The trigger overrun error status bit is set, and otherwise, the premature trigger event is ignored. A trigger event which occurs before the servicing of the previous trigger event is through does not disturb the queue execution in progress. MPC561/MPC563 Reference Manual, Rev. 1.2 14-54 Freescale Semiconductor...
Page 597 Figure 14-26. CCW Priority Situation 2 Situation S3 (Figure 14-26) shows that when the pause feature is in use, the trigger overrun error status bit is set the same way, and that queue execution continues unchanged. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-55...
Page 598 1 execution is not disturbed. Situation S5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in use in either queue. MPC561/MPC563 Reference Manual, Rev. 1.2 14-56 Freescale Semiconductor...
Page 599 RESUME=0 IDLE ACTIVE IDLE ACTIVE PAUSE ACTIVE IDLE ACTIVE ACTIVE IDLE SUSPEND 0000 1000 0100 0110 1010 0010 0000 QADC S6 Figure 14-30. CCW Priority Situation 6 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-57...
Page 600 CCW, not the first CCW in the queue. RESUME=1 PAUSE IDLE ACTIVE ACTIVE ACTIVE IDLE IDLE IDLE ACTIVE SUSPEND ACTIVE 0000 1000 0100 0110 1010 0010 0000 QADC S8 Figure 14-32. CCW Priority Situation 8 MPC561/MPC563 Reference Manual, Rev. 1.2 14-58 Freescale Semiconductor...
Page 601 TOR2 TOR2 IDLE IDLE ACTIVE ACTIVE PAUSE SUSPEND IDLE ACTIVE ACTIVE SUSPEND ACTIVE IDLE PAUSE 0000 0010 1010 0110 0101 0110 1010 0010 0000 QADC S10 Figure 14-34. CCW Priority Situation 10 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-59...
Page 602 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished. Situations 12 through 19 (Figure 14-36 Figure 14-43) show examples of all of the freeze situations. FREEZE QADC S12 Figure 14-36. CCW Freeze Situation 12 MPC561/MPC563 Reference Manual, Rev. 1.2 14-60 Freescale Semiconductor...
Page 603 Figure 14-38. CCW Freeze Situation 14 (TRIGGERS IGNORED) FREEZE T2 T2 T1 T1 QADC S15 Figure 14-39. CCW Freeze Situation 15 (TRIGGERS IGNORED) FREEZE QADC S16 Figure 14-40. CCW Freeze Situation 16 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-61...
Page 604 Q1 begins with CCW0 and ends with CCW3 • CCW0 has pause bit set • CCW1 does not have pause bit set • External trigger rise-edge for Q1 • CCW4 = BQ2 and Q2 is disabled MPC561/MPC563 Reference Manual, Rev. 1.2 14-62 Freescale Semiconductor...
Page 605 When the gate closes and opens again the conversions start with the first CCW in Q1. When the gate closes the active conversion completes before the queue goes idle. When Q1 completes both the CF1 bit sets and the SSE bit clears. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-63...
Page 606 NOTE At the end of Q1,the completion flag CF1 sets and the queue restarts. Also, note that if the queue starts a second time and completes, the trigger overrun flag TOR1 sets. MPC561/MPC563 Reference Manual, Rev. 1.2 14-64 Freescale Semiconductor...
Page 607 Figure 14-1. There are 16 channel signals that can also be used as general-purpose digital input/output signals. With external multiplexing MPC561/MPC563 can support 41 analog inputs. In addition, there are three analog reference signals and two analog submodule power signals, shared by each QADC64E module.
Page 608 ) and of the analog multiplexer inputs. Figure 14-47 is a diagram of the analog input circuitry. SAMPLE 16 CHANNELS RC DAC Comparator QADC64E 16CH SAMPLE AMP Figure 14-47. Equivalent Analog Input Circuitry MPC561/MPC563 Reference Manual, Rev. 1.2 14-66 Freescale Semiconductor...
Page 609 Two important factors influencing performance in analog integrated circuits are supply filtering and grounding. Generally, digital circuits use bypass capacitors on every V signal pair. This applies to analog sub-modules also. The distribution of power and ground is equally important. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-67...
Page 610 Two similar approaches designed to improve or eliminate the problems associated with grounding excess transient currents involve star-point ground systems. One approach is to star-point the different grounds at the power supply origin, thus keeping the ground isolated. Refer to Figure 14-49. MPC561/MPC563 Reference Manual, Rev. 1.2 14-68 Freescale Semiconductor...
Page 611 Separating the reference inputs from the power supply signals allows for additional external filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-69...
Page 612 Figure 14-50 is a simplified model of an input channel. Refer to this model in the following discussion of the interaction between the external circuitry and the circuitry inside the QADC64E. MPC561/MPC563 Reference Manual, Rev. 1.2 14-70 Freescale Semiconductor...
Page 613 QADC64E analog input signal through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC64E analog input channel is displayed. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-71...
Page 614 0.01 µF SOURCE MUXIN FILTER SOURCE FILTER 0.01 µF SOURCE MUXIN FILTER FILTER SOURCE 0.01 µF SOURCE FILTER SAMP C PCB QADC64E EXT MUX EX Figure 14-51. External Multiplexing of Analog Signal Sources MPC561/MPC563 Reference Manual, Rev. 1.2 14-72 Freescale Semiconductor...
Page 615 Table 14-26 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance. The error is listed in terms of 10-bit counts. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-73...
Page 616 PNP transistor. STRESS INJN Signal Under STRESS Stress PARASITIC DEVICE SELECTED Adjacent ANn+1 Signal QADC64E PAR Figure 14-52. Input Signal Subjected to Negative Stress MPC561/MPC563 Reference Manual, Rev. 1.2 14-74 Freescale Semiconductor...
Page 617 QADC64E inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 14-75...
Page 618 QADC64E Enhanced Mode Operation MPC561/MPC563 Reference Manual, Rev. 1.2 14-76 Freescale Semiconductor...
Page 619 Chapter 15 Queued Serial Multi-Channel Module The MPC561/MPC563 contains one queued serial multi-channel module (QSMCM). The QSMCM provides three serial communication interfaces: the queued serial peripheral interface (QSPI) and two serial communications interfaces (SCI/UART). These submodules communicate with the CPU via a common slave bus interface unit (SBIU).
Page 620 Programmable Peripheral Chip-Selects — four pins select up to 16 SPI chips • Wraparound Transfer Mode — for autoscanning of serial A/D (or other) peripherals, with no CPU overhead • Programmable Transfer Length — from 8–16 bits inclusive MPC561/MPC563 Reference Manual, Rev. 1.2 15-2 Freescale Semiconductor...
Page 621 15.2.1 MPC561/MPC563 QSMCM Details The QSMCM module has an identical function to the MPC555. The MUXing of the pins is controlled by the QPAPCS3 bit in the QSMCM pin assignment register (PQSPAR). MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-3...
Page 622 The address offsets shown are from the base address of the QSMCM module. Refer to Figure 1-4 for a diagram of the MPC561/MPC563 internal memory map. Table 15-1. QSMCM Register Map Access...
Page 623 The QSMCM assignable data space segment contains the control and status registers for the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM can be accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries. Word accesses require two consecutive IMB3 bus cycles. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-5...
Page 624 When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only space. For any access from within user mode, the IMB3 address acknowledge (AACK) signal is asserted and a bus error is generated. MPC561/MPC563 Reference Manual, Rev. 1.2 15-6 Freescale Semiconductor...
Page 625 ILQSPI) bits located in the interrupt configuration register (QDSCI_IL and QSPI_IL). This value determines which interrupt signal (IRQB[0:7]) is driven onto the bus during the programmed time slot. Figure 15-3 shows a block diagram of the interrupt hardware. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-7...
Page 626 The QSMCMMCR contains parameters for interfacing to the CPU and the intermodule bus. This register can be modified only when the CPU is in supervisor mode. Field STOP FRZ1 — SUPV — SRESET 00_0000 000_0000 Addr 0x30 5000 Figure 15-4. QSMCM Configuration Register (QSMCMMCR) MPC561/MPC563 Reference Manual, Rev. 1.2 15-8 Freescale Semiconductor...
Page 627 Figure 15-5. QSM2 Dual SCI Interrupt Level Register (QDSCI_IL) Table 15-5. QDSCI_IL Bit Descriptions Bits Name Description — Reserved ILDSCI Interrupt level of Dual SCIs 00000lowest interrupt level request (level 0) 11111highest interrupt level request (level 31) 8:15 — Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-9...
Page 628 DDRQS does not affect SCI pin function. TXDx pins are always outputs, and RXDx pins are always inputs, regardless of whether they are functioning as SCI pins or as PORTQS pins. MPC561/MPC563 Reference Manual, Rev. 1.2 15-10 Freescale Semiconductor...
Page 629 (8-bit). This allows the SCI GPIO pin data to written separately than the QSPI GPIO pin values. This allows either the SCI pins or the QSPI pins to be used independently as GPIO. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-11...
Page 630 QGPI2 RXD2 C_CNRX0 QGPO2 TXD2 C_CNTX0 QGPI1 RXD1 — QGPO1 TXD1 — QGPIO6 — QGPIO5 MOSI — QGPIO4 MISO — QGPIO3 PCS3 — QGPIO2 PCS2 — QGPIO1 PCS1 — QGPIO0 PCS0 — MPC561/MPC563 Reference Manual, Rev. 1.2 15-12 Freescale Semiconductor...
Page 631 All QSPI pins are configured during reset as general-purpose inputs. This register does not affect SCI operation. The TXD1 and TXD2 remain output pinsdedicated to the SCI submodules, and the RXD1and RXD2 pins remain input pins dedicated to the SCI submodules. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-13...
Page 632 The QSPI can perform full duplex three-wire or half duplex two-wire transfers. Several transfer rates, clocking, and interrupt-driven communication options are available. Figure 15-10 is a block diagram of the QSPI. MPC561/MPC563 Reference Manual, Rev. 1.2 15-14 Freescale Semiconductor...
Page 633 An inter-transfer delay of approximately 0.8 to 204 µs (using a 40-MHz IMB3 clock) can be programmed. The default delay is 17 clocks (0.425 µs at 40 MHz). Programmable delay simplifies the interface to devices that require different delays between transfers. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-15...
Page 634 CPU. The memory map can be divided into supervisor-only data space and assignable data space. The address offsets shown are from the base address of the QSMCM module. Refer Figure 1-4 for a diagram of the MPC561/MPC563 internal memory map. Table 15-12. QSPI Register Map Access...
Page 635 Writing a new value to SPCR0 while the QSPI is enableddisrupts operation. Field MSTR WOMQ BITS CPOL CPHA SPBR SRESET 0000 0000_0100 Addr 0x30 5018 Figure 15-11. QSPI Control Register 0 (SPCR0) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-17...
Page 636 × SPBR Refer to Section 15.6.5.2, “Baud Rate Selection” for more information. Table 15-14. Bits Per Transfer Bits[3:0] Bits per Transfer 0000 0001 to 0111 Reserved (defaults to 8) 1000 1001 1010 MPC561/MPC563 Reference Manual, Rev. 1.2 15-18 Freescale Semiconductor...
Page 637 DTL is in the range of 1 to 255. A zero value for DTL causes a delay-after-transfer value of 8192 ÷ f (204.8 µs with a 40-MHz IMB3 clock). Refer to Section 15.6.5.4, “Delay After Transfer for more information. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-19...
Page 638 The CPU has read/write access to SPCR3, but the QSPI has read access only. SPCR3 must be initialized before QSPI operation begins. Writing a new value to SPCR3 while the QSPI is enabled disrupts operation. MPC561/MPC563 Reference Manual, Rev. 1.2 15-20...
Page 639 0000_0000_0000_0000 Addr 0x30 501E (SPSR) See bit descriptions in Table 15-17 SPSR can be accessed as an 8-bit register at location 0x30 501F or 0x30 541F. Figure 15-15. QSPI Status Register (SPSR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-21...
Page 640 RAM. Receive data is information received from a serial device external to the MCU. Transmit data is information stored for transmission to an external device. Command data defines transfer parameters. Figure 15-16 shows RAM organization. MPC561/MPC563 Reference Manual, Rev. 1.2 15-22 Freescale Semiconductor...
Page 641 A maximum of 32 commands can be in the queue. These bytes are assigned an address from 0x00 to 0x1F. Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-23...
Page 642 Table 15-20 identifies the QSPI pins and their functions. Register DDRQS determines whether the pins are designated as input or output. The user must initialize DDRQS for the QSPI to function correctly. MPC561/MPC563 Reference Manual, Rev. 1.2 15-24 Freescale Semiconductor...
Page 643 CPTQP, the internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer address unless the NEWQP value is changed. After each command is executed, ENDQP and CPTQP are MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-25...
Page 644 MODF, and HALTA. When the CPU responds to a QSPI interrupt, the interrupt cause must ascertained by reading the SPSR. Any interrupt that was set may then be cleared by writing to SPSR with a zero in the bit position corresponding to the interrupt source. MPC561/MPC563 Reference Manual, Rev. 1.2 15-26 Freescale Semiconductor...
Page 645 QSPI is enabled for master mode operation. Any data to be transmitted should be written into transmit RAM before the QSPI is enabled. During wraparound operation, data for subsequent transmissions can be written at any time. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-27...
Page 646 Global Registers Initialize PQSPAR, PORTQS, and DDRQS in this Order QSPI Initialization Initialize QSPI Control Registers Initialize QSPI RAM Enable QSPI MSTR = 1 ? Figure 15-18. Flowchart of QSPI Initialization Operation MPC561/MPC563 Reference Manual, Rev. 1.2 15-28 Freescale Semiconductor...
Page 647 Is PCS To SCK Delay Execute Programmed Delay Programmed? Execute Standard Delay Execute Serial Transfer Store Received Data In RAM Using Queue Pointer Address Figure 15-19. Flowchart of QSPI Master Operation (Part 1) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-29...
Page 648 To CPTQP Status Bits Is Continue Bit Asserted? Negate Peripheral Chip Selects Is Delay After Transfer Execute Programmed Delay Asserted? Execute Standard Delay Figure 15-20. Flowchart of QSPI Master Operation (Part 2) MPC561/MPC563 Reference Manual, Rev. 1.2 15-30 Freescale Semiconductor...
Page 649 Is HALT Halt QSPI and Or FREEZE Set HALTA Asserted? Is Interrupt Request Interrupt Enable Bit HMIE Set? Is HALT Or FREEZE Asserted? Figure 15-21. Flowchart of QSPI Master Operation (Part 3) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-31...
Page 650 Asserted? Execute Serial Transfer When SCK Received Store Received Data In RAM Using Queue Pointer Address Write Queue Pointer to CPTQP Status Bits Figure 15-22. Flowchart of QSPI Slave Operation (Part 1) MPC561/MPC563 Reference Manual, Rev. 1.2 15-32 Freescale Semiconductor...
Page 651 Halt QSPI and or FREEZE Set HALTA Asserted? Is Interrupt Request Interrupt Enable Bit HMIE Set? Is HALT Or FREEZE Asserted? QSPI SLV2 FLOW6 Figure 15-23. Flowchart of QSPI Slave Operation (Part 2) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-33...
Page 652 RAM address pointed to by NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM. MPC561/MPC563 Reference Manual, Rev. 1.2 15-34 Freescale Semiconductor...
Page 653 SCK baud rates with a 40-MHz IMB3 clock. Table 15-21. Example SCK Frequencies with a 40-MHz IMB3 Clock Division Ratio SPBR Value Frequency 10.00 MHz 6.67 MHz 5.00 MHz MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-35...
Page 654 A zero value for DTL causes a delay-after-transfer value of 8192 ÷ IMB3 clock frequency (204.8 µs with a 40-MHz IMB3 clock). If DT is zero in a command RAM byte, a standard delay is inserted. Standard Delay after Transfer ------------- f SYS MPC561/MPC563 Reference Manual, Rev. 1.2 15-36 Freescale Semiconductor...
Page 655 15.6.5.7 Optional Enhanced Peripheral Chip Selects The MPC561/MPC563 have an optional on-chip decoder for the peripheral chip selects. It is enabled if any of the PCS[4:7]EN bits are enabled in the PDMCR2 register (see Table 2-6).
Page 656 The QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue after WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, SPE can be cleared. MPC561/MPC563 Reference Manual, Rev. 1.2 15-38 Freescale Semiconductor...
Page 657 SS is negated. SS does not need to go high between transfers as the QSPI transfers data until reaching the end of the queue, whether SS remains low or is toggled between transfers. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 658 PCS0/SS is negated (brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS0/SS is negated before the proper number of bits (according to BITS) is received, the next time the MPC561/MPC563 Reference Manual, Rev. 1.2 15-40...
Page 659 QSPI register SPSR with SPIF asserted, followed by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in wraparound mode even while the QSPI is requesting interrupt service from the CPU. The internal working queue pointer is incremented to the next address and the commands are MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-41...
Page 660 Freescale SCI systems. The DSCI has all of the capabilities of previous SCI systems as well as several significant new features. Figure 15-24 is a block diagram of the SCI transmitter. Figure 15-25 is a block diagram of the SCI receiver. MPC561/MPC563 Reference Manual, Rev. 1.2 15-42 Freescale Semiconductor...
Page 661 7 6 5 4 3 2 1 0 L Parity Generator Transmitter Control Logic SCxSR STATUS Register SCCxR1 CONTROL Register TDRE Internal Data Bus SCI Rx SCI Interrupt Requests Request Figure 15-24. SCI Transmitter Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-43...
Page 662 All Ones Parity Detect Wake-up Logic SCCxR1 CONTROL Register 1 SCxDR RX Buffer (READ-ONLY) SCxSR STATUS Register SCI TX SCI Interrupt Internal Requests Request Data Bus Figure 15-25. SCI Receiver Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 15-44 Freescale Semiconductor...
Page 663 QTPNT. See <XrefBlue>Table 15-32 for bit descriptions. 0x30 502A QSCI1SR QSCI1 Status Register OverRun error flag, queue status flags, QRPNT, and QPEND. See <XrefBlue>Table 15-33 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-45...
Page 664 SCxBR disables the baud rate generator. Baud clock rate is calculated as follows: f SYS SCI Baud Rate ----------------------------- - 32xSCxBR where SCxBR is in the range of 1 to 8191. Refer to Section 15.7.7.3, “Baud Clock,” for more information. MPC561/MPC563 Reference Manual, Rev. 1.2 15-46 Freescale Semiconductor...
Page 665 1 SCI receiver awakened by address mark (last bit set). Transmit interrupt enable 0 SCI TDRE interrupts disabled. 1 SCI TDRE interrupts enabled. TCIE Transmit complete interrupt enable 0 SCI TC interrupts disabled. 1 SCI TC interrupts enabled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-47...
Page 666 Note further that reading either byte of SCxSR causes all 16 bits to be accessed, and any status bits already set in either byte are armed to clear on a subsequent read or write of SCxDR. MPC561/MPC563 Reference Manual, Rev. 1.2 15-48 Freescale Semiconductor...
Page 667 0 SCI receiver did not detect an idle-line condition. 1 SCI receiver detected an idle-line condition. For receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a read of SCRQ[0:15]. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-49...
Page 668 RDRx. The transmit data register (TDRx) is a write-only register that contains data to be transmitted. Data is first written to TDRx, then transferred to the transmit serial shifter, where additional format bits are added before transmission. MPC561/MPC563 Reference Manual, Rev. 1.2 15-50 Freescale Semiconductor...
Page 669 Stop bit One bit-time of logic one that indicates the end of a data frame. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-51...
Page 670 (SCCxR0). The baud rate is derived from the MCU IMB3 clock by a modulus counter. Writing a value of zero to SCxBR[12:0] disables the baud rate generator. The baud rate is calculated as follows: f SYS SCI Baud Rate ----------------------------- - 32xSCxBR Eqn. 15-4 MPC561/MPC563 Reference Manual, Rev. 1.2 15-52 Freescale Semiconductor...
Page 671 Enabling parity affects the number of data bits in a frame, which can in turn affect frame size. Table 15-31 shows possible data and parity formats. Table 15-31. Effect of Parity Checking on Data Size Result 8 data bits 7 data bits, 1 parity bit MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-53...
Page 672 If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and TC are set and TXD is held at logic level one (mark). MPC561/MPC563 Reference Manual, Rev. 1.2 15-54 Freescale Semiconductor...
Page 673 To accomplish this an RT clock, which is 16 times the baud rate, is used to sample each bit. Each bit-time can thus be divided into 16 time periods called RT1–RT16. The receiver MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 674 NF flag in SCxSR is set concurrently with the RDRF flag in SCxSR when the data is transferred to register RDRx. The user must determine if the data received with NF set is valid. Noise on the RXDx pin does not necessarily corrupt all data. MPC561/MPC563 Reference Manual, Rev. 1.2 15-56 Freescale Semiconductor...
Page 675 Although error conditions are detected as bits are received, the noise flag (NF), the parity flag (PF), and the framing error (FE) flag in SCxSR are not set until data is transferred from the serial shifter to the RDRx. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 676 Hardware activates each receiver in a system under certain conditions. Resident software must process address information and enable or disable receiver operation. MPC561/MPC563 Reference Manual, Rev. 1.2 15-58 Freescale Semiconductor...
Page 677 SCI1 serial unit. 15.8.2 Queued SCI1 Status and Control Registers The SCI1 queue uses the following registers: • QSCI1 control register (QSCI1CR, address offset 0x28) • QSCI1 status register (QSCI1SR, address offset 0x2A) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-59...
Page 678 When clear, the SCI1 functions as described in the previous sections and the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with the exception of QTE. 0 Transmit queue is disabled 1 Transmit queue is enabled MPC561/MPC563 Reference Manual, Rev. 1.2 15-60 Freescale Semiconductor...
Page 679 QSCI1SR is read with QTHF set, followed by a write of QTHF to zero. 0 The queue locations SCRQ[0:7] are partially filled with newly received data or is empty 1 The queue locations SCRQ[0:7] are completely full of newly received data MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-61...
Page 680 From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can be specified. 15.8.3 QSCI1 Transmitter Block Diagram The block diagram of the enhancements to the SCI transmitter is shown in Figure 15-33. MPC561/MPC563 Reference Manual, Rev. 1.2 15-62 Freescale Semiconductor...
Page 681 Available transmit wrap function to prevent message breaks for transmits greater than 16. This is achieved by the transmit wrap enable (QTWE) bit. When QTWE is set, the hardware is allowed to MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-63...
Page 682 TC = 1 followed by a write to SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates as originally designed. • When the transmit queue is enabled (QTE = 1), writes to the transmit data register (SC1DR) have no effect. MPC561/MPC563 Reference Manual, Rev. 1.2 15-64 Freescale Semiconductor...
Page 683 Possible Set of QTWE Increment QTPNT Set QTHE QTPNT=1000? Clear QBHE QBHE=0? Set QBHE QTPNT = 1111? QPEND = 1111 QTWE = 1 Clear QTWE & QTHE = 0? Set QTHE, QBHE Clear QTE MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-65...
Page 684 If Finished Transmitting, If Transmitting Greater Then Clear QTE and/or TE Than 8 Data Frames on Wrap Read QBHE=1,Write QBHE=0 Write New Data to SCTQ[8:15] DONE Figure 15-35. Queue Transmit Software Flow MPC561/MPC563 Reference Manual, Rev. 1.2 15-66 Freescale Semiconductor...
Page 685 1111 Data to be transferred SCTQ7 0111 SCTQ8 1000 Available register space SCTQ15 1111 Load QPEND with QTSZ (0) Clear QTWE Reset QTPNT Figure 15-36. Queue Transmit Example for 17 Data Bytes MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-67...
Page 686 Queued Serial Multi-Channel Module 15.8.7 Example SCI Transmit for 25 Data Bytes Figure 15-37 below is an example of a transmission of 25 data frames. MPC561/MPC563 Reference Manual, Rev. 1.2 15-68 Freescale Semiconductor...
Page 687 SCTQ8 1000 1000 0000 0000 1001 1111 SCTQ15 SCTQ15 1111 1111 Load QPEND with QTSZ Clear QTWE Reset QTPNT Write SCTQ8 Clear QBHE Figure 15-37. Queue Transmit Example for 25 Data Frames MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-69...
Page 688 When the queue is enabled, software should ignore the RDRF bit. • When the queue is disabled (QRE = 0), the SCI functions in single buffer receive mode (as originally designed) and RDRF and OR function as previously defined. Locations SCRQ[0:15] can MPC561/MPC563 Reference Manual, Rev. 1.2 15-70 Freescale Semiconductor...
Page 689 (QTHF, QBHF). Data is not lost provided that the receive queue is re-enabled before OR (SC1SR) is set, which occurs when a new data frame is received in the shifter MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 690 (SC1DR) is still full. The data in the shifter that generated the OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost. MPC561/MPC563 Reference Manual, Rev. 1.2 15-72...
Page 691 QRPNT=8 & QBHF Set QOR QRPNT=0 & QTHF Load RX Data to SCRQ[QRPNT], Clear QTHF Increment QRPNT Set QTHF QRPNT = 1000? Clear QBHF QRPNT = 0000? Set QBHF Figure 15-39. Queue Receive Flow MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-73...
Page 692 QBHF = 1? Read Status Register With QBHF = 1 Read SCRQ[8:15] Write QBHF = 0 IDLE = 1? Clear QRE and/or RE To Exit the Queue DONE Figure 15-40. Queue Receive Software Flow MPC561/MPC563 Reference Manual, Rev. 1.2 15-74 Freescale Semiconductor...
Page 693 SCRQ0 SCRQ0 0001 SCRQ7 SCRQ7 0111 0111 SCRQ8 SCRQ8 1000 1000 SCRQ15 SCRQ15 1111 1111 Read SCRQ0 Read SCRQ[8:15] Clear QRE/RE Clear QBHF Figure 15-41. Queue Receive Example for 17 Data Bytes MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 15-75...
Page 694 Queued Serial Multi-Channel Module MPC561/MPC563 Reference Manual, Rev. 1.2 15-76 Freescale Semiconductor...
Page 695 Chapter 16 CAN 2.0B Controller Module The MPC561/MPC563 contains three CAN 2.0B controller modules (TouCAN). Each TouCAN is a communication controller that implements the Controller Area Network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (one Mbit/sec), short distance, priority based protocol that can run over a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires).
Page 696 Support for DeviceNet™ and Smart Distributed System 16.2 External Signals Each TouCAN module interface to the external CAN bus consists of two signals: CNTX0 which transmits serial data, and CNRX0 which receives serial data. MPC561/MPC563 Reference Manual, Rev. 1.2 16-2 Freescale Semiconductor...
Page 697 (Tx) buffer or a receive (Rx) buffer. In addition, to reduce the CPU overhead required for message handling, each message buffer is assigned an interrupt flag bit to indicate that the transmission or reception completed successfully. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-3...
Page 698 Time Stamp Contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the CAN bus. Code Refer to Table 16-2 Table 16-3. MPC561/MPC563 Reference Manual, Rev. 1.2 16-4 Freescale Semiconductor...
Page 699 Data frame to be transmitted only once, unconditionally, and 0b1010 then only as a response to remote frame, always. When a matching remote request frame is detected, the code for such a message buffer is changed to be 0b1110. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-5...
Page 700 Only one serial message buffer is active at a time, and its function depends upon the operation of the TouCAN at that time. These buffers are not accessible or visible to the user. MPC561/MPC563 Reference Manual, Rev. 1.2 16-6 Freescale Semiconductor...
Page 701 Table 16-6 shows mask bit values. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-7...
Page 702 The time quanta clock operates at the S-clock frequency. Table 16-8 provides examples of system clock, CAN bit rate, and S-clock bit timing parameters, and Figure 16-5 shows the relationship between MPC561/MPC563 Reference Manual, Rev. 1.2 16-8 Freescale Semiconductor...
Page 703 PRESDIV Value + 1 (MHz) Frequency (MHz) Time Quanta/Bit (MHz) 10, 20 10, 20 2, 1 8, 16 8, 16 2, 1 0.500 0.500 0.500 0.500 1, 2, 2.5 2, 4, 5 20, 10, 8 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-9...
Page 704 Decrement by one • Avoid decrement when equal to zero • Rx error counter reset to a value between 119 and 127 inclusive, when the TouCAN transitions from error passive to error active MPC561/MPC563 Reference Manual, Rev. 1.2 16-10 Freescale Semiconductor...
Page 705 119 and 127, to enable a return to the error active state. The three basic states and the transition behavior of the CAN controller are shown in Figure 16-6. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-11...
Page 706 TouCAN Reset The TouCAN can be reset in two ways: • Hard reset of the module via SRESET. • Soft reset of the module, using the SOFTRST bit in the module configuration register MPC561/MPC563 Reference Manual, Rev. 1.2 16-12 Freescale Semiconductor...
Page 707 ID to be transmitted into a message buffer and then activating that buffer as an active transmit buffer. Once this is done, the TouCAN performs all additional steps necessary to transmit the message onto the CAN bus. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-13...
Page 708 Reception of Transmitted Frames The TouCAN receives a frame it has transmitted if an empty message buffer with a matching identifier exists. 16.4.4 Receive Process During the receive process, the following events occur: MPC561/MPC563 Reference Manual, Rev. 1.2 16-14 Freescale Semiconductor...
Page 709 Because the received identifier field is always stored in the matching receive message buffer, the contents of the identifier field in a receive message buffer may change if one or more of the ID bits are masked. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 710 If the control/status word of a receive message buffer is read, it should be followed by a read of the control/status word of another buffer, or by a read of the free-running timer, to ensure that the locked buffer is unlocked. MPC561/MPC563 Reference Manual, Rev. 1.2 16-16 Freescale Semiconductor...
Page 711 CAN bus, or until the TouCAN enters the error passive or bus off state. Once one of these conditions exists, the TouCAN waits for the completion of all internal activity. Once this happens, the following events occur: MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-17...
Page 712 WAKEINT bit in the error and status register (ESTAT) to be set. This event generates an interrupt if the WAKEMSK bit in CANMCR is set. Consider the following notes regarding low-power stop mode: MPC561/MPC563 Reference Manual, Rev. 1.2 16-18 Freescale Semiconductor...
Page 713 No Rx/Tx frame in progress • No transfer of Rx/Tx frames to and from a serial message buffer, and no Tx frame awaiting transmission in any message buffer • No CPU access to the TouCAN module MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-19...
Page 714 Furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. Figure 16-7 displays the interrupt levels on IRQ with ILBS. MPC561/MPC563 Reference Manual, Rev. 1.2 16-20 Freescale Semiconductor...
Page 715 “A”, “B” or “C” for the TouCAN_A, TouCAN_B, or TouCAN_C module, respectively. Refer Figure 1-4 to locate each TouCAN module in the MPC561/MPC563 address map. The column labeled “Access” indicates the privilege level at which the CPU must be operating to access the register.
Page 716 0x30 78A0(C) 0x30 70A2(A) Interrupt Masks (IMASK_x) 0x30 74A2(B) Table 16-26 for bit descriptions. 0x30 78A2(C) 0x30 70A4(A) Interrupt Flags (IFLAG_x) 0x30 74A4(B) Table 16-27 for bit descriptions. 0x30 78A4(C) MPC561/MPC563 Reference Manual, Rev. 1.2 16-22 Freescale Semiconductor...
Page 717 0x30 71D0 — 0x30 71DF(A) MBUFF13 0x30 75D0 — 0x30 75DF(B) TouCAN X Message Buffer 13. 0x30 79D0 — 0x30 79DF(C) Figure 16-3 Figure 16-4 for message buffer definitions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-23...
Page 718 , 0x30 790E Reserved 0x30 7110, 0x30 7510 , 0x30 7910 Message Buffers 1 – 15 0x30 71FF, 0x30 75FF , 0x30 79FF TouCAN Message Buffer Map Figure 16-8. TouCAN Message Buffer Memory Map MPC561/MPC563 Reference Manual, Rev. 1.2 16-24 Freescale Semiconductor...
Page 719 1 TouCAN is in low-power stop mode or debug mode. WAKEMSK Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests. 0 Wake up interrupt is disabled 1 Wake up interrupt is enabled MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-25...
Page 720 1 The TouCAN has entered low-power stop mode and its clocks are stopped 12:15 — Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TouCAN implementations that use hardware interrupt arbitration. MPC561/MPC563 Reference Manual, Rev. 1.2 16-26 Freescale Semiconductor...
Page 721 — Reserved 16.7.4 Control Register 0 (CANCTRL0) Field BOFFMSK ERRMSK — RXMODE TXMODE CANCTRL1 SRESET 0000_0000_0000_0000 Addr 0x30 7086 (CANCTRL0_A); 0x30 7486 (CANCTRL0_B); 0x30 7886 (CANCTRL0_C) Figure 16-11. Control Register 0 (CANCTRL0) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-27...
Page 722 (open drain mode forces the polarity to be positive). 16.7.5 Control Register 1 (CANCTRL1) Field CANCTRL0 SAMP — TSYNC LBUF — PROPSEG SRESET 0000_0000_0000_0000 Addr 0x30 7086 (CANCTRL1_A); 0x30 7486 (CANCTRL1_B); 0x30 7886 (CANCTRL1_C) Figure 16-12. Control Register 1 (CANCTRL1) MPC561/MPC563 Reference Manual, Rev. 1.2 16-28 Freescale Semiconductor...
Page 723 1 Time Quantum = 1 Serial Clock (S-Clock) Period 16.7.6 Prescaler Divide Register (PRESDIV) Field PRESDIV CANCTRL2 SRESET 0000_0000_0000_0000 Addr 0x30 7088 (PRESDIV_A); 0x30 7488 (PRESDIV_B); 0x30 7888 (PRESDIV_C) Figure 16-13. Prescaler Divide Register MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-29...
Page 724 The valid programmed values are zero through seven. The length of phase buffer segment two is calculated as follows: Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta MPC561/MPC563 Reference Manual, Rev. 1.2 16-30 Freescale Semiconductor...
Page 725 Addr 0x30 7090 (RxGMSKHI_A); 0x30 7490 (RxGMSKHI_B); 0x30 7890 (RxGMSKHI_C); 0x30 7092 (RxGMSKLO_A); 0x30 7492 (RxGMSKLO_B); 0x30 7892 (RxGMSKLO_C) Field MID SRESET Figure 16-16. Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-31...
Page 726 The IDE bit of a received frame is always compared to determine if the message contains a standard or extended identifier. Its location in the mask registers (bit 12) is always one, regardless of any write to this bit. MPC561/MPC563 Reference Manual, Rev. 1.2 16-32 Freescale Semiconductor...
Page 727 This register reflects various error conditions, general status, and has the enable bits for three of the TouCAN interrupt sources. The reported error conditions are those which have occurred since the last time the register was read. A read clears these bits to zero. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-33...
Page 728 FCS[1:0]. However, as soon as the TouCAN exits reset, FCS[1:0] bits will again reflect the bus off state. Refer to Section 16.3.4, “Error Counters” for more information on entry into and exit from the various fault confinement states. — Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 16-34 Freescale Semiconductor...
Page 729 Error active Error passive Bus off 16.7.13 Interrupt Mask Register (IMASK) Field IMASKH IMASKL SRESET 0000_0000_0000_0000 Addr 0x30 70A2 (IMASK_A); 0x30 74A2 (IMASK_B); 0x30 78A2 (IMASK_C) Figure 16-20. Interrupt Mask Register (IMASK) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-35...
Page 730 Figure 16-22. Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR) Table 16-28. RXECTR, TXECTR Bit Descriptions Bits Name Description 0:7, RXECTR, Both counters are read only, except when the TouCAN is in test or debug mode. 8:15 TXECTR MPC561/MPC563 Reference Manual, Rev. 1.2 16-36 Freescale Semiconductor...
Page 731 CAN 2.0B Controller Module MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 16-37...
Page 732 CAN 2.0B Controller Module MPC561/MPC563 Reference Manual, Rev. 1.2 16-38 Freescale Semiconductor...
Page 733 12 MIOS14 pulse-width modulation submodules (MPWMSM) • One MIOS14 16-bit parallel port I/O submodule (MPIOSM) • Two interrupt request submodules (MIRSM) 17.1 Block Diagram Figure 17-1 is a block diagram of the MIOS14. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-1...
Page 734 MPWM16 Modular I/O Bus (MIOB) (To all submodules) 6xPWMSM PWMSM21 MIRSM0/1 MCPSM MPWM21 Bus Interface Interrupt Counter Unit Submodule Prescaler Submodules MPIO32B0 IMB3 Bus MPIOSM32 MPIO32B15 Figure 17-1. MPC561/MPC563 MIOS14 Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 17-2 Freescale Semiconductor...
Page 735 — Flag setting and possible interrupt generation after MDASM action completion — Software selection of output pulse polarity — Software selection of totem-pole or open-drain output — Software readable output signal status MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-3...
Page 736 A block is a group of four 16-bit registers. Each of the blocks within the MIOS14 addressing range is assigned a block number. The first block is located at the base address of the MIOS14. The blocks are numbered sequentially starting from 0. MPC561/MPC563 Reference Manual, Rev. 1.2 17-4 Freescale Semiconductor...
Page 737 MMCnC and its input load pin named MMCnL. MMC6C is input on MDA11 and MMC22C is input on MDA13. The MMC6L is input on MDA12 and MMC22C is input on MDA14. • MDASM: — submodule short_prefix: “DA” — signal attribute suffix: none MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-5...
Page 738 PWMSM 0x30 PWM, I/O MPWM4 MPWM4 MDO6/ 6020 MPIO32B6 PWMSM 0x30 PWM, I/O MPWM5 MPWM5 MPIO32B7 6028 MMCSM 0x30 Clock In MDA11 6030 Load In MDA12 MMCSM 0x30 Clock In MDA30 6038 MPC561/MPC563 Reference Manual, Rev. 1.2 17-6 Freescale Semiconductor...
Page 739 MPWM MPWM MPIO32B9 60A8 MMCSM CB22 0x30 Clock In MDA13 60B0 Load In MDA14 MMCSM CB23 0x30 Clock In MDA27 60B8 Load In MDA28 MMCSM CB24 0x30 Clock In MPWM MDO6 60C0 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-7...
Page 740 MPIO32 VFLS1 GPIO MPIO32 MPIO32 MDO5 GPIO MPIO32 MPIO32 MPWM4/ MDO6 GPIO MPIO32 MPIO32 MPWM5 GPIO MPIO32 MPIO32 MPWM20 GPIO MPIO32 MPIO32 MPWM21 GPIO MPIO32 MPIO32 PPM_ TSYNC GPIO MPIO32 MPIO32 C_CNRX0 MPC561/MPC563 Reference Manual, Rev. 1.2 17-8 Freescale Semiconductor...
Page 741 The internal bus system within the MIOS14 is called the modular I/O bus (MIOB). The MIOB makes communications possible between any submodule and the IMB3 bus master through the MBISM. The MIOB is divided into three dedicated buses: MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-9...
Page 742 Attempted access to unimplemented 16-bit registers within the decoded register block boundary. • Attempted user access to supervisor registers • Attempted access to test registers when not in test mode • Attempted write to read-only registers MPC561/MPC563 Reference Manual, Rev. 1.2 17-10 Freescale Semiconductor...
Page 743 Modular Input/Output Subsystem (MIOS14) 17.4.2 Wait States The MIOS14 does not generate wait states. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-11...
Page 744 0x30 6C40 MIRSM1 0x30 6C06 Supervisor MIOS14RPR0 Reserved Reserved 0x30 6FFF 0x30 6C30 MIOS1LVL0 Reserved 0x30 6C40 MIOS14SR1 0x30 6C42 Reserved 0x30 6C44 MIOS14ER1 0x30 6C46 MIOS14RPR1 Reserved 0x30 6C70 MIOS14LVL1 Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 17-12 Freescale Semiconductor...
Page 745 MIOS14 Test and Signal Control Register (MIOS14TPCR) This register is used for MIOS14 factory testing and to control the VF and VFLS Signal usage. Control of other multiplexed functions is in the PDMCR2 register. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-13...
Page 746 Field Reset Unaffected Addr 0x30 6804 Figure 17-6. MIOS14 Module/Version Number Register (MIOS14VNR) This field contains the revision level of the MIOS module and may change with different revisions of the device. MPC561/MPC563 Reference Manual, Rev. 1.2 17-14 Freescale Semiconductor...
Page 747 Modular Input/Output Subsystem (MIOS14) Table 17-4. MIOS14VNR Bit Descriptions Bits Name Description Module number = 0x0E on the MPC561/MPC563 8:15 Version number. May change with different revisions of the device. 17.6.1.4 MIOS14 Module Configuration Register (MIOS14MCR) The MIOS14MCR register is a collection of read/write stop, freeze, reset, and supervisor bits, as well as interrupt arbitration number bits.
Page 748 The following sections describe the MCPSM in detail. Dec. Clock 4-bit Prescaler Overflow Counter Clock = 1? Decrementer Register Load Enable MCPSMSCR PREN Figure 17-8. MCPSM Block Diagram 17.7.1 MCPSM Features • Centralized counter clock generator MPC561/MPC563 Reference Manual, Rev. 1.2 17-16 Freescale Semiconductor...
Page 749 The privilege level to access to the MCPSM registers is supervisor only. 17.7.3.1 MCPSM Registers Organization Table 17-6. MCPSM Register Address Map Address Register 0x30 6810 Reserved 0x30 6812 Reserved 0x30 6814 Reserved 0x30 6816 MCPSM Status/Control Register (MCPSMSCR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-17...
Page 750 Binary 0b0000 0b0001 No counter clock output 0b0010 0b0011 0b1110 0b1111 NOTE If the binary value 0b0001 is entered in PSL[3:0], the output signal is stuck at zero, no clock is output. MPC561/MPC563 Reference Manual, Rev. 1.2 17-18 Freescale Semiconductor...
Page 751 The polarity of the external input signal is also programmable. The following sections describe the MMCSM in detail. A block diagram of the MMCSM is shown in Figure 17-10. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-19...
Page 752 Maximum increment frequency of the counter: — clocked by the internal MCPSM output: f — clocked by the external signal: f • Flag setting and possible interrupt generation on overflow of the up-counter register MPC561/MPC563 Reference Manual, Rev. 1.2 17-20 Freescale Semiconductor...
Page 753 • The MMCSM uses the request bus to transmit the FLAG line to the interrupt request submodule (MIRSM). A flag is set when an overflow has occurred in the up-counter register. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-21...
Page 754 0x30 603E MMCSM7 Status/Control Register (MMCSMSCR) MMCSM8 0x30 6040 MMCSM8 Up-Counter Register (MMCSMCNT) 0x30 6042 MMCSM8 Modulus Latch Register (MMCSMML) 0x30 6044 MMCSM8 Status/Control Register Duplicated (MMCSMSCRD) 0x30 6046 MMCSM8 Status/Control Register (MMCSMSCR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-22 Freescale Semiconductor...
Page 755 Counter value — These bits are read/write data bits representing the 16-bit value of the up-counter. It contains the value that is driven onto the 16-bit counter bus. Note: Writing to MMCSMCNT simultaneously writes to MMCSMML. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-23...
Page 756 8-bit read/write data register, as detailed below. Field PINC PINL FREN EDGN EDGP — SRESET Undefined Addr 0x30 6036, 0x30 603E, 0x30 6046, 0x30 60B6, 0x30 60BE, 0x30 60C6 Figure 17-14. MMCSM Status/Control Register (MMCSMSCR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-24 Freescale Semiconductor...
Page 757 MMCSMCNT load on rising and falling edges MMCSMCNT load on falling edges MMCSMCNT load on rising edges None (disabled) Table 17-14. MMCSMCNT Clock Signal Clocking Selected MMCSM clock prescaler Clock signal rising-edge Clock signal falling-edge None (disable) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-25...
Page 758 All control and status bits are contained in the MDASM status and control register. The following sections describe the MDASM in detail. A block diagram of the MDASM is shown in Figure 17-15. MPC561/MPC563 Reference Manual, Rev. 1.2 17-26 Freescale Semiconductor...
Page 759 • Flag setting and possible interrupt generation after MDASM action completion • Software selection of output pulse polarity • Software selection of totem-pole or open-drain output • Software readable output signal status MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-27...
Page 760 (after being Schmitt triggered and synchronized). In the output modes the PIN bit reflects the value present on the output flip-flop. The output flip-flop is used in output modes to hold the logic level applied to the output signal. MPC561/MPC563 Reference Manual, Rev. 1.2 17-28 Freescale Semiconductor...
Page 761 PIN bit in the MDASMSCR register. All control bits remain accessible, allowing the software to prepare for future MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 762 The input pulse width is calculated by subtracting the value in data register B from the value in data register Figure 17-16 provides an example of how the MDASM can be used for input pulse width measurement. MPC561/MPC563 Reference Manual, Rev. 1.2 17-30 Freescale Semiconductor...
Page 763 A is transferred to register B1. This sequence of events is repeated for each subsequent capture. Reading data register B returns the value in register B2. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-31...
Page 764 MDASM functions as a standard input capture function. In this case the value latched in channel B can be ignored. Figure 17-18 provides an example of how the MDASM can be used for input capture. MPC561/MPC563 Reference Manual, Rev. 1.2 17-32 Freescale Semiconductor...
Page 765 The values stored in registers A and B are compared with the count value on the selected 16-bit counter bus when their corresponding comparators are enabled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-33...
Page 766 In this mode, registers A and B2 are accessible to the user software (at consecutive addresses). Figure 17-19 provides an example of how the MDASM can be used to generate a single output pulse. MPC561/MPC563 Reference Manual, Rev. 1.2 17-34 Freescale Semiconductor...
Page 767 In this mode, registers A and B2 are accessible to the user software (at consecutive addresses). Figure 17-20 provides an example of how the MDASM can be used to perform a single output compare. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-35...
Page 768 B2 is compared with the value on the 16-bit counter bus each time the counter bus is updated. When a match occurs on B, the output flip-flop is reset. MPC561/MPC563 Reference Manual, Rev. 1.2 17-36 Freescale Semiconductor...
Page 769 This is controlled by bits MODE2, MODE1and MODE0. The frequency of the PWM output ) is given by the following equation (assuming the MDASM is connected to a 16-bit counter bus used as time reference and f is the frequency of the MIOS14 CLOCK): MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-37...
Page 770 15 (to zero) allows normal comparisons to occur and the normal output waveform is obtained. Changes to and from the 100% duty cycle are done synchronously on an A or B match, as are all other width changes. MPC561/MPC563 Reference Manual, Rev. 1.2 17-38...
Page 771 MDASM11 Data A Register (MDASMAR) Section 17.9.6.2, “MDASM Data A (MDASMAR) Register” for bit descriptions. 0x30 605A MDASM11 Data B Register (MDASMBR) Section 17.9.6.3, “MDASM Data B (MDASMBR) Register” for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-39...
Page 772 0x30 60DA MDASM27 Data B Register (MDASMBR) 0x30 60DC MDASM27 Status/Control Register Duplicated (MDASMSCRD) 0x30 60DE MDASM27 Status/Control Register (MDASMSCR) MDASM28 0x30 60E0 MDASM28 Data A Register (MDASMAR) 0x30 60E2 MDASM28 Data B Register (MDASMBR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-40 Freescale Semiconductor...
Page 773 MDASM Data A (MDASMAR) Register Field SRESET Undefined Addr 0x30 6058, 0x30 6060, 0x30 6068, 0x30 6070, 0x30 6078, 0x30 60D8, 0x30 60E0, 0x30 60E8, 0x30 60F0, 0x30 60F8 Figure 17-22. MDASM Data A Register (MDASMAR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-41...
Page 774 MDASM Data B (MDASMBR) Register Field SRESET Undefined Addr 0x30 605A, 0x30 6062, 0x30 606A, 0x30 6072, 0x30 607A, 0x30 60DA, 0x30 60E2, 0x30 60EA, 0x30 60F2, 0x30 60FA Figure 17-23. MDASM DataB Register (MDASMBR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-42 Freescale Semiconductor...
Page 775 The signal input status bit reflects the status of the corresponding signal when in input mode. When in output mode, the PIN bit only reflects the status of the output flip-flop. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-43...
Page 776 In the DIS, IPWM, IPM and IC modes, the FORCA bit is not used and writing to it has no effect. FORCA is cleared by reset and is always read as zero. Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop. MPC561/MPC563 Reference Manual, Rev. 1.2 17-44 Freescale Semiconductor...
Page 777 OPWM – Output pulse width modulation 1010 OPWM – Output pulse width modulation 1011 OPWM – Output pulse width modulation 1100 OPWM – Output pulse width modulation 1101 OPWM – Output pulse width modulation MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-45...
Page 778 40 MHz). The MWPMSM can run in a double-buffered mode, to avoid spurious update. The following sections describe the MPWMSM in detail. A block diagram of the MPWMSM is shown in Figure 17-25. MPC561/MPC563 Reference Manual, Rev. 1.2 17-46 Freescale Semiconductor...
Page 779 The term “resolution” is used in this document to define the minimum MPWMSM output increment in time units. 17.10.2 MPWMSM Features • Output pulse width modulated (PWM) signal generation with no software intervention • Built-in 8-bit programmable prescaler clocked by the MCPSM MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-47...
Page 780 3.2 µs (312.5 KHz) with six bits of resolution (still assuming a f = 40 MHz and the MCPSM set to divide by two). The MPWMSM is composed of: MPC561/MPC563 Reference Manual, Rev. 1.2 17-48 Freescale Semiconductor...
Page 781 MPWMPERR will be transferred to the counter only when the counter reaches the value of 0x0001 and generates a load signal. Period values of 0x0000, 0x0001, and 0x0002 are MPWMSM special cases: MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-49...
Page 782 The PWM output pulse width can be as wide as one period minus one MPWMSM clock count: (i.e., MPWMPULR2 = MPWMPERR — [one MPWMSM clock count]). At the other end of the pulse width range, MPWMPULR2 can contain 0x0001 to create a pulse width of one PWM clock count. MPC561/MPC563 Reference Manual, Rev. 1.2 17-50 Freescale Semiconductor...
Page 783 When a PWM output period is selected to be 65536 PWM clocks by loading 0x0000 in the period register, it is not possible to have an 100% duty cycle output signal. In this case, the maximum duty cycle available is of 65535/65536. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-51...
Page 784 12.8 µs/512 1.192 2.384 4.768 9.536 19.07 38.14 76.29 152.5 305.1 610.3 1220 2441 4882 9765 19.5K 19.2 µs/768 0.794 1.589 3.178 6.357 12.71 25.43 50.86 101.7 203.4 406.9 813. 1627 3255 6510 13 K MPC561/MPC563 Reference Manual, Rev. 1.2 17-52 Freescale Semiconductor...
Page 785 Section 17.12, “MIOS14 Interrupts,” Section 17.12.1, “MIOS14 Interrupt Structure” and Section 17.12.2, “MIOS14 Interrupt Request Submodule (MIRSM)” for details about interrupts). A set flag pulse is generated at the start of every period. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-53...
Page 786 The MPWMSM is affected by reset according to what is described in the section related to register description. The MPWMPERR, MPWMPULR, and MPWMCNTR registers, together with the clock prescaler register bits, must be initialized by software, since they are undefined after hardware reset. MPC561/MPC563 Reference Manual, Rev. 1.2 17-54 Freescale Semiconductor...
Page 787 MPWMSM2 Period Register (MPWMPERR) 0x30 6012 MPWMSM2 Pulse Register (MPWMPULR) 0x30 6014 MPWMSM2 Count Register (MPWMCNTR) 0x30 6016 MPWMSM2 Status/Control Register (MPWMSCR) MPWMSM3 0x30 6018 MPWMSM3 Period Register (MPWMPERR) 0x30 601A MPWMSM3 Pulse Register (MPWMPULR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-55...
Page 788 MPWMSM18 Pulse Register (MPWMPULR) 0x30 6094 MPWMSM18 Count Register (MPWMCNTR) 0x30 6096 MPWMSM18 Status/Control Register (MPWMSCR) MPWMSM19 0x30 6098 MPWMSM19 Period Register (MPWMPERR) 0x30 609A MPWMSM19 Pulse Register (MPWMPULR) 0x30 609C MPWMSM19 Count Register (MPWMCNTR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-56 Freescale Semiconductor...
Page 789 Period. These bits contain the binary value corresponding to the period to be generated. 17.10.6.3 MPWMSM Pulse Width Register (MPWMPULR) The pulse width register contains the binary value of the pulse width to be generated. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-57...
Page 790 Undefined Addr 0x30 6004, 0x30 600C, 0x30 6014, 0x30 601C, 0x30 6024, 0x30 602C, 0x30 6084, 0x30 608C, 0x30 6094, 0x30 609C, 0x30 60A4, 0x30 60AC Figure 17-29. MPWMSM Status/Control Register (MPWMSCR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-58 Freescale Semiconductor...
Page 791 Signal State Periodic Edge Variable Edge Direction InterruptIon Input INPUT — — — Output Always Low — — — Output High Pulse Falling Edge Rising Edge Falling Edge Input INPUT — — — MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-59...
Page 792 The following sections describe the MPIOSM in detail. A block diagram of one bit of the MPIOSM is shown in Figure 17-30. The MPIOSM contains 16 such blocks. Data Direction Register Data Register Signal Output Driver Input Figure 17-30. MPIOSM 1-Bit Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 17-60 Freescale Semiconductor...
Page 793 17.11.3.2 Non-Bonded MPIOSM Pads A non-bonded MPIOSM pad reads ‘0’ when it is configured as an input. When configured as an output, it indicates the current state of the output data latch. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-61...
Page 794 17.11.8.1 MPIOSM Data Register (MPIOSMDR) Field Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data SRESET Undefined Addr 0x30 6100 Figure 17-32. MPIOSM Data Register (MPIOSMDR) MPC561/MPC563 Reference Manual, Rev. 1.2 17-62 Freescale Semiconductor...
Page 795 The MIRSM gathers in service request flags from each group of up to 16 submodules and transfers those requests to the MIOS14 interrupt control section (ICS). Figure 17-34 shows a block diagram of the whole interrupt architecture. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-63...
Page 796 Enable register IRQ Pend. register IMB3 NOTE: Submodules 9, 10, 25, and 26 are reserved on the MPC561, MPC562, MPC563, and MPC564. Figure 17-34. MIOS14 Interrupt Structure 17.12.2 MIOS14 Interrupt Request Submodule (MIRSM) Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. On MPC561/MPC563 each MIRSM serves 14 submodules.
Page 797 3. The reminder of the division gives the bit position 17.12.3 MIRSM0 Interrupt Registers 17.12.3.1 Interrupt Status Register (MIOS14SR0) This register contains the flag bits that are raised when the submodules generate an interrupt. Each bit corresponds to a given submodule. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-65...
Page 798 This register is a read only register that contains the interrupt pending bits for the submodules. Each bit corresponds to a given submodule. When one of these bits is set, it means that a submodule raised its flag and the corresponding enable was set. MPC561/MPC563 Reference Manual, Rev. 1.2 17-66 Freescale Semiconductor...
Page 799 Table 17-38. MIOS14SR1 Bit Descriptions Bits Name Description FLG31:27 Flag Bits — MDASM flag bits [31:27] — Reserved FLGL24:22 Flag Bits— MMCSM flag bits [24:22] 10:15 FLG21:16 Flag Bits — PWMSM flag bits [21:16] MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-67...
Page 800 Field — SRESET Undefined Addr 0x30 6C46 Figure 17-40. Interrupt Request Pending Register (MIOS14RPR1) Table 17-40. MIOS14RPR1 Bit Descriptions Bits Name Description IRP31:27 Pending Bits — MDASM pending bits [31:27] — Reserved MPC561/MPC563 Reference Manual, Rev. 1.2 17-68 Freescale Semiconductor...
Page 801 17.12.6.1 MIOS14 Interrupt Level Register 0 (MIOS14LVL0) This register contains the interrupt level that applies to the submodules numbers 15 to zero. Field — — SRESET 0000_0000_0000_0000 Addr 0x30 6C30 Figure 17-41. MIOS14 Interrupt Level Register 0 (MIOS14LVL0) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-69...
Page 802 To measure the width of an input pulse, the MIOS14 double action submodule (MDASM) has two capture registers so that only one interrupt is needed after the second edge. The software can read both edge MPC561/MPC563 Reference Manual, Rev. 1.2 17-70...
Page 803 32-bit coherent read instruction can get both the current and the previous samples. Depending on the prescaler divide ratio, period times can be measured from 50 ns to 6.7 s. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 804 After the trailing edge, the MDASM stops to await further commands from the software. Note that a single edge output can be generated by writing to only one register. MPC561/MPC563 Reference Manual, Rev. 1.2 17-72...
Page 805 Subsequent changes to the output pulse width are made by writing a new time into register B1. Updates to the pulse width are always synchronized to the leading edge of the waveform. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 17-73...
Page 806 To do that, the two’s complement of the value is put in the modulus register and the interrupt occurs when the counter overflows. MPC561/MPC563 Reference Manual, Rev. 1.2 17-74 Freescale Semiconductor...
Page 807 Using the PPM in this way can reduce the number of signals required to connect the MPC561/MPC563 to an external device or devices. The second function allows the PPM to short internal signals thus giving increased access to multiple functions multiplexed on the same device signal.
Page 808 RX_CONFIG_2 0x30 5C10 RX Input Configuration — Reserved 0x30 5C12 — — Reserved 0x30 5C14 — RX_DATA 0x30 5C16 Receives data from RX_SHIFTER on SAMP[0:2] update rate — Reserved 0x30 5C18 — MPC561/MPC563 Reference Manual, Rev. 1.2 18-2 Freescale Semiconductor...
Page 809 In order to reduce the number of signals on the devices, many signals have multiple functions and each signal must be configured for access to any of these functions. The PPM module is designed to increase the availability of MPC561/MPC563 signal multiplexed functions. It can do this is two ways: •...
Page 810 18.3.1.1 Internal Multiplexing In the MPC561/MPC563 devices, the PPM module supports multiplexing of four modules: TPU3_A, TPU3_B, MIOS and GPIO registers, internal to the PPM. Internal multiplexers route data between the MCU internal modules and the external device through the PPM. Four configuration registers, TX_CONFIG_1, TX_CONFIG_2, RX_CONFIG_1 and RX_CONFIG_2, control these internal multiplexers.
Page 811 The PPM can be configured to transfer data in one of two clock modes, SPI and TDM. Figure 18-5 shows examples of PPM_TCLK in SPI and TDM modes. The frequency of PPM_TCLK is a function of the system clock (SYSCLK) and is programmable using the MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-5...
Page 812 PPM_TSYNC. PPM_TSYNC stays low until the contents of TX_DATA have been shifted out and/or 16 bits have been shifted into RX_SHIFTER. One data bit is transferred every PPM_TCLK cycle. MPC561/MPC563 Reference Manual, Rev. 1.2 18-6 Freescale Semiconductor...
Page 813 For transmit operations, the sample rate is the rate at which TX_DATA receives data from the internal modules. For receive operations, it is the rate at which the internal modules read RX_SHIFTER. The register RX_DATA is updated from RX_SHIFTER on completed receive (PPM_TSYNC) cycles. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-7...
Page 814 PPM_TCLK from its inactive edge to active edge. Section 18.4.2, “PPM Control Register (PPMPCR)” for more information on SPI mode PPM_TCLK settings. MPC561/MPC563 Reference Manual, Rev. 1.2 18-8 Freescale Semiconductor...
Page 815 18.3.2.2 TPU Shorting There are two TPU3 modules on the MPC561/MPC563 devices. Using the PPM, it is possible to internally short channel A_TPUCH0 with B_TPUCH0 and channel A_TPUCH1 with B_TPUCH1. Two bits of the SHORT_CH register (SH_TPU[1:0]) control the internal shorting. The input/output enable states of the TPU channels themselves determine the effect that the short bits have on the TPU modules’...
Page 816 Refer to Chapter 2, “Signal Descriptions,” for more details. 18.4 PPM Registers 18.4.1 Module Configuration Register (PPMMCR) Field STOP RESERVED SUPV RESERVED SRESET 0000_0000_0000_0000 Addr 0x30 5C00 Figure 18-8. Module Configuration Register (PPMMCR) MPC561/MPC563 Reference Manual, Rev. 1.2 18-10 Freescale Semiconductor...
Page 817 When PPMMCR[STOP] is set, the PPM module enters stop mode and the PPM module clocks will be stopped. While in stop mode, none of the PPM registers will be accessible, except for the PPMPCR register. If the STOP bit is clear, stop mode is disabled. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-11...
Page 818 0 Valid data can be latched on the transition of TCLK from inactive phase to active phase. 1 Valid data can be latched on the transition of TCLK from active phase to inactive phase. MPC561/MPC563 Reference Manual, Rev. 1.2 18-12...
Page 819 18-11. To transmit the first data frame correctly, set ENTX and ENRX simultaneously. Table 18-4. SAMP[0:2] Bit Settings SAMP[0:2] Sample Rate Every TCLK Every 2 TCLK Every 4 TCLK Every 8 TCLK 100 – 111 Every 16 TCLK MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-13...
Page 820 “1” “1” PPM_TX CH[K] PPM_RX Figure 18-10. Set ENRX While ENTX = 1 ENTX PPM_TCLK One Cycle PPM_TSYNC CH[K] “1” PPM_TX “1” CH[K] PPM_RX Figure 18-11. Set ENTX while ENRX = 1 MPC561/MPC563 Reference Manual, Rev. 1.2 18-14 Freescale Semiconductor...
Page 821 1-bit channel from an internal module to the PPM transmit data register. See Table 18-6 for more information on channel control and setting the channel values. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-15...
Page 822 (PPMPCR[ENRX] = 0). While receive mode is enabled these registers read as 0x00 and writing them will return TEA (bus error access). Field SRESET 0000_0000_0000_0000 Addr 0x30 5C0E Figure 18-16. Receive Configuration Register 1 (RX_CONFIG_1) MPC561/MPC563 Reference Manual, Rev. 1.2 18-16 Freescale Semiconductor...
Page 823 A_TPUCH15 B_TPUCH15 MDA14 18.4.5 Receive Data Register (RX_DATA) RX_DATA receives data from the RX_SHIFTER register. It is updated from RX_SHIFTER at the end of a receive cycle (i.e., rising edge of PPM_TSYNC). MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-17...
Page 824 RX_SHIFTER receives data serially from the PPM input signals PPM_RX[0:1] (depending on the value of PPMPCR[OP_16_8]). Data bits are shifted in on every PPM_TCLK cycle. Data in the RX_SHIFTER register is delivered directly to the MPC561/MPC563 internal modules with no wait time. Field...
Page 825 Figure 18-22. General Purpose Data In Register (GPDI) 18.4.10 Short Register (SHORT_REG) SHORT_REG allows the shorting of certain internal signals in the MPC561/MPC563 devices. This feature allows functions, whose internal signals are multiplexed on external signals, to be accessible simultaneously.
Page 826 No Short No Short No Short TouCAN_C[C_CNRX0, C_CNTX0] shorted to TouCAN_B[B_CNRX0, B_CNTX0] Both modules communicate via B_CNTX0, B_CNRX0. No Short TouCAN_C[C_CNRX0, C_CNTX0] shorted to TouCAN_A[A_CNRX0, A_CNTX0] Both modules communicate via A_CNTX0, A_CNRX0. MPC561/MPC563 Reference Manual, Rev. 1.2 18-20 Freescale Semiconductor...
Page 827 Input B_TPUCH0 Input Output Output data on B_TPUCH0 will be the input to A_TPUCH0 Output Input Output on A_TPUCH0 will be the input data to B_TPUCH0 Output Output No Short No Short MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-21...
Page 828 EXAMPLE If SHORT_CHx = 1, transmit TX_DATAx during TX_DATAx bit time and repeat TX_DATAx during TX_DATA[x-1] bit time. MPC561/MPC563 Reference Manual, Rev. 1.2 18-22 Freescale Semiconductor...
Page 829 0x1234 Normal transmission. Example 2 SHORT_CH_REG 0x00F0 SHORT_CH[7:4] = 1, therefore TX_DATA[1, 3, 5, 7] are enabled for re-transmission. TX_DATA[0:15] 0x1234 0b 0001 0010 0011 0100 Underlines show bits to be re-transmitted MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 18-23...
Page 830 • SCT[6:0] = 0 F /256 SYSCLK • SCT[6:0] = 1 to 127 F / (2 * SCT[6:0]) SYSCLK Writing to SCT[6:0] while the PPM is enabled will cause an irregular PPM cycle to occur. MPC561/MPC563 Reference Manual, Rev. 1.2 18-24 Freescale Semiconductor...
Page 831 CPU intervention. Consequently, for each timer event, the CPU setup and service times are minimized or eliminated. The MPC561/MPC563 contains two independent TPU3s: TPU_A and TPU_B. These two TPU3 modules are memory mapped as shown in Table 19-1.
Page 832 Each occurrence of either operation is called an event. A programmed series of events is called a function. TPU functions replace software functions that would require CPU interrupt service. The microcode ROM TPU3 functions that are available in the MPC561/MPC563 are described in Appendix D, “TPU3 ROM Functions.”...
Page 833 The time needed to respond to and service an event is determined by which channels and the number of channels requesting service, the relative priorities of the channels requesting service, and the microcode execution time of the active functions. Worst-case event service MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-3...
Page 834 TPU microcode ROM control store. To support changing TPU application requirements, Freescale has established a TPU function library. The function library is a collection of TPU functions written for easy assembly in combination with each other MPC561/MPC563 Reference Manual, Rev. 1.2 19-4 Freescale Semiconductor...
Page 835 — If the standard prescaler is selected (EPSCKE = 0), then the PSCK bit determines whether the standard prescaler divides the system clock input by 32 (PSCK = 0) or 4 (PSCK = 1) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 836 If DIV2 is zero, the TCR1 increment rate is defined by the output of the TCR1 prescaler (which, in turn, takes as input the output of either the standard or enhanced prescaler). Figure 19-3 shows a diagram of the TCR1 prescaler control block. MPC561/MPC563 Reference Manual, Rev. 1.2 19-6 Freescale Semiconductor...
Page 837 T2CLK clock pin must be at least nine system clocks. TPUMCR3[TCR2PSCK2] and TPUMCR[TCR2] determine how the clock source is divided to provide the output, see Table 19-5. Figure 19-4 illustrates the TCR2 pre-divider and pre-scaler control. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-7...
Page 838 TPU3 Test Configuration Register (TCR) 0x30 4402(TPU_B) 0x30 4004(TPU_A) Development Support Control Register (DSCR) 0x30 4404(TPU_B) Table 19-8 for bit descriptions. 0x30 4006(TPU_A) Development Support Status Register (DSSR) 0x30 4406(TPU_B) Table 19-9 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 19-8 Freescale Semiconductor...
Page 839 0x30 402A(TPU_A) TPU Module Configuration 3 (TPUMCR3) 0x30 442A(TPU_B) Table 19-21 for bit descriptions. 0x30 402C(TPU_A) Internal Scan Data Register (ISDR) 0x30 442C(TPU_B) 0x30 402E(TPU_A) Internal Scan Control Register (ISCR) 0x30 442E(TPU_B) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-9...
Page 840 0x30 45D0 – 0x30 45DF(TPU_B) 0x30 41E0 – 0x30 41EF(TPU_A) Channel 14 Parameter Registers 0x30 45E0 – 0x30 45EF(TPU_B) 0x30 41F0 – 0x30 41FF(TPU_A) Channel 15 Parameter Registers 0x30 45F0 – 0x30 45FF(TPU_B) MPC561/MPC563 Reference Manual, Rev. 1.2 19-10 Freescale Semiconductor...
Page 841 1 TPU3 is stopped (STOP bit has been set) SUPV Supervisor data space 0 Assignable registers are accessible from user or supervisor privilege level 1 Assignable registers are accessible from supervisor privilege level only MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-11...
Page 842 1 Do not latch conditions into branch condition register before exiting the halted state or during the time-slot transition period CLKS Stop clocks (to TCRs) 0 Do not stop TCRs 1 Stop TCRs during the halted state MPC561/MPC563 Reference Manual, Rev. 1.2 19-12 Freescale Semiconductor...
Page 843 T4 is one of the four basic timers (T1, T2, T3 & T4) used for microengine timing. 19.4.3 Development Support Status Register (DSSR) This register is accessible only when the TPU is in test mode; see Section 19.4.14, “Factory Test Registers.” MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-13...
Page 844 FREEZE being negated. 13:15 — Reserved 19.4.4 TPU3 Interrupt Configuration Register (TICR) Field — CIRL ILBS — SRESET 0000_0000_0000_0000 Addr 0x30 4008 (TPU_A), 0x30 4408 (TPU_B) Figure 19-8. TICR — TPU3 Interrupt Configuration Register MPC561/MPC563 Reference Manual, Rev. 1.2 19-14 Freescale Semiconductor...
Page 845 Encoded 4-bit fields within the channel function select registers specify one of 16 time functions to be executed on the corresponding channel. Encodings for predefined functions are found in Table D-1 Table D-2. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-15...
Page 846 The meaning of the host sequence bits depends on the time function specified. See Appendix D, “TPU3 Functions,” for definitions of the host service request bits for the predefined TPU ROM functions. MPC561/MPC563 Reference Manual, Rev. 1.2 19-16 Freescale Semiconductor...
Page 847 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 SRESET 0000_0000_0000_0000 Addr 0x30 401A (TPU_A), 0x30 441A (TPU_B) Figure 19-17. HSRR1 — Host Service Request Register 1 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-17...
Page 848 Table 19-16. Channel Priorities CHx[1:0] Service Guaranteed Time Slots Disabled — 1 out of 7 Middle 2 out of 7 High 4 out of 7 MPC561/MPC563 Reference Manual, Rev. 1.2 19-18 Freescale Semiconductor...
Page 849 0 TCR1 increments at rate determined by control bits in the TCR1P and PSCK fields of the TPUMCR register 1 Causes TCR1 counter to increment at a rate of the system clock divided by two MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-19...
Page 850 400 ns 242 ns 200 ns 143 ns 800 ns 485 ns 400 ns 286 ns 1.6 µs 970 ns 800 ns 571 ns 3.2 µs 1.94 µs 1.60 µs 1.14 µs MPC561/MPC563 Reference Manual, Rev. 1.2 19-20 Freescale Semiconductor...
Page 851 — Reserved 11:15 EPSCK Enhanced prescaler value that will be loaded into the enhanced prescaler counter. Prescaler value(EPSCK + 1) x 2. Refer to Section 19.3.8, “Prescaler Control for TCR1,” for details. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-21...
Page 852 Internal Scan Control Register (ISCR) 0x30 402E 0x30 442E TPU3 Test Configuration Register (TCR) 0x30 4002 0x30 4402 Development Support Control Register (DSCR) 0x30 4004 0x30_4404 Development Support Status Register (DSSR) 0x30 4006 0x30 4406 MPC561/MPC563 Reference Manual, Rev. 1.2 19-22 Freescale Semiconductor...
Page 853 0x30 45F0(B) 0x30 45F2(B) 0x30 45F4(B) 0x30 45F6(B) 0x30 45F8(B) 0x30 45FA(B) 0x30 45FC(B) 0x30 45FE(B) 19.5 Time Functions Descriptions of the MPC561/MPC563 pre-programmed time functions are shown in Appendix D, “TPU3 Functions.” MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 19-23...
Page 854 Time Processor Unit 3 MPC561/MPC563 Reference Manual, Rev. 1.2 19-24 Freescale Semiconductor...
Page 855 IMB3. In the MPC561/MPC563, the DPTRAM base address register (RAMBAR) must be set to a particular value to fit into the IMB memory map of the part. The DPTRAM RAMBAR register must be programmed to 0xFFA0.
Page 856 DPTRAM control and status registers. The addresses shown are offsets from the internal system base address (see Section 6.2.2.1.2, “Internal Memory Map Register (IMMR)”). Refer to Figure 1-3 to locate the DPTRAM control block in the MPC561/MPC563 address map. MPC561/MPC563 Reference Manual, Rev. 1.2 20-2 Freescale Semiconductor...
Page 857 Last memory Read Only Section 20.3.5, “MISC Counter (MISCNT)” for bit address descriptions. The DPTRAM array occupies an 8-Kbyte block. In the MPC561/MPC563, the array must be located at the address 0x30 2000. Refer to Figure 1-3 Figure 20-2. 0x30 2000...
Page 858 RAM Base Address Register (RAMBAR) The RAMBAR register is used to specify the 16 MSBs of the starting DPTRAM array location in the memory map. In order to be accessible in the MPC561/MPC563 memory map, this register must be programed to 0xFFA0.
Page 859 DPTRAM array. This allows the array to be placed on a 8-Kbyte boundary anywhere in the memory map. Do not overlap the DPTRAM array memory map with other modules on the chip. On the MPC561/MPC563 the value 0xFFA0 must be used for DPTRAM 6 Kbyte. 12:14 —...
Page 860 In order to guarantee valid DPTRAM data during power-down, external low voltage inhibit circuitry (external to the MPC561/MPC563) must be designed to force the RESET pin of the MPC561/MPC563 into the active state before V drops below its normal limit. This is necessary to inhibit spurious writes to the DPTRAM during power-down.
Page 861 Chapter 7, “Reset” for a description of MPC561/MPC563 reset sources, operation, control, and status.) Reset will also reconfigure some of the fields and bits in the DPTRAM control registers to their default reset state. See the description of the control registers to determine the effect of reset on these registers.
Page 862 The contents of the RAM are validated using a multiple input signature calculator (MISC). MISC reads of the RAM are performed only when the MPC561/MPC563 is in emulation mode and the MISC is enabled (MISEN = 1 in the DPTMCR).
Page 863 (MCU) applications targeted for high-speed read performance and high-density byte count requirements. The MPC563 has one Flash module of 512 Kbytes but the MPC561 has no internal Flash; this chapter, therefore, applies only to the MPC563. The UC3F array uses a single transistor Flash bit cell and is configured for a module of 512 Kbytes (524,288 bytes) of non-volatile memory (NVM).
Page 864 The two read page buffers are independently updated by page management logic contained in the BIU which interfaces to the UC3F EEPROM module. MPC561/MPC563 Reference Manual, Rev. 1.2 21-2 Freescale Semiconductor...
Page 865 External Flash program or erase enable inputs for block 0 or entire Flash array (B0EPEE and EPEE) • Low power disable via an external signal or UC3F register bit • Censor mode for Flash memory array access restriction with a user bypass for unrestricted array access MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-3...
Page 866 If B0EM = 0 when EHV is asserted, high voltage operations are disabled for small block 0 or the lowest numbered block of the UC3F array regardless of the state of EPEE. MPC561/MPC563 Reference Manual, Rev. 1.2 21-4 Freescale Semiconductor...
Page 867 SUPV HRESET Addr 0x2F C800 Field DATA PROTECT HRESET Reset state determined by NVM registers. These bits will be set to 01 by the factory. Figure 21-2. UC3F EEPROM Configuration Register (UC3FMCR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-5...
Page 868 SIE is modified making the next UC3F array access an off page access. 0 = normal array access 1 = disables normal array access and selects the shadow information rows MPC561/MPC563 Reference Manual, Rev. 1.2 21-6 Freescale Semiconductor...
Page 869 SBSUPV bit while the remainder of that array block is controlled by its SUPV bit. 0 array block M is placed in unrestricted address space 1 array block M is placed in supervisor address space MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-7...
Page 870 UC3F EEPROM Extended Configuration Register (UC3FMCRE) The UC3FMCRE is an extended module configuration register used for configuring the small block functions. In addition, 16 bits of the UC3FMCRE are used to provide a source for module identification. MPC561/MPC563 Reference Manual, Rev. 1.2 21-8 Freescale Semiconductor...
Page 871 SBSUPV bit is compared with the address space attributes to determine validity of an array access. 0 small block M is placed in unrestricted address space 1 small block M is placed in supervisor address space MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-9...
Page 872 When MAP = 1, the UC3F array is mapped to the top (ending at address all $F’s) of the 2 space in which the array resides. 0 UC3F array is mapped to bottom of 2 address space 1 UC3F array is mapped to top of 2 address space MPC561/MPC563 Reference Manual, Rev. 1.2 21-10 Freescale Semiconductor...
Page 873 0 no program or erase of the UC3F array or shadow information or CENSOR bits in progress 1 program or erase of the UC3F array or shadow information or CENSOR bits in progress MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 874 When programming, only those blocks intended to be enabled for programming should have their corresponding BLOCK[M] or SBBLOCK[M] bit set. 0 Small block M is not selected for program or erase 1 Small Block M is selected for program or erase MPC561/MPC563 Reference Manual, Rev. 1.2 21-12 Freescale Semiconductor...
Page 875 SES = 1 the SIE bit will be write locked. When PE = 1, the array is configured for erasing and SES will not write lock the SIE bit. 0 Configure for program operation 1 Configure for erase operation MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-13...
Page 876 0 Program or erase pulse disabled 1 Program or erase pulse enabled PEGOOD PEGOOD PEGOOD Valid Time Valid Time Figure 21-5. PEGOOD Valid Time MPC561/MPC563 Reference Manual, Rev. 1.2 21-14 Freescale Semiconductor...
Page 877 NOTE A module cannot read its own shadow row. On the MPC563 the program accessing the Flash shadow row must be executing from external memory or from internal SRAM. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-15...
Page 878 — Reset Unchanged Programmed by the user. Available only on the MPC564 When UC3FMCR[SIE] = 1, UC3FCFIG is the first word of the shadow row. Figure 21-7. Hard Reset Configuration Word (UC3FCFIG) MPC561/MPC563 Reference Manual, Rev. 1.2 21-16 Freescale Semiconductor...
Page 879 (RSTCONF=0) or the default internal reset configuration word (RSTCONF=1 and HC=1). 0 Interlock write is a write to any UC3F array location 1 Interlock write is a write to the UC3FMCR register. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-17...
Page 880 UC3FCFIG. If HC = 0 and the USIU requests internal configuration during reset the reset configuration word will be provided by UC3FCFIG. The default reset state of the UC3FCFIG after an erase operation of the UC3F module is no configuration word available (HC = 1). MPC561/MPC563 Reference Manual, Rev. 1.2 21-18 Freescale Semiconductor...
Page 881 Reset terminates any other mode of operation and forces the UC3F EEPROM module to a state ready to receive accesses. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-19...
Page 882 In the MPC563, the UC3F module contains two 32-byte read page buffers. In the module, one buffer is dedicated to the most recently accessed instruction fetches and the other read page buffer is dedicated to the most recently loaded data access. MPC561/MPC563 Reference Manual, Rev. 1.2 21-20 Freescale Semiconductor...
Page 883 Programming uses a program data latch to store the data to be programmed and an address latch to store the word address to be programmed. The UC3F Array may be programmed by byte (8 bits), half-word (16 bits), or word (32 bits). MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-21...
Page 884 EPEE and B0EPEE inputs are setup prior to the assertion of EHV. 5. Read the UC3FCTL register until HVS = 0. 6. Read the UC3FCTL, confirm PEGOOD = 1. MPC561/MPC563 Reference Manual, Rev. 1.2 21-22 Freescale Semiconductor...
Page 885 Table 21-7. Program Interlock State Descriptions Next State Mode Transition Requirement State Normal Operation: Write PE = 0, SES = 1. Normal array reads and register accesses. The block protect information can be modified. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-23...
Page 886 1 prior to initiating the programming sequence. Only the lowermost addresses are used to encode words that get programmed in the shadow row. The shadow information is physically located in MPC561/MPC563 Reference Manual, Rev. 1.2 21-24...
Page 887 For instance, if BLOCK[0:7] = 0x78 and SBEN[0:1] = 0b00, then blocks 1, 2, 3, and 4 are selected for erase. The embedded erase hardware algorithm first erases block 1 and then erases block 2 followed MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 888 UC3F EEPROM can be used reliably. 6. Read the UC3FCTL register. Confirm PEGOOD =1. 7. Write EHV = 0 in the UC3FCTL register. 8. Write SES =0 in the UC3FCTL register. MPC561/MPC563 Reference Manual, Rev. 1.2 21-26 Freescale Semiconductor...
Page 889 Write HSUS = 1 or disable the UC3F control logic. During erase the array will not module. respond to any address. Accesses to the registers are allowed. A write to UC3FCTL can change EHV or HSUS only. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-27...
Page 890 The UC3F EEPROM goes into a low power operation, or stop operation, while STOP = 1. When the STOP bit is set, only the control registers can be accessed on the UC3F EEPROM module. The UC3F EEPROM array may not be programmed, erased or read while STOP = 1. MPC561/MPC563 Reference Manual, Rev. 1.2 21-28 Freescale Semiconductor...
Page 891 CENSOR[0:1] bits are irrelevant. The second mode, censored mode, enables the UC3F EEPROM to exercise censorship based on the state of ACCESS, FIC, and CENSOR[0:1]. The device will enter censored mode only if one of following events occurs: • booting from external memory MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-29...
Page 892 While the device remains in the uncensored mode, ACCESS may be set to allow the device to enter censored mode and still access the UC3F array. ACCESS may not be set while the device is in censored mode but may be cleared. MPC561/MPC563 Reference Manual, Rev. 1.2 21-30 Freescale Semiconductor...
Page 893 Reading CENSOR[0:1] while setting or clearing with the high voltage applied (CSC = 1 and EHV = 1) will return 0’s. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-31...
Page 894 BLOCK[0:7] and SBBLOCK[0:1] set to 1, as well as PROTECT[0:7] and SBPROTECT[0:1] set to 0, are required for a valid erase interlock write during the clear censor operation. 4. Write EHV = 1 in the UC3FCTL register. MPC561/MPC563 Reference Manual, Rev. 1.2 21-32 Freescale Semiconductor...
Page 895 Information Censorship Data Data CENSOR[0:1] = 11 Data No Censorship Data CENSOR[0:1] = 10 CENSOR[0:1] = 01 Data Data Cleared Censorship Data CENSOR[0:1] = 00 Unknown Figure 21-11. Censorship States and Transitions MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 21-33...
Page 896 Set both CENSOR[0] and CENSOR[1]. 21.3.12 Background Debug Mode or Freeze Operation While in background debug mode, the UC3F should respond normally to accesses except that LOCK is writable. See the LOCK bit in Table 21-3. MPC561/MPC563 Reference Manual, Rev. 1.2 21-34 Freescale Semiconductor...
Page 897 Chapter 22 CALRAM Operation The calibration static random access memory (CALRAM) module provides the MPC561/MPC563 with a general purpose memory that may be read from or written to as either bytes, half-words, or words. In addition to this, a portion of the CALRAM, called the overlay region, can be used for calibration.
Page 898 28-Kbyte SRAM (Non Overlay) 4-Kbyte Overlay Figure 22-1. System Block Diagram 22.3 CALRAM Memory Map The MPC561/MPC563 chip internal memory map is shown in Figure 22-2. The CALRAM module is divided into two sections. • Control section: — Includes all the registers in the CALRAM module •...
Page 899 0x3F FFFF NOTE: Available on MPC563 only Figure 22-2. MPC561/MPC563 Memory Map with CALRAM Address Ranges When the normal device power (VDD) is off, portions of the CALRAM array can be powered by separate power supply sources (IRAMSTBY) as shown in Figure 22-3, thus allowing the data to be retained.
Page 900 Figure 22-3. Standby Power Supply Configuration for CALRAM Array 22.4 Modes of Operation The CALRAM module has the following modes of operation: • Reset • One-cycle • Two-cycle • Standby • Stop • Overlay MPC561/MPC563 Reference Manual, Rev. 1.2 22-4 Freescale Semiconductor...
Page 901 The memory array is also supplied by VDD during normal operation; however, when the VDD is off, the CALRAM array is backed up by a switched source (IRAMSTBY) that is also known as standby power. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-5...
Page 902 In an RBA register, RGN_SIZE[0:3] ={0101} select the size to be 128 bytes, and even if CRAM_RBAx [25:29] are not all 0’s, they will be considered as 0’s so that the address becomes 128-byte naturally aligned. MPC561/MPC563 Reference Manual, Rev. 1.2 22-6 Freescale Semiconductor...
Page 903 0x3F F200 to 0x3F F2FF. The rest of overlay region 1 from 0x3F F300 to 0x3F F3FF is available for normal (non-overlay) array access. Overlay regions 2, 3, 6, and 7 are disabled for overlay and hence can be used, in their entirety, for normal (non-overlay) array accesses. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-7...
Page 904 CALRAM Normal Array Access CALRAM Overlay Access Figure 22-5. CALRAM Module Overlay Map of Flash (CLPS = 0) Figure 22-6 illustrates the address spaces occupied by the two CALRAM modules available in MPC561/MPC563. MPC561/MPC563 Reference Manual, Rev. 1.2 22-8 Freescale Semiconductor...
Page 905 CALRAM, for example, from 0x3F FFE0 to 0x3F FFFF. The remainder (4 Kbytes – 32 bytes) is not only available for normal array access but also contiguous with a 28-Kbyte non-overlay array. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-9...
Page 906 CALRAM Normal Array Access CALRAM Overlay Access Figure 22-7. CALRAM Module Overlay Map of Flash (CLPS = 1) Figure 22-8 shows the overlay regions when the CLPS bit is set for CALRAM in MPC561/MPC563. MPC561/MPC563 Reference Manual, Rev. 1.2 22-10 Freescale Semiconductor...
Page 907 This “observing and disabling the highest priority region” loop can continue until all regions are disabled. This allows moving from one set of parameters to another with MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-11...
Page 908 CALRAM registers requires the bus master to be in supervisor data mode. On a privilege violation, the register is not accessed and the access generates an error. Table 22-2 shows the register address map for the MPC561/MPC563. MPC561/MPC563 Reference Manual, Rev. 1.2 22-12...
Page 909 RAM accesses. Field LCK — SRESET 0000_0000_0000_0000 Addr 0x38 0000 Field — SRESET 0000_0000_0000_0000 Figure 22-9. CALRAM Module Configuration Register (CRAMMCR) A brief description of each bit is provided in Table 22-3 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-13...
Page 910 D0 = 0 and DR = 1 data and/or Instruction (array 8-Kbyte block) D0 = 1 and DR = 0 data and/or Instruction (array 8-Kbyte block) D0 = 1 and DR = 1 data only (array 8-Kbyte block) MPC561/MPC563 Reference Manual, Rev. 1.2 22-14 Freescale Semiconductor...
Page 911 The RGN_SIZE[0] is reserved and should never be programmed to a one, because the MPC563 has only 512 Kbytes of Flash, and CRAM_RBAx[11] and CRAM_RBAx[12] should never be programmed to a one. Also, note that if CRAM_OVLCR[CLPS] is set, each of the eight sizes are forced MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-15...
Page 912 Overlay block is 64 bytes 0101 Overlay block is 128 bytes 0110 Overlay block is 256 bytes 0111 Overlay block is 512 bytes 1xxx Reserved Note: The overlay size of 8 bytes cannot be selected MPC561/MPC563 Reference Manual, Rev. 1.2 22-16 Freescale Semiconductor...
Page 913 This register is provided to support a separate module called READI. Refer to Chapter 24, “READI Module.” The reads from this register will return 0’s. NOTE CRAM_OTR is also defined as READI_OTR. See Section 24.6.1.1, “User-Mapped Register (OTR).” MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 22-17...
Page 914 CALRAM Operation Field Ownership Trace Register SRESET 0000_0000_0000_0000 Addr 0x38 002C Field Ownership Trace Register SRESET 0000_0000_0000_0000 Figure 22-12. CALRAM Ownership Trace Register (CRAM_OTR) MPC561/MPC563 Reference Manual, Rev. 1.2 22-18 Freescale Semiconductor...
Page 915 The program instructions flow is visible on the external bus when the MPC561/MPC563 is programmed to operate in serial mode and show all fetch cycles on the external bus. This mode is selected by...
Page 916 These status pins are used for both functions because queue flushes only happen in clocks that there is no fetch type information to be reported. Possible instruction types are defined in Table 23-1. MPC561/MPC563 Reference Manual, Rev. 1.2 23-2 Freescale Semiconductor...
Page 917 History Buffer Flushes Status Pins— VFLS [0:1] The history buffer flushes status pins denote how many instructions are flushed from the history buffer this clock due to an exception.Table 23-3 shows VFLS encodings. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-3...
Page 918 When program trace is needed, the external hardware needs to sample the status pins (VF and VFLS) each clock cycle and the address of all cycles marked with the program trace cycle attribute. MPC561/MPC563 Reference Manual, Rev. 1.2 23-4 Freescale Semiconductor...
Page 919 9. The external hardware starts sampling the program trace information upon the report on the VF pins of VSYNC 10. The hardware generates a breakpoint when the programmed event is detected and the machine enters debug mode MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-5...
Page 920 VSYNC on the VF pins (VF = 011) until all addresses marked with the program trace cycle attribute were visible externally. Therefore, the external hardware should stop MPC561/MPC563 Reference Manual, Rev. 1.2 23-6 Freescale Semiconductor...
Page 921 Programming a certain internal watchpoint to generate an internal breakpoint can be done either in MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-7...
Page 922 External breakpoints can be generated by any of the peripherals of the system, including those found on the MPC561/MPC563 or externally, and also by an external development system. Peripherals found on the external bus use the serial interface of the development port to assert the external breakpoint.
Page 923 The L-data comparators can operate on fix point data of load or store. When operating on fix point data the L-data comparators are able to perform compare on bytes, half-words and words and can treat numbers either as signed or as unsigned values. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-9...
Page 924 Two dedicated 16-bit down counters. Each can be programmed to count either an instruction watchpoint or an load/store watchpoint. Only architecturally executed events are counted, (count up is performed in case of recovery). MPC561/MPC563 Reference Manual, Rev. 1.2 23-10 Freescale Semiconductor...
Page 925 In order to use this feature, program the byte mask for each of the L-data comparators and to write the needed match value to the correct half-word of the data MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 926 Both byte masks = 0x0 Both L-data comparators program to half-word mode — Result: The event will be correctly detected as long as the compiler does not use a load/store instruction with data size of byte. MPC561/MPC563 Reference Manual, Rev. 1.2 23-12 Freescale Semiconductor...
Page 927 However, if an internal breakpoint is recognized when MSR[RI] = 0 (SRR0 and SRR1 are busy), the machine enters into a non-restartable state. For more information refer to Section 3.13.4, “Exceptions.” MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-13...
Page 928 There are four instruction address comparators A,B,C, and D. Each is 30 bits long, generating two output signals: equal and less than. These signals are used to generate one of the following four events: equal, not equal, greater than, less than. MPC561/MPC563 Reference Manual, Rev. 1.2 23-14 Freescale Semiconductor...
Page 929 (A | B) AND-OR I-Watchpoint 2 Logic Comparator C I-Watchpoint 3 (C & D) Compare (C | D) Type I-Breakpoint Logic Comparator D Compare Type Logic Figure 23-3. Instruction Support General Structure MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-15...
Page 930 The four load/store data events together with the match events of the load/store address comparators and the instruction watchpoints are used to generate the load/store watchpoints and breakpoint according to the programming. MPC561/MPC563 Reference Manual, Rev. 1.2 23-16 Freescale Semiconductor...
Page 931 Note that when programming the load/store watchpoints to ignore L-addr events and L-data events, it does not reduce the load/store watchpoints detection logic to be instruction watchpoint detection logic since the instruction must be a load/store instruction for the load/store watchpoint event to trigger. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-17...
Page 932 Logic Size Size Compare Size Logic Logic Byte Mask Byte 0 Byte 1Byte 2 Byte 3 Byte 0 Byte 1 Byte 2 Byte 3 Byte Mask Figure 23-4. Load/Store Support General Structure MPC561/MPC563 Reference Manual, Rev. 1.2 23-18 Freescale Semiconductor...
Page 933 Controlling the activity of the system from the development port is done when the CPU is in the debug mode. The development port is a relatively MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor...
Page 934 CPU enters debug mode after running code. The relationship between the debug mode logic to the rest of the CPU chip is shown in Figure 23-5. MPC561/MPC563 Reference Manual, Rev. 1.2 23-20 Freescale Semiconductor...
Page 935 Shift Register DSDI Figure 23-5. Functional Diagram of MPC561/MPC563 Debug Mode Support The development port provides a full duplex serial interface for communications between the internal development support logic of the CPU and an external development tool. The development port can operate in two working modes: the trap enable mode and the debug mode.
Page 936 An example is the ability of the development port to detect a debug mode access to a non existing memory space. Figure 23-6 illustrates the debug mode logic implemented in the CPU. MPC561/MPC563 Reference Manual, Rev. 1.2 23-22 Freescale Semiconductor...
Page 937 For protection purposes two possible working modes are defined: debug mode enable and debug mode disable. These working modes are selected only during reset. See Figure 23-7 for BDM mode selection. Debug mode is enabled by asserting DSCK during reset. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-23...
Page 938 Because SRESET negation is done by an external pull up resistor any reference here to SRESET negation time refers to the time the MPC561/MPC563 releases SRESET. If the actual negation is slow due to a large resistor, set up time for the debug port signals should be set accordingly.
Page 939 Section 3.15.4.1, “System Reset Exception and NMI (0x0100).” • Check stop. Refer to Section 23.3.1.3, “Check Stop State and Debug Mode,” for more information. • Machine check exception • Implementation specific instruction protection error MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-25...
Page 940 The CPU enters the check stop state if the machine check interrupt is disabled (MSR[ME] = 0) and a machine check interrupt is detected. However, if a machine check interrupt is detected when MSR[ME] = MPC561/MPC563 Reference Manual, Rev. 1.2 23-26...
Page 941 SRR0 and SRR1. ECR_OR is asserted before the next fetch occurs to allow the development system to detect the excepting instruction. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-27...
Page 942 The development system may monitor the freeze status to make sure the MPC561/MPC563 is out of debug mode. It is the responsibility of the software to read the exception cause register (ECR) before performing the rfi. Failing to do so will force the CPU to immediately re-enter to debug mode and to re-assert the freeze indication in case an asserted bit in the interrupt cause register (ECR) has a corresponding enable bit set in the debug enable register (DER).
Page 943 The freeze indication means that the processor is in debug mode (i.e., normal processor execution of user code is frozen). On the MPC561/MPC563, the freeze state can be indicated by three different pins. The FRZ signal is generated synchronously with the system clock. This indication may be used to halt any off-chip device while in debug mode as well as a handshake means between the debug tool and the debug port.
Page 944 The contents of the control register are used to drive the six trap enable signals, the two breakpoint signals, and the VSYNC signal to the CPU. The “transfer data to trap enable control register” commands will cause the appropriate bits to be transferred to the control register. MPC561/MPC563 Reference Manual, Rev. 1.2 23-30 Freescale Semiconductor...
Page 945 The first method allows the transmission to occur without being externally synchronized with CLKOUT, in this mode a serial clock DSCK must be supplied to the MPC561/MPC563. The other communication method requires a data to be externally synchronized with CLKOUT.
Page 946 7 or 32 input data bits. Debug Port drives “ready” bit onto DSDO when CPU starts a read of DPIR or DPDR. Figure 23-10. Synchronous Self Clock Serial Communication MPC561/MPC563 Reference Manual, Rev. 1.2 23-32 Freescale Semiconductor...
Page 947 The encoding of data shifted into the development port shift register (through the DSDI pin) is shown in Table 23-10 Table 23-11 below: MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-33...
Page 948 In trap enable mode the only response out of the development port is “sequencing error.” Data that can come out of the development port is shown in Table 23-12. “Valid data from CPU” and “CPU interrupt” status cannot occur in trap enable mode. MPC561/MPC563 Reference Manual, Rev. 1.2 23-34 Freescale Semiconductor...
Page 949 32-bit data field. The encoding of data shifted into the development port shift register (through the DSDI pin) is shown below in Table 23-13. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-35...
Page 950 Also, any interrupt that is recognized at the same time that there is valid data is not related to the execution of an MPC561/MPC563 Reference Manual, Rev. 1.2 23-36...
Page 951 Save RX, RY RY <- Memory Block address- 4 repeat: mfspr RX, DPDR DATA word to be moved to memory stwu RX, 0x4(RY) until here Restore RX,RY Figure 23-12. Download Procedure Code Example MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-37...
Page 952 In order to enable a software monitor debugger to broadcast the fact that the debug software is now executed, it is possible to assert and negate the internal freeze signal also when debug mode is disabled. MPC561/MPC563 Reference Manual, Rev. 1.2 23-38 Freescale Semiconductor...
Page 953 Breakpoint Counter B Value and Control Register (COUNTB) Table 23-21 for bit descriptions. Comparator E Value Register (CMPE) Table 23-22 for bit descriptions. Comparator F Value Register (CMPF) Table 23-22 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-39...
Page 954 ECR is not cleared when read. Reading DPDR yields indeterminate data. Read is performed. ECR is cleared when read. Program exception is generated. Read is not performed. ECR is not cleared when read. MPC561/MPC563 Reference Manual, Rev. 1.2 23-40 Freescale Semiconductor...
Page 955 When the hardware sets a bit in this register, debug mode is entered only if debug mode is enabled and the corresponding mask bit in the DER is set. All bits are cleared to zero following reset. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-41...
Page 956 Implementation specific data protection error This bit is set as a result of an data protection error. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. MPC561/MPC563 Reference Manual, Rev. 1.2 23-42 Freescale Semiconductor...
Page 957 Checkstop enable bit 0 Debug mode entry disabled 1 Debug mode entry enabled (reset value) MCEE Machine check exception enable bit 0 Debug mode entry disabled (reset value) 1 Debug mode entry enabled MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-43...
Page 958 0 Debug mode entry disabled (reset value) 1 Debug mode entry enabled 22:27 — Reserved LBRKE Load/store breakpoint enable bit. 0 Debug mode entry disabled 1 Debug mode entry enabled (reset value) MPC561/MPC563 Reference Manual, Rev. 1.2 23-44 Freescale Semiconductor...
Page 959 Reserved 30:31 CNTC Counter source select 00 not active (reset value) 01 I-bus first watchpoint 10 L-bus first watchpoint 11 Reserved Note: COUNTA[16:31] are cleared following reset; COUNTA[0:15] are unaffected by reset. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-45...
Page 960 SPR 152, SPR 153 Figure 23-20. Comparator E–F Value Registers (CMPE–CMPF) Table 23-22. CMPE–CMPF Bit Descriptions Bits Mnemonic Description 0:31 CMPE-F Address bits to be compared Note: These registers are unaffected by reset. MPC561/MPC563 Reference Manual, Rev. 1.2 23-46 Freescale Semiconductor...
Page 961 Compare type, comparator H 12:13 CRWE Select match on read/write of 0X don’t care (reset value) comparator E 10 match on read 11 match on write 14:15 CRWF Select match on read/write of comparator F MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-47...
Page 962 LW0LD LW1IA LW1LA IADC LADC LDDC IADC SRESET 0000_0000_0000_0000 Field LW1LD — DLW0 DLW1 SLW0 SLW1 LADC LDDC NOMSK SRESET 0000_0000_0000_0000 Addr SPR 157 Figure 23-23. L-Bus Support Control Register 2 (LCTRL2) MPC561/MPC563 Reference Manual, Rev. 1.2 23-48 Freescale Semiconductor...
Page 963 2nd L-bus watchpoint I-addr watchpoint selection 00 first I-bus watchpoint 01 second I-bus watchpoint 10 third I-bus watchpoint 11 fourth I-bus watchpoint LW1IADC 2nd L-bus watchpoint care/don’t care I-addr events 0 Don’t care 1 Care MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-49...
Page 964 1 trap enabled Note: LCTRL2 is cleared following reset. For each watchpoint, three control register fields (LWxIA, LWxLA, LWxLD) must be programmed. For a watchpoint to be asserted, all three conditions must be detected. MPC561/MPC563 Reference Manual, Rev. 1.2 23-50 Freescale Semiconductor...
Page 965 10 = match from comparator D 11 = match from comparators (C | D) 0x = not active (reset value) 10 = match from comparator D 11 = match from comparators (C | D) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-51...
Page 966 RCPU is fully serialized and show cycles will be performed for all indirect changes in the program flow RCPU is fully serialized and no show cycles will be performed for fetched instructions MPC561/MPC563 Reference Manual, Rev. 1.2 23-52 Freescale Semiconductor...
Page 967 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Field Data Reset Unaffected Addr SPR 630 Figure 23-26. Development Port Data Register (DPDR) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 23-53...
Page 968 Development Support MPC561/MPC563 Reference Manual, Rev. 1.2 23-54 Freescale Semiconductor...
Page 969 ID or operating system task is activated. An ownership trace message is transmitted to indicate when a new process/task is activated, allowing development tools to trace process/task flow. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-1...
Page 970 — Two bits are uploaded per clock in reduced port mode. For example, with system clock running at 56 MHz, this translates to a upload rate of 112 Mbits/s. 24.1.1 Functional Block Diagram The functional block diagram of the READI module is shown in Figure 24-1. MPC561/MPC563 Reference Manual, Rev. 1.2 24-2 Freescale Semiconductor...
Page 971 The various operating modes of the READI module are: 1. Reset 2. Secure 3. Normal 4. Disabled 24.2.1 Reset Configuration The READI reset configuration is explained in Section 24.7.6, “READI Reset Configuration.” MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-3...
Page 972 The queue is only 16 messages deep on revisions prior to Rev. D of the MPC561 and is 16 deep in Rev. B and earlier versions of the MPC563. For reduced port mode, the data trace feature should not be used, or used sparingly, so as not to cause queue overruns.
Page 973 Program Trace - Resource Full Message. Refer to Section 24.8.2.4.5, “Resource Full Message.” This message is not available on the MPC561 prior to revision D and is not available on the MPC563 revision B and earlier. Table 24-2. Vendor-Defined Messages TCODE...
Page 974 The process of driving valid instruction bits inside the processor. The instruction is decoded by each execution unit, and the appropriate execution unit prepares to execute the instruction during the next clock cycle. MPC561/MPC563 Reference Manual, Rev. 1.2 24-6 Freescale Semiconductor...
Page 975 MPC561/MPC563 Upload Device sends information to the tool. VSYNC Internal RCPU signal Internal RCPU signal which indicates instruction queue status. VFLS Internal RCPU signal which indicates history buffer flush status. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-7...
Page 976 ID information. The OTR register can only be accessed by supervisor data attributes. Only CPU writes to this register will be transmitted. This register is not accessible via the auxiliary port download request message. NOTE This is the only READI register that is reset by HRESET. MPC561/MPC563 Reference Manual, Rev. 1.2 24-8 Freescale Semiconductor...
Page 977 Accessing the DID register provides key attributes to the development tool concerning the MCU. This information is also transmitted via the auxiliary output port upon exit of READI reset (RSTI), if EVTI is asserted at RSTI negation. Table 24-6 gives the bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-9...
Page 978 READI Manufacturer ID. This field identifies the manufacturer of the device, Freescale’s ID is 0x0E. The value of this register for the MPC561 prior to Revision D silicon is 0x1C, and the value for the MPC563 prior to Revision B and earlier silicon is 0x1C.
Page 979 RCPU to halt. 24.6.1.5 Mode Control Register (MC) The MC register is used to select different modes of the READI module. Table 24-7 shows the location of register bits. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-11...
Page 980 READI Module NOTE The MC register is not available prior to Revision D of the MPC561 and is not available in Revision B and earlier versions of the MPC563. Prior revisions have only the default features. Field QTST — PTSM...
Page 981 Bits 0:31 31:0 The user base address (UBA) field defines the memory map address for the OT register. The MPC561/MPC563 user base address is 0x38002C. The UBA register is read-only by the development tool. 24.6.1.7 Read/Write Access Register (RWA) The RWA register provides DMA-like access to memory-mapped locations, MPC500 special purpose registers, and READI tool mapped registers.
Page 982 NOTE: The RWD field of the UDI register is shared with the WD field of the RWA register. The read/write (RW) field can be configured to allow selection of a read or a write access. 0 Read access 1 Write access MPC561/MPC563 Reference Manual, Rev. 1.2 24-14 Freescale Semiconductor...
Page 983 The UDI register, a 34-bit register, is used to store the data to be written for block write access, and the data read for read (single and block) accesses. Table 24-12 gives a description of the register bits. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-15...
Page 984 Not allowed Table 24-14. Write Access Status Status Write access has completed and no access error occurred Write access error occurred (Error Message sent out) Write access has not yet completed Not allowed MPC561/MPC563 Reference Manual, Rev. 1.2 24-16 Freescale Semiconductor...
Page 985 Table 24-15. DTA 1 AND 2 Bit Descriptions RCPU Nexus Name Description Bits Bits 0:22 47:25 DTEA The Read/Write End Field defines the end address for the address range. Refer to Table 24-16. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-17...
Page 986 (TCODE 18) which contains write attributes, write data, and target address. 2. The tool waits for device ready for upload/download (TCODE 16) message before initiating next access. MPC561/MPC563 Reference Manual, Rev. 1.2 24-18 Freescale Semiconductor...
Page 987 0b0. The bits transmitted will be aligned such that the last bit transmitted will be the most significant bit of the register. Therefore a message size that is divisible by the input port size should be transmitted. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-19...
Page 988 (ISCTL field = 0b01), or the PTM bit must be set and ISCTL must be set to a value other than 0b11. (See Table 23-26.) 24.7 Signal Interface This section details information regarding the READI signals and signal protocol. MPC561/MPC563 Reference Manual, Rev. 1.2 24-20 Freescale Semiconductor...
Page 989 Internal latching of MDI will occur on rising edge of MDI0 MCKI. Two signals are implemented on the MPC561/MPC563. MDI[1:0] are used in full port mode, MDI[0] only is used in reduced port mode.
Page 990 1 being the highest priority and 5 being the lowest priority: 1. Invalid message 2. READI register access handshakes (device ready/download information) 3. Watchpoint messages 4. Read/write access message 5. RCPU development access message MPC561/MPC563 Reference Manual, Rev. 1.2 24-22 Freescale Semiconductor...
Page 991 TCODE = 4 Number of Sequential Instructions since last taken branch = 4 Don’t care data Relative Address = 0x534 (idle clock) Figure 24-12. Auxiliary Signal Packet Structure for Program Trace Indirect Branch Message MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-23...
Page 992 Size Size Type (bits) (bits) Device ID Fixed TCODE number = 1 From Device Fixed Device ID information Ownership Trace Fixed TCODE number = 2 From Message Device Fixed Task/Process ID tag MPC561/MPC563 Reference Manual, Rev. 1.2 24-24 Freescale Semiconductor...
Page 993 Program Trace — Fixed TCODE number = 12 (0xC) From Indirect Branch Device Variable number of program trace messages Synchronization cancelled Message (PTSM = 0) Variable full target address MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-25...
Page 994 (10, 18, or 34 bits) will be uploaded/downloaded from/to device. 2). Depending upon opcode selected for upload from internal READI registers, information to be uploaded to the device will vary. MPC561/MPC563 Reference Manual, Rev. 1.2 24-26 Freescale Semiconductor...
Page 995 Variable resource code Refer to Table 24-20 for the error message codes. Not available on the MPC561 prior to revision D and not available on MPC563 revision B and earlier. Table 24-20. Error Message Codes Error Code Description 00000 Ownership trace overrun...
Page 996 Message formatting is performed in the signal interface block. Raw messages read from the message queue are independent of the number of MDO signals implemented. Table 24-22 shows the various message formats that the signal interface formatter has to encounter. MPC561/MPC563 Reference Manual, Rev. 1.2 24-28 Freescale Semiconductor...
Page 997 Message (PTSM = 0) Program Trace — Variable Variable 37 bits 8 bits Indirect Branch (0xC) Max = 8 Max = 23 Synchronization Min = 1 Min = 1 Message (PTSM = 1) MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor 24-29...
Page 998 Max = 23 Compressed Code Program Trace — Fixed = 6 Variable 35 bits 13 bits Direct Branch (0x3C) Max = 23 Synchronization Min = 1 Message With Compressed Code (PTSM = 0) MPC561/MPC563 Reference Manual, Rev. 1.2 24-30 Freescale Semiconductor...
Page 999 Table 24-20. Not available prior to Rev. D of the MPC561 and is not available in Rev. B and earlier versions of the MPC563 Only available on MPC562/MPC564 The maximum message length is 94 bits. The maximum number of fields is three, excluding the TCODE itself.
Page 1000 Tx = TCODE number (fixed) Ix = Number of sequential instructions (variable) Ax = Unique portion of the address (variable) NOTE During clock 7, the tool should ignore data on MDO signals. MPC561/MPC563 Reference Manual, Rev. 1.2 24-32 Freescale Semiconductor...

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