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Freescale Semiconductor MPC5604B Quick Start Manual

Based on qorrivva architecture
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See also: Reference Manual
LAAS-CNRS
Quick Start to MPC5604B
Embedded Development
Sahin Serdar
21/06/2013

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Summary of Contents for Freescale Semiconductor MPC5604B

  • Page 1 LAAS-CNRS Quick Start to MPC5604B Embedded Development Sahin Serdar 21/06/2013...

  • Page 2: Table Of Contents

    Table of Contents Introduction ..................................1 About this document ............................1 About of embedded programming ....................... 2 Associated documents ............................3 Chapter 1 Initialisation of the µcontroller ....................... 4 ME: Mode Entry Modules ..........................4 1.1. Introduction ..............................4 1.2. Enabling modes ............................
  • Page 3 PIT: Periodic Interrupt Timer ........................27 RTC/API: Real Time Clock/ Autonomous Periodic Interrupt ............29 Timer Examples ..............................31 Chapter 5 eMIOS: Enhanced Modular I/O Subsystem ................32 Module Configuration ............................. 33 Channel Configuration ............................ 34 1.1. Introduction .............................. 34 1.2.
  • Page 4 2.6. Channel Registers ........................... 55 ADC Example with PIT and eMIOS ......................55 Chapter 7 CTU: Cross Triggering Unit ......................58 Introduction ................................ 58 Configuring CTU ..............................59 Configuring ADC ..............................60 Implementing a feedback loop with ADC-CTU-eMIOS ..............60 Chapter 8 WKPU: Wakeup Unit .........................
  • Page 5 4.2.4. User interface ............................80 4.2.5. Testing ..............................80 Chapter 10 UART: Universal Asynchronous Receiver Transmitter ............82 Introduction to UART............................82 Module Presentation ............................82 Configuration ..............................83 3.1. Signal Configuration ..........................83 3.2. LINFlex Module Configuration ......................83 3.3.
  • Page 6 1.4. Error detection ............................105 1.5. Bit-rate and sampling ......................... 106 FlexCAN Module Configuration ....................... 107 7.1. Module Description ..........................107 7.2. Message Buffer mode and RX FIFO mode .................. 108 7.2.1. Message Buffers ..........................108 7.2.2. RX FIFO Engine ..........................110 7.3.

  • Page 7: Introduction

    Our tests were carried out on the starter kit evaluation board of MPC5604B, which embodies a CAN transceiver, a potentiometer, four LEDs and buttons; practical for examples.

  • Page 8: About Of Embedded Programming

    2. About embedded programming Most embedded software is built on a multi-layer architecture, where lower layers provide drivers for a simpler way of using different hardware peripherals. Then those drivers can be used for implementing drivers for more complex devices or for high-level application related functions.

  • Page 9: Associated Documents

    3. Associated documents This document is not as detailed as the MPC5604B’s reference manual and it may not give all the required information for implementing some specific behaviour with a peripheral. In this case following documents might be useful:  MPC5604B/C Reference Manual Rev. 8: The official Freescale document which explains the use of each peripheral.

  • Page 10: Initialisation Of The Μcontroller

    Chapter 1 Initialisation of the µcontroller 1. ME: Mode Entry Modules 1.1. Introduction This module controls the device modes, their settings and the transitions between them. On Figure 1, you can find different modes that are available in this µcontroller. They have to be initialised properly, after reset, in order to get the right configuration for the system.

  • Page 11: Enabling Modes

    1.2. Enabling modes The first thing to be done once the device enters in DRUN is to enable the modes that are going to be used by the software. This is done using the Mode Enable Register (MER). This register allows all modes to be enabled/disabled except for RESET, DRUN, SAFE, and RUN0 which are always enabled.

  • Page 12: Configuring Peripherals

    Example for configuring RUN0: 1.4. Configuring peripherals  ME.RUN[0].R = 0x001F0074; /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */ Having configured different modes, we possess 8 different registers that allow us to configure a peripheral to only run on a set of specific mode. These registers are called Run Peripheral Configuration Registers (RUNPC[0] to RUNPC[7]).

  • Page 13: Device Mode Selection

    (0...7) for low power operation and RUN_CFG allows to select a normal run mode from RUNPC registers. Note that by default, all peripherals run on RUNPC[0] register. Example for configuring SIUL peripheral (System Integration Unit Line: GPIO and external interrupt manager) to run only in RUN0 mode, using RUNPC1: ME.RUNPC[1].R = 0x00000010;...

  • Page 14: Cgm: Clock Generation Module

    To ensure that the operation was successful, you need to use the read only Global Status Register to check the current mode. Figure 9 : Global Status Register (Reference Manual Rev8 – Fig. 8-2) Here’s an example code for a transition towards RUN0 mode: ME.MCTL.R = 0x40005AF0;...

  • Page 15: Clock Out

    We can see that there are five possible clock sources in this architecture:  FXOSC: Fast External Crystal Oscillator, between 4-16MHz (8 MHz on TRK- MPC5604B),  FIRC: Fast Internal RC Oscillator, 16MHz,  SXOSC: Slow External Crystal Oscillator, 32kHz, ...

  • Page 16: Sysclk

    2.3. Sysclk Each of the four clock source has a single control register for its gating towards next blocks. We will focus only on FXOSC’s control register. Figure 13 : Fast External Crystal Oscillator Control Register (Reference Manual Rev8 – Fig. 6-2) Bypass allows using original crystal signal as clock without going through the oscillator, end of Count Value is used to check the stability of the clock once the software powers it up.

  • Page 17: Fmpll

    Here’s an example of using a 1MHz by dividing FXOSC by 8, and supplying a 1MHz clock for peripheral set 1, 100 kHz for peripheral set 2, 250 kHz for peripheral set 3. CGM.FXOSC_CTL.R = 0x00800700; /* keep reset settings divide /* Here insert code that configures a user mode’s system clock with divided xtal fast oscillator, you can check it with CGM.SC_SS.R read only register */...
  • Page 18 Fields of this register are defined as; IDF[3:0]=IDF-1; and IDF [3:0] =1111 means clock inhibition, ODF[1:0]=log (ODF)-1, NDIV[6:0]=NDIV. These values must only be changed while the PLL is not the system clock source. The other fields on this register are defined as: ...

  • Page 19: A Device Initialisation Procedure

    Figure 19 : FMPLL Modulation Register (Reference Manual Rev8 – Fig. 6-8) Different fields of this register are defined as:  STRB_BYPASS: Strobe bypass; when this bit is set to ‘0’, it allows to change other fields while FM is not enabled, but if it is set to ‘1’, other fields has to be static while FMPLL is powered on, ...

  • Page 20: Swt: Software Watchdog Timer

    Here’s an example for setting a 64MHz system clock and making SIUL (GPIO) run on this mode. void initModesAndClock(void) { ME.MER.R = 0x0000001D; /* Enable DRUN, RUN0, SAFE, RESET modes CGM.FMPLL_CR.R = 0x02400100; /* 8 MHz xtal: Set PLL0 to 64 MHz ME.RUN[0].R = 0x001F0074;...

  • Page 21: Siul: System Integration Unit Line

    Figure 20 : SIUL Block Diagram (Reference Manual Rev8 – Fig. 19-1) This module is used for pad management and configuration. It can also process external interrupts that can be triggered on rising/falling edges. On TRK-MPC5604B there are 123 pads with GPIO functionality and 16 with external interrupt ability.
  • Page 22 It can be seen that there are two registers that are used for configuring pads; PCR (Pad Configuration Register) and PSMI (Pas Selection for Multiplexed Inputs). Figure 22 : Pad Configuration Register (Reference Manual Rev8 – Fig. 19-9) There are 123 PCR registers, one for each pad, with following fields: ...

  • Page 23: Gpio: General Purpose Input/Output

    Some peripherals’ inputs can be received from multiple pads, in this case using PSMI registers’ PADSEL fields; one of the possible pads must be selected. See Appendix 3 for more information about possible selections. It is mostly needed by communication modules. Here’s an example code that sets pads connected to four LEDs as GPIO outputs and switch S1 as an input.
  • Page 24 Here’s an example of usage of these registers on TRK-MPC5604B: /* This extract of code will blink LEDs 1 to 4 sequentially while the button S1 is pressed. uint32_t LED_state, i; main (void) { initModesAndClock(); /* Initialisation of the device config_PORT_E();...

  • Page 25: External Interrupts

    Figure 27 : Masked Parallel GPIO Pad Data Out Registers (Reference Manual Rev7 – Table 8-18) Here’s the equivalent code for turning all LEDs off for the previous code written with these new registers: 4. External interrupts SIU.MPGPDO[4].R = 0x0F000F00; // All LEDs are off.
  • Page 26 There’s also a glitch filter for these pads that avoids erroneous requests that may be triggered by noise. Interrupt Filter Enable Register (IFER) can set which pads are to be filtered. And IFMC and IFCPR are used to set filters parameters. These two registers together have only two fields MAXCNT[x][3:0] (x: one for each pad) is the Maximum Couter, IFCP[3:0] is the clock prescaler setting common to all pads.

  • Page 27: Intc: Interrupt Controller

    INTC: Interrupt Controller 1. Introduction The core of MPC5604B (e200z0h) is associated with registers called Interrupt Vector Offset Register (IVOR), which handles different kinds of exceptions that might occur during runtime. Different kinds of core exceptions are handled by different IVORs. IVOR4 is the one used for interrupt handling.
  • Page 28 There are 294 vectors on the ISR, the first 11 being vectors from IVOR Vector Table, and among the rest only 142 are usable (the others are reserved). Of these usable vectors, 8 of them are reserved for software triggered interrupts (software ISR) and the other 134 are hardware ISR linked to the peripherals.

  • Page 29: Intc Configuration (Software Mode)

    2. INTC configuration (Software mode) 2.1. Enabling interrupt requests There are two stages for enabling interrupts; first, at a general level, the interrupt handling in the microcontroller has to be enabled, then, at the peripheral level, for an ISR to be raised, the registers in charge of that interrupt has to be configured.

  • Page 30: Configuring Software Isrs

    The led will blink with a frequency of 1Hz. It should be noted that it’s common to use finite state machines in interrupt handlers. 2.3. Configuring software ISRs There are 8 ISRs that can be triggered by the software, the ISR configuration is done in the same way as hardware ISRs but triggering the interrupt is more complicated.
  • Page 31 Figure 33 : INTC SW/HW mode comparison (Freescale Tutorial)

  • Page 32: Chapter 4 Timer Modules

    Chapter 4 Timer Modules 1. Introduction There are various timer-like peripherals available in this microcontroller with different characteristics and uses. Here’s a list of timer modules with brief descriptions:  System Timer Module (STM): A 32-bit running-up counter, clocked by the system clock.

  • Page 33: Stm: System Timer Module

    2. STM: System Timer Module This module has two general registers for control and count value, and 3 register for each one of four channels. Figure 35 : STM Control Register (R.M. Rev8 – Fig. 24-2) The control register (STM_CR) can enable the clock using TEN (Timer Enable, write ‘1’ to enable) and it can set the timers behaviour in debug with FRZ (Freeze, write ‘1’...
  • Page 34 Figure 37 : PIT Module Control Register (R.M. Rev8 – Fig. 24-57) The module is disabled by default, to enable it; we have to write ‘0’ to MDIS (Module Disable) field. The FRZ field allows stopping the timers in debug mode by writing ‘1’. Each of the six timers [0...5] have the following registers: ...

  • Page 35: Rtc/Api: Real Time Clock/ Autonomous Periodic Interrupt

    4. RTC/API: Real Time Clock/ Autonomous Periodic Interrupt Figure 40 : RTC/API Architecture (R.M. Rev8 – Fig. 13-1) The Real Time Clock is an independent 32-bit timer, clocked by either internal RC oscillators (128kHz or 16MHz) or by a slow external crystal (32kHz). By using dividers by 32 and/or 512, we can count in resolutions of a few µs or a few ms up to thousands of seconds (see the last table of this section).
  • Page 36 RTC Control (RTCC) register assembles main parameters of this module, modifiable fields are:  CNTEN: Counter enable (write ‘1’ for enabled),  RTCIE: RTC interrupts enable (write ‘1’ for enabled),  FRZEN: Freeze enable (write ‘1’ for freezing the module in debug mode), ...

  • Page 37: Timer Examples

    5. Timer Examples A timer configuration example has been built using STM, PIT and RTC/API where each module has to toggle a LED at 5Hz frequency (therefore generating à 2.5Hz square wave). Their precision and ease of use will be compared. Let’s start with PIT;...

  • Page 38: Emios: Enhanced Modular I/O Subsystem

    Chapter 5 eMIOS: Enhanced Modular I/O Subsystem These modules use timer channels to generate or measure time based events like PWM, counter generation, period measurement etc. Channels can be configured up to 12 different operation modes shown on the figure below. Figure 43 : eMIOS Channel Configuration (R.M.

  • Page 39: Module Configuration

    1. Module Configuration Without making any channel configurations, this block can be seen as multiple 16-bit up- counting channels that can select a counter among its internal counter, the 16-bit counter bus A or one of 16-bit counter busses B, C, D or E, depending on the channel’s position. Each of these counter busses are controlled by one particular channel configured as a counter, previous figure shows that bus A is controlled by channel 23 and B, C, D and E are respectively controlled by channels 0, 8, 16 and 24.

  • Page 40: Channel Configuration

    2. Channel Configuration 1.1. Introduction Unified Channels are made of: A counter bus selector, which can select among three time base sources, to be used for time- based events. An internal 16-bit counter clocked by the prescaled eMIOS internal clock. Two data registers A and B, double buffered and related to four internal registers (A1, B1, A2, and B2) that can be used for input capture or output compare.
  • Page 41  Edge Selection (EDSEL) bit: for input modes, this bit selects whether both edges are triggering (‘1’) or a single edge defined by EDPOL (‘0’). For GPIO input mode, it selects if a flag can be generated (‘1’: no flag is generated, ‘0’: it’s generated as defined by EDPOL). And for SAOC mode, it selects if output flip-flop is toggled at each match (see the section below).

  • Page 42: Gpio: General Purpose Input/Output

    Figure 47 : eMIOS A, B and Alt A Register R/W (R.M. Rev8 – Table 24-16) Primary Counter Bus A eMIOS Internal Secondary Counter Bus Counter Clock (B,C…) UCIN Prescaler UCPREN Internal UCPRE Counter Bus Counter Input Select (BSL) Edge Detect Filter EDPOL IF, FCK...

  • Page 43: Saic: Single Action Input Capture

    When in GPIO input mode (MODE[0:6]=0000000), the input pin status can be read by UCIN bit in the status register and a flag can be generated at on a rising or an falling edge. (Detection of both edges isn’t implemented for GPIO). In GPIO output mode (MODE[0:6]=0000001), the channel is used as a single output pin and the value of EDPOL is transferred to the output flip-flop.

  • Page 44: Ipwm: Input Pulse Width Measurement

    1.5. IPWM: Input Pulse Width Measurement The Input Pulse Width Measurement mode (MODE[0:6]=0000100), is the measurement of the width of a positive or a negative (depending on EDPOL) pulse by capturing the leading edge on B1 and the trailing edge on A2. The capture on A2 is disabled until B2 gets its first leading edge, then the selected counter bus (BSL) count value is stored on B2.

  • Page 45: Daoc: Double Action Output Compare

    In order to get coherent measurement, a read on the register A (so A2) will disable transfers from B2 to B1 and force a transfer from A1 to B1. The value in B1 will be intact for the upcoming read on the register B. By subtracting B1 from A2, we can get the period. (See figure below for an illustration of these register transfers).

  • Page 46: Mc: Modulus Counter

    is DAOC with a flag generation on the B match and MODE[0:6]=0000111 is DAOC with a flag generated on both matches. For further pulse generation, the comparators have to be re-enabled by transfer of data written to A2/B2 to A1/B1. 1.8.

  • Page 47: Mcb: Modulus Counter Buffered

    any problem, but if it’s above then we’ll have to wait the counter to roll-over for getting normal operation. 1.9. MCB: Modulus Counter Buffered In this Modulus Counter Buffered mode (MODE[0:6]=1010b0b), the register A is double buffered, allowing smoother transitions when the value of A is changed. The match register A1 is only updated at the end of a cycle, avoiding the need of wait for a roll over.
  • Page 48 At entry, the output flip-flop is set to the value of EDPOL. When the internal counter match occurs on comparator A, the output is set to the value of EDPOL, when a match occurs on comparator B, the output will be set to the complement of EDPOL. Therefore, using A1 as the duty cycle and B1 as the frequency, the EDPOL must be set to the opposite polarity of the pulse we want.

  • Page 49: Opwmcb: Center Aligned Output Pulse Width Buffered

    1.11. OPWMCB: Center Aligned Output Pulse Width Buffered The Center Aligned Output PWM Buffered with Dead-Time mode (MODE[0:6]=10111bb) is another way of generating a PWM. The time base can be selected via BSL, and it should be a up/down MCB counter. It is also recommended to start the MCB channel after starting the OPWMCB mode.

  • Page 50: Opwmb: Output Pulse Width Modulation Buffered

    Register B1 controls the dead time, it is compared with the internal counter, for a leading edge dead time, the duty cycle of the signal is , where MAXCNT is the maximum value 2 ( ������������−��1 ) −��1 2 ( ������������−1 ) of the time base.

  • Page 51: Opwmt: Output Pulse Width Modulation With Trigger

    Figure 62 : OPWMB mode with duty cycle going from 100% to 0% (R.M. Rev8 – Fig. 24-42) 1.13. OPWMT: Output Pulse Width Modulation with Trigger The Output Pulse Width Modulation with Trigger mode (MODE[0:6]=0100110) works in a similar way to OPWMB but with some important differences: ...

  • Page 52: Pwm Channel Initialisation

    3. PWM Channel Initialisation In order to initialise a PWM channel and a time base channel for it without getting erroneous signals the following procedure should be followed: 1. Ensure that the channel is in GPIO mode; 2. (eMIOS) Disable global prescaler; 3.
  • Page 53 Now we have counter bus running, we can select any channel connected to the bus A and configure it as OPMWB. For instance we can select channel 21, set the leading edge (register A) at 0 and trailing edge at 499, running on bus A, with a positive polarity (output is set at leading edge etc.).

  • Page 54: Adc: Analog-To-Digital Converter

    Chapter 6 ADC: Analog-to-Digital Converter 1. Presentation of the ADC module 1.1. Introduction Figure 64 : ADC Architecture (R.M. Rev8 – Fig. 25-1) The ADC block is made of multiplexing of 32 channels (expandable to 64 via external multiplexing) to a 10-bit resolution, successive approximation converter. A conversion can be triggered by software or hardware (PIT or CTU) and there are different conversion modes like one shot or scan.

  • Page 55: Conversion

    1.2. Conversion There are three conversion modes available for this module; normal conversion, injected conversion and CTU triggered conversion. CTU triggered conversion will be explained in the chapter dedicated to the CTU module, this section is only about normal and injected modes. A normal conversion can be started from the software by setting the NSTART (Normal Start) bit 1.2.1.

  • Page 56: Adc Clock And Conversion Timing

    Once the conversion starts, JSTART is reset for further conversion requests. At the end of each conversion JEOX interrupt is issued and at the end of an injected sequence, JECH interrupt is triggered. Any ongoing conversion can be stopped using the ABORT bit in the configuration register, then the next channel in line will be converted.

  • Page 57: Pre-Sampling

    The following table gives some example values for different clock settings: Figure 69 : ADC sampling and conversion timing (R.M. Rev8 – Table 25-2) 1.4. Pre-sampling For higher quality sampling, resetting the sampling capacitor after a previous sampling is needed; the ADC capacitor is charged or discharged to one of the two internal voltage references. This phase can be enabled for a channel, and it would take as much time as a sampling phase.

  • Page 58: Adc Configuration

    2. ADC Configuration 2.1. Pad Configuration Using the SIUL module, the software has to set the APC bit of the PCR register of a pad with ADC functionality, there is no need to bother with other fields or alternate functions. 2.2.

  • Page 59: Conversion Registers

    Figure 72 : Main Status Register (R.M. Rev8 – Fig. 25-9) The Main Status Register (MSR) is a read-only register allowing the access the current status of the ADC module: NSTART, JSTART, CTUSTART respectively indicate whether a conversion of normal, injected or CTU modes is ongoing, CHADDR indicates current conversion channel address, JABORT signals if an injected conversion is aborted.

  • Page 60: Interrupt Registers

    INPLATCH, INPCMP and INPSAMP. The OFFSHIFT field is only available for precision channels (CTR[0]) and it allows selecting how the last bit of the converted data field should behave: 00: The transition between 0x000 and 0x001 happens when the input is equal to 1LSB. 01: The transition between 0x000 and 0x001 happens when the input is equal to ½...

  • Page 61: Channel Registers

    And finally, there is an interrupt flag register (WTISR) for all watchdogs, containing six flags, WDGxL and WDGxH, x=0…3, for each interrupt. And a mask register (WTIMR) with six match bits, MSKWDGxL and MSKWDGxH, x=0…3, that has to be set to enable the corresponding interrupts.
  • Page 62 The system clock runs at 8MHz so to get a PIT2 flag with a 1kHz frequency requires a TimeOut value of 8000. Also ADC has to be configured to run with injected conversions with triggers coming from PIT 2. Channel 1 and its end of conversion are set: Meanwhile, from the SIUL, LEDs have to be selected as GPIO output, two buttons as GPIO inputs, two pins as eMIOS channels and a pin for ADC input.
  • Page 63 The main program launches each modules, initialises and configures them, the PIT is started with a time out of 8000, and ADC’s end of conversion interrupt is connected to the ADC_EOC_Interrupt handler: Depending on an internal state variable, the value read by the ADC either affects the OPWM’s duty cycle or some LEDs.

  • Page 64: Ctu: Cross Triggering Unit

    Chapter 7 CTU: Cross Triggering Unit 1. Introduction The Cross Triggering Unit synchronises an ADC conversion with a timer (a PIT or eMIOS) without needing to generate an interrupt. A conversion is only delayed by a cycle from the trigger event of the timer. The following block diagram illustrates the CTU module. Figure 75 : CTU Block Diagram (R.M.

  • Page 65: Configuring Ctu

    Figure 76 : Trigger Sources (R.M. Rev8 – Table 26-3) 2. Configuring CTU Figure 77 : Event Configuration Registers (R.M. Rev8 – Fig. 26-2)

  • Page 66: Configuring Adc

    An EVTCFGR[n] register has the following fields:  A trigger masking bit (TM), set this bit to enable triggers.  A clear flag (CLR_FLAG) bit to force the software to send and Flag_Ack signal to the timers. If this bit is set, the Flag_Ack is sent continuously ( may cause a loss of event), and when it is clear Flag_Ack is handled automatically.
  • Page 67 One of the differences comes from the ADC initialisation, where the CTU triggers are enabled: And the eMIOS channel is changed to an OPWMT from generating triggers (with alt A register): And in the main code, the CTU is set so that eMIOS channel 22 triggers ADC channel 0:...

  • Page 68: Wkpu: Wakeup Unit

    Chapter 8 WKPU: Wakeup Unit 1. Low power consumption modes There are three low power user modes: HALT, STOP and STANDBY. We will not go into details about HALT, as it is very similar to STOP but cannot process wakeup signals. 1.1.

  • Page 69: Introduction

    Figure 80 : STANDBY Mode Configuration Register (R.M. Rev8 – Fig. 8-16) In this mode, the power supply is only used for MC_RGM (Reset Generation Module), MC_PCU (Power Control Unit), WKPU (Wakeup unit), 8k RAM, RTC/API, CAN_Sampler, SIRC, FIRC and SXOSC.
  • Page 70 A wakeup signal can be generated from 20 different sources, the source number 0 is the API, the source number 1 is the RTC and the other ones are external sources that are located on some specifics pads of some ports that has also communication functionalities like CAN or LIN. This can allow, for example, to put the device en low power mode while awaiting information/commands from CAN.

  • Page 71: Configuration Of Wakeup Events

    On external interrupts, DSPI is not mentioned because it is thought to be used in master mode but it can still be done (see pad configurations) if needed. A more appropriate use would be, for instance, to wake up the device using CAN signals. The 18 external sources of the Wakeup Unit will trigger a wakeup signal in STANDBY/STOP modes but they can still be used as extra external interrupts during a RUN mode.

  • Page 72: Dspi: Deserial Serial Peripheral Interface

    Chapter 9 DSPI: Deserial Serial Peripheral Interface 1. Introduction There are three identical DSPI modules (0…2) in this microcontroller for using SPI serial bus protocol in order to communicate with external devices. 1.1. SPI Protocol Description The Serial Peripheral Interface (SPI) is a synchronous serial communication bus in which there is only one master and at least one slave.
  • Page 73 Figure 85 : A time diagram of different signals involved in SPI, depending on CPOL/CPHA When using SPI with multiple slaves there are different possibilities for connecting them. If the master has enough chip select signals, then each slave can be independent and communicate with the master only when asked.

  • Page 74: Module Presentation

    1.2. Module Presentation The DSPI Modules provide an implementation of the SPI protocol with some enhancements like FIFO buffers in the memory for simpler communication, various interrupts and a precise control on the baud rate and delays. Figure 87 : The DSPI module block diagram (R.M. Rev8 – Fig. 23-1) Each DSPI module has six chip select (CSx) signals that can handle communication with a considerable amount of external devices.

  • Page 75: Configuration

    2. Configuration 2.1. Signal Configuration Depending on whether the DSPI is configured as a master or a slave, CS[0:5]_x pins have to be configured using SIUL. Output type signals need an output buffer, so the OBE bit SIUL’s pad configuration register is needed.

  • Page 76: Transfer Configuration Register

     SMPL_PT: Sample point, allows the moment where the master can sample the SIN pin when using modified transfer format: at the odd-numbered-edge of SCK(00), one system clock cycle following that(01) or two system clock cycles following the SCK edge(10). ...

  • Page 77: Data Attributes

    registers should not be changed while DSPI is running. Most of its fields are only used in the master mode. Figure 92 : Clock and Transfer Attributes Registers (CTAR) (R.M. Rev8 –Fig. 23-5) This configuration register’s fields are explained in different subsections below for better clarity. The figure below illustrates the influence of different parameters on the transfer.

  • Page 78: Baud Rate

     LSBFE: LSB First Enable, if cleared, MSB is transferred first, otherwise LSB is transferred first. Master mode only. 2.3.2. Baud rate These fields are related to the baud rate:  PBR: baud rate prescaler, used in establishing the transfer baud rate; the prescaler value is either 2 (00), 3(01), 5(10) or 7(11).

  • Page 79: Cs To Sck Delay

    2.3.3. CS to SCK delay These fields are used to set the delay between the slave select signal and the start of the transfer.  PCSSCK: CS to SCK delay prescaler, used in establishing a delay between Chip Select signal and the SCK start; the delay prescaler value is ������������ =2×PCSSCK[0:1]+1.

  • Page 80: Transmit/Receive Registers

    The DSPI Status Register (SR) contains both flags and information about the current status of the module. It’s fields are:  TCF: Transfer complete flag, this flag is raised once the last incoming data of a frame is sampled and before �� delay is started.

  • Page 81: Developing A General Purpose Spi Driver

    These sub-fields are:  CONT: Continuous chip selection enable, if set, continuous selection mode is activated. Available both to the master and to a slave.  CTAS: Clock and transfer attributes select, selects one of CTARx registers. (‘000’ selects CTAR0, ‘001’ selects CTAR1 etc. until ‘101’). Available only to master. ...
  • Page 82 An array transfer method called with an array size of ‘1’ is pretty much equivalent to a single data transfer (with a few excessive useless clock cycles). Each time a transfer is completed a ‘Completed’ flag in the driver structure is set to 1 and it is automatically cleared when a new transfer method is called.

  • Page 83: Driving Smart-Mos Switches Mc33984 Using Spi Driver

    N-MOSFETs with an RDSon of 4mOhms. In this example, we will develop a serial terminal interface for MPC5604B for commanding this chip. It will have to initialise the device via SPI, then it can directly control its inputs via IN[0:1] either as a continuous logic level or as a PWM signal.
  • Page 84 This driver uses SPI to initialise and enable switches. It sets the over-current thresholds to minimal value. It activates the logical AND mode for the output, so both SPI_INx field in OCR register and direct control input pin INx has to be set high to close the switch. The SPI_INx field is therefore used for enabling a switch.

  • Page 85: Definitions

    4.2.1. Definitions 4.2.2. Initialization The initialization function of the driver sends required RST and WAKE signals to prepare the device and it configures some basic parameters using SPI. This function also calls eMIOS initialisation functions to set the PWM on specific pads.

  • Page 86: Operations

    4.2.3. Operations Some common operations are defined, using SPI and PWM, (see code for details), config_HS: Enabling/disabling a high-side switch, write_HS: Sets/clears a high-side switch output, conf_PWM_HS: Starts a 300Hz PWM applied on the high-side switches. duty_cycle_PWM_HS: Sets the duty cycle of an output PWM. read_fault: a function that updates the _MC33984_STATUS structure’s flag registers.

  • Page 88: Uart: Universal Asynchronous Receiver Transmitter

    Chapter 10 UART: Universal Asynchronous Receiver Transmitter 1. Introduction to UART Universal Asynchronous Receiver/Transmitter is a very common circuit used for serial communication between computer hardware, microcontrollers etc. It is at least made of an emitter write register, a receiver read register, two shift register (one for TX, one for RX), a clock source and a control logic around it.

  • Page 89: Configuration

    3. Configuration 3.1. Signal Configuration Following configurations are needed in the SIUL module. Output pads(Tx) need an output buffer, so the OBE bit SIUL’s pad configuration register is needed. Also the slew rate of the port might need improving so SRC bit should be set. For the input types the input buffer has to be enabled using IBE and also a pull up resistor is needed, so the internal pull up can be used by setting WPE and WPS.

  • Page 90: Uart Mode Configuration

    Here is the list of data fields relevant to the UART in the LIN control register 1 (LINCR1):  AWUM: Automatic Wake-Up Mode, when set, on activity on Rx or in internal transmit registers, the module goes automatically to the Normal mode, clearing SLEEP bit. ...

  • Page 91: Status Registers And Interrupt Configuration

    LFDIV is set using two registers: LINIBRR, the integer part of LFDIV and LINFBRR where the fractional part is encoded. LINIBRR contains the 13-bit field, DIV_M, which sets a mantissa between 1 and 8191. If DIV_M is set to 0, then the LINFlex clock is disabled. LINFBRR register contains a 4-bit DIV_F field where DIV_F = 16×...

  • Page 92: Data Transmit/Receive

    All the fields of this register can be cleared by writing ‘1’, and they are:  NF: Noise Flag, set when hardware detects noise on a receive channel.  DTF: Data Transmission Completed, set by the hardware when the number of bytes programmed in TDFL have been transmitted.

  • Page 93: Developing A General Purpose Uart Driver

    //must be called before using the driver enableIrq(); UART[0].init(UART_BAUD_9600, UART_FRAME_8N1); //Initialize UART module //Connect pins of PORT B to a serial interface of a PC UART[0].rprintf("Welcome to MPC5604B!\n\r",); //simple way for sending //messages to a PC serial terminal UART[0].rprintf("What do you want to do?\n\r1.PWM\n\r2.ADC",);); UART[0].read(RxData);...

  • Page 94: Using The Uart Driver For A Terminal Interface

    Similarly, an rscanf function was implemented for a scanf like function, reading input until a NUL character. 5. Using the UART Driver for a terminal interface UART can be used for providing a simple human-machine interface using an UART-USB adaptor (like an FTDI FTR232 or PL2303HX) and a free serial terminal like RealTerm.

  • Page 95: Adc Configuration

    5.3. ADC configuration ADC will be used in normal mode; a conversion will be made on a user request. As the system clock is 64MHz, we will set ADC to the maximum possible clock, 32MHz, with the minimum timing parameters given in the documentation. Only channel 0 connected to a potentiometer is configured, in normal, one-shot mode.

  • Page 96: Emios Configuration

    5.4. eMIOS configuration eMIOS will be configured to have an output PWM at a fixed frequency whose duty cycle can be easily altered. The channel 23 is configured as a buffered modulus counter, giving a 1kHz roll- over frequency. And the channel 22 is configured as OPWMB with a 50% duty cycle initially. A function for setting the duty cycle is implemented.
  • Page 97 The main function starts by initializing the system and configuring peripherals. UART driver is set as 9600 8N1. And then the program sends some welcome and information message and enters in an infinite loop of communication with a PC. The program waits for an ASCII message made of 3 strings separated by space characters, ending with a NUL character.

  • Page 98: Results

    ADC treatment’s detail: PWM treatment’s detail: 5.6. Results This example works as foreseen, basic commands are executed through a friendly user interface. One may even create a GUI exploiting COM port drivers to communicate with the device. Error management is really important in this kind of loops to avoid needing to reset the device.
  • Page 99 You can see a communication example below where unknown commands are dismissed and other ones correctly executed:...

  • Page 100: I²C: Inter-Integrated Circuit Bus Controller

    Chapter 11 I²C: Inter-Integrated Circuit Bus Controller 1. Presentation of I²C protocol 1.1. Description I²C is an half-duplex, two-wire, bidirectional, multi-master, multi-slave communication bus. It supports addressing, data acknowledging, detecting arbitration loss or busy bus and using multiple baud rates. Figure 104 : Physical Interface of I²C Bus Only masters can initiate a communication with a slave, either for transmitting or receiving, and most of the devices can switch between master and slave modes.

  • Page 101: Baud Rate

    The two wires on the bus are called SDA (Serial Data Line) and SCL (Serial Clock Line), once a transmission starts, slave devices synchronise on these signals, START, STOP, Data Change, Data Capture and ACKnowledge conditions are carefully chosen for avoiding glitches. START: SCL High, SDA Falling Edge, ACK: slave brings SDA to Low for the next clock pulse,...

  • Page 102: Pull-Up Resistor Calculation

    Therefore a pull-up resistor of 2.2kΩ is a good choice at this specifications. 2. Using the I²C module 2.1. Module Presentation There is only one I²C module in MPC5604B and it features pretty much every I²C features except for general call address and 10-bit addressing. These modules pins and signals are compatible...

  • Page 103: Module Registers

    with standard I²C bus specifications simply by setting open drain option for the SDA/SCL pads in SIUL. This module is designed to operate in Standard or Fast Mode I²C but it is capable of going at baud rates up to module_clock/20 as long as the bus can support it with the right pull-up device. This module brings simplicity in implementing I²C bus, electrical characteristics are met, different phases of the transfer like the start signal, stop signal, acknowledge and byte transfer are handled automatically.
  • Page 104  Address Setting The address of the module during the slave mode will be stored in the I²C Bus Address Register (IBAD) on the 7-bit field ADR.  Transfer setting For configuring various aspects of the module, I²C BUS Control Register (IBCR) can be used. Figure 107 : I²C Bus Control Register (R.M.

  • Page 105: Communication

     IAAS: Addressed as a slave. When a master’s calling address is matched with the address in the IBAD register, this flag is set.  IBB: Bus busy. When a START signal is detected, this flag is set and it is cleared when STOP is detected and bus gets into the idle state.
  • Page 106 This section will explain the practical use of this module. After system reset, the I²C module has to be initialised as follows:  Set SCL frequency from system clock using Frequency Divider Register (IBFD),  Define its slave address by setting I²C Bus Address Register ...

  • Page 107: Developing A General Purpose I²C Driver

    Figure 110 : Flow-chart of a typical I²C interrupt handler (R.M. Rev8 – Fig. 20-13) 2.4. Developing a general purpose I²C Driver A driver can be built for this module, similar to the one for DSPI or UART, building methods around the previous interrupt routine.

  • Page 108: Can: Controller Area Network

    Chapter 12 CAN: Controller Area Network 6. CAN protocol 1.1. Introduction Controller Area Network is a half-duplex serial protocol developed in the 80’s and evolved multiple times since then, becoming very popular in automotive and industrial applications. It was a particularly effective data bus for usage in vehicles by meeting real-time processing, reliability and bandwidth specifications.

  • Page 109: Frame Description

    1.2. Frame Description CAN protocol uses variable length frames (depending on data size or standard/extended ID) as data frames. Figure 112 : CAN 2.0A standard frame format The figure above shows different fields included in a frame. Here’s brief descriptions of some fields: ...

  • Page 110: Physical Layer

    When a device requests data from another by sending a frame with no data where RTR is recessive, that frame is called a remote frame. The device which is identified with this frame starts transmitting the requested data frame(with same ID). 1.3.

  • Page 111: Error Detection

    Figure 114 : Arbitration process with the use of dominant/recessive signals The advantage of using this king of dominant/recessive data is the simplification of arbitration. As it can be seen on the figure above, the first frame is transferred by the device n°2 where devices n°1 and n°3 have to wait and acknowledge using a dominant bit while device n°2 is emitting recessive.

  • Page 112: Bit-Rate And Sampling

    1.5. Bit-rate and sampling CAN controllers have a system clock that allow them to process registers, set outputs and read inputs. The period duration of this clock is called the time quantum �� and used as a base to �� transmit and receive frames.

  • Page 113: Flexcan Module Configuration

     Finding the number of quanta in the bit-time.  Finding the number of quanta in the propagation segment depending on the delay.  Check the parity of (bit_time – prop_seg – 1), and fix the number of quanta in Phase_Seg_1 and Phase_Seg_2 (ensuring Phase_Seg_2 >...

  • Page 114: Message Buffer Mode And Rx Fifo Mode

    The FlexCAN module is a CAN controller implementation with some enhancements over CAN 2.0B standard, with no transceiver (so the user is free to choose the communication medium). The block diagram above show different building blocks of this module, we can see that the CAN Controller itself is joined by a mailbox system that can either work as 64 message buffers or a 6 frame RX FIFO with 56 message buffers.
  • Page 115  PRIO: Local priority, for internal Tx arbitration, only used when LPRIO_EN is set, these extra 3 bits are appended to the ID (making 32-bit ID), for giving more possibilities over priority. MB’s with 000 PRIO have the highest priority. ...

  • Page 116: Rx Fifo Engine

    Message buffer data coherence mechanisms:  Deactivation: when the user tries to write to the Control & Status word of an MB, the MB will be excluded from the ongoing Tx/Rx arbitration/matching cycle. This will allow maintaining some data coherency but there still some situations where incoherencies can occur (see R.M Rev8, 22.4.7.2).

  • Page 117: Configuration Registers

    The MB zone of the FIFO is used for accessing frames. The engine automatically changes data read on MB depending on FIFO’s state. Reading data is similar to the MB structure, first the Control & Status word is read, then the ID field and the Data. The 8 words of the ID table can be used in four separate modes configurable in MCR register: A.
  • Page 118  HALT: if FRZ is set, the module enters into Freeze Mode. Message buffers and registers are accessible but no reception or transmission can be done. FlexCAN leaves Freeze Mode is this bit or FRZ bit is cleared.  NOT_RDY: read only; if set, then the module is in Disable or Freeze mode; else, it is in Normal, Listen-Only or Loop-Back mode.

  • Page 119: Status And Interrupt Registers

     PSEG1: Phase Segment 1; this field defines the number of quanta in Phase Segment 1 as PSEG1+1. Similarly for PSEG2 and PROPSEG.  BOFF_MSK is a mask for Bus Off interrupt. Set this bit for enabling the interrupt.  ERR_MSK is a mask for Error interrupt. Set this bit for enabling the interrupt. ...
  • Page 120 This register’s main fields are:  TWRN_INT: TX Warning Interrupt Flag; if WRN_EN bit is set in MCR, then this flag is raised whenever TX Error Counter goes from <96 to ≥ 96. If WRN_MSK bit is set in CTRL then an interrupt is generated. It is cleared by writing ‘1’. Similarly for RWRN_INT but for RX.

  • Page 121: Flexcan Usage Explained With An Example

    Overflow, BUF6I is FIFO Warning (FIFO almost full with 5 over 6 buffers being occupied). BUF5I: Frames available in FIFO (frames ready to be read). 8. FlexCAN usage explained with an example In this section, through an example program, we will explain how to initialise and configure FlexCAN correctly.

  • Page 122: Initialisation

    And the timer interrupt is at left; it transmits the counter ‘myData’ and increments it. LEDs are altered to alert the user. The transmissions will be made with an ID equal to 666 and receptions will be expected from an ID of 555. 8.1.

  • Page 123: Reception

    Every activated MB participates in an arbitration process where the highest priority message will be selected, depending on the user’s configuration. And eventually once the message is transmitted the CODE and TIME STAMP fields are updated and a flag is raised. Here is this program’s code for transmission: 8.3.

  • Page 124: Can Transceiver(Mcz33905S5Ek) Configuration

    9. CAN Transceiver(MCZ33905S5EK) Configuration The starter kit TRK-MPC5604B is equipped with a SBC (System Basis Chip) which also fulfils the role of a CAN transceiver for FlexCAN1 (or FlexCAN4, they both have the same pins). For this transceiver to work, this chip has to be powered up and put in debug mode for configuration.
  • Page 125 Other commands, not needed but related to CAN for special usage, are: 0x60C0: set CAN in TX/RX mode, fast slew rate, 0x6000: set CAN in sleep mode, wake up disabled, 0x6080: set CAN in sleep mode, wake up enabled, 0x6040: set CAN in receive only, 0x60D8: set CAN in TxRX mode, medium slew rate.

  • Page 126: Appendix 1 Using Code Warrior Ide

    Appendix 1 Using Code Warrior IDE There is a version of Freescale’s CodeWarrior development environment specifically made for MPC55xxx/MPC56xxx. It has a practical debug environment and some basic library for resetting the device, setting software INTC, mapping registers to the memory etc. For creating a new project first you have to select your device: Then you can select your project’s name and location and you should select C language, with unsigned chars and VLE.
  • Page 127 When your project is created, you have a basic main program loop with minimal microprocessor libraries included in the project. You should quickly change the project target from RAM to internal_Flash and update the register memory mapping header file from “MPC5604B_M27V.h” to “MPC5604B_0M27V_102.h”...
  • Page 128 means higher chances of undefined behaviour if you didn’t use volatile variables where you should have). While programming, you will need a lot of peeking into the “MPC5604B_0M27V_102.h” file, because it contains registers’ mapping. For instance the ADC MCR register is defined by the reference manual as: This is implemented in that file as a structure:...
  • Page 129 Each peripheral is defined as a structure in this case it is ADC_tag, and then memory is mapped following the offset mentioned in the reference manual. MCR’s offset is zero so it is directly located at the beginning of the ADC_tag structure. It is defined as a union of a 32-bit register and a total 32-bit bit-field made of different fields of the register.
  • Page 130 If device is not found, ensure that it is connected and then press Refresh List. For starting the debugger you’ll have to click Connect (Reset). It will start by initialising the debugger and the download the code and data to the flash. Debugger while the flash is being programmed: Once the debugger is initialised, status window will tell you to use ‘gotil main’...
  • Page 131 In the green box you can see moving commands on the high level code, the one on the left will make a single step in the high level code, the middle one will make multiple steps at a slow pace, updating all register and variable information on the debugger, and the last one will execute the program at its normal speed.

  • Page 133: Appendix 2 Pad Configurations

    Appendix 2 Pad Configurations...

  • Page 141: Appendix 3 Peripheral Input Pin Selection

    Appendix 3 Peripheral input pin selection...

  • Page 143: Appendix 4 Interrupt Vector Table

    Appendix 4 Interrupt Vector Table...

  • Page 148: Appendix 5 I²C Baud Rate Prescaler Values

    Appendix 5 I²C Baud Rate Prescaler Values...

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