Freescale Semiconductor MPC5553 Reference Manual

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Freescale Semiconductor

MPC5553/5554 Microcontroller

Reference Manual

by: Microcontroller Solutions Group

This is the MPC5553/5554 Microcontroller Reference Manual set consisting of the following files:

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MPC5553/5554 Reference Manual Addendum, Rev 3

•

MPC5553/5554 Microcontroller Reference Manual, Rev 5

MPC5553_MPC5554_RM

Rev. 5.1, 03/2012

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Summary of Contents for Freescale Semiconductor MPC5553

Page 1 MPC5553_MPC5554_RM Rev. 5.1, 03/2012 MPC5553/5554 Microcontroller Reference Manual by: Microcontroller Solutions Group This is the MPC5553/5554 Microcontroller Reference Manual set consisting of the following files: • MPC5553/5554 Reference Manual Addendum, Rev 3 • MPC5553/5554 Microcontroller Reference Manual, Rev 5 © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 2 MPC5553_MPC5554_RM. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com/ for the latest updates. The current version available of the MPC5553/5554 Microcontroller Reference Manual is Revision 5. © Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
Page 3: Errata For Revision 5
Table 2. Revision History Table Rev. Number Substantive Changes Date of Release Changes in Rev. 1 of this errata have been incorporated in MPC5553/5554 10/2009 Reference Manual Rev. 5. Not publicly released. Changes in Rev. 2 of this errata have been incorporated —...
Page 4 MPC5553/5554 Microcontroller Reference Manual Devices Supported: MPC5553 MPC5554 MPC5553_MPC5554_RM Rev. 5 December 2011 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 5 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 6: Table Of Contents
1.5.22 Calibration Bus (MPC5553 Only) ........
Page 7 3.2.2 Core-Specific Registers ..........3-10 3.2.3 e200Z6 Core Complex Features Not Supported in the MPC5553/MPC5554 ..3-11 Functional Description .
Page 8 6.3.1 Register Descriptions ........... 6-8 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 9 External Signal Description ........... . . 9-3 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 10 10.6 Revision History ............10-43 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 11 13.1.1 Block Diagram ............13-1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 12 14.4.12Collision Handling ........... 14-45 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 13 16.4 Revision History ............16-15 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 14 18.1 Introduction ..............18-1 18.1.1 The MPC5553/MPC5554 eTPU Implementation ......18-1 18.1.2 Block Diagram .
Page 15 20.3.1 Memory Map ............20-6 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 16 21.4.9 Interrupt Operation ..........21-33 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 17 23.5.2 Recommended Power Transistors ........23-5 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 18 25.6.2 Register Descriptions ..........25-14 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 19 25.15 Revision History ............25-89 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 20 B.3.1 MPC5554 Calibration Bus Implementation ....... . . B-5 B.3.2 MPC5553 Calibration Bus Implementation ....... . . B-5 B.4 Signals and Pads .
Page 21: Mpc5553/Mpc5554 Microcontroller Reference Manual,
MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 22: Introduction
64-kilobyte internal SRAM and internal flash memory (2 MB flash in the MPC5554, 1.5 MB in the MPC5553). Both the internal SRAM and the flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family.
Page 23 SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. The MPC5553 has a fast Ethernet controller (FEC) with a built-in FIFO and a DMA controller. Figure 1-1...
Page 24 – Enhanced queued analog/digital converter eSCI – Enhanced serial communications interface eTPU – Enhanced time processing units FMPLL – Frequency modulated phase-locked loop SRAM – Static RAM Figure 1-1. MPC5554 Block Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 25 – Enhanced queued analog/digital converter eSCI – Enhanced serial communications interface eTPU – Enhanced time processing units FMPLL – Frequency modulated phase-locked loop SRAM – Static RAM Figure 1-2. MPC5553 Block Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 26: Features
— Branch processing unit — Fully pipelined load/store unit — 32 kilobyte unified cache (in the MPC5554), 8 kilobyte unified cache (in the MPC5553) with line locking – 8-way set associative in the MPC5554, 2-way set associative in the MPC5553 –...
Page 27 • System bus crossbar switch (XBAR) — 3 master ports in the MPC5554, 4 master ports in the MPC5553; 5 slave ports — 32-bit address bus, 64-bit data bus — Simultaneous accesses from different masters to different slaves (there is no clock penalty when a parked master accesses a slave) •...
Page 28 – Programmable timeout period (with 8 external bus clock resolution) — Chip selects – In both the MPC5553 and MPC5554, four chip select (CS[0:3]) signals; but the MPC5553 has no CS signals in the 208 MAPBGA package. – In the MPC5553 only, support for dynamic calibration with up to three calibration chip selects (CAL_CS[0] and CAL_CS[2:3]) —...
Page 29 (used for EEPROM emulation and data calibration) — 20 blocks (MPC5554) or 16 blocks (MPC5553) with sizes ranging from 16 Kbytes to 128 Kbytes to support features such as boot block, operating system block, and EEPROM emulation —...
Page 30 — DMA and interrupt request support — Supports all functional modes from QADC (MPC5xx family) • Four (MPC5554) or three (MPC5553) deserial serial peripheral interface modules (DSPI) — SPI – Full-duplex communication ports with interrupt and eDMA request support – Supports all functional modes from QSPI submodule of QSMCM (MPC5xx family) –...
Page 31 — DMA support — Interrupt request support • Three (MPC5554) or two (MPC5553) FlexCANs — 64 message buffers each — Full implementation of the CAN protocol specification, Version 2.0B — Based on and including all existing features of the Freescale TouCAN module —...
Page 32: Mpc5553-Specific Modules
— Provides initial reset condition up to the voltage at which pins (RESET) can be read safely. It does not guarantee the safe operation of the chip at specified minimum operating voltages. MPC5553-Specific Modules The MPC5553 has two modules not found on the MPC5554, a fast Ethernet controller (FEC) module and a calibration bus: •...
Page 33: Mpc5500 Family Comparison
MPC5500 Family Comparison Table 1-1. MPC5500 Family Members MPC5500 Device MPC5533 MPC5534 MPC5553 MPC5554 MPC5565 MPC5566 MPC5567 Power Architecture Core e200z3 e200z3 e200z6 e200z6 e200z6 e200z6 e200z6 Variable Length Instruction Support Cache None None Unified Unified Unified Unified Unified Memory Management Unit (MMU)
Page 34: Detailed Features
The following sections provided detailed information about each of the on-chip modules. 1.5.1 e200z6 Core Overview The MPC5553 and MPC5554 use the e200z6 core explained in detail in the e200z6 PowerPC Core Reference Manual. The e200z6 CPU utilizes a seven stage pipeline for instruction execution. The...
Page 35: System Bus Crossbar Switch
The system bus’s XBAR multi-port crossbar switch supports simultaneous connections between three(MPC5554) or four (MPC5553) master ports and five slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width at all master and slave ports.
Page 36: Edma
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 64 (MPC5554) or 32 (MPC5553) programmable channels, with minimal intervention from the CPU. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
Page 37: Ecsm
1.5 Mbytes of flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The MPC5553/MPC5554 flash also contains a flash bus interface unit (FBIU) that interfaces the system bus to a dedicated flash memory array controller. The FBIU supports a 64-bit data bus width at the system bus port, and a 256-bit read data interface to flash memory.
Page 38: Sram
Serial boot loading (a program is downloaded into RAM via eSCI or the FlexCAN and then executed). The BAM also reads the reset configuration halfword (RCHW) from flash memory (either internal or external) and configures the MPC5553 and MPC5554 hardware accordingly. 1.5.13 eMIOS The enhanced modular I/O system (eMIOS) module provides the functionality to generate or measure time events.
Page 39: Eqadc
The channels and register content are transmitted using a SPI-like protocol. There are four identical DSPI modules (DSPI_A, DSPI_B, DSPI_C, and DSPI_D) on the MPC5554 MCU. The MPC5553 has three DSPI modules (DSPI_B, DSPI_C, and DSPI_D).
Page 40: Flexcan
The JTAGC module is compliant with the IEEE 1149.1-2001 standard. 1.5.21 FEC (MPC5553 Only) The fast Ethernet controller (FEC) of the MPC5553 supports several standard MAC-PHY interfaces to connect to an external Ethernet transceiver: • 10/100 Mbps MII interface •...
Page 41: Calibration Bus (Mpc5553 Only)
As a general rule, when a feature is added bit field will need a non-zero value to activate it. Reserved memory also may be used in future family members. These areas should not be used if reserved. Table 1-2 shows a detailed memory map. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 1-20 Freescale Semiconductor...
Page 42 Table 1-2. Detailed MPC5554/MPC5553 Family Memory Map Allocated Size Used Size Address Range (bytes) (bytes) 0x0000_0000–0x001F_FFFF 2 Mbytes 2 Mbytes FLASH Memory Array (MPC5554) (MPC5554) 0x0000_0000–0x0017_FFFF 1.5 Mbytes (MPC5553) (MPC5553) 0x0020_0000–0x00FF_FBFF (14 Mbytes - Reserved (MPC5554) 1 Kbyte) 0x0018_0000–0x00FF_FBFF (MPC5554) (MPC5553) (14.5 Mbytes -...
Page 43 Table 1-2. Detailed MPC5554/MPC5553 Family Memory Map (Continued) Allocated Size Used Size Address Range (bytes) (bytes) 0xC3FC_C000–0xC3FC_FFFF 16 Kbytes 3 Kbytes eTPU Shared Data Memory (Parameter RAM) mirror (MPC5554) 2.5 Kbytes (MPC5553) 0xC3FD_0000–0xC3FD_3FFF 16 Kbytes 16 Kbytes eTPU Shared Code RAM...
Page 44: Multi-Master Operation Memory Map
BAM address range is configured so that 4Kbyte BAM occupies 0xFFFF_F000–0xFFFF_FFFF Multi-Master Operation Memory Map When the MPC5553/MPC5554 MCU acts as a slave in a multi-master system, the external bus interface (EBI) translates the 24-bit external address to a 32-bit internal address.
Page 45 The shadow row of the slave FLASH is not accessible by an external master. Table 1-5 shows the memory map for the MPC5553 and MPC5554 family MCU configured as a master in multi-master system with another MPC5500 family MCU acting as the slave.
Page 46: Revision History
• Added wording for Power Architecture throughout chapter. Removed PowerPC terminology. • In Features List, added section for Calibration interface • In Features List, beefed up the section titled “MPC5553-Specific Modules” by adding more information about the FEC. • In the MPC5553-Specific Modules section, added a section titled “Calibration Bus”...
Page 47 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 1-26 Freescale Semiconductor...
Page 48: Block Diagram
Chapter 2 Signal Description This chapter describes the signals of the MPC5553 and the MPC5554 that connect off chip. It includes a table of signal properties, detailed descriptions of signals, and the I/O pin power/ground segmentation. Block Diagram Figure 2-1...
Page 49 SSSYN GPIO[100]_SOUTD_PCSA[4] (not available on the 208 package) POWER/ DSPI FLASH GPIO[101]_PCSB[3]_PCSA[5] GROUND GPIO[102]_PCSC[1]_SCKB STBY GPIO[103]_PCSC[2]_SINB GPIO[104]_PCSC[5]_SOUTB DDEn GPIO[105]_PCSD[2]_PCSB[0] DDEHn GPIO[106]_PCSD[0]_PCSB[1] DD33 GPIO[107]_SOUTC_PCSB[2] (GND) GPIO[108]_SINC_PCSB[3] GPIO[109]_SCKC_PCSB[4] GPIO[110]_PCSC[0]_PCSB[5] Figure 2-1. MPC5553 Signal Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 50 DAN2+_AN[4] SSSYN DAN2-_AN[5] FLASH DAN3+_AN[6] DAN3-_AN[7] STBY POWER/ ANW_AN[8] GROUND ANX_AN[9] DDEHn ANY_AN[10] eQADC DDEn ANZ_AN[11] DD33 SDS_MA[0]_AN[12] SDO_MA[1]_AN[13] SSAn SDI_MA[2]_AN[14] DDAn FCK_AN[15] (GND) AN[16:39] ETRIG[0:1]_GPIO[111:112] REFBYPC Figure 2-2. MPC5554 Signal Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 51: External Signal Description
This section summarizes the external signal functions, their static electrical characteristics, and pad configuration settings for this device. Table 2-1 gives a summary of the MPC5553 external signals, and Table 2-2 provides a summary of the MPC5554 external signals. The signal properties and their electrical characteristics are set in the system integration unit (SIU) pad configuration registers (PCR).
Page 52: Mpc5553 Signals Summary
2.2.1 MPC5553 Signals Summary Table 2-1 gives a summary of the MPC5553 external signals and properties. Table 2-1. MPC5553 Signal Properties Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset Reset / Configuration Signals...
Page 53 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset AA4, AA3, AB4, AC3, AC5, T3, U3:4, AB3, U1, AB5, T3, V2, V1, T2, T1, P1:2, W2, W1,...
Page 54 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset DATA[20]_ External Data Bus FEC_TXD[0]_ Ethernet Transmit Data – / Up – / Up — — DDE3...
Page 55 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset RD_WR_ External Data Bus Read/Write – / Up – / Up — DDE2 GPIO[62] General Purpose I/O...
Page 56 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset MSEO / G24, F23, E16, MSEO[1:0] Nexus Message Start/End Out O / High G21:22 DDE7 High Nexus Ready Output...
Page 57 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset SCKA_ — — — PCSC[1]_ DSPI C Peripheral Chip Select – / Up – / Up —...
Page 58 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset PCSB[3]_ DSPI B Peripheral Chip Select SINC_ DSPI C Data Input – / Up – / Up...
Page 59 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset AN[15]_ Single-ended Analog Input A, M I / – AN[15] / – DDEH9 eQADC Free Running Clock...
Page 60 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset ETPUA[12]_ eTPU A Channel – / – / PCSB[1]_ DSPI B Peripheral Chip Select DDEH1 WKPCFG WKPCFG...
Page 61 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset eMIOS Signals AD17, AF15, AB10:11, AD21, AE15, T4:5, AC16, AA11, R22, AD15, AB12, EMIOS[0:9]_ eMIOS Channel – / –...
Page 62 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset Power / Ground Signals Voltage Regulator Control 3.3 V I / – AD26 AC25 RC33 DDINT RC33 3.3 V Supply...
Page 63 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset Flash Program/Erase Supply 5.0 V I / – DDINT Input Internal SRAM Standby Power 1.0 V I / –...
Page 64 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset G26, G27, H26, C25, C23, B21, C24, B26, A23, C25, C22, D24, A20, E23, B26, A24, K14,...
Page 65 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset AF22, AG22, AG23, AH23, AD17, AD21, R22, AD18, AD22 P22, AD19 N21, External I/O Supply Input 3.3–5.0 V —...
Page 66 Table 2-1. MPC5553 Signal Properties (Continued) Status Pin Labels / Package Type Signal Name Signal Functions Voltage During After Type Type Reset Reset AA27, W26, AB27, AA26, Y28, AB26, AB24, AA24, W24, Y26, V24, U26, Y27, Y24, External I/O Supply Input 3.3–5.0 V...
Page 67 AD23 Because more than one signal is often multiplexed to one pin, each line in the signal name column is a separate function. For all MPC5553 I/O pins the selection of the primary pin function, alternate function, or GPIO is determined in the SIU_PCR registers.
Page 68 Because the CBI and the EBI share the same external bus, TS is used for both the CBI and the EBI. The BR and BG functions are not implemented on the MPC5553 and are replaced by FEC and calibration functions. The pin name on the ball map, however, does remain BR and BG.
Page 69: Mpc5554 Signals Summary
V DD33 The pins are reserved for the clock and inverted clock outputs for the DDR memory interface. In the MPC5553 416-pin package, the two NC pins are isolated (not shorted together in the package substrate).
Page 70 General Purpose I/O External Transfer Acknowledge – / Up – / Up DDE2 GPIO[70] General Purpose I/O TEA_ External Transfer Error Acknowledge – / Up – / Up DDE2 GPIO[71] General Purpose I/O MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-23...
Page 71 – / Up AG23 AF22 DDEH4 GPIO[85] General Purpose I/O CNRXB_ FlexCAN B Receive PCSC[4]_ DSPI C Peripheral Chip Select – / Up – / Up AH23 AF23 DDEH4 GPIO[86] General Purpose I/O MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-24 Freescale Semiconductor...
Page 72 – / Up – / Up DDEH6 GPIO[87] General Purpose I/O CNRXC_ FlexCAN C Receive PCSD[4]_ DSPI D Peripheral Chip Select – / Up – / Up DDEH6 GPIO[88] General Purpose I/O MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-25...
Page 73 – / Up – / Up DDEH6 GPIO[102] General Purpose I/O SINB_ DSPI B Data Input PCSC[2]_ DSPI C Peripheral Chip Select – / Up – / Up DDEH6 GPIO[103] General Purpose I/O MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-26 Freescale Semiconductor...
Page 74 DAN3– Negative Differential Analog Input AN[8]_ Single-Ended Analog Input I / – AN[8] / – DDA1 MUX Input AN[9]_ Single-Ended Analog Input I / – AN[9] / – DDA1 MUX Input MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-27...
Page 75 GPIO[111:112] General Purpose I/O Voltage Reference High – / – DDINT DDA0 Voltage Reference Low – / – SSINT DDA0 REFBYPC Reference Bypass Capacitor Input – / – REFBYPC DDA0 DDINT MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-28 Freescale Semiconductor...
Page 76 External Interrupt Request DDEH1 WKPCFG WKPCFG GPIO[141] General Purpose I/O ETPUA[28]_ eTPU A Channel (Output Only) – / – / PCSC[1]_ DSPI C Peripheral Chip Select DDEH1 WKPCFG WKPCFG GPIO[142] General Purpose I/O MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-29...
Page 77 A19, ETPUB[20:31]_ eTPU B Channel – / – / B18, E17, B18, C18, DDEH8 GPIO[167:178] General Purpose I/O WKPCFG WKPCFG E22, B19, A20, B19, C18, E21, D19, E23, C19 C19, B20 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-30 Freescale Semiconductor...
Page 78 AA26 DDSYN EXTCLK External Clock Input CLKOUT / CLKOUT / CLKOUT System Clock Output AF25 AE24 DDE5 Enabled Enabled ENGCLK/ ENGCLK / ENGCLK Engineering Clock Output AG26 AF25 DDE5 Enabled Enabled MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-31...
Page 79 AG24, AD22, DDE5 AH24 AE23, AF24 C27, D26, B26, C25, F24, H22, D24, E23, J21, L15:18, External I/O Supply Input 1.8–3.3 V N.A. K14:17, DDE7 M11, M18, L17, M17, N11:13, N17, MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-32 Freescale Semiconductor...
Page 80 External I/O High Supply Input – N.A. 5.0 V DDEH DDEH10 DDEH10 B26, D2, C1, U4, 3.3v I/O SUPPLY Input 3.3 V N.A. W5, AE27, AD9, DD33 DD33 DD33 A25, AD26 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-33...
Page 81 This segment is labelled V DDE2 DDE3 DDE2 in the BGA map. Refer to Table 2-3 for a definition of the I/O pins that are powered by each segment. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-34 Freescale Semiconductor...
Page 82 The No Connect (NC) pins are reserved for the clock and inverted clock outputs for the DDR memory interface. In the MPC5554 416-pin package, the two No Connect (NC) pins are isolated (not shorted together in the package substrate). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 83: Detailed Signal Description
2.3.1.1 External Reset Input RESET The RESET input is asserted by an external device to reset the all modules of the MPC5553/MPC5554 MCU. The RESET pin must be asserted during a power-on reset. Refer to Section 4.2.1, “Reset Input (RESET).”...
Page 84: External Bus Interface (Ebi) Signals
Refer to the previous and following functions. The alternate function is used for the calibration bus addressing and is only available on the MPC5553. The calibration function is not available on the MPC5554. These pins can be used as GPIO signals.
Page 85: External Data Signals
2.3.3 External Data Signals The MPC5553/MPC5554 can be configured for 16-bit or 32-bit data bus operation. 2.3.3.0.1 External Data / GPIO DATA[0:15]_GPIO[28:43] DATA[0:15]_GPIO[28:43] are the EBI data signals. For 16-bit data bus operation, the data signals can be divided into 0 through 7 for data, and 28 through 35 GPIO. These pins can be used as GPIO signals.
Page 86 FEC or calibration function can be used, but not both. The FEC and calibration functions are not available on the MPC5554. This pin can be used as a GPIO signal. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-39...
Page 87 The FEC receive data signal is the first alternate function, and the calibration data function is the second alternate function. This pin can also be used as a GPIO signal. The FEC and calibration signals are MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-40...
Page 88 TSIZ[0:1]_GPIO[60:61] indicates the size of an external bus transfer when in external master operation or in slave mode. The TSIZ[0:1] signals are not driven by the EBI in single master operation. The TSIZ[0:1] signal function is not available on the MPC5553. These pins can also be used as GPIO signals for the MPC5554 only.
Page 89 (CBI) shares the bus with the external bus interface (EBI), the TS primary function is also used for the calibration transmit start function. The MPC5554 does not use the calibration bus. This pin can be used as a GPIO signal on either the MPC5553 or MPC5554. 2.3.3.7...
Page 90: Nexus Signals
BB_GPIO[74] BB_GPIO[74] has a primary function of BB that indicates the external bus interface (EBI) is busy. The BB_GPIO[74] signal function is not available on the MPC5553. This pin can be used as a GPIO signal for the MPC5554 only.
Page 91: Jtag Signals
The JCOMP pin is used to enable the JTAG TAP controller. 2.3.5.6 Test Mode Enable Input TEST Use the TEST signal to place the chip in test mode. The TEST signal must be negated for normal operation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-44 Freescale Semiconductor...
Page 92: Flexcan Signals
CNRXB_PCSC[4]_GPIO[86] has a primary signal function of FlexCAN B receive for the FlexCAN B module and is only available on the MPC5554. Because the MPC5553 has FlexCAN A and C only, the FlexCAN B signal function CNRXB is not available on the MPC5553. The alternate signal function is a peripheral chip select output for the DSPI C module.
Page 93: Esci Signals
SCKA_PCSC[1]_GPIO[93] has a primary signal function of the DSPI clock SCKA for the DSPI A module and is only available on the MPC5554. Because the MPC5553 does not have a DSPI A module, the primary signal function SCKA is not available on the MPC5553. The peripheral chip select PCSC[1] for the DSPI C module is the alternate signal function.
Page 94 PCSA[1]_PCSB[2]_GPIO[97] has a primary signal function of PCSA[1] that is a peripheral select output for the DSPI A module for the MPC5554. Because the MPC5553 does not have a DSPI A module, the primary signal function PCSA[1] is not available on the MPC5553. The peripheral chip select output for the DSPI B module PCSB[2] is the alternate signal function.
Page 95 MPC5554. Because the MPC5553 does not have a DSPI A module, the primary signal function PCSA[5] is not available on the MPC5553. The SPI output for the DSPI B module is the alternate function. This pin can also be used as a GPIO signal.
Page 96: Eqadc Signals
Analog Input / Differential Analog Input AN[3]_DAN1– AN[3] is a single-ended analog input to the two on-chip ADCs. DAN1– is the negative terminal of the differential analog input DAN1 (DAN1+ to DAN1–). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-49...
Page 97 AN[12]_MA[0]_SDS is an analog input pin. The alternate function, MA[0], is a MUX address pin. SDS is the serial data strobe for the eQADC SSI; select this function by setting the PA field of SIU_PCR215 to MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-50...
Page 98 AN[16:39] are analog input pins. 2.3.9.18 External Trigger / GPIO ETRIG[0:1]_GPIO[111:112] ETRIG[0:1]_GPIO[111:112] are external trigger input pins for the eQADC. 2.3.9.19 Voltage Reference High is the voltage reference high input pin for the eQADC. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-51...
Page 99: Etpu Signals
. The value of this capacitor should be 100 nF. 2.3.10 eTPU Signals The MPC5553 and MPC5554 support eTPU A signals. Only the MPC5554 supports eTPU B signals. 2.3.10.1 eTPU A TCR Clock / External Interrupt Request / GPIO TCRCLKA_IRQ[7]_GPIO[113] TCRCLKA_IRQ[7]_GPIO[113] is the TCR A clock input for the eTPU module.
Page 100 2.3.10.11 MPC5554: eTPU B Channel / GPIO ETPUB[20:31]_GPIO[167:178] ETPUB[20:31]_GPIO[167:178] are input/output channel pins for the eTPU B module. These pins can be used by the MPC5554 as GPIO signals. ETPUB signal functions are not available on the MPC5553. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 101: Emios Signals
2.3.12 GPIO Signals 2.3.12.1 GPIO EMIOS[14:15]_GPIO[203:204] The EMIOS[14:15]_GPIO[203:204] pins’ primary function is EMIOS[14:15]. When configured as EMIOS[14:15], the balls function as output channels for the eMIOS module. Because other balls already MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-54 Freescale Semiconductor...
Page 102: Clock Synthesizer Signals
CLKOUT is an MPC5553/MPC5554 system clock output. 2.3.13.4 Engineering Clock Output ENGCLK ENGCLK is a 50% duty cycle output clock with a maximum frequency of the MPC5553/MPC5554 system clock divided by two. ENGCLK is not synchronous to CLKOUT. 2.3.14 Power/Ground Signals 2.3.14.1 Voltage Regulator Control Supply Input...
Page 103 SRAM during STBY power down. If V is not used, tie V to V STBY STBY 2.3.14.11 Internal Logic Supply Input is the 1.5 V logic supply input. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-56 Freescale Semiconductor...
Page 104: I/O Power/Ground Segmentation
2.3.15 I/O Power/Ground Segmentation Table 2-3 gives the preliminary power/ground segmentation of the MPC5553 MCU. Table 2-4 gives the preliminary power/ground segmentation of the MPC5554 MCU. Each segment provides the power and ground for the given set of I/O pins and can be powered by any voltage within the allowed voltage range regardless of the power on the other segments.
Page 105 DDEH8 3.3–5.0 V AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, AN[15]_FCK DDEH9 SCKB_PCSC[1]_GPIO[102], SINB_PCSC[2]_GPIO[103], DDEH10 3.3–5.0 V SOUTB_PCSC[5]_GPIO[104], PCSB[0]_PCSD[2]_GPIO[105], PCSB[1]_PCSD[0]_GPIO[106], PCSB[2]_SOUTC_GPIO[107] 1.8–3.3 V CS[0]_ADDR[8]_GPIO[0], CS[1:3]_ADDR[9:11]_GPIO[1:3], DDE2 ADDR[8:11]_CAL_ADDR[27:30]_GPIO[4:7], ADDR[8:31]_GPIO[4:27], RD_WR_GPIO[62], BDIP_GPIO[63], WE/BE[0:1]_GPIO[64:65], WE/BE[2:3]_CAL_WE/BE[0:1]_GPIO[66:67], TS_GPIO[69], TA_GPIO[70], TEA_CAL_CS[0]_GPIO[71] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-58 Freescale Semiconductor...
Page 106 The BR and BG functions are not implemented on the MPC5553 and are replaced by FEC and calibration functions. The pin name on the ball map, however, does remain BR and BG. The primary functions for these pins are CAL_ADDR[10] and CAL_ADDR[11], respectively.
Page 107 TDO, TMS, JCOMP, TEST 5.0 V AN[22:35], V REFBYPC DDA0 5.0 V AN[0]_DAN0+, AN[1]_DAN0-, AN[2]_DAN1+, AN[3]_DAN1-, AN[4]_DAN2+, DDA1 AN[5]_DAN2-, AN[6]_DAN3+, AN[7]_DAN3-, AN[8]_ANW, AN[9]_ANX, AN[10]_ANY, AN[11]_ANZ, AN[16:21], AN[36:39] — SSA0 — SSA1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-60 Freescale Semiconductor...
Page 108: Etpu Pin Connections And Serialization
Table 2-5. Although not shown in Figure 2-5, the output channels of ETPUA[12:15] are connected to the ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117] pins. The eTPU TCRA clock input is connected to an external pin only. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-61...
Page 109 • • • IN 4 IN 13 IN 14 IN 3 DSPI C Figure 2-5. ETPUA[0:15]—DSPI C I/O Connections Table 2-5. ETPUA[0:15]—DSPI C I/O Mapping DSPI C Serialized eTPU A Channel Output Input MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-62 Freescale Semiconductor...
Page 110: Etpua[16:31]
Figure 2-7. ETPUA[24:29] — DSPI B and DSPI D I/O Connections Table 2-6. ETPUA[16:31] — DSPI B I/O Mapping DSPI B Serialized eTPU A Channel Output eTPU A Channel Input Inputs / Outputs MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-63...
Page 111 This allows the input and output of those channels to be connected to different pins. The outputs of ETPUB[16:31] are multiplexed on the ETPUB[0:15] pins. The outputs of ETPUB[0:7] are multiplexed on the EMIOS[16:23] pins so that the output channels of ETPUB[0:7] can MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 2-64 Freescale Semiconductor...
Page 112 IN 8 IN 7 IN 0 DSPI A Figure 2-8. ETPUB[31:0] — DSPI A I/O Connections Table 2-8. ETPUB[0:15] — DSPI A I/O Mapping DSPI A Serialized eTPU B Channel Output Inputs MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 2-65...
Page 113: Emios Pin Connections And Serialization
Inputs eMIOS Pin Connections and Serialization The eMIOS channels connect to external pins or may be serialized in and out of the MPC5553/MPC5554. The input and output channels of EMIOS[0:11, 16:23] connect to pins. Only the output channels of EMIOS[12:15] connect to pins. The output channels of EMIOS[10:13] may be serialized out, and the inputs of EMIOS[12:15] may be serialized in.
Page 114: Revision History
• Added the word ‘internal’ to the note in the Reset Output (RSTOUT) signal description to read ‘During an internal power-on-reset (POR), RSTOUT is tri-stated.’ • Combined MPC5554 and MPC5553 detailed signal function descriptions using conditional text. • Changed Table 2-3 Table 2-4 to comply with the MPC556X model.
Page 115 • Reconciled all footnotes with those in the MPC556X devices. • Footnote 6 of the previous manual became Footnote 10 of MPC5553, and it was changed to read: “BOOTCFG[0] is not available and will always be read as 0 in the 208 package of the MPC5553”...
Page 116: Introduction
Core Complex Introduction The core complex of the MPC5553/MPC5554 consists of the e200z6 core, a 32 Kbyte (MPC5554) or an 8 kilobyte (MPC5553) unified cache memory, a 32-entry memory management unit (MMU), a Nexus Class 3 block, and a bus interface unit (BIU). The e200z6 core is the central processing unit (CPU) in the MPC5553/MPC5554.
Page 117: Block Diagram
Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch target address cache to allow single-cycle branches in many cases. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 118: Features
Instruction buffer holds up to 6 sequential instructions • Dedicated PC incrementer supporting instruction prefetches • Branch target address cache with dedicated branch address adder, and branch lookahead logic supporting single cycle execution of successful lookahead branches MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 119 • Linefill buffer • 32-bit address bus plus attributes and control • Separate unidirectional 64-bit read data bus and 64-bit write data bus • Supports cache line locking • Supports way allocation MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 120: Microarchitecture Summary
32-bits and the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, divide, compare, and conversion operations are provided, and most operations can be pipelined. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 121: Core Registers And Programmer's Model
The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 122 1 - These e200z6-specific registers may not be supported by other Power Architecture processors L1CFG0 SPR 515 L1FINV0 SPR 1016 2 - Optional registers defined by the Power Architecture embedded category Figure 3-2. Supervisor Mode Programmer’s Model MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 123: Power Architecture Registers
• The time base facility (TB) consists of two 32-bit registers: time base upper (TBU) and time base lower (TBL). These two registers are accessible in a read-only fashion to user-level software. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 124 CSRR1 is used to save machine state on a critical interrupt, and stores the MSR register contents. The MSR value is restored when an rfci instruction is executed at the end of a critical class interrupt routine. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 125: Core-Specific Registers
L1 Unified cache. 3.2.2.2 Supervisor-Level Registers The following supervisor-level registers are defined in e200z6 core in addition to the Power Architecture embedded category registers described above: • Configuration registers MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 3-10 Freescale Semiconductor...
Page 126: E200Z6 Core Complex Features Not Supported In The Mpc5553/Mpc5554
More details about these registers can be found in the e200z6 core reference. 3.2.3 e200Z6 Core Complex Features Not Supported in the MPC5553/MPC5554 The MPC5553/MPC5554 implements a subset of the e200z6 core complex features. The e200z6 core complex features that are not supported in the MPC5553/MPC5554 are described in Table 3-1.
Page 127 Table 3-1. e200z6 Features Not Supported in the MPC5553/MPC5554 Core Description Function / Category These events are disabled: External Debug Event (DEVT2) Unconditional Debug Event (UDE) The e200z6 Core Halted State and Stopped State are not Power Management supported. The following low power modes are not supported:...
Page 128: Functional Description
MSR[DS], is compared to the appropriate number of bits of the EPN field and the TS field of TLB entries. If the contents of the effective address plus the address space bit matches the EPN field and TS bit MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 129 Effective Page Address Offset n–1 n Virtual Address multiple-entry RPN field of matching entry Real Page Number Offset n–1 n 32-bit Real Address Figure 3-5. Effective to Real Address Translation Flow MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 3-14 Freescale Semiconductor...
Page 130 (ISI or DSI). Access Granted MSR[PR] Instruction Fetch TLB_entry[UX] TLB_entry[SX] Load-class Data Access TLB_entry[UR] TLB_entry[SR] Store-class Data Access TLB_entry[UW] TLB_entry[SW] Figure 3-6. Granting of Access Permission MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 3-15...
Page 131 Field VALID IPROT — — TSIZE — Undefined on Power Up  Unchanged on Reset Reset SPR 625 Figure 3-8. MMU Assist Register 1 (MAS1) MAS1 fields are defined in Table 3-4. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 3-16 Freescale Semiconductor...
Page 132 Figure 3-9. MMU Assist Register 2 (MAS2) MAS2 fields are defined in Table 3-5. Table 3-5. MAS2—EPN and Page Attributes Bits Name Description 0–19 Effective page number 20–26 — Reserved, should be cleared. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 3-17...
Page 133 Only bits that correspond to a page number are valid. Bits that represent offsets within a page are ignored and should be zero. 20–21 — Reserved, should be cleared. 22–25 U0–U3 User bits 26–31 PERMIS Permission bits (UX, SX, UW, SW, UR, SR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 3-18 Freescale Semiconductor...
Page 134 15 16 Field — SPID — Undefined on Power Up  Unchanged on Reset Reset SPR 630 Figure 3-12. MMU Assist Register 6 (MAS6)) MAS6 fields are defined in Table 3-8. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 3-19...
Page 135: L1 Cache
The e200z6 processor supports a 32-kilobyte, 8-way set-associative, unified (instruction and data) cache with a 32-byte line size in the MPC5554; the MPC5553 provides an 8-Kbyte, 2-way set associative unified cache with a 32-byte line size. The cache improves system performance by providing low-latency data to the e200z6 instruction and data pipelines, which decouples processor performance from system memory performance.
Page 136 Figure 3-13. e200z6 Unified Cache Block Diagram 3.3.2.1 Cache Organization The e200z6 cache is organized as eight (MPC5554)/two (MPC5553) ways of 128 sets with each line containing 32 bytes (four doublewords) plus parity of storage. Figure 3-14 illustrates the cache organization, terminology used, the cache line format and cache tag formats.
Page 137 Following initial power-up, the cache contents will be undefined. The L, D and V bits may be set on some lines, necessitating the invalidation of the cache by software before being enabled. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 3-22 Freescale Semiconductor...
Page 138 (for a read access), or can be written with new data depending on the status of the W access control bit from the MMU (for a write access). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 3-23...
Page 139: Interrupt Types
(if any). After a cache line is successfully filled without error, the replacement pointer increments to point to the next cache way. 3.3.3 Interrupt Types The interrupts implemented in the MPC5553/MPC5554 and the exception conditions that cause them are listed in Table 3-9.
Page 140: Bus Interface Unit (Biu)
64-bits is implemented. The memory interface supports read and write transfers of 8, 16, 24, 32, and 64 bits, supports burst transfers of four doublewords, and operates in a pipelined fashion. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 141: Timer Facilities
64-bit GPRs. The shaded half is the only region operated on by the 32-bit Power Architecture embedded category instructions. GPRx Upper/Most Significant Word Lower/Least Significant Word GPRx Figure 3-16. 64-bit General-Purpose Registers MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 3-26 Freescale Semiconductor...
Page 142: Spe Programming Model
• VLEPIM: Variable Length Encoding (VLE) Extension Programming Interface Manual • Addendum to e200z6 PowerPC Core Reference Manual: e200z6 with VLE • Errata to e200z6 PowerPC Core Reference Manual, Rev. 0 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 3-27...
Page 143: Revision History
Revision History Table 3-10. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Added wording throughout the chapter specifying Power Architecture information. This replaced PowerPC information. • Added the following bullet to the Feature List: “Periodic system integrity may be monitored through parallel signature checks”...
Page 144: Introduction
Section 4.2.2, “Reset Output (RSTOUT)”). This does not reset the MPC5553/MPC5554 MCU. All other reset sources initiate an internal reset of the MCU. For all reset sources, the BOOTCFG[0:1] and PLLCFG[0:1] signals can be used to determine the boot mode and the configuration of the FMPLL, respectively. If the RSTCFG pin is asserted during reset, the values on the BOOTCFG[0:1] pins are latched in the SIU_RSR 4 clock cycles prior to the negation of the RSTOUT pin, determining the boot mode.
Page 145: External Signal Description
4.2.4 Weak Pull Configuration (WKPCFG) WKPCFG determines whether specified eTPU and EMIOS pins are connected to a weak pull up or weak pull down during and immediately after reset. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 146: Boot Configuration (Bootcfg[0:1])
BAM reset: CS[0:3], ADDR[12:31], DATA[0:31], TSIZ[0:1], RD_WR, BDIP, WE[0:3], OE, TS, TA, TEA, BR, BG, BB. In the MPC5553, BOOTCFG determines the function and state of the following pins after a BAM reset: CS[0:3], ADDR[8:31], DATA[0:31], RD_WR, BDIP, WE[0:3], OE, TS, TA, TEA. Refer to Table 4-11.
Page 147 0 No watchdog timer or debug reset has occurred. 1 A watchdog timer or debug reset has occurred. Checkstop reset status 0 No enabled checkstop reset has occurred. 1 An enabled checkstop reset has occurred. 6–13 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 148 The CRE bit in the SIU_SRCR allows software to enable a checkstop reset. If enabled, a checkstop reset will occur if the checkstop reset input to the reset controller is asserted. The checkstop reset is enabled by default. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 149 The CRE bit defaults to checkstop reset enabled. This bit is reset at POR. 0 No reset occurs when the e200z6 core enters a checkstop state. 1 A reset occurs when the e200z6 core enters a checkstop state. 17–31 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 150: Functional Description
4.4.2.2 Flash High Voltage There is no flash access gating signal implemented in the MPC5553/MPC5554. However, the device is held in reset for a long enough period of time to guarantee that high voltage circuits are reset and stabilized and that flash memory is accessible.
Page 151 (LOCRE) bit in the FMPLL_SYNCR is set. The internal reset signal is asserted (as indicated by assertion of RSTOUT). Starting at the assertion of the internal reset MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 152 BOOTCFG[0:1] pins are only sampled if RSTCFG is asserted), and their associated bits/fields are updated in the SIU_RSR. The reset source status bits in the SIU_RSR are unaffected. Refer to Chapter 24, “IEEE 1149.1 Test Access Port Controller (JTAGC),” for more information. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 153: Reset Configuration And Configuration Pins
Table 4-5. RSTCFG Settings RSTCFG Description Use default configuration of: – booting from internal flash – clock source is a crystal on FMPLL Get configuration information from: – BOOTCFG[0:1] – PLLCFG[0:1] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 4-10 Freescale Semiconductor...
Page 154 Description,” for information about the BOOTCFG pins. 4.4.3.3.1 BOOTCFG[0:1] Configuration in the 208 Package In the 208 BGA package of the MPC5553, the BOOTCFG0 pin is unavailable and BOOTCFG1 has a constant value based on PLLCFG0. The device configuration is mapped based on Table 4-7.
Page 155 The boot ID of the RCHW must be read as 0x5A. BOOT_BLOCK_ADDRESS is explained in Section 16.3.2.2.5, “Reset Configuration Halfword Read.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 4-12 Freescale Semiconductor...
Page 156 LAS blocks in internal flash memory. If the device is configured for a boot from external memory, a valid boot ID must be read at 0x00_0000 of CS0. Refer to Chapter 16, “Boot Assist Module (BAM)” for more information. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 4-13...
Page 157 0x5A), or if BOOTCFG0 is negated and BOOTCFG1 is asserted at the negation of the RSTOUT pin, then RCHW is not applicable, and serial boot mode is performed. Table 4-11 summarizes the RCHW location options. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 4-14 Freescale Semiconductor...
Page 158: Reset Configuration Timing
Note that the BOOTCFG[0:1] = 11 is a meaningless configuration for the MPC5553, because the arbitration pins and TSIZ have been removed. Table 4-11. MPC5553/MPC5554 Reset Configuration Half Word Sources Boot Identifier RSTCFG BOOTCFG0 BOOTCFG1 Field Boot Mode Configuration Word Source...
Page 159 This clock count is dependent on the configuration of the FMPLL (See Section 4.2.2, “RSTOUT”). If the FMPLL is configured for 1:1 (dual controller) operation or for bypass mode, this clock count is 16000. Figure 4-4. MPC5553/MPC5554 Reset Configuration Timing MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 4-16 Freescale Semiconductor...
Page 160: Reset Flow
Clock Cycles False RESET Asserted True Set Latch, Wait 8 Clock Cycles False RESET Set RGF Bit Asserted True To Entry Point in Internal Reset Flow Figure 4-5. External Reset Flow Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 4-17...
Page 161 The clock count is dependent on the configuration of the FMPLL (refer to Section 5.3.1.2, ‘RSTOUT’). If the FMPLL is configured in 1:1 (dual controller) or bypass mode, this clock count is 16000. Figure 4-6. Internal Reset Flow Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 4-18 Freescale Semiconductor...
Page 162: Revision History
Revision History Table 4-12. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • In Section 4.2.3 Reset Configuration (RSTCFG), added this paragraph: “In the 208 package there is no RSTCFG pin; this signifies that external bus access is not available in this package.
Page 163 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 4-20 Freescale Semiconductor...
Page 164: Introduction
IDs and the peripherals associated with each master and slave. More information on access protection may be found in Section 13.3.2.9, “Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR).” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 165 Master 3 (MPC5553 only) (MPC5553 only) Slave 0 FLASH Slave 1 Slave 3 L2SRAM Slave 6 PBRIDGE_A PBRIDGE_A FMPLL EBI Control FLASH Control eMIOS eTPU reg eTPU PRAM eTPU PRAM Mirror eTPU SCM MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 166: Features
Supports a pair of slave accesses for 64-bit instruction fetches. • Provides configurable per-module write buffering support. • Provides configurable per-module and per-master access protections. 5.1.4 Modes of Operation The PBRIDGE has only one operating mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 167: Base + 0X0004- Base + 0X001F
Off-platform peripheral access control register 1 Base + 0x0048 PBRIDGE_B_OPACR2 Off-platform peripheral access control register 2 Base + 0x004C PBRIDGE_B_OPACR3 Off-platform peripheral access control register 3 Base + 0x0050– — Reserved — Base + 0x0053 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 168: Register Descriptions
The registers provide one field per bus master. Note that access field 4 is available only in the MPC5553. Access Field 2...
Page 169 Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the EBI. Writes not able to be buffered by default. 0 Write accesses from the EBI are not bufferable 1 Write accesses from the EBI are allowed to be buffered MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 170 0 Write accesses from the FEC are not bufferable 1 Write accesses from the FEC are allowed to be buffered Note: Applies only to MPC5553. Reserved in MPC5554. MTR4 Master trusted for reads. Determines whether the FEC is trusted for read accesses.
Page 171 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7 Reset A_PACR0 Reset B_PACR0 Reset B_PACR2 Reg Addr Base + 0x0020 (PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0); Base + 0x0028 (PBRIDGE_B_PACR2) Figure 5-3. Peripheral Access Control Registers (PBRIDGE_x_PACRn) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 172 1 This peripheral requires supervisor privilege level for accesses. The PBRIDGE_x_MPCR[MPLy] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the slave bus. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 173: Pbridge_A_Pacr0
PBRIDGE_A_Base + 0x020 PBRIDGE_A 0b0101 — 0b0000 PBRIDGE_A_OPACR0 PBRIDGE_A_Base + 0x040 FMPLL 0b0100 EBI Control 0b0100 Flash Control 0b0100 — 0b0100 0b0100 — 0b0100 PBRIDGE_A_OPACR1 PBRIDGE_A_Base + 0x044 eMIOS 0b0100 — 0b0100 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 5-10 Freescale Semiconductor...
Page 174: Pbridge_A_Opacr2
PBRIDGE_B_Base + 0x048 FlexCAN_A 0b0100 FlexCAN_B 0b0100 FlexCAN_C 0b0100 — 0b0100 PBRIDGE_B_OPACR3 PBRIDGE_B_Base + 0x04C — 0b0100 0b0100 In MPC5553 only, not present in MPC5554 In MPC5554 only, not present in MPC5553 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 5-11...
Page 175: Functional Description
Read accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller, and is not misaligned across a 32-bit boundary. 64-bit data reads (not instruction) are not supported. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 5-12 Freescale Semiconductor...
Page 176: General Operation
Off-platform module selects and control register storage do not have the same degree of configurability. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 5-13...
Page 177 The PBRIDGE also supports buffered writes, allowing write accesses to be terminated on the system bus in a single clock cycle, and then subsequently performed on the slave interface. Write buffering is controllable on a per-peripheral basis. The PBRIDGE implements a two-entry 32-bit write buffer. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 5-14 Freescale Semiconductor...
Page 178: Revision History
Revision History Table 5-8. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Added a NOTE to Section 5.3.1.2, “Peripheral Access Control Registers (PBRIDGE_x_PACR) and Off-Platform Peripheral Access Control Registers (PBRIDGE_x_OPACR)” : “PBRIDGE_x_PACR and PBRIDGE_x_OPACR should be written with a read/modify/write for code compatibility.”...
Page 179 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 5-16 Freescale Semiconductor...
Page 180: Introduction
Chapter 6 System Integration Unit (SIU) Introduction This chapter describes the MPC5553/MPC5554 system integration unit (SIU), which controls MCU reset configuration, pad configuration, external interrupt, general-purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 181: Block Diagram
Figure 6-1. SIU Block Diagram 6.1.2 Overview The MPC5553/MPC5554 system integration unit (SIU) controls MCU reset configuration, pad configuration, external interrupt, general-purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration module contains the external pin boot configuration logic.
Page 182: Features
— Rising- or falling-edge event detection — Programmable digital filter for glitch rejection • GPIO — GPIO function: 214 GPIO I/O pins on the MPC5554; 177 GPIO pins on the MPC5553. — Dedicated input and output registers for each GPIO pin. • Internal multiplexing —...
Page 183: External Signal Description
V input pins. The switch point lies between the maximum DDEH and minimum V specifications for the V input pins. DDEH MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 184 (SIU_RSR). Table 6-2. BOOTCFG[0:1] Configuration Value Meaning 0b00 Boot from Internal flash memory 0b01 FlexCAN / eSCI bBoot 0b10 Boot from external memory (no arbitration) 0b11 Boot from external memory (external arbitration) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 185 6.2.1.6 External Interrupt Request Input Pins (IRQ[0:15]) The MPC5554 uses 16 interrupt request signals IRQ[0:15]; the MPC5553 uses 15 interrupt request signals IRQ[0:5,7:15] to connect to the SIU IRQ inputs. SIU_ETISR select register 1 is used to select the input pins for the IRQs.
Page 186: Memory Map/Register Definition
Base + 0x0024 SIU_ORER Overrun request enable register Base + 0x0028 SIU_IREER IRQ rising-edge event enable register Base + 0x002C SIU_IFEER IRQ falling-edge event enable register Base + 0x0030 SIU_IDFR IRQ digital filter register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 187: Register Descriptions
Reserved — Base + 0x09FF 6.3.1 Register Descriptions The figures that describe the MPC5553/MCP5554 registers use the following notational conventions in this section: A write instruction of 1 clears the bit to 0. — Not applicable. Reserved or unimplemented bit. Do not write to this bit.
Page 188 The current value applies to revision 0 and will be updated for each mask revision. The MCU ID register is 32-bits. Figure 6-2 shows the MPC5553 MCU ID register values. Address: Base + 0x0004 Access: Read only [0:15] PARTNUM...
Page 189 Reserved. Major revision number of MCU mask. Read-only, mask programmed mask number of 24–27 the MCU. Reads 0x0 for the initial mask set of the MPC5554 and the MPC5553, and MASKNUM_MAJOR changes sequentially for each mask set. Minor revision number of MCU mask. Read-only, mask programmed mask number of 28–31...
Page 190 0 The last reset source acknowledged by the reset controller was not an enabled checkstop reset. 1 The last reset source acknowledged by the reset controller was an enabled checkstop reset. Reserved. 6–13 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-11...
Page 191 The SIU_SRCR enables software to generate a system or external reset. A system reset invoked by software causes an internal reset. An external reset invoked by software asserts RSTOUT on the external IRQ pin. When written to 1, the SER bit automatically clears. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-12...
Page 192 SIU_IREER or SIU_IFEER for an IRQ[n] input and then sensed, the corresponding SIU_EISR flag bit is set. The IRQ flag bit is set regardless of the state of the MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 193 SIU_EISR. The external interrupt request enable bits enable the interrupt or DMA request. There is only one interrupt request from the SIU to the interrupt controller. The EIRE bits allow selection of which external interrupt request flag bits cause assertion of the one interrupt request signal. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-14...
Page 194 Address: Base + 0x001C Access: Read / Write[28:31] Reset Address: Base + 0x001C Access: Read / Write[28:31] DIRS3 DIRS2 DIRS1 DIRS0 Reset Figure 6-8. DMA/Interrupt Request Select Register (SIU_DIRSR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-15...
Page 195 The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If any overrun request enable bit and the corresponding flag bit are set, the single combined overrun request from the SIU to the interrupt controller is asserted. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-16...
Page 196 Address: Base + 0x0028 Access: Read/Write [16:31] IREE15 IREE14 IREE13 IREE12 IREE11 IREE10 IREE9 IREE8 IREE7 IREE6 IREE5 IREE4 IREE3 IREE2 IREE1 IREE0 Reset Figure 6-11. IRQ Rising-Edge Event Enable Register (SIU_IREER) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-17...
Page 197 IRQ pins to be recognized as an edge triggered event. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-18...
Page 198 Refer to the specific SIU_PCR definition. All MPC5553/MPC5554 pin names begin with the primary function, followed by the alternate function, and then GPIO. In some cases the third function may not be GPIO. Those exceptions are noted in the MPC5553/MPC5554 Microcontroller Reference Manual, Rev.
Page 199 The PA fields in PCR0 through 3 and PCR4 through 7 must not be configured simultaneously to select ADDR[8:11] as an input. Only one pin is to be configured to provide the address input. If external master operation is enabled, clear the HYS bit to 0. Figure 6-14. Register Diagram Description MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-20 Freescale Semiconductor...
Page 200 1 Open drain is enabled for the pad. Input hysteresis. Controls whether hysteresis is enabled for the pad. 0 Hysteresis is disabled for the pad. 1 Hysteresis is enabled for the pad. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-21...
Page 201 Refer to the EBI section for weak pullup settings when configured as CS[0:3] or ADDR[8:11] (only MPC5554). Figure 6-15. CS[0:3]_ADDR[8:11]_GPIO[0:3] Pad Configuration Registers (SIU_PCR0–SIU_PCR3) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-22 Freescale Semiconductor...
Page 202 NOTE The definitions and settings for PCR8 through PCR27 for the MPC5554 device differ from the MPC5553 definitions and settings. The SIU_PCR8–SIU_PCR27 registers control the pin function, direction, and static electrical attributes of the ADDR[12:31]_GPIO[8:27] pins. The ADDR[12:26] pins are shared by the external bus interface (EBI) and the calibration bus interface (CBI).
Page 203 6.3.1.12.4 MPC5554: Pad Configuration Registers 4–27 (SIU_PCR4–SIU_PCR27) NOTE The definitions and settings for PCR4 through PCR27 in the MPC5553 device differ from the MPC5554 definitions and settings. Refer to the previous two sections for a description of the MPC5553 settings.
Page 204 6.3.1.12.5 MPC5554: Pad Configuration Registers 28–59 (SIU_PCR28–SIU_PCR59) NOTE The MPC5553 register definitions for PCR44 through PCR59 differ from this MPC5554 register definition. The register definitions for MPC5553 PCR44 through PCR59 are described in the following section. The SIU_PCR28 through SIU_PCR59 registers control the pin function, direction, and static electrical attributes of the DATA[0:31]_GPIO[28:59] pins.
Page 205 System Interface Unit (SIU) 6.3.1.12.6 MPC5553: Pad Configuration Register 44 (SIU_PCR44) The SIU_PCR44 register controls the pin function, direction, and static electrical attributes of the DATA[16]_FEC_TX_CLK_CAL_DATA[0]_GPIO[44] pin. Address: Base + 0x0098 Access: Read [0:15] / Write[3:11, 14:15] RESET: CAL_DATA[0] is for calibration only.
Page 206 System Interface Unit (SIU) 6.3.1.12.7 MPC5553: Pad Configuration Register 45 (SIU_PCR45) The SIU_PCR45 register controls the pin function, direction, and static electrical attributes of the DATA[17]_FEC_CRS_CAL_DATA[1]_GPIO[45] pin. Address: Base + 0x009A Access: Read / write[3:11, 14:15] RESET: CAL_DATA[1] is for calibration only.
Page 207 System Interface Unit (SIU) 6.3.1.12.8 MPC5553: Pad Configuration Register 46 (SIU_PCR46) The SIU_PCR46 register controls the pin function, direction, and static electrical attributes of the DATA[18]_FEC_TX_ERR_CAL_DATA[2]_GPIO[46] pin. Address: Base + 0x009C Access: Read / write[3:11, 14:15] RESET: CAL_DATA[2] is for calibration only.
Page 208 System Interface Unit (SIU) 6.3.1.12.9 MPC5553: Pad Configuration Register 47 (SIU_PCR47) The SIU_PCR47 register controls the pin function, direction, and static electrical attributes of the DATA[19]_FEC_RX_CLK_CAL_DATA[3]_GPIO[47] pin. Address: Base + 0x009E Access: Read / write[3:11, 14:15] RESET: CAL_DATA[3] is for calibration only.
Page 209 System Interface Unit (SIU) 6.3.1.12.10 MPC5553: Pad Configuration Register 48 (SIU_PCR48) The SIU_PCR48 register controls the pin function, direction, and static electrical attributes of the DATA[20]_FEC_TXD[0]_CAL_DATA[4]_GPIO[48] pin. Address: Base + 0x00A0 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[4] is for calibration only.
Page 210 System Interface Unit (SIU) 6.3.1.12.11 MPC5553: Pad Configuration Register 49 (SIU_PCR49) The SIU_PCR49 register controls the pin function, direction, and static electrical attributes of the DATA[21]_FEC_RX_ERR_CAL_DATA[5]_GPIO[49] pin. Address: Base + 0x00A2 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[5] is for calibration only.
Page 211 System Interface Unit (SIU) 6.3.1.12.12 MPC5553: Pad Configuration Register 50 (SIU_PCR50) The SIU_PCR50 register controls the pin function, direction, and static electrical attributes of the DATA[22]_FEC_RXD[0]_CAL_DATA[6]_GPIO[50] pin. Address: Base + 0x00A4 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[6] is for calibration only.
Page 212 System Interface Unit (SIU) 6.3.1.12.13 MPC5553: Pad Configuration Register 51 (SIU_PCR51) The SIU_PCR51 register controls the pin function, direction, and static electrical attributes of the DATA[23]_FEC_TXD[3]_CAL_DATA[7]_GPIO[51] pin. Address: Base + 0x00A6 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[7] is for calibration only.
Page 213 System Interface Unit (SIU) 6.3.1.12.14 MPC5553: Pad Configuration Register 52 (SIU_PCR52) The SIU_PCR52 register controls the pin function, direction, and static electrical attributes of the DATA[24]_FEC_COL_CAL_DATA[8]_GPIO[52] pin. Address: Base + 0x00A8 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[8] is for calibration only.
Page 214 System Interface Unit (SIU) 6.3.1.12.15 MPC5553: Pad Configuration Register 53 (SIU_PCR53) The SIU_PCR53 register controls the pin function, direction, and static electrical attributes of the DATA[25]_FEC_RX_DV_CAL_DATA[9]_GPIO[53] pin. Address: Base + 0x00AA Access: Read / write[3:11, 14:15] RESET: CAL_DATA[9] is for calibration only.
Page 215 System Interface Unit (SIU) 6.3.1.12.16 MPC5553: Pad Configuration Register 54 (SIU_PCR54) The SIU_PCR54 register controls the pin function, direction, and static electrical attributes of the DATA[26]_FEC_TX_EN_CAL_DATA[10]_GPIO[54] pin. Address: Base + 0x00AC Access: Read / write[3:11, 14:15] RESET: CAL_DATA[10] is for calibration only.
Page 216 System Interface Unit (SIU) 6.3.1.12.17 MPC5553: Pad Configuration Register 55 (SIU_PCR55) The SIU_PCR55 register controls the pin function, direction, and static electrical attributes of the DATA[27]_FEC_TXD[2]_CAL_DATA[11]_GPIO[55] pin. Address: Base + 0x00AE Access: Read / write[3:11, 14:15] RESET: CAL_DATA[11] is for calibration only.
Page 217 System Interface Unit (SIU) 6.3.1.12.18 MPC5553: Pad Configuration Register 56 (SIU_PCR56) The SIU_PCR56 register controls the pin function, direction, and static electrical attributes of the DATA[28]_FEC_TXD[1]_CAL_DATA[12]_GPIO[56] pin. Address: Base + 0x00B0 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[12] is for calibration only.
Page 218 System Interface Unit (SIU) 6.3.1.12.19 MPC5553: Pad Configuration Register 57 (SIU_PCR57) The SIU_PCR57 register controls the pin function, direction, and static electrical attributes of the DATA[29]_FEC_RXD[1]_CAL_DATA[13]_GPIO[57] pin. Address: Base + 0x00B2 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[13] is for calibration only.
Page 219 System Interface Unit (SIU) 6.3.1.12.20 MPC5553: Pad Configuration Register 58 (SIU_PCR58) The SIU_PCR58 register controls the pin function, direction, and static electrical attributes of the DATA[30]_FEC_RXD[2]_CAL_DATA[14]_GPIO[58] pin. Address: Base + 0x00B4 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[14] is for calibration only.
Page 220 System Interface Unit (SIU) 6.3.1.12.21 MPC5553: Pad Configuration Register 59 (SIU_PCR59) The SIU_PCR59 register controls the pin function, direction, and static electrical attributes of the DATA[31]_FEC_RXD[3]_CAL_DATA[15]_GPIO[59] pin. Address: Base + 0x00B6 Access: Read / write[3:11, 14:15] RESET: CAL_DATA[15] is for calibration only.
Page 221 The SIU_PCR62 register controls the pin function, direction, and static electrical attributes of the RD_WR_GPIO[62] pin. Because the MPC5553 calibration bus interface (CBI) and external bus interface (EBI) share the same physical bus, the MPC5553 uses the RD_WR signal for the CBI as well as the EBI. Address: Base + 0x00BC...
Page 222 When configured as BDIP, clear the ODE bit to 0. Refer to the EBI section for weak pullup settings when configured as BDIP. Figure 6-37. BDIP_GPIO[63] Pad Configuration Register (SIU_PCR63) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-43...
Page 223 Refer to the EBI section for weak pullup settings when configured as WE/BE[2:3], CAL_WE/BE[0:1]. Figure 6-39. MPC5553: WE/BE[2:3]_CAL_WE/BE[0:1]_GPIO[66:67] Pad Configuration Registers (SIU_PCR66–SIU_PCR67) Refer to Table 6-16 for bit field definitions. The PA field for the MPC5553 PCR66–PCR67 is given in Table 6-35. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 224 OE_GPIO[68] pin. Because the MPC5553 calibration bus interface (CBI) and external bus interface (EBI) share the same physical bus, the MPC5553 uses the OE signal for the CBI as well as the EBI. The OE function is not available in the 208 MAP BGA package. The GPIO function is the only signal available on this pin in the 208 package.
Page 225 The SIU_PCR69 register controls the pin function, direction, and static electrical attributes of the TS_GPIO[69] pin. Because the MPC5553 calibration bus interface (CBI) and external bus interface (EBI) share the same physical bus, the MPC5553 uses the TS signal for the CBI as well as the EBI. Address: Base + 0x00CA...
Page 226 Refer to the EBI section for weak pullup settings when configured as TEA or CAL_CS[0]. Figure 6-43. MPC5553: TEA_CAL_CS[0]_GPIO[71] Pad Configuration Register (SIU_PCR71) Refer to Table 6-16 for bit field definitions. The PA field for the MPC5553’s PCR71 is given in Table 6-38. MPC5553/MPC5554 Microcontroller Reference Manual, Rev.
Page 227 System Interface Unit (SIU) Table 6-38. MPC5553: PCR71 PA Field Definition PA Field Pin Function 0b000 GPIO[71] 0b001 0b010 Reserved 0b011 0b100 CAL_CS[0] For calibration only. 6.3.1.12.32 MPC5554: Pad Configuration Register 71 (SIU_PCR71) The SIU_PCR71 register controls the pin function, direction, and static electrical attributes of the TEA_GPIO[71] pin.
Page 228 Access: Read / write[3:11, 14:15] RESET: The BR function is not available on the MPC5553. Set the PA field to 0b001 or 0b011 to select the CAL_ADDR[10] signal to use the calibration bus on the MPC5553. When configured as CAL_ADDR[10], FEC_MDC, or CAL_CS[2], the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
Page 229 Access: Read / write[3:11, 14:15] RESET: The BG function is not available on the MPC5553. Set the PA field to 0b001 or 0b011 to select CAL_ADDR[11] to use the calibration bus. When configured as CAL_ADDR[11], FEC_MDIO, or CAL_CS[3], the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
Page 230 6.3.1.12.37 MPC5554: Pad Configuration Register 74 (SIU_PCR74) NOTE The MPC5553 does not implement PCR74, therefore this register is reserved on the MPC5553. The SIU_PCR74 register controls the pin function, direction, and static electrical attributes of the BB_GPIO[74] pin.
Page 231 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as BB. Figure 6-49. MPC5554: BB_GPIO[74] Pad Configuration Register (SIU_PCR74) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-52 Freescale Semiconductor...
Page 232 IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-51. CNTXA_GPIO[83] Pad Configuration Register (SIU_PCR83) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-53...
Page 233 RESET: The CNTXB function is not available on the MPC5553. Do not select 0b01 or 0b11 for the PA field. When configured as CNTXB (MPC5554 only) or PCS, the OBE bit has no effect. When configured as GPO, set the OBE bit to When configured as CNTXB (MPC5554 only) or PCS or GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register.
Page 234 RESET: The CNRXB function is not available on the MPC5553. Do not select 0b01 or 0b11 for the PA field. When configured as CNRXB or PCS, the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
Page 235 IBE bit must be set to 1. Clear the IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-57. TXDA_GPIO[89] Pad Configuration Register (SIU_PCR89) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-56 Freescale Semiconductor...
Page 236 SCI loop back operation the IBE bit must be set to 1. Clear the IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-59. TXDB_PCSD[1]_GPIO[91] Pad Configuration Register (SIU_PCR91) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-57...
Page 237 RESET: The SCKA function is not available on the MPC5553. Do not select 0b01 or 0b11 for the PA field. When configured as SCKA, set the OBE bit to 1 for master operation, or clear the OBE bit to 0 for slave operation. When configured as PCS, the OBE bit has no effect.
Page 238 RESET: The SINA function is only available on the MPC5554; it is not available on the MPC5553. Therefore, set the PA field value for 0b01 or 0b11 only on the MPC5554. Valid MPC5553 PA settings are 0b10 for the PCSC[2] or 0b00 for GPIO.
Page 239 RESET: The PCSA[0] function is only available on the MPC5554; it is not available on the MPC5553. Therefore, set the PA field value for 0b01 or 0b11 only on the MPC5554. Valid MPC5553 PA settings are 0b10 for the PCSD[2] or 0b00 for GPIO.
Page 240 RESET: The PCSA[2] function is only available on the MPC5554; it is not available on the MPC5553. Therefore, set the PA field value for 0b01 or 0b11 only on the MPC5554. Valid MPC5553 PA settings are 0b10 for the SCKD or 0b00 for GPIO.
Page 241 The PCSA[4] function is only available on the MPC5554; it is not available on the MPC5553. Therefore, set the PA field value for 0b01 or 0b11 only on the MPC5554 to select PCSCA[4]. Valid MPC5553 PA settings are 0b10 for the SOUTD or 0b00 for GPIO.
Page 242 When configured as GPI, set the IBE bit to 1. to 0 to reduce power consumption. Figure 6-71. SINB_PCSC[2]_GPIO[103] Pad Configuration Register (SIU_PCR103) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-63...
Page 243 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-73. PCSB[0]_PCSD[2]_GPIO[105] Pad Configuration Register (SIU_PCR105) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-64 Freescale Semiconductor...
Page 244 Clear the IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-75. PCSB[2]_SOUTC_GPIO[107] Pad Configuration Register (SIU_PCR107) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-65...
Page 245 GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clear the IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-77. PCSB[4]_SCKC_GPIO[109] Pad Configuration Register (SIU_PCR109) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-66 Freescale Semiconductor...
Page 246 IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. Figure 6-79. ETRIG[0:1]_GPIO[111:112] Pad Configuration Register (SIU_PCR111–SIU_PCR112) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-67...
Page 247 Pad Configuration Register (SIU_PCR114–SIU_PCR125) Refer to Table 6-16 for bit field definitions. 6.3.1.12.70 Pad Configuration Register 126 (SIU_PCR126) The SIU_PCR126 register controls the pin function, direction, and static electrical attributes of the ETPUA[12]_PCSB[1]_GPIO[126] pin. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-68 Freescale Semiconductor...
Page 248 Figure 6-83. ETPUA[13]_PCSB[3]_GPIO[127] Pad Configuration Register (SIU_PCR127) Refer to Table 6-16 for bit field definitions. 6.3.1.12.72 Pad Configuration Register 128 (SIU_PCR128) The SIU_PCR128 register controls the pin function, direction, and static electrical attributes of the ETPUA[14]_PCSB[4]_GPIO[128] pin. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-69...
Page 249 The weak pullup/down selection at reset for the ETPUA[15] pin is determined by the WKPCFG pin. Figure 6-85. ETPUA[15]_PCSB[5]_GPIO[129] Pad Configuration Register (SIU_PCR129) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-70 Freescale Semiconductor...
Page 250 The weak pullup/down selection at reset for the ETPUA[17] pin is determined by the WKPCFG pin. Figure 6-87. ETPUA[17]_PCSD[2]_GPIO[131] Pad Configuration Register (SIU_PCR131) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-71...
Page 251 The weak pullup/down selection at reset for the ETPUA[19] pin is determined by the WKPCFG pin. Figure 6-89. ETPUA[19]_PCSD[4]_GPIO[133] Pad Configuration Register (SIU_PCR133) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-72 Freescale Semiconductor...
Page 252 The weak pullup/down selection at reset for the ETPUA[28] pin is determined by the WKPCFG pin. Figure 6-91. ETPUA[28]_PCSC[1]_GPIO[142] Pad Configuration Register (SIU_PCR142) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-73...
Page 253 The weak pullup/down selection at reset for the ETPUA[30] pin is determined by the WKPCFG pin. Figure 6-93. ETPUA[30]_PCSC[3]_GPIO[144] Pad Configuration Register (SIU_PCR144) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-74 Freescale Semiconductor...
Page 254 6.3.1.12.83 MPC5554: Pad Configuration Register 146 (SIU_PCR146) NOTE The MPC5553 does not implement PCR146. This register is reserved in the MPC5553. The SIU_PCR146 register controls the pin function, direction, and static electrical attributes of the TCRCLKB_IRQ[6]_GPIO[146] pin.
Page 255 6.3.1.12.85 MPC5554: Pad Configuration Register 163 (SIU_PCR163) NOTE The MPC5553 does not implement PCR163. This register is reserved in the MPC5553. The SIU_PCR163 register controls the pin function, direction, and static electrical attributes of the ETPUB[16]_PCSA[1]_GPIO[163] pin. Both the input and output channel of ETPUB[16] are connected to the pin.
Page 256 6.3.1.12.86 MPC5554: Pad Configuration Register 164 (SIU_PCR164) NOTE The MPC5553 does not implement PCR164. This register is reserved in the MPC5553. The SIU_PCR164 register controls the pin function, direction, and static electrical attributes of the ETPUB[17]_PCSA[2]_GPIO[164] pin. Both the input and output channel of ETPUB[17] are connected to the pin.
Page 257 System Interface Unit (SIU) 6.3.1.12.87 MPC5554: Pad Configuration Register 165 (SIU_PCR165) NOTE The MPC5553 does not implement PCR165. This register is reserved in the MPC5553. The SIU_PCR165 register controls the pin function, direction, and static electrical attributes of the ETPUB[18]_PCSA[3]_GPIO[165] pin. Both the input and output channel of ETPUB[18] are connected to the pin.
Page 258 6.3.1.12.89 MPC5554: Pad Configuration Register 167–178 (SIU_PCR167–SIU_PCR178) NOTE The MPC5553 does not implement PCR167–178. These registers are reserved in the MPC5553. The SIU_PCR167–SIU_PCR178 registers control the pin function, direction, and static electrical attributes of the ETPUB[20:31]_GPIO[167:178] pins. Both the inputs and outputs of ETPUB[20:31] are connected to these pins.
Page 259 The weak pullup/down selection at reset for the EMIOS[10:11] pins is determined by the WKPCFG pin. Figure 6-103. EMIOS[10:11]_GPIO[189:190] Pad Configuration Register (SIU_PCR189–SIU_PCR190) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-80 Freescale Semiconductor...
Page 260 The weak pullup/down selection at reset for the EMIOS[13] pin is determined by the WKPCFG pin. Figure 6-105. EMIOS[13]_SOUTD_GPIO[192] Pad Configuration Register (SIU_PCR192) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-81...
Page 261 6.3.1.12.95 Pad Configuration Register 195–202 (SIU_PCR195–SIU_PCR202) MPC5553: The SIU_PCR195 through SIU_PCR202 registers control the pin function, direction, and static electrical attributes of the EMIOS[16:23]_ETPUB[0:7]_GPIO[195:202] pins. The input and output functions of EMIOS[16:23] are connected to pins. The alternate functions, ETPUB[0:7], are not available on the MPC5553.
Page 262 GPI, set the IBE bit to 1. Clear the IBE to 0 to reduce power consumption. Figure 6-109. GPIO[205] Pad Configuration Registers (SIU_PCR205) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-83...
Page 263 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1. When configured as IRQ, set the HYS bit to 1. Figure 6-111. PLLCFG[0]_IRQ[4]_GPIO[208] Pad Configuration Register (SIU_PCR208) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-84 Freescale Semiconductor...
Page 264 When configured as GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. When configured as GPI, set the IBE bit to 1. Figure 6-113. RSTCFG_GPIO[210] Pad Configuration Register (SIU_PCR210) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-85...
Page 265 When configured as GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. When configured as GPI, set the IBE bit to 1. Figure 6-115. WKPCFG_GPIO[213] Pad Configuration Register (SIU_PCR213) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-86 Freescale Semiconductor...
Page 266 The PA field for PCR215 is given in Table 6-41. Table 6-41. PCR215 PA Field Definition PA Field Pin Function 0b00 0b01 Reserved 0b10 MA[0] 0b11 AN[12] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-87...
Page 267 Set the WPS bit to 1 when SDI is configured as the active signal. Figure 6-119. AN[14]_MA[2]_SDI Pad Configuration Register (SIU_PCR217) Refer to Table 6-16 for bit field definitions. The PA field for PCR217 is given in Table 6-43. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-88 Freescale Semiconductor...
Page 268 The SIU_PCR219 register controls the drive strength of the MCKO pin. Address: Base + 0x01F6 Access: Read / write[8:9] RESET: Figure 6-121. MCKO Pad Configuration Register (SIU_PCR219) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-89...
Page 269 The SIU_PCR226 register controls the drive strength of the RDY pin. Address: Base + 0x0204 Access: Read / write[8:9] RESET: Figure 6-124. RDY Pad Configuration Register (SIU_PCR226) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-90 Freescale Semiconductor...
Page 270 CLKOUT pin is enabled and disabled by setting and clearing the OBE bit. The CLKOUT pin is enabled during reset. Address: Base + 0x020A Access: Read / write[6, 8:9] RESET: Figure 6-127. CLKOUT Pad Configuration Register (SIU_PCR229) Refer to Table 6-16 for bit field definitions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-91...
Page 271 PCR. Address: Base + 0x0600 + n Access: Read / write[7] PDOn Reset Figure 6-129. GPIO Pin Data Output Register 0–213 (SIU_GPDOn) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-92 Freescale Semiconductor...
Page 272 GPIO pin, is given in Figure 6-130. The n notation in the name of the 178 (MPC5553) or 214 (MPC5554) SIU_GPDIn registers corresponds to the pins with the same GPIO pin numbers. For example, PDI0 is the bit for the CS[0]_GPIO[0] data input pin and is set in SIU_GPDI0; PDI213 is the bit for the data input WKPCFG_GPIO[213] pin and is found in SIU_GPDI213.
Page 273 10 EMIOS[12] channel 11 ETRIG[1] pin eQADC trigger input select 4. Specifies the input for eQADC trigger 4. 00 GPIO[206] 2–3 01 ETPUA[27] channel TSEL4 10 EMIOS[13] channel 11 ETRIG[0] pin MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-94 Freescale Semiconductor...
Page 274 ESEL11 ESEL10 ESEL9 ESEL8 Reset Address: Base + 0x0904 Access: Read / write[0:31] ESEL7 ESEL6 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0 Reset Figure 6-132. External IRQ Input Select Register 1 (SIU_EIISR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-95...
Page 275 External IRQ input select 7. Specifies the input for IRQ[7]. 00 IRQ[7] pin 16–17 01 DSPI_B[7] serialized input (ETPUA[16] pin) ESEL7 10 DSPI_C[8] serialized input (ETPUA[4] pin) 11 DSPI_D[9] serialized input (EMIOS[12] pin) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-96 Freescale Semiconductor...
Page 276 ESEL6 10 DSPI_C[7] serialized input (ETPUA[3] pin) 11 DSPI_D[8] serialized input (EMIOS[13] pin) Note: IRQ[6] functions on the MPC5554 only. It is not functional on the MPC5553. External IRQ input select 5. Specifies the input for IRQ[5]. 00 IRQ[5] pin 20–21...
Page 277 Figure 6-134. MPC5554 DSPI Input Select Register (SIU_DISR) All bits and muxed signals on the MPC5554 are valid. The MPC5553 does not have a DSPI A port, therefore bits 0–8 are reserved. The muxed signals used for DSPI A are invalid on the MPC5553. The following table describes the fields for the DSPI input select register and notes the settings that are invalid for the MPC5553.
Page 278 11 PCSD[4] DSPI C data input select. Specifies the source of the DSPI_C data input. 00 PCSA[2]_SINC_GPIO[108] pin 16–17 PCSA[2] and 01 SOUTA SINSELC SOUTA not available 10 SOUTB 11 SOUTD MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-99...
Page 279 DSPI D trigger input select. Specifies the source of the DSPI_D trigger input for master or slave mode. 00 Reserved 30–31 PCSA[4] not TRIGSELD 01 PCSA[4] available 10 PCSB[4] 11 PCSC[4] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-100 Freescale Semiconductor...
Page 280 Do not change this bit from its negated state at reset. TEST 0 Undocumented production test registers cannot be read or written. 1 Undocumented production test registers can be read or written. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-101...
Page 281 0 External bus signals have zero output hold times. 1 External bus signals have non-zero output hold times. Note: The EBTS bit must not be modified while an external bus transaction is in progress. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-102...
Page 282 CMPAH field is read/write and is reset by the synchronous reset signal. Address: Base + 0x0988 Access: Read / write [0:31] CMPAH Reset CMPAH Reset Figure 6-137. Compare A High Register (SIU_CARH) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-103...
Page 283 The SIU_CBRH holds the 32-bit value that is compared against the value in the SIU_CARH. The CMPBH field is read/write and is reset by the synchronous reset signal. Address: Base + 0x0990 Access: Read / write[0:31] CMPBH Reset CMPBH Reset Figure 6-139. Compare B High Register (SIU_CBRH) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-104 Freescale Semiconductor...
Page 284: Functional Description
RSTOUT, the BOOTCFG pins are ignored and the boot mode defaults to boot from internal flash memory. Table 6-53. BOOTCFG[0:1] Configuration Value Meaning 0b00 Boot from internal flash memory 0b01 FlexCAN/eSCI boot 0b10 Boot from external memory (no arbitration) 0b11 Boot from external memory (external arbitration) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 6-105...
Page 285: Reset Control
The SIU contains an overrun request for each IRQ and one combined overrun request which is the logical OR of the individual overrun requests. Only the combined overrun request is used in the MPC5553/MPC5554, and the individual overrun requests are not connected. MPC5553/MPC5554 Microcontroller Reference Manual, Rev.
Page 286: Gpio Operation
GPIO functionality has an associated pin configuration register in the SIU where the GPIO function is selected for the pin. In addition, each MPC5553/MPC5554 pin with GPIO functionality has an input data register (SIU_GPDIn_n) and an output data register (SIU_GPDOn_n).
Page 287 Figure 6-144. As shown in the figure, the IRQ[0] input of the SIU can be connected to either the IRQ[0]_GPIO[203] pin, the DSPI B[0] serial input signal, the DSPI C[1] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 6-108 Freescale Semiconductor...
Page 288 MTRIG output connected to the master trigger input. Parallel chaining allows the PCS and SCK from one DSPI to be used by more than one external SPI device, thus reducing pin use of the MPC5553/MPC5554 MCU. An example of a parallel chain is shown in Figure 6-146.
Page 289 System Interface Unit (SIU) MPC5553/MPC5554 DSPI_A (master in MPC5554) DSPI_B (slave in MPC5554) DSPI_B (master in MPC5553) DSPI_C (slave in MPC5553) SOUT SOUT Trigger MTRIG PCS[0] SCK IN SCK IN External SPI device SOUT Figure 6-145. DSPI Serial Chaining MPC5553/MPC5554 Microcontroller Reference Manual, Rev.
Page 290 System Interface Unit (SIU) MPC5553/MPC5554 DSPI_A (master in MPC5554) DSPI_B (slave in MPC5554) DSPI_B (master in MPC5553) DSPI_C (slave in MPC5553) SOUT SOUT Trigger MTRIG PCS[0] SCK IN SCK IN SOUT SCK IN SOUT External SPI device External SPI device Figure 6-146.
Page 291: Revision History
(RCHW)”, • Incorporated comments: • MPC5553 Only: Changed the reset value of the drive strength control (DSC) field from 0b11 to 0b00 for PCR72 and PCR73 registers. See section Section 6.3.1.12.33, “MPC5553: Pad Configuration Register 72 (SIU_PCR72).
Page 292: Introduction
Figure 7-1. XBAR Block Diagram Table 7-1. XBAR Switch Ports Module XBAR Port Master ID e200z6 core—CPU instruction/data Master 0 e200z6—Nexus eDMA Master 1 External Bus Interface Master 2 FEC (MPC5553 only) Master 3 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 293: Overview
Memory,” for information on accessing flash) — EBI — Internal SRAM — Peripheral bridge A — Peripheral bridge B • 32-bit address, 64-bit data paths • Fully concurrent transfers between independent master and slave ports MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 294: Modes Of Operation
Master priority register for slave port 6 Base + 0x0604– — Reserved — Base + 0x060F Base + 0x0610 XBAR_SGPCR6 General-purpose control register for slave port 6 Base + 0x0614– — Reserved — Base + 0x06FF MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 295: Register Descriptions
Attempts to write to it will have no effect on the MPR and will result in an error response. NOTE XBAR_MPR should be written with a read/modify/write for code compatibility. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 296 10 This master has the 3rd highest priority when accessing the slave port. 11 This master has the lowest priority when accessing the slave port. Note: This field is supported only in the MPC5553. Note: In the MPC5554, this master is not used. Setting its value to its reset value (0b011) insures that it does not conflict with other master priorities.
Page 297 XBAR_SGPCR, the XBAR_SGPCR and the SBAR_MPR can only be read. Attempts to write to them will have no effect and will result in an error response. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 298 10 LPP – Low power park. When no master is making a request, the arbiter will park the slave port on no master and will drive all slave port outputs to a safe state. 11 Reserved MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 299: Functional Description
000 Park on master port 0 001 Park on master port 1 010 Park on master port 2 011 Park on master port 3 (Applies to MPC5553 only) 100 Illegal master port 101 Illegal master port 110 Illegal master port...
Page 300: Master Ports
There is only one instance when the XBAR will force a bubble onto the slave bus when a master is actively making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 301: Priority Assignment
After it is granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line will be granted access MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 7-10...
Page 302 In this case all slave bus activity will effectively halt because all slave bus signals will not be toggling. This can save power if the slave port will not be in use for MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 303: Revision History
Revision History Table 7-5. Changes to MPC5553/5554 for Rev. 4.0 Release Description of Change • Added to Register Descriptions section: “Please note the difference in numerical values of XBAR Master Port and Master...
Page 304: Introduction
8.1.1 Overview The ECSM provides a set of registers that configure and report ECC errors for the MPC5553/MPC5554 device including accesses to SRAM and flash memory. The application may configure the device for the types of memory errors to be reported, and then query a set of read-only status and information registers to identify any errors that have been signalled.
Page 305: Memory Map/Register Definition
Base + 0x0064– — Reserved — Base + 0x0065 Base + 0x0066 ECSM_REMR RAM ECC master register Base + 0x0067 ECSM_REAT RAM ECC attributes register Base + 0x0068 ECSM_REDRH RAM ECC data high register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 306: Register Descriptions
These registers provide control and configuration for a software watchdog timer, and are included as part of a standard Freescale ECSM module incorporated in the MPC5553/MPC5554. The e200z6 core also provides this functionality and is the preferred method for watchdog implementation. See Section 8.2.1.1.
Page 307: Ecc Configuration Register (Ecsm_Ecr)
The ECSM allows a maximum of one bit of the ECSM_ESR to be asserted at any given time. This preserves the association between the ECSM_ESR and the corresponding address and attribute registers, MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 308 ECC events, double-bit noncorrectable errors that are terminated with an error response. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 309 2-bit ECC error in the RAM. After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 310: Flash Ecc Address Register (Ecsm_Fear)
(FLASH_AR)” to retrieve the doubleword address. FEAR Reset Reg Addr Base + 0x0050 FEAR Reset Reg Addr Base + 0x0050 “U” signifies a bit that is uninitialized. Figure 8-4. Flash ECC Address Register (ECSM_FEAR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 311: Flash Ecc Master Number Register (Ecsm_Femr)
ECC event in the flash causes the address, attributes, and data associated with the access to be loaded into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDRs, and the appropriate flag (FNCE) in the ECSM_ESR to be asserted. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 312 ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDRs, and the appropriate flag (FNCE) in the ECSM_ESR to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 313 ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDRs, and the appropriate flag (FNCE) in the ECSM_ESR to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 8-10 Freescale Semiconductor...
Page 314: Ram Ecc Address Register (Ecsm_Rear)
ECSM_REAT and ECSM_REDRs, and the appropriate flag (RNCE) in the ECSM_ESR to be asserted. REAR Reset Reg Addr Base + 0x0060 REAR Reset Reg Addr Base + 0x0060 “U” signifies a bit that is uninitialized. Figure 8-9. RAM ECC Address Register (ECSM_REAR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 8-11...
Page 315: Ram Ecc Master Number Register (Ecsm_Remr)
ECSM_ESR to be asserted. WRITE SIZE PROT0 PROT1 PROT2 PROT3 Reset Reg Addr Base + 0x0067 “U” signifies a bit that is uninitialized. Figure 8-11. RAM ECC Attributes Register (ECSM_REAT) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 8-12 Freescale Semiconductor...
Page 316 ECC event in the RAM causes the address, attributes and data associated with the access to be loaded into the ECSM_REAR, ECSM_REMR, ECSM_REAT, and ECSM_REDRH and ECSM_REDRL, and the appropriate flag (RFNCE) in the ECSM_ESR to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 8-13...
Page 317 ECC event in the RAM causes the address, attributes and data associated with the access to be loaded into the ECSM_REAR, ECSM_REMR, ECSM_REAT, ECSM_REDRH, and ECSM_REDRL, and the appropriate flag (RFNCE) in the ECSM_ESR to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 8-14 Freescale Semiconductor...
Page 318: Initialization/Application Information
0. The 0 priority level is the lowest priority and is never recognized, resulting in only the data storage interrupt (IVOR2) being taken. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 319: Revision History
Revision History Table 8-16. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • No changes since the 3.1 release. Table 8-17. Changes to MPC5553/5554 RM for Rev. 5.0 Release Description of Change • No change for Rev. 5 release.
Page 320: Introduction
Chapter 9 Enhanced Direct Memory Access (eDMA) Introduction This chapter describes the MPC5553/MPC5554’s enhanced direct memory access (eDMA) controller, a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 321: Block Diagram
The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination — Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 322: Modes Of Operation
— One interrupt per channel, optionally asserted at completion of major iteration count — Error terminations are enabled per channel, and logically summed together to form two optional error interrupts (MPC5554) or a single error interrupt (MPC5553). • Support for scatter/gather DMA processing.
Page 323: Memory Map/Register Definition
4 priority register Base + 0x0105 EDMA_CPR5 eDMA channel 5 priority register Base + 0x0106 EDMA_CPR6 eDMA channel 6 priority register Base + 0x0107 EDMA_CPR7 eDMA channel 7 priority register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 324 36 priority register Base + 0x0125 EDMA_CPR37 eDMA channel 37 priority register Base + 0x0126 EDMA_CPR38 eDMA channel 38 priority register Base + 0x0127 EDMA_CPR39 eDMA channel 39 priority register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 325 03 Base + 0x1080 TCD04 eDMA transfer control descriptor 04 Base + 0x10A0 TCD05 eDMA transfer control descriptor 05 Base + 0x10C0 TCD06 eDMA transfer control descriptor 06 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 326 35 Base + 0x1480 TCD36 eDMA transfer control descriptor 36 Base + 0x14A0 TCD37 eDMA transfer control descriptor 37 Base + 0x14C0 TCD38 eDMA transfer control descriptor 38 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 327: Register Descriptions
“L” suffixes, signaling the “high” and “low” portions of the control function. Note that for the MPC5553, only the Low register is implemented for its 32 channels. High (H) registers are reserved on the MPC5553 and accessing them will generate a bus error.
Page 328 3 (in the MPC5554; priority level 1 for the MPC5553) is the highest and priority level 0 is the lowest. The group priorities are assigned in the GRPnPRI fields of the eDMA control register (EDMA_CR). All group priorities must have unique values prior to any channel service requests occur, otherwise a configuration error will be reported.
Page 329 20–21 GRP1PRI Channel group 1 priority. Group 1 priority level when fixed priority group arbitration is enabled. Note: In the MPC5553, only bit 21 is used 22–23 GRP0PRI Channel group 0 priority. Group 0 priority level when fixed priority group arbitration is enabled.
Page 330 Note: Do not rely on the number in the ERRCHN field for group and channel priority errors. Group and channel priority errors need to be resolved by inspection. The application code must interrogate the priority registers to find groups or channels with duplicate priority level. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-11...
Page 331 9.3.1.3 eDMA Enable Request Registers (EDMA_ERQRH, EDMA_ERQRL) The EDMA_ERQRH and EDMA_ERQRL provide a bit map for the 64 (MPC5554) or 32 (MPC5553) implemented channels to enable the request signal for each channel. For the MPC5554, EDMA_ERQRH supports channels 63–32, while EDMA_ERQRL covers channels 31–00. For the MPC5553, EDMA_ERQRL maps to channels 31-0.
Page 332 TCD.D_REQ bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is complete, disabling the DMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the EDMA_ERQR bit is unaffected. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-13...
Page 333 9.3.1.4 eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL) The EDMA_EEIRH and EDMA_EEIRL provide a bit map for the 64 channels (32 in the MPC5553) to enable the error interrupt signal for each channel. For the MPC5554, EDMA_EEIRH supports channels 63–32, while EDMA_EEIRL covers channels 31–00. For the MPC5553, EDMA_EEIRL maps to channels 31-0.
Page 334 EDMA_ERQRH or EDMA_ERQRL to be set. Setting bit 1 (SERQn) provides a global set function, forcing the entire contents of EDMA_ERQRH and EDMA_ERQRL to be asserted. Reads of this register return all zeroes. For the MPC5553, bit 2 (SERQ1) is not used.
Page 335 EDMA_EEIRH or EDMA_EEIRL to be set. Setting bit 1 (SEEIn) provides a global set function, forcing the entire contents of EDMA_EEIRH or EDMA_EEIRL to be asserted. Reads of this register return all zeroes. For the MPC5553, bit 2 (SEEI1) is not used. SEEI[0:6]...
Page 336 0–63 Clear corresponding bit in EDMA_EEIRH or EDMA_EEIRL 64–127 Clear all bits in EDMA_EEIRH and EDMA_EEIRL Note: For the MPC5553, the value 32-63 [bit 2 (CEEI1)] is reserved. 9.3.1.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR) The EDMA_CIRQR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_IRQRH or EDMA_IRQRL to disable the interrupt request for a given channel.
Page 337 Setting bit 1 (SSBn) provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. For the MPC5553, bit 2 (SSB1) is not used. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 338 The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting bit 1 (CDSBn) provides a global clear function, forcing all DONE bits to be cleared. Reads of this register return all zeroes. For the MPC5553, bit 2 (CDSB1) is not used. CDSB[0:6]...
Page 339 Table 9-14. EDMA_IRQRH, EDMA_IRQRL Field Descriptions Bits Name Description 0–31 INTn eDMA interrupt request n. 0 The interrupt request for channel n is cleared. 1 The interrupt request for channel n is active. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-20 Freescale Semiconductor...
Page 340 The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across groups of 16, 32, and 64 channels (MPC5554) or 16 and 32 channels (MPC5553) to form several group error interrupt requests which is then routed to the interrupt controller. During the execution of the interrupt service routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit,...
Page 341 (attempting to preempt a preempting channel) is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected for both group and channel arbitration modes. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-22 Freescale Semiconductor...
Page 342 Each channel requires a 256-bit transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 63 (MPC5554) or channel 0, channel 1,... channel 31 (MPC5553). The definitions of the TCD are presented as twenty-three variable-length fields.
Page 343 Channel Interrupt Enable When Current Major INT_MAJ Iteration Count Complete 0x1000 + (32 x n) + 255 Channel Start START Figure 9-21 Table 9-18 define the fields of the TCDn structure. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-24 Freescale Semiconductor...
Page 344 For this circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-25...
Page 345 MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Note: This bit must be equal to the BITER.E_LINK bit otherwise a configuration error will be reported. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-26 Freescale Semiconductor...
Page 346 Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field, otherwise a configuration error will be reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-27...
Page 347 Channel active. This flag signals the channel is currently in execution. It is set when 0x1C [25] channel service begins, and is cleared by the eDMA engine as the inner minor loop completes or if any error condition is detected. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-28 Freescale Semiconductor...
Page 348 0x1C [31] hardware automatically clears this flag after the channel begins execution. 0 The channel is not explicitly started. 1 The channel is explicitly started via a software initiated service request. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-29...
Page 349: Functional Description
Transfer size is defined as the following” if (ssize < dsize) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-30 Freescale Semiconductor...
Page 350 — Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM memory array. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-31...
Page 351: Edma Basic Data Flow
The source reads are initiated and the fetched data is temporarily stored in the data path module until it is gated onto the system bus during the destination write. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-32...
Page 352 BITER field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 353: Edma Performance
Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase. • All slave reads require two wait-states, and slave writes three wait-states, again viewed from the system bus data phase. • All slave accesses are 32-bits in size. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-34 Freescale Semiconductor...
Page 354 Cycle 8 – n: The last part of the TCD is read in. This cycle represents the 1st data phase for the read, and the address phase for the destination write. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-35...
Page 355 Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase. • All slave reads require two wait-states, and slave writes three wait-states, again viewed from the system bus data phase. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-36 Freescale Semiconductor...
Page 356: Initialization / Application Information
TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 357 (CITER) DMA Request • Minor Loop • • DMA Request • Minor Loop Major Loop • • DMA Request • Minor Loop • • Figure 9-25. Example of Multiple Loop Iterations MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-38 Freescale Semiconductor...
Page 358: Dma Programming Errors
EDMA_ER and the error interrupt request line are undetermined because they reflect the ‘undefined’ channel. A group priority error is global and any request in any group will cause a group priority error. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-39...
Page 359: Dma Request Assignments
Note that the MPC5554 has 64 channels but the MPC5553 has 32 channels, and in Table 9-22 channels 0-31 function for both the MPC5553/MPC5554, but only channels 32-63 function for the MPC5554. Table 9-22. DMA Request Summary for eDMA...
Page 360 17 Flag eMIOS_GFR_F18 EMIOS.GFR[F18] eMIOS channel 18 Flag eMIOS_GFR_F19 EMIOS.GFR[F19] eMIOS channel 19 Flag eTPU_CDTRSR_A_DTRS12 ETPU.CDTRSR_A[DTRS12] eTPUA Channel 12 Data Transfer Request Status eTPU_CDTRSR_A_DTRS13 ETPU.CDTRSR_A[DTRS13] eTPUA Channel 13 Data Transfer Request Status MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-41...
Page 361: Dma Arbitration Mode Considerations
If the eDMA is programmed so the channels within one group use ‘fixed’ priorities, and that group is assigned the highest ‘fixed’ priority of all groups, it is possible for that group MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-42...
Page 362 Service latency will be short on the highest priority group, but could potentially get very much longer and longer as the group priority decreases. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 363: Dma Transfer
-> third iteration of the minor loop g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c) -> last iteration of the minor loop -> major loop complete MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-44 Freescale Semiconductor...
Page 364 -> second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008) -> third iteration of the minor loop g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c) -> last iteration of the minor loop MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-45...
Page 365 4 bytes and the mod field is set to 4, allowing for a 2 byte (16-byte) size queue. Table 9-23. Modulo Feature Example Transfer Address Number 0x12345670 0x12345674 0x12345678 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-46 Freescale Semiconductor...
Page 366: Tcd Status
The eDMA will read back the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 367: Channel Linking
When minor loop linking is disabled (TCD.CITER.E_LINK = 0), the TCD.CITER field uses a 15-bit vector to form the current iteration count. The bits associated with the TCD.CITER.LINKCH field are concatenated onto the CITER value to increase the range of the CITER. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 9-48 Freescale Semiconductor...
Page 368: Dynamic Programming
3. Test the TCD.MAJOR.E_LINK request status: a) If the bit is set, the dynamic link attempt was successful. b) If the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 9-49...
Page 369: Revision History
Table 9-25. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Added NOTE to these registers: SERQR, CERQR, SEEIR, CEEIR, CIRQR, CER, SSBR, CDSBR: “For the MPC5553, the value 32-63 [bit 2 (xxxx1)] is reserved.” • In the section on DMA Performance, made this change:...
Page 370: Introduction
The INTC provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and protocol support. Interrupts implemented by the MPC5553 and the MPC5554 are defined in the e200z6 PowerPC Core Reference Manual.
Page 371: Block Diagram
Memory mapped registers Non-memory mapped logic The total number of interrupt sources in the MPC5553 is 212, which includes 191 peripheral, 13 reserved sources, and 8 software sources. The total number of interrupt sources in the MPC5554 is 308, which includes 278 peripheral, 22 reserved sources, and 8 software sources.
Page 372 Figure 10-2 displays the interrupt sources for the MPC5553. Figure 10-3 displays the interrupt sources for the MPC5554. Refer to Table 10-9 for interrupt source vector details. Software IRQs Watchdog IRQ Memory IRQ eDMA IRQs FMPLL IRQs External Interrupt External IRQ Input Pins...
Page 373 ISR_3071 NOTES: 1 The number of interrupt sources in the MPC5553 is 210, which includes 13 reserved. Figure 10-4. Program Flow—Software Vector Mode In hardware vector mode, the e200z6 branches to a unique interrupt exception handler whose location is unique for each interrupt request source. Typical program flow for hardware vector mode is shown in Figure 10-5.
Page 374: Features
Features Features include the following: • Total number of interrupt vectors is 308 (MPC5554) or 212 (MPC5553) of which — 278 (MPC5554) or 191 (MPC5553) are peripheral interrupt request sources, — 8 are software settable sources, and — 22 (MPC5554) or 13 (MPC5553) are reserved sources.
Page 375 (IVPR) is added to an offset which corresponds to the peripheral or software interrupt source which caused the interrupt request. The offset matches the value in the Interrupt Vector MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-6...
Page 376: External Signal Description
— / — / AD18 WKPCFG WKPCFG IRQ[0:1] External interrupt request GPIO[193:194] GPIO BOOTCFG[0:1] AA25: BOOTCFG[0:1] Boot configuration input BOOTCFG / — / Down Down IRQ[2:3] External interrupt request GPIO[211:212] GPIO MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-7...
Page 377: Memory Map/Register Definition
Primary, alternate, or GPIO function. For each pin in the table, each line in the function column is a separate function of the pin. For all MPC5554/MPC5553 I/O pins the selection of primary, secondary or tertiary function is done in the MPC5554/MPC5553 SIU except where explicitly noted.
Page 378 In the MPC5554, the PRI fields are reserved for peripheral interrupt requests whose vectors are 147, 148, 150, 151, 154, 175, 194–201, 282 and 301–307. In the MPC5553, the PRI fields are reserved for peripheral interrupt requests whose vectors are 147, 148, 150, 151, 154, 175, 197-201, 210, 211.
Page 379: Register Descriptions
‘0’s determines the size of each vector table entry. VTES impacts software vector mode operation but also affects INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode. 0 4 bytes (Normal expected use) 1 8 bytes MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-10 Freescale Semiconductor...
Page 380 PRI field. Refer to Section 10.5.5.2, “Ensuring Coherency.” Reset Reg Addr Base + 0x0008 Reset Reg Addr Base + 0x0008 Figure 10-9. INTC Current Priority Register (INTC_CPR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-11...
Page 381 Reading the INTC_IACKR does not have side effects in hardware vector mode. NOTE In software vector mode, the INTC_IACKR must be read before setting MSR[EE]. No synchronization instruction is needed after reading the INTC_IACKR and before setting MSR[EE]. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-12 Freescale Semiconductor...
Page 382 INTC_EOIR are ignored. Those values and sizes written to this register neither update the INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0’s to the INTC_EOIR. Reading the INTC_EOIR has no effect on the LIFO. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-13...
Page 383 Although INTC_SSCIn is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. CLRn SETn Reset Reg Addr Base + 0x0020 + n Figure 10-12. INTC Software Set/Clear Interrupt Register 0–7 (INTC_SSCIR0–INTC_SSCIR7) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-14 Freescale Semiconductor...
Page 384 The software settable interrupt requests 0–7 are assigned vectors 0–7, and their priorities are configured in INTC_PSR0–INTC_PSR7, respectively. The peripheral interrupt requests are assigned vectors 8–307 (MPC5554)/8–211 (MPC5553) and their priorities are configured in INTC_PSR8 through INTC_PSR307 (MPC5554) / INTC_PSR8 through INTC_PSR211 (MPC5553), respectively.
Page 385: Functional Description
Interrupt 2 0x00E0 EDMA_IRQRL[INT03] EDMA_IRQRL[INT03] eDMA channel Interrupt 3 0x00F0 EDMA_IRQRL[INT04] EDMA_IRQRL[INT04] eDMA channel Interrupt 4 0x0100 EDMA_IRQRL[INT05] EDMA_IRQRL[INT05] eDMA channel Interrupt 5 0x0110 EDMA_IRQRL[INT06] EDMA_IRQRL[INT06] eDMA channel Interrupt 6 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-16 Freescale Semiconductor...
Page 386 Interrupt 31 0x02B0 FMPLL_SYNSR[LOCF] FMPLL_SYNSR[LOCF] FMPLL Loss of Clock Flag 0x02C0 FMPLL_SYNSR[LOLF] FMPLL_SYNSR[LOLF] FMPLL Loss of Lock Flag 0x02D0 SIU_OSR[OVF15:OVF0] SIU_OSR[OVF15:OVF0] SIU combined overrun interrupt requests of the external interrupt Overrun Flags MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-17...
Page 387: Emios_Gfr_F1
Engine A Channel 0 Interrupt Status 0x0450 ETPU_CISR_A[CIS1] ETPU_CISR_A[CIS1] eTPU Engine A Channel 1 Interrupt Status 0x0460 ETPU_CISR_A[CIS2] ETPU_CISR_A[CIS2] eTPU Engine A Channel 2 Interrupt Status 0x0470 ETPU_CISR_A[CIS3] ETPU_CISR_A[CIS3] eTPU Engine A Channel 3 Interrupt Status MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-18 Freescale Semiconductor...
Page 388 Engine A Channel 28 Interrupt Status 0x0610 ETPU_CISR_A[CIS29] ETPU_CISR_A[CIS29] eTPU Engine A Channel 29 Interrupt Status 0x0620 ETPU_CISR_A[CIS30] ETPU_CISR_A[CIS30] eTPU Engine A Channel 30 Interrupt Status 0x0630 ETPU_CISR_A[CIS31] ETPU_CISR_A[CIS31] eTPU Engine A Channel 31 Interrupt Status MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-19...
Page 389 0x07A0 EQADC_FISR4[PF] EQADC_FISR4[PF] eQADC command FIFO 4 Pause Flag 0x07B0 EQADC_FISR4[EOQF] EQADC_FISR4[EOQF] eQADC command FIFO 4 command queue End of Queue Flag 0x07C0 EQADC_FISR4[CFFF] EQADC_FISR4[CFFF] eQADC Command FIFO 4 Fill Flag MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-20 Freescale Semiconductor...
Page 390 DSPI_DSR[EOQF] DSPI_D transmit FIFO End of Queue Flag 0x08F0 DSPI_DSR[TFFF] DSPI_DSR[TFFF] DSPI_D Transmit FIFO Fill Flag 0x0900 DSPI_DSR[TCF] DSPI_DSR[TCF] DSPI_D Transfer Complete Flag 0x0910 DSPI_DSR[RFDF] DSPI_DSR[RFDF] DSPI_D Receive FIFO Drain Flag MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-21...
Page 391 ESCIB_SR[CERR] ESCIB_SR[CKERR] ESCIB_SR[CKERR] ESCIB_SR[FRC] ESCIB_SR[FRC] ESCIB_SR[OVFL] ESCIB_SR[OVFL] 0x0960 Reserved Reserved Reserved 0x0970 Reserved Reserved Reserved FlexCAN_A and FlexCAN_B 0x0980 CANA_ESR[BOFF_INT] CANA_ESR[BOFF_INT] FLEXCAN_A Bus off Interrupt 0x0990 CANA_ESR[ERR_INT] CANA_ESR[ERR_INT] FLEXCAN_A Error Interrupt MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-22 Freescale Semiconductor...
Page 392 FLEXCAN_C Buffer 4 Interrupt 0x0B50 CANC_IFRL[BUF5] CANC_IFRL[BUF5] FLEXCAN_C Buffer 5 Interrupt 0x0B60 CANC_IFRL[BUF6] CANC_IFRL[BUF6] FLEXCAN_C Buffer 6 Interrupt 0x0B70 CANC_IFRL[BUF7] CANC_IFRL[BUF7] FLEXCAN_C Buffer 7 Interrupt 0x0B80 CANC_IFRL[BUF8] CANC_IFRL[BUF8] FLEXCAN_C Buffer 8 Interrupt MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-23...
Page 393: Emios_Gfr_F16
17 Flag 0x0CC0 EMIOS_GFR[F18] EMIOS_GFR[F18] eMIOS channel 18 Flag 0x0CD0 EMIOS_GFR[F19] EMIOS_GFR[F19] eMIOS channel 19 Flag 0x0CE0 EMIOS_GFR[F20] EMIOS_GFR[F20] eMIOS channel 20 Flag 0x0CF0 EMIOS_GFR[F21] EMIOS_GFR[F21] eMIOS channel 21 Flag MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-24 Freescale Semiconductor...
Page 394: Emios Channel 7 Flag
Interrupt 54 0x0EA0 — EDMA_IRQRH[INT55] eDMA channel Interrupt 55 0x0EB0 — EDMA_IRQRH[INT56] eDMA channel Interrupt 56 0x0EC0 — EDMA_IRQRH[INT57] eDMA channel Interrupt 57 0x0ED0 — EDMA_IRQRH[INT58] eDMA channel Interrupt 58 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-25...
Page 395 Engine B Channel 21 Interrupt Status 0x1090 — ETPU_CISR_B[CIS22] eTPU Engine B Channel 22 Interrupt Status 0x10A0 — ETPU_CISR_B[CIS23] eTPU Engine B Channel 23 Interrupt Status 0x10B0 — ETPU_CISR_B[CIS24] eTPU Engine B Channel 24 Interrupt Status MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-26 Freescale Semiconductor...
Page 396 FLEXCAN_B Buffer 8 Interrupt 0x1240 — CANB_IFRL[BUF9] FLEXCAN_B Buffer 9 Interrupt 0x1250 — CANB_IFRL[BUF10] FLEXCAN_B Buffer 10 Interrupt 0x1260 — CANB_IFRL[BUF11] FLEXCAN_B Buffer 11 Interrupt 0x1270 — CANB_IFRL[BUF12] FLEXCAN_B Buffer 12 Interrupt MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-27...
Page 397 Peripheral Interrupt Requests An interrupt event in a peripheral’s hardware sets a flag bit which resides in that peripheral. The interrupt request from the peripheral is driven by that flag bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-28 Freescale Semiconductor...
Page 398: Priority Management
Also, a unique vector for the preempting peripheral or software settable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-29...
Page 399 The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-30 Freescale Semiconductor...
Page 400: Details On Handshaking With Processor
This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-31...
Page 401 The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-32 Freescale Semiconductor...
Page 402: Initialization/Application Information
Interrupt Exception Handler These example interrupt exception handlers use Power Architecture embedded category assembly code. 10.5.2.1 Software Vector Mode interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-33...
Page 403 4 instructions available, branch to continue interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-34 Freescale Semiconductor...
Page 404: Isr, Rtos, And Task Hierarchy
Because the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-35...
Page 405: Order Of Execution
300 asserted first. ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute. ISR308 completes. Interrupt exception handler writes to INTC_EOIR. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-36 Freescale Semiconductor...
Page 406: Priority Ceiling Protocol
ISR2 has asserted. As the processor is responding to the interrupt request from the INTC, and as it is aborting transactions and flushing its pipeline, it is possible MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 407 The example is for software vector mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the processor, hardware vector mode is identical. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-38 Freescale Semiconductor...
Page 408 LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop from LIFO is the priority from before peripheral interrupt request 100 interrupted. ISR108 now can access data block coherently after interrupt exception handler executes rfi instruction. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-39...
Page 409: Selecting Priorities According To Request Rates And Deadlines
(INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SETn causes a software settable interrupt request. This software settable interrupt request, which usually will have a lower PRIn value in the INTC_PSRn, therefore will not cause preemptive scheduling inefficiencies. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-40 Freescale Semiconductor...
Page 410: Lowering Priority Within An Isr
ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 10-41...
Page 411: Examining Lifo Contents
In hardware vector mode, reading the INTC_IACKR does not push the INTC_CPR[PRI] onto the LIFO, therefore the LIFO contents cannot be restored in hardware vector mode. push_lifo: load stacked PRI value and store to INTC_CPR MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 10-42 Freescale Semiconductor...
Page 412: Revision History
10.6 Revision History Table 10-12. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Added a note to the Block Diagram: “The total number of interrupt sources in the MPC5554 is 308, which includes 278 peripheral, 22 reserved sources, and 8 software sources.”...
Page 413 Table 10-12. Changes to MPC5553/5554 RM for Rev. 4.0 Release (Continued) • In Section 10.5.10 “Examining LIFO Contents”: Removed: “Normally the user does not need to know the contents of the LIFO. One may not even know how deeply the LIFO is nested.
Page 414 Table 10-12. Changes to MPC5553/5554 RM for Rev. 4.0 Release (Continued) Throughout the chapter, replaced “priority inversion” with “scheduling inefficiencies” as follows: SECTION 10.5.5.1 Elevating Priority From: "After they release the resource, they must lower the PRI value in INTC_CPR to prevent further priority inversion."...
Page 415 Moved the text in Section 10.5.5.2: Ensuring Coherency under a new “Section 10.5.5.2.1: Interrupt with Blocked Priority”. Added a new “Section 10.5.5.2.2: Raised Priority Preserved”. • TABLE 10.9 INTC: Interrupt Request Sources Removed ETPU_MCR[MGEB] and ETPU_MCR[ILFB] from the “Source MPC5553” column under eTPU_A for hardware vector mode offset 0x0430. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 416: Introduction
This section describes the features and function of the FMPLL module. 11.1.1 Block Diagrams This section contains block diagrams that illustrate the FMPLL, the clock architecture, and the various FMPLL and clock configurations that are available on the MPC5553/MPC5554. The following diagrams are provided: • Figure 11-1, “FMPLL and Clock Architecture”...
Page 417 FlexCAN x 3 (2 in MPC5553) MDIS Message Buffer CLK CLK_SRC Core, INTC, eDMA, SIU, BAM, eSCI x 2 RAMs, eQADC, Flash, XBAR, MDIS PBRIDGE_A, PBRIDGE_B Figure 11-1. FMPLL Block and Clock Architecture MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-2 Freescale Semiconductor...
Page 418 FlexCAN x 3 (2 in MPC5553) MDIS Message Buffer CLK CLK_SRC Core, INTC, eDMA, SIU, BAM, eSCI x 2 RAMs, eQADC, Flash, XBAR, MDIS PBRIDGE_A, PBRIDGE_B Figure 11-2. FMPLL Bypass Mode MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-3...
Page 419 FlexCAN x 3 (2 in MPC5553) MDIS Message Buffer CLK CLK_SRC Core, INTC, eDMA, SIU, BAM, eSCI x 2 RAMs, eQADC, Flash, XBAR, MDIS PBRIDGE_A, PBRIDGE_B Figure 11-3. FMPLL External Reference Mode MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-4 Freescale Semiconductor...
Page 420 (2 in MPC5553) MDIS Message Buffer CLK CLK_SRC Core, INTC, eDMA, SIU, BAM, eSCI x 2 RAMs, eQADC, Flash, XBAR, MDIS PBRIDGE_A, PBRIDGE_B Figure 11-4. FMPLL Crystal Reference Mode without FM MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-5...
Page 421 (2 in MPC5553) MDIS Message Buffer CLK CLK_SRC Core, INTC, eDMA, SIU, BAM, eSCI x 2 RAMs, eQADC, Flash, XBAR, MDIS PBRIDGE_A, PBRIDGE_B Figure 11-5. FMPLL Crystal Reference Mode with FM MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-6 Freescale Semiconductor...
Page 422 FlexCAN x 3 (2 in MPC5553) MDIS Message Buffer CLK CLK_SRC Core, INTC, eDMA, SIU, BAM, eSCI x 2 RAMs, eQADC, Flash, XBAR, MDIS PBRIDGE_A, PBRIDGE_B Figure 11-6. FMPLL Dual Controller (1:1) Mode MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-7...
Page 423: Overview
(INTC),” for details.) — User-selectable ability to generate a system reset upon loss of clock (See Chapter 4, “Reset,” for details.) • Self-clocked mode (SCM) operation in event of input clock failure MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-8 Freescale Semiconductor...
Page 424: Fmpll Modes Of Operation
The 324 and 416 package sizes of the MPC5553 also default to crystal reference mode. For the MPC5554 and the 324 and 416 package sizes of the MPC5553, if the user should desire to change from this mode, the RSTCFG and PLLCFG[0:1] package pins must be driven to the appropriate state for the desired mode from the time RSTOUT asserts until it negates.
Page 425 Crystal reference is the default clock mode for the MPC5554 and for the 324 and 416 packages of the MPC5553. It is not necessary to force PLLCFG[0:1] to enter this mode. In the 208 package size, because it has no RSTCFG pin, the crystal reference mode can only be selected through the PLLCFG pins.
Page 426 Frequency modulation is not available when configured for dual-controller mode for both the master and slave devices. Enabling frequency modulation on the device supplying the reference clock to the slave in dual-controller mode will produce unreliable clocks on the slave. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-11...
Page 427: External Signal Description
(FMPLL_SYNSR). The following sections describe these registers in detail. 11.3.1.1 Synthesizer Control Register (FMPLL_SYNCR) The synthesizer control register (FMPLL_SYNCR) contains bits for defining the clock operation for the system. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-12 Freescale Semiconductor...
Page 428 Note: Programming a PREDIV value such that the ICO operates outside its specified range will cause unpredictable results and the FMPLL will not lock. Refer to the MPC5553 Microcontroller Data Sheet and MPC5554 Microcontroller Data Sheet for details on the ICO range.
Page 429 Note: Programming an MFD value such that the ICO operates outside its specified range will cause unpredictable results and the FMPLL will not lock. Refer to the MPC5553 Microcontroller Data Sheet and MPC5554 Microcontroller Data Sheet for details on the ICO range.
Page 430 LOCIRQ bit causes an interrupt request. In bypass mode LOCIRQ has no effect. 0 Ignore loss of clock - interrupt not requested 1 Request interrupt on loss of clock. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-15...
Page 431 The synthesizer status register (FMPLL_SYNSR) is a 32-bit register. Only the LOLF and LOCF flag bits are writable in this register. Writes to bits other than the LOLF and LOCF have no effect. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-16...
Page 432 LOLF is set again. To avoid generating an unintentional interrupt, clear LOLIRQ before changing MFD or PREDIV, or before enabling FM after a previous interrupt and relock occurred. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-17...
Page 433 PREDIV bit fields, or frequency modulation enabled. 1 PLL has not lost lock since last system reset, a write to FMPLL_SYNCR to modify the MFD and PREDIV bit fields, or frequency modulation enabled. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-18 Freescale Semiconductor...
Page 434 FMPLL simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the FMPLL. If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the MPC5553 Microcontroller Datasheet and MPC5554 Microcontroller Datasheet for the lock/unlock range. 0 PLL is unlocked.
Page 435: Functional Description
MCKO – Nexus auxiliary port clock • ENGCLK – Engineering clock The MPC5553/MPC5554 MCU has been designed so that the oscillator clock can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance. Figure 11-1 shows a block diagram of the FMPLL and the system clock architecture.
Page 436 (NPC). The reset value of the MCKO_DIV selects an MCKO clock frequency one half of the system clock frequency. The MCKO divider is configured by writing to the NPC through the JTAG port. Chapter 25, “Nexus Development Interface” for more information. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-21...
Page 437: Clock Operation
Chapter 22, “FlexCAN2 Controller Area Network” for more information on the FlexCAN modules. 11.4.1.3.5 FEC Clocks In the MPC5553, the FEC TX_CLK and RX_CLK are inputs. An external source provides the clocks to these pins. 11.4.2 Clock Operation 11.4.2.1 Input Clock Frequency The FMPLL is designed to operate over an input clock frequency range as determined by the operating mode.
Page 438 FMPLL_SYNCR[LOLIRQ] bit. An interrupt is requested by the FMPLL if LOLIRQ is set and loss of lock occurs. In bypass mode, the FMPLL cannot lock. Therefore a loss of lock condition cannot occur, and the LOLIRQ bit has no effect. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-23...
Page 439 The FMPLL remains in SCM until the next reset. Note that when the FMPLL is operated in SCM, writes to FMPLL_SYNCR[RFD] have no effect on clock frequency. The SCM system frequency stated in the MPC5553 Microcontroller Data Sheet and the MPC5554 Microcontroller Data Sheet assumes that the RFD has been programmed to 0x0.
Page 440: Clock Configuration
PREDIV normal reset value is 0. Caution: Programming a PREDIV value such that the ICO operates outside its specified range will cause unpredictable results and the FMPLL will not lock. Refer to the MPC5553 Microcontroller Data Sheet and MPC5554 Microcontroller Data Sheet for details on the ICO range.
Page 441 MFD factor that can be paired with an RFD factor to provide the desired frequency. The maximum MFD value that can be used is determined by the ICO range. See the MPC5553 Microcontroller Data Sheet and the MPC5554 Microcontroller Data Sheet for the maximum frequency of the ICO.
Page 442 Clear FMPLL_SYNCR[LOLRE]. If this bit is set, the MCU will go into reset when MFD is written. c) Initialize the FMPLL for less than the desired final frequency: — Disable LOLIRQ. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-27...
Page 443 8 MHz the resulting modulation frequency will be proportionally skewed. Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than 20%. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-28 Freescale Semiconductor...
Page 444 Rounding this value to the closest integer yields the value of 48 that should be entered into the EXP field for this example. Table 11-11. Multiplied Factor Dividers with M Values MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-29...
Page 445 CALPASS remains a 1. Figure 11-11 shows a block diagram of the calibration circuitry and its associated registers. Figure 11-12 shows a flow chart showing the steps taken by the calibration circuit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-30 Freescale Semiconductor...
Page 446 Expected Error Count 0 (EXP) (ERR) Reference Counter Control Counter A-B = Delta Count C-D = Error Count Figure 11-11. FM Auto-Calibration Data Flow MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 11-31...
Page 447 For MFD = 21 to 31: M = 160 DIFF > 0 PCALPASS = 0 Let ERR = DIFF-EXP ERR > 0 CAL[N] = 0 Figure 11-12. FM Auto-Calibration Flow Chart MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 11-32 Freescale Semiconductor...
Page 448: Revision History
FMPLL. If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the MPC5553 Microcontroller Datasheet and MPC5554 Microcontroller Datasheet for the lock/unlock range.
Page 449 Table 11-13. Changes to MPC5553/5554 RM Rev. 5.0 Release Description of Change • In the FMPLL Calibration Routine section, corrected the equation at the end of the third paragraph: changed value of M from 640 to 480. • Updated Figure 11-9: Synthesizer Status Register (FMPLL_SYNSR) to reflect that bits 23:28 and bits 30:31 are read-only.
Page 450: Introduction
12.1 Introduction This chapter describes the external bus interface (EBI) of the MPC5553/MPC5554, which handles the transfer of information between the internal buses and the memories or peripherals in the external address space and enables an external master to access internal address space. For an overview of how the EBI used in the MPC5553/MPC5554 differs from the EBI used in MPC5xx devices, refer to Section 12.5.6,...
Page 451: Block Diagram
EBI. The signals shown are external pins to the MCU. All signals are implemented in the MPC5554 and in the 416 and 324 BGA of the MPC5553 except where noted. The MPC5553 208 BGA does not have EBI signals pinned out.
Page 452: Overview
• 32-bit internal address bus with transfer size indication, but — 24 bits available as external pins in the MPC5554 and in the MPC5553 416 and 324 BGA packages — 20 bits available in the MPC5553 416 and 324 BGA packages —...
Page 453: Modes Of Operation
• Configurable wait states • Four chip select (CS[0:3]) signals; but the MPC5553 has no CS signals in the 208 BGA package. • Support for dynamic calibration with up to three calibration chip selects (CAL_CS[0] and CAL_CS[2:3]) – in the VertiCal assembly of the MPC5553 only •...
Page 454 EBI space, it will never get a bus grant, and the operation will time out. Because the MPC5553 does not have transfer size pins (TSIZ[0:1]), the SIZEN and SIZE fields of the EBI_MCR must be used for MCU-to-MCU transfers to indicate transfer size.
Page 455: External Signal Description
Function Pull Packages Package ADDR[8:11] Address Bus — ADDR[12:31] Address Bus — 416, 324 Bus Busy None Bus Grant None Bus Request None BDIP Output Burst Data in Progress 416, 324 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-6 Freescale Semiconductor...
Page 456: Detailed Signal Descriptions
The CLKOUT signal is driven by the FMPLL Module. 12.2.1 Detailed Signal Descriptions The MPC5554 and the 416 and 324 BGA packages of the MPC5553 have pinned out EBI signals. The 208 BGA package of the MPC5553 does not pin out these signals. 12.2.1.1 Address Lines 8–31 (ADDR[8:31])
Page 457 BB and BG) by the EBI when an external bus transaction is to be executed by the MCU. NOTE The MPC5553 does not implement BG, thus for this device the ball’s primary function is the calibration address CAL_ADDR[11]. 12.2.1.5 Bus Request (BR) — MPC5554 Only BR is asserted to request ownership of the external bus.
Page 458 12.2.1.9 Data Lines 0–31 (DATA[0:31]) In the 416-pin package of the MPC5553 and the MPC5554, the DATA[0:31] signals contain the data to be transferred for the current transaction. In the 324-pin package of the MPC5553, DATA[0:15] carry the data.
Page 459 12.2.1.13 Transfer Error Acknowledge (TEA) In the 416-pin package of the MPC5553/MPC5554, TEA is asserted by either the EBI or an external device to indicate that an error condition has occurred during the bus cycle. TEA assertion terminates the cycle immediately, overriding the value of the TA signal.
Page 460: Signal Function/Direction By Mode
EBI. See Section 12.3.1.3, “EBI Module Configuration Register (EBI_MCR).” Note that in the MPC5553, the EBI_MCR[SIZEN] bit must be set to 1 in order to run external master accesses to the MPC5553. 12.2.1.16 Write/Byte Enables (WE / BE) Write enables are used to enable program operations to a particular memory.
Page 461 The open drain mode of the pads configuration module is not used for any EBI signals. For a description of how signals are driven by multiple devices in external master mode, see Section 12.4.2.10, “Bus Operation in External Master Mode.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-12 Freescale Semiconductor...
Page 462: Memory Map/Register Definition
IDLE). In such cases, the behavior is undefined. Exceptions that can be written while an EBI transaction is in progress are the following: • All bits in EBI_TESR MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-13...
Page 463 Transfer size. The SIZE field determines the transfer size of external master transactions to internal address space when SIZEN=1. This field is ignored when SIZEN=0. SIZE encoding: 00 32-bit 01 Byte 10 16-bit 11 Reserved MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-14 Freescale Semiconductor...
Page 464 GPIO) prior to EXTM being set to 1, or erroneous behavior may result. 0 External master mode is inactive (single master mode) 1 External master mode is active Note: In the MPC5553, only master/slave systems support the EXTM functionality. Refer Section 12.5.5, “Dual-MCU Operation with Reduced Pinout MCUs.“...
Page 465 This bit can be cleared by writing a 1 to it. 12.3.1.5 EBI Bus Monitor Control Register (EBI_BMCR) The EBI_BMCR controls the timeout period of the bus monitor and whether it is enabled or disabled. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-16 Freescale Semiconductor...
Page 466 The EBI_BRn are used to define the base address and other attributes for the corresponding chip select. The EBI_CAL_BRn appear in the MPC5553 only and are used to define the base address and other attributes for the corresponding calibration chip select.
Page 467 0 8-word burst length 1 4-word burst length WEBS Write enable/byte select. Controls the functionality of the WE[0:3]/BE[0:3] signals. 0 The WE[0:3]/BE[0:3] signals function as WE[0:3]. 1 The WE[0:3]/BE[0:3] signals function as BE[0:3]. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-18 Freescale Semiconductor...
Page 468 The EBI_ORn registers are used to define the address mask and other attributes for the corresponding chip select. The EBI_CAL_ORn registers appear in the MPC5553 only and are used to define the address mask and other attributes for the corresponding calibration chip select.
Page 469: Functional Description
Valid transaction sizes are 8, 16, and 32 bits. In the MPC5554 and in the 416 BGA package of the MPC5553, only 24 address lines are pinned out externally, but a full 32-bit decode is done internally MPC5553/MPC5554 Microcontroller Reference Manual, Rev.
Page 470 The entire 32-bit data bus is available for both external memory accesses and transactions involving an external master in the MPC5554 and in the 416 BGA package of the MPC5553. In the 324 BGA package of the MPC5553, the data bus is 16 bits.
Page 471 32-bit or 16-bit external transactions according to the port size. See Section 12.4.2.6, “Small Accesses (Small Port Size and Short Burst Length)” for more detail on these cases. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-22 Freescale Semiconductor...
Page 472 12.4.1.13 Four Write/Byte Enable (WE/BE) Signals — Only MPC5554 and 416 BGA of MPC5553 In the MPC5554 and in the 416 BGA of the MPC5553, the functionality of the WE[0:3]/BE[0:3] signals depends on the value of the WEBS bit in the corresponding base register. Setting WEBS to 1 configures these pins as BE[0:3], while resetting it to 0 configures them as WE[0:3].
Page 473 This case consists of two 16-bit external transactions, but for both transactions the WE[0:1]/BE[0:1] signals are the only WE/BE signals affected. NOTE: All areas of the table, both shaded and clear, apply to the 416 BGA package of the MPC5553 and to the MPC5554.
Page 474 EBI_MCR. NOTE This feature must be disabled for multi-master systems. In those cases, one master is getting its clock source from the other master and needs CLKOUT to stay valid continuously. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-25...
Page 475: External Bus Operations
TS signal, and kept valid until the bus master receives TA asserted (the EBI holds them one cycle beyond TA for writes and external TA accesses). Note that for writes with internal TA, RD_WR is not held one cycle past TA. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-26 Freescale Semiconductor...
Page 476 Mode,” to see how the flow and timing diagrams change for external master mode. 12.4.2.4.1 Single Beat Read Flow The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-27...
Page 477 Figure 12-9. Basic Flow Diagram of a Single Beat Read Cycle CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid Figure 12-10. Single Beat 32-bit Read Cycle, CS Access, Zero Wait States MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-28 Freescale Semiconductor...
Page 478 The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. Figure 12-12. Single Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-29...
Page 479 Drives Data Receives Data CS Access Asserts Transfer Acknowledge (TA) Asserts Transfer Acknowledge (TA) Waits 1 Clock Stops Driving Data Figure 12-13. Basic Flow Diagram of a Single Beat Write Cycle MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-30 Freescale Semiconductor...
Page 480 Figure 12-14. Single Beat 32-bit Write Cycle, CS Access, Zero Wait States CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA is valid DATA[0:31] Wait state WE[0:3] Figure 12-15. Single Beat 32-bit Write Cycle, CS Access, One Wait State MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-31...
Page 481 TS assertion of the second access. See Section 12.4.2.9, “Termination Signals Protocol,” for more details. Figure 12-17, Figure 12-18, and Figure 12-19 show a few examples of back-to-back accesses on the external bus. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-32 Freescale Semiconductor...
Page 482 Figure 12-17. Back-to-Back 32-bit Reads to the Same CS Bank CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid Figure 12-18. Back-to-Back 32-bit Reads to Different CS Banks MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-33...
Page 483 Figure 12-19. Write After Read to the Same CS Bank CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA is valid DATA is valid DATA[0:31] Figure 12-20. Back-to-Back 32-bit Writes to the Same CS Bank MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-34 Freescale Semiconductor...
Page 484 The selected slave device must internally increment ADDR[27:29] (also ADDR30 in the case of 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 485 Because burst writes are not supported by the EBI , the EBI negates BDIP during write cycles. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-36 Freescale Semiconductor...
Page 486 Asserts Transfer Acknowledge (TA) Receives Data Next to Last Data Beat Negate BDIP Drives Last Data Asserts Transfer Acknowledge (TA) Receives Last Data Figure 12-22. Basic Flow Diagram of a Burst Read Cycle MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-37...
Page 487 TBDIP = 0 in the appropriate EBI base register results in BDIP being asserted (SCY+1) cycles after the address transfer phase, and being held asserted throughout the cycle regardless of the wait MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-38...
Page 488 ‘00’ Expects more data BDIP DATA[0:31] DATA is valid Wait state Wait state Wait state Wait state Figure 12-26. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-39...
Page 489 The following sections show a few examples of small accesses. The timing for the remaining cases in Table 12-16 can be extrapolated from these and the other timing diagrams in this document. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-40 Freescale Semiconductor...
Page 490 RD_WR does not toggle between the accesses unless that access is the end of a 64-bit boundary. In this case, an extra cycle is required between TA and the next TS in order to get the next 64-bits of write data internally and RD_WR negates during this extra cycle. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-41...
Page 491 0x10 (no carry) Masking Lower 4 Bits) 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-42 Freescale Semiconductor...
Page 492 For burst accesses of any size, address bits 29-31 must be 0. The EBI of the MPC5553 and MPC5554 does not support misaligned accesses. If a misaligned access to the EBI is attempted by an internal master, the EBI errors the access on the internal bus and does not start the access (nor assert TEA) externally.
Page 493 Figure 12-31 shows the device connections on the DATA[0:31] bus. Interface Output Register DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31] 32-bit Port Size 16-bit Port Size Figure 12-31. Interface to Different Port Size Devices MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-44 Freescale Semiconductor...
Page 494 — 32-bit OP0/OP2 OP1/OP3 TSIZ is not enabled on the MPC5553. Also applies when DBM=1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and OP3.
Page 495 BR0 and BR1 signals shown are inputs to the arbiter from the BR pin of each master. The BG0 and BG1 signals are outputs from the arbiter that connect to the BG pin of each master. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-46...
Page 496 The external master is given 2 cycles to start its access after a posed CLKOUT in which bus grant was given to it by the internal arbiter (BG asserted, BB negated for 2 cycles). This means when BG is negated MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 497 ATTR refers to control signals such as RD_WR and TSIZ. Figure 12-35. Internal/External Arbitration Timing Diagram (EARP = 1) Table 12-21 shows a description of the states defined for the internal arbiter protocol. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-48 Freescale Semiconductor...
Page 498 Ext. Owner Ext. Owner Ext. Owner MCU Bus Wait Ext. Owner MCU Bus Wait MCU Bus Wait MCU Bus Wait MCU Bus Wait MCU Bus Wait MCU Bus Wait MCU Owner Busy MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-49...
Page 499 The ETP signal is never asserted in states where it is shown as an ‘X’ for all transitions. RGB is always high in this state, thus it is ignored in the transition logic. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-50...
Page 500 ‘window-of-opportunity’ is satisfied before the internal master may be able to grab the bus again (depending on BR, BB, etc., according to normal transition logic). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 501 EBI only drives TA for the cycle it asserts TA to return data and for 1 cycle afterwards to ensure fast negation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-52 Freescale Semiconductor...
Page 502 EBI recognizes the termination signals provided from an external device. Table 12-23. Termination Signals Protocol Action Negated Negated No Termination Asserted Transfer Error Termination Negated Asserted Normal Transfer Termination MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-53...
Page 503 MCU to an external master (a second MCU) and a shared SDR memory to operate in external master mode. Multi-master support is only available in the MPC5554. Limited support for external master accesses (master/slave systems only) is available in the MPC5553, see Section 12.5.5, “Dual-MCU Operation with Reduced Pinout MCUs.”...
Page 504 EBI, there is no need to use the open drain mode of the pads configuration module for any EBI pins. The Power Architecture storage reservation protocol is not supported by the EBI. Coherency between multiple masters must be maintained via software techniques, such as event passing. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-55...
Page 505 Value on bits 8:11 of 32-bit internal address bus. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode”. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-56 Freescale Semiconductor...
Page 506 External arbiter is the EBI unless a central arbiter device is used. Determined by the internal arbiter of the external master device. Figure 12-39. Basic Flow Diagram of an External Master Read Access MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-57...
Page 507 MCU. Note that the minimal latency for an external master access is 3 clock cycles. The actual MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-58 Freescale Semiconductor...
Page 508 If the external master is another MCU with this EBI, then BB and other control pins are turned off as shown due to use of latched TA internally. This extra cycle is not required by the slave EBI. Figure 12-41. External Master Read from MCU MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-59...
Page 509 See Section 12.4.2.4, “Single Beat Transfer,” and Section 12.4.2.5, “Burst Transfer.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-60 Freescale Semiconductor...
Page 510 Drives Address and Attributes Receives Address Drives Data CS Access Asserts Transfer Acknowledge (TA) Asserts Transfer Acknowledge (TA) Receives Data Figure 12-43. Basic Flow Diagram of an EBI Read Access in External Master Mode MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-61...
Page 511 This case assumes the MCU has no higher priority internal request pending and is able to park the external master on the bus. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-62 Freescale Semiconductor...
Page 512 External master starts read access Both masters off ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid Figure 12-45. External Master Read followed by MCU Read to Same CS Bank MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-63...
Page 513 External master starts read access Both masters off ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid Figure 12-46. MCU Read followed by External Master Read to Different CS Bank MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-64 Freescale Semiconductor...
Page 514 Figure 12-48 shows a 32-bit read from an external master in 16-bit data bus mode. Figure 12-49 shows a 32-bit write from an external master in 16-bit data bus mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-65...
Page 515 TS ADDR[8:31] RD_WR ‘00’ TSIZ[0:1] BDIP TS (Input) DATA is valid DATA is valid DATA[0:15] TA (Output) Minimum 3 wait states Figure 12-49. External Master 32-bit Write to MCU with DBM=1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-66 Freescale Semiconductor...
Page 516 12.4.2.12 Calibration Bus Operation — MPC5553 Only The MPC5553 EBI has a second external bus, intended for calibration use. This bus consists of a second set of the same signals present on the primary external bus (some are shared), except that arbitration, (and optionally other signals also) are excluded.
Page 517: Initialization/Application Information
The EBI block does not support booting directly to external memory (i.e. fetching the first instruction after reset externally). The MPC5553 and MPC5554 use an internal boot assist module, which executes after each reset. The BAM code performs basic configuration of the EBI block, allowing for external boot if desired.
Page 518 16-bit asynchronous memory using three wait states. Figure 12-54 shows a timing diagram of a write operation to a 16-bit asynchronous memory using three wait states. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-69...
Page 519 Figure 12-53. Read Operation to Asynchronous Memory, Three Initial Wait States CLKOUT ADDR[8:31] WE[0:1] DATA is valid DATA[0:31] 3 wait states Figure 12-54. Write Operation to Asynchronous Memory, Three Initial Wait States MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 12-70 Freescale Semiconductor...
Page 520: Connecting An Mcu To Multiple Memories
This scenario is straightforward. Simply connect DATA[0:15] between both MCUs, and configure both for 16-bit data bus mode operation (DBM=1 in EBI_MCR). Note that 32-bit external memories are not supported in this scenario. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 12-71...
Page 521: Summary Of Differences From Mpc5Xx
BDIP is required in your system. 12.5.6 Summary of Differences from MPC5xx Below is a summary list of the significant differences between this EBI used in the MPC5553/MPC5554 and that of the MPC5xx parts: • SETA feature is no longer available —...
Page 522 Added support for 32-bit coherent read and write non-chip select accesses in 16-bit data bus mode • Misaligned accesses are not supported • The MPC5553 has calibration features implemented by four calibration chip selects • Removed support for 3-master systems •...
Page 523: Revision History
Only, made this change to the last sentence: From: Note that in the MPC5553, the EBI_MCR[SIZEN] bit must be set to 1. To: Note that in the MPC5553, the EBI_MCR[SIZEN] bit must be set to 1 in order to run external master accesses to the MPC5553.
Page 524: Introduction
The MPC5553/MPC5554 flash contains a flash bus interface unit (FBIU) and a flash memory array. The FBIU interfaces the system bus to a dedicated flash memory array controller. The FBIU supports a 64-bit data bus width at the system bus port, and a 256-bit read data interface from the flash memory array.
Page 525 (MAS) is also 256-KB in size. High-address space (HAS) is 1.5 MB in size in the MPC5554, and 1.0 MB in the MPC5553. Total address space is 2.0 MB for the MPC5554 and 1.5 MB for the MPC5553. Flash Array Blocks Low-Address Space —256 KB...
Page 526: Features
Section 13.4.2, “Flash Memory Array: User Mode.” 13.1.4.2 Stop Mode In stop mode (FLASH_MCR[STOP] = 1), all DC current sources in the flash are disabled. Refer to Section 13.4.3, “Flash Memory Array: Stop Mode.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-3...
Page 527: External Signal Description
The FBIU occupies a 512-MB portion of the address space. The actual flash array is multiply-mapped within this space. The MPC5553/MPC5554 internal flash has a feature that allows the internal flash timing to be modified to emulate an external memory, hence the name, external emulation mode. The upper five address lines are used to provide additional timing control that allows the FBIU response timing on the system bus (which must be controlled in order to provide for timing emulation of alternate memory types).
Page 528 01101 0x1600_0000 0x161F_FFFF 10101 0x1700_0000 0x171F_FFFF 11101 0x1800_0000 0x181F_FFFF 00110 0x1900_0000 0x191F_FFFF 01110 0x1A00_0000 0x1A1F_FFFF 10110 0x1B00_0000 0x1B1F_FFFF 11110 0x1C00_0000 0x1C1F_FFFF 00111 0x1D00_0000 0x1D1F_FFFF 01111 0x1E00_0000 0x1E1F_FFFF 10111 0x1F00_0000 0x1F1F_FFFF 11111 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-5...
Page 529: Flash Memory Map
13.3.1 Flash Memory Map Table 13-3 shows the flash array memory map and how it is mapped assuming byte addressing. Base addresses for the MPC5554 and the MPC5553 are the following: • Shadow base address = 0x00FF_FC00 • Array base address = 0x0000_0000 •...
Page 530 Flash shadow row, FLASH_SLMLR reset configuration Array Base+ For general use 0xFF_FDFC – 0xFF_FFFF Not available in the MPC5553; only available in the MPC5554. The shadow row does not support RWW. See Section 13.4.2.5, “Flash Shadow Block. Table 13-5 shows the register set for the flash module.
Page 531: Register Descriptions
PGM PSUS ERS ESUS EHV W w1c w1c MPC5554 Reset MPC5553 Reset Reg Addr Base (0xC3F8_8000) + 0x0000 Figure 13-4. Module Configuration Register (FLASH_MCR) Table 13-6. FLASH_MCR Field Descriptions Bits Name Description 0–3 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-8 Freescale Semiconductor...
Page 532 LAS and the configuration to which each value corresponds are shown below. LAS is read only. 110 The LAS value of 110 provides two 16 KB blocks, two 48 KB blocks, and two 64 KB blocks. This is the space configuration for both the MPC5553 and the MPC5554. 12–14 —...
Page 533 EHV = 1 starts the sequence which clears DONE and returns the flash module to program. The flash module cannot exit program suspend and clear DONE while EHV is low. PSUS is cleared on reset. 0 Program sequence is not suspended. 1 Program sequence is suspended. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-10 Freescale Semiconductor...
Page 534 This should be avoided due to reliability implications. Aborting a high voltage operation will leave flash core addresses in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-11...
Page 535 These bits along with bits in the secondary LMLOCK field (FLASH_SLMLR), determine if the block is locked from program or erase. An “OR”’ of FLASH_LMLR and FLASH_SLMLR determine the final lock status. Section 13.3.2.4, “Secondary Low-/Mid-Address Space Block Locking Register (FLASH_SLMLR)” for more information on FLASH_SLMLR. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-12 Freescale Semiconductor...
Page 536 SLOCK is not writable unless LME is high. 0 Shadow row is available to receive program and erase pulses. 1 Shadow row is locked for program and erase. 12–13 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-13...
Page 537 The reset value of these bits is determined by flash values in the shadow row. An erased array will cause the reset value to be 1. Figure 13-7. High-Address Space Block Locking Register (FLASH_HLR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-14 Freescale Semiconductor...
Page 538 The reset value of these bits is determined by flash values in the shadow row. An erased array will cause the reset value to be 1 Figure 13-8. Secondary Low-/Mid-Address Space Block Locking Register (FLASH_SLMLR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-15...
Page 539 SLLOCK bits will default to locked, and will not be writable. 13.3.2.5 Low/Mid Address Space Block Select Register (FLASH_LMSR) The FLASH_LMSR provides a means to select blocks to be operated on during erase. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-16 Freescale Semiconductor...
Page 540 0b1_1111 Five low-address space blocks are selected for erase 0b11_1111 Six low-address space blocks are selected for erase 13.3.2.6 High-Address Space Block Select Register (FLASH_HSR) The FLASH_HSR provides a means to select blocks to be operated on. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-17...
Page 541 Section 13.3.2.5, “Low/Mid Address Space Block Select Register (FLASH_LMSR).” In both the MPC5553 and the MPC5554: 0b0000 High-address space blocks are not selected for erase 0b0001 One high-address space block is selected for erase 0b0011 Two high-address space blocks are selected for erase...
Page 542 This register should only be written in a 32-bit write operation. Reset Reg Addr Base (0xC3F8_8000) + 0x001C WWSC RWSC DPFEN IPFEN PFLIM BFEN Reset Reg Addr Base (0xC3F8_8000) + 0x001C Figure 13-12. Flash Bus Interface Unit Control Register (FLASH_BIUCR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-19...
Page 543 M4PFE is functional only in the MPC5553. Table 13-14. FLASH_BIUCR Field Descriptions Bits Name Description 0-11 — Reserved 12–15 MnPFE Master n prefetch enable. Used to control whether prefetching may be triggered based on the master ID of a requesting master. These bits are cleared by hardware reset. Refer to Table 7-1.
Page 544 For maximum flash performance, this should be set to 0b1. This setting allows for 100 MHz system clock with 2% frequency modulation. This setting allows for 128 MHz system clock with 2% frequency modulation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-21...
Page 545 11 Both read and write accesses may be performed by this master These fields are identified as follows: M0AP= e200z6 core M1AP= Nexus M2AP= eDMA M3AP= EBI M4AP = FEC (implemented in the MPC5553 only) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-22 Freescale Semiconductor...
Page 546: Functional Description
FBIU. Request pipelining allows for improved performance by reducing the access latency seen by the system bus master. Access pipelining can be applied to both read and write cycles by the flash array. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-23...
Page 547 Prefetch triggering can be enabled for data reads. Triggering can be enabled for all data reads or only for data burst reads. Prefetches are not triggered by write cycles. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-24...
Page 548: Flash Memory Array: User Mode
The read state is active when FLASH_MCR[PGM] = 1 and FLASH_MCR[PSUS] = 1 in the MCR. (Program suspend). • The read state is active when FLASH_MCR[ERS] = 1 and FLASH_MCR[ESUS] = 1 and FLASH_MCR[PGM] = 0 in the MCR. (Erase suspend). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-25...
Page 549 Attempts to program the adjoining word will probably result in an operation failure. It is recommended that all programming operations be from 64 bits to 256 bits, and be 64-bit aligned. The programming operation should completely fill selected ECC segments within the page. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-26 Freescale Semiconductor...
Page 550 8 of the program sequence. An aborted program will result in FLASH_MCR[PEG] being set low, indicating a failed operation. The data space being operated on before the abort will contain indeterminate data. The user may not abort a program sequence while in program suspend. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-27...
Page 551 WARNING Aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-28 Freescale Semiconductor...
Page 552 Note: PEG will remain valid under this condition until EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 User Mode Read State ESUS Erase Suspend Figure 13-14. Program Sequence MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-29...
Page 553 See Section 13.3.2.2, “Low-/Mid-Address Space Block Locking Register (FLASH_LMLR), Section 13.3.2.3, “High-Address Space Block Locking Register (FLASH_HLR)” and Section 13.3.2.4, “Secondary Low-/Mid-Address Space Block Locking Register (FLASH_SLMLR)” for more information. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-30 Freescale Semiconductor...
Page 554 The erase operation is resumed by clearing the FLASH_MCR[ESUS] bit. The flash continues the erase sequence from one of a set of predefined points. This can extend the time required for the erase operation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 555 WARNING In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-32 Freescale Semiconductor...
Page 556 Note: PEG will remain valid under this condition until EHV is set high or ERS is cleared. Write MCR Step 9 ERS = 0 User Mode Read State Figure 13-15. Erase Sequence MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-33...
Page 557 FLASH_BIUAPR bitfields, and/or set the boot default value. 13.4.2.6.2 Flash Disable Censorship logic disables read and write access to internal flash according to the logic presented in Table 13-17. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-34 Freescale Semiconductor...
Page 558 Table 13-18. Table 13-18. PFBAPR Modification Logic BOOTCFG Censorship Control Word PFBAPR Bitfields EXTM Writable Upper Half Lower Half 0x55AA 0xXXXX !0x55AA 0xXXXX 0x55AA 0xXXXX !0x55AA 0xXXXX 0x55AA 0xXXXX !0x55AA 0xXXXX MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 13-35...
Page 559: Flash Memory Array: Stop Mode
Reset aborts all operations and forces the flash into normal operating mode ready to receive accesses. FLASH_MCR[DONE] will be set to 1 at the exit of reset. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-36 Freescale Semiconductor...
Page 560: Revision History
FLASH_MCR[DONE] may be polled to determine if reset has been exited. 13.5 Revision History Table 13-19. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • In the Overview section, made this change: From: “...and a 256-bit read data interface to flash memory. If enabled, the FBIU contains a two-entry, 256-bit prefetch buffer and a prefetch controller that prefetches sequential lines of data from the flash array into the buffer.
Page 561 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 13-38 Freescale Semiconductor...
Page 562: Introduction
14.1 Introduction This fast Ethernet control chapter of the MPC5553/MPC5554 reference manual provides a feature-set overview, a functional block diagram, and transceiver connection information for both the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included.
Page 563: Block Diagram
RAM I/F (RISC + microcode) FEC Bus Transmit Receive Counters MDEN FEC_TX_EN FEC_TX_CLK FEC_RX_CLK FEC_TXD[3:0] FEC_RX_DV FEC_CRS FEC_TX_ER FEC_RXD[3:0] FEC_COL FEC_RX_ER MII/7-WIRE DATA FEC_MDIO FEC_MDC OPTION Figure 14-1. FEC Block Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-2 Freescale Semiconductor...
Page 564: Overview
FEC but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3 counters. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-3...
Page 565: Features
Throughputs of 200 Mbps in full-duplex operations and 100 Mbps in half-duplex operations can be attained. 14.2.2 Interface Options The following interface options are supported. A detailed discussion of the interface configurations is provided in Section 14.4.5, “Network Interface Options”. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-4 Freescale Semiconductor...
Page 566: Address Recognition Options
32-bit accesses. There is no support for accesses other than 32-bit. Table 14-1. Module Memory Map Address Function FFF4_C000 (Base Address) – Control/Status Registers FFF4_C1FF FFF4_C200 – FFF4_C3FF MIB Block Counters MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-5...
Page 567: Detailed Memory Map (Control/Status Registers)
Lower 32 Bits of Individual Hash Table 0x0120 GAUR Upper 32 bits of Group Hash Table 0x0124 GALR Lower 32 bits of Group Hash Table 0x0144 TFWR Transmit FIFO Watermark 0x014C FRBR FIFO Receive Bound Register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-6 Freescale Semiconductor...
Page 568: Mib Block Counters Memory Map
RMON Tx Packets < 64 bytes, bad crc 0x0220 RMON_T_JAB RMON Tx Packets > MAX_FL bytes, bad crc 0x0224 RMON_T_COL RMON Tx collision count 0x0228 RMON_T_P64 RMON Tx 64 byte packets MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-7...
Page 569 RMON Rx Packets < 64 bytes, bad crc 0x02A0 RMON_R_JAB RMON Rx Packets > MAX_FL bytes, bad crc 0x02A4 — Reserved 0x02A8 RMON_R_P64 RMON Rx 64 byte packets 0x02AC RMON_R_P65TO127 RMON Rx 65 to 127 byte packets MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-8 Freescale Semiconductor...
Page 570 IEEE_R_OCTETS_OK Octet count for Frames Rcvd w/o Error All accesses to and from the FEC memory map must be via 32-bit accesses. There is no support for accesses other than 32-bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-9...
Page 571: Registers
14.3.4 Registers 14.3.4.1 FEC Burst Optimization Master Control Register (FBOMCR) (MPC5553 Only) Although not an FEC register, the FEC burst optimization master control register (FBOMCR) controls FEC burst optimization behavior on the system bus, hence it is described below. FEC registers are described in Section 14.3.4.2.1, “Ethernet Interrupt Event Register...
Page 572 In other words, an error response to the first half will be seen in the response to the second half, even if the second half does not error. 11-31 — Reserved, should be cleared. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-11...
Page 573 Reset Address Base (0xFFF4_C000) + 0x0004 Reset Address Base (0xFFF4_C000) + 0x0004 “w1c” signifies the bit is cleared by writing 1 to it. Figure 14-3. Ethernet Interrupt Event Register (EIR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-12 Freescale Semiconductor...
Page 574 Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded. 13-31 — Reserved, should be cleared. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-13...
Page 575 FEC will clear R_DES_ACTIVE and cease receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have been placed into the receive descriptor ring. The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-14 Freescale Semiconductor...
Page 576 The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 577 ECR is a read/write user register, though both fields in this register may be altered by hardware as well. The ECR is used to enable/disable the FEC. Reset Address Base + 0x0024 ETHER_EN RESET Reset Address Base + 0x0024 Figure 14-7. Ethernet Control Register (ECR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-16 Freescale Semiconductor...
Page 578 This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero. Reset Address Base + 0x0040 DATA Reset Address Base + 0x0040 “U” signifies a bit that is uninitialized. Figure 14-8. MII Management Frame Register (MMFR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-17...
Page 579 The MSCR provides control of the MII clock (FEC_MDC signal) frequency, allows a preamble drop on the MII management frame, and provides observability (intended for manufacturing test) of an internal counter used in generating the FEC_MDC clock signal. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-18 Freescale Semiconductor...
Page 580 Table 14-12. Programming Examples for MSCR System Clock Frequency MII_SPEED (field in reg) FEC_MDC frequency 50 MHz 2.5 MHz 66 MHz 2.36 MHz 80 MHz 2.5 MHz MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-19...
Page 581 Receive Control Register (RCR) The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-20 Freescale Semiconductor...
Page 582 MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10 Mbps). This bit controls the interface mode for both transmit and receive blocks. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-21...
Page 583 This bit will automatically clear when the pause duration is complete. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-22 Freescale Semiconductor...
Page 584 PAUSE frames. This register is not reset and must be initialized by the user. PADDR1 Reset Address Base + 0x00E4 PADDR1 Reset Address Base + 0x00E4 “U” signifies a bit that is uninitialized. Figure 14-13. Physical Address Low Register (PALR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-23...
Page 585 This register is not reset and must be initialized by the user. Refer to Section 14.4.10, “Full-Duplex Flow Control” for information on using the OPD register. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-24 Freescale Semiconductor...
Page 586 Table 14-18. OPD Field Descriptions Bits Name Description 0–15 OPCODE Opcode field used in PAUSE frames. These bits are a constant, 0x0001. 16–31 PAUSE_DUR Pause duration field used in PAUSE frames. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-25...
Page 587 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-26 Freescale Semiconductor...
Page 588 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-27...
Page 589 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-28 Freescale Semiconductor...
Page 590 FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-29...
Page 591 FIFO RAM. Drivers can use this value, along with the FRSR register, to appropriately divide the available FIFO RAM between the transmit and receive data paths. Reset Address Base + 0x014C R_BOUND Reset Address Base + 0x014C Figure 14-21. FIFO Receive Bound Register (FRBR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-30 Freescale Semiconductor...
Page 592 The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-31...
Page 593 128-bit aligned (evenly divisible by 16). Bits 30 and 31 should be written to 0 by the user. Non-zero values in these two bit positions are ignored by the hardware. This register is not reset and must be initialized by the user prior to operation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-32 Freescale Semiconductor...
Page 594 To minimize bus utilization (descriptor fetches) it is recommended that EMRBR be greater than or equal to 256 bytes. The EMRBR register does not reset, and must be initialized by the user. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-33...
Page 595: Functional Description
By deasserting ECR[ETHER_EN], the configuration control registers such as the TCR and RCR will not be reset, but the entire data path will be reset. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-34 Freescale Semiconductor...
Page 596: User Initialization (Prior To Asserting Ecr[Ether_En])
FEC FIFO/DMA registers that require initialization are defined in Table 14-31. Table 14-31. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR Initialize ETDSR Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-35...
Page 597: Microcontroller Initialization
EMAC Signal Transmit Clock FEC_CLK Transmit Enable FEC_TX_EN Transmit Data FEC_TXD[3:0] Transmit Error FEC_TX_ER Collision FEC_COL Carrier Sense FEC_CRS Receive Clock FEC_RX_CLK Receive Data Valid FEC_RX_DV Receive Data FEC_RX_D[3:0] Receive Error FEC_RX_ER MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-36 Freescale Semiconductor...
Page 598: Fec Frame Transmission
MIB block. Short frames are automatically padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame buffer = 1). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-37...
Page 599: Fec Frame Reception
RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory. The Ethernet controller then waits for a new frame. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-38 Freescale Semiconductor...
Page 600: Ethernet Address Recognition
MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. In general, when a frame is rejected, it is flushed from the FIFO. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-39...
Page 601 NOTES: BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register (PROMiscous mode) Pause Frame - valid Pause frame received Figure 14-26. Ethernet Address Recognition—Receive Block Decisions MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-40 Freescale Semiconductor...
Page 602: Hash Algorithm
Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-41...
Page 603 F5:ff:ff:ff:ff:ff DB:ff:ff:ff:ff:ff FB:ff:ff:ff:ff:ff BB:ff:ff:ff:ff:ff 8B:ff:ff:ff:ff:ff 0B:ff:ff:ff:ff:ff 3B:ff:ff:ff:ff:ff 7B:ff:ff:ff:ff:ff 5B:ff:ff:ff:ff:ff 27:ff:ff:ff:ff:ff 0x10 07:ff:ff:ff:ff:ff 0x11 57:ff:ff:ff:ff:ff 0x12 77:ff:ff:ff:ff:ff 0x13 F7:ff:ff:ff:ff:ff 0x14 C7:ff:ff:ff:ff:ff 0x15 97:ff:ff:ff:ff:ff 0x16 A7:ff:ff:ff:ff:ff 0x17 99:ff:ff:ff:ff:ff 0x18 B9:ff:ff:ff:ff:ff 0x19 F9:ff:ff:ff:ff:ff 0x1A MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-42 Freescale Semiconductor...
Page 604 0x2B BF:ff:ff:ff:ff:ff 0x2C 9F:ff:ff:ff:ff:ff 0x2D DF:ff:ff:ff:ff:ff 0x2E EF:ff:ff:ff:ff:ff 0x2F 93:ff:ff:ff:ff:ff 0x30 B3:ff:ff:ff:ff:ff 0x31 F3:ff:ff:ff:ff:ff 0x32 D3:ff:ff:ff:ff:ff 0x33 53:ff:ff:ff:ff:ff 0x34 73:ff:ff:ff:ff:ff 0x35 23:ff:ff:ff:ff:ff 0x36 13:ff:ff:ff:ff:ff 0x37 3D:ff:ff:ff:ff:ff 0x38 0D:ff:ff:ff:ff:ff 0x39 5D:ff:ff:ff:ff:ff 0x3A MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-43...
Page 605: Full-Duplex Flow Control
(graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are deasserted internally. The user must specify the desired pause duration in the OPD register. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-44 Freescale Semiconductor...
Page 606: Inter-Packet Gap (Ipg) Time
For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for loopback. 14.4.14 Ethernet Error-Handling Procedure The Ethernet controller reports frame reception and transmission error conditions using the FEC RxBDs, the EIR register, and the MIB block counters. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-45...
Page 607 The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error, MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-46...
Page 608: Buffer Descriptors
(W) bit. When set, W indicates that the next descriptor in the ring is at the location pointed to by ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-47...
Page 609 RDAR register. As frames are received the FEC will fill receive buffers and update the associated BDs, then read the next BD in the receive descriptor ring. If the FEC reads a receive BD and MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-48...
Page 610: Ethernet Receive Buffer Descriptor (Rxbd)
Last in frame. Written by the FEC. 0 The buffer is not the last in a frame. 1 The buffer is the last in a frame. Offset + 0 Bits 5-6 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-49...
Page 611 The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-50 Freescale Semiconductor...
Page 612: Ethernet Transmit Buffer Descriptor (Txbd)
Offset + 0 Bit 2 Wrap. Written by user. 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ETDSR. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-51...
Page 613: Revision History
BD in the ring. 14.6 Revision History Table 14-39. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Changed the FEC signal names. Prepended “FEC_” to all signal names. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 614 Table 14-40. Changes to MPC5553/5554 RM for Rev. 5.0 Release Description of Change No change for Rev. 5 release. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 14-53...
Page 615 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 14-54 Freescale Semiconductor...
Page 616: Introduction
Allows reads and writes of the SRAM memory arrays. 15.2.2 Standby Mode Preserves the 32 KB of standby memory when the 1.5 V power is less than the level of V STBY MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 15-1...
Page 617: External Signal Description
Internal SRAM write operations are performed on the following byte boundaries: — 1 byte (0:7 bits) — 2 bytes (0:15 bits) — 4 bytes or 1 word (0:31 bits) — 8 bytes or 2 words (0:63 bits) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 15-2 Freescale Semiconductor...
Page 618: Access Timing
(access operation during the previous clock) Wait States Lists the number of wait states (bus clocks) used by the access operation according to the combination of the current and previous access operation MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 15-3...
Page 619: Reset Operation
Any data stored during such an access becomes the intended data, and no other address locations are accessed or changed. If the MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 15-4...
Page 620: Initialization/Application Information
# write all 32 GPRs to L2SRAM addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128 bdnz init_l2ram_loop # loop for 64k of L2SRAM # done MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 15-5...
Page 621: Revision History
15.8 Revision History Table 15-3. Changes to MPC5553/5554RM for Rev. 4.0 Release Description of Change • Added Modes of Operation section and the subsections Normal Functional Mode, Standby Mode, and Data Retention. • Replaced Functional Description, Section 15.5, “Functional Description” with new wording: From: The RAM BIU generates a 72-bit code word based upon a 64-bit data write.
Page 622 Table 15-3. Changes to MPC5553/5554RM for Rev. 4.0 Release (Continued) • Incorporated review comments: Section 15.6, “SRAM ECC Mechanism added the following paragraph The SRAM ECC detects the following conditions and produces the following results: Detects and corrects all 1-bit errors...
Page 623 Table 15-3. Changes to MPC5553/5554RM for Rev. 4.0 Release (Continued) Changed Section 15.7, “Initialization/Application Information from: In order to use the SRAM, it is essential for the ECC check bits to be initialized after power on. A 64-bit cache inhibited write to each location in SRAM should be used to initialize the SRAM array as part of the application initialization code.
Page 624: Introduction
16.1.2 Overview The MPC5553/MPC5554 BAM contains the MCU boot program code. The BAM control block is connected to peripheral bridge B and occupies the last 16 KB of the MCU memory space. The BAM program supports four different booting modes: from internal flash, from external memory without bus arbitration, from external memory with bus arbitration, serial boot via SCI or CAN interfaces.
Page 625: Modes Of Operation
BAM address space. The CPU starts the BAM program execution at its reset vector from address 0xFFFF_FFFC. Table 16-1 shows the BAM address map. Table 16-1. BAM Memory Map Address Description 0xFFFF_C000– BAM Program Mirrored 0xFFFF_CFFF MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-2 Freescale Semiconductor...
Page 626: Functional Description
Guarded Big Endian Global PID Internal flash 0x0000_0000 0x0000_0000 16 MB Cache enabled Not guarded Big Endian Global PID 0x2000_0000 0x2000_0000 16 MB Cache enabled Not guarded Big Endian Global PID MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 16-3...
Page 627 BOOTCFG pins to enable/disable the internal flash memory and the Nexus interface. The memory address of the censorship word is 0x00FF_FDE0. The censorship word consists of two fields: MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-4 Freescale Semiconductor...
Page 628 RCHW in six predefined locations. If a valid RCHW is found, the BAM program enables the e200z6 watchdog timer with the RCHW[WTE] bit. If a valid RCHW is not found, the BAM program proceeds to the serial boot mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 16-5...
Page 629 16-5, the BAM program sets up the two MMU regions differently than in internal flash boot mode. The internal flash logical address space is mapped to the physical addresses of the EBI. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-6 Freescale Semiconductor...
Page 630 2. Configures EBI for external arbitration (sets the EARB bit). 3. Configures the additional I/O signals BB, BG, BR for bus function. (This applies only to the MPC5554.) See Table 16-6. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 16-7...
Page 631 If the BAM program does find a valid RCHW, it configures data pins and CS0 port size according to the RCHW[PS0] bit and the e200z6 core watchdog according to the RCHW[WTE] bit. The watchdog timeout MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-8...
Page 632 Serial Boot Mode MMU and EBI Configuration The BAM program sets up the MPC5553/MPC5554 MMU for all peripheral and memory regions in one of two different modes and sets up the EBI in one of three different modes; depending on how serial boot mode was entered.
Page 633 All data received is assumed to be good and is echoed out on the TXD signal. It is the responsibility of the host computer to compare the echoes with the sent data and restart the process if an error is detected. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-10...
Page 634 CAN Serial Boot Mode Download Protocol The download protocol follows 4 steps: 1. Download 64-bit password 2. Download start address and size of download 3. Download data 4. Execute code from start address MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 16-11...
Page 635 The host should not send another CAN message until the echo of the previous message has been received by the host. A CAN message sent before the echo is received is ignored. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-12...
Page 636 Serial Boot Mode Protocol The download protocol follows four steps: 1. Download 64-bit password 2. Download start address and size of download 3. Download data 4. Execute code from start address MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 16-13...
Page 637 (maximum 4 bytes). The BAM also writes 0x00 to all memory locations from the last byte of data downloaded to the following 8 byte boundary (maximum 7 bytes). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 16-14 Freescale Semiconductor...
Page 638: Interrupts
No interrupts are generated by or are enabled by the BAM. 16.4 Revision History Table 16-13. Changes to MPC5553/5554 for Rev. 4 Release Description of Change • Added footnote: “Signal enabled for MPC5554” to BB, BR, BG, TSIZ signals in External Bus Interface Configuration table.
Page 639 Table 16-14. Changes to MPC5553/5554 for Rev. 5 Release Description of Change • In the table “MMU Configuration for Internal Flash Boot”, for the TLB entry 2- EBI region, updated the Physical Base Address to 0x2000_0000. • In section “CAN and eSCI Configuration”, updated the watchdog timer time-out period from 3 x 2^28 system clock cycles to 2^27 system clock cycles.
Page 640: Introduction
Chapter 17 Enhanced Modular Input/Output Subsystem (eMIOS) 17.1 Introduction This chapter describes enhanced modular input/output subsystem (eMIOS) MPC5553/MPC5554, which provides functionality to generate or measure timed events. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-1...
Page 641: Block Diagram
Note 1: Connection between UC[n-1] and UCn necessary to implement QDEC mode. Note 2: On channels 12–15, there is no input from EMIOS[12:15], but only from the DSPI module. Figure 17-1. eMIOS Block Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-2 Freescale Semiconductor...
Page 642: Overview
In debug mode, all clocks are running and all registers are accessible; thus, this mode is not intended for power saving, but for use during software debugging. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-3...
Page 643 Center aligned output pulse width modulation with dead time insertion, buffered Output pulse width modulation, normal Output pulse width modulation, buffered These modes are described in Section 17.4, “Functional Description.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-4 Freescale Semiconductor...
Page 644: External Signal Description
A value of 0 refers to the reset value of the signal. Hi-Z refers to the state of the external pin if a tri-state output buffer is controlled by the corresponding eMIOS signal. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 645 EMIOS_CCRn[ODISSL] field. ETPUx_ODIy input signals disable outputs for eTPU engine x, channels (y*8) through (y*8+7). Refer to the ETPU chapter for more details. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-6 Freescale Semiconductor...
Page 646: Memory Map/Register Definition
Base + 0x0260 UC18 Unified Channel 18 Registers Base + 0x0280 UC19 Unified Channel 19 Registers Base + 0x02A0 UC20 Unified Channel 20 Registers Base + 0x02C0 UC21 Unified Channel 21 Registers MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-7...
Page 647: Register Description
EMIOS_MCR contains global control bits for the eMIOS module. MDIS FRZ GTBE ETB GPREN Reset Reg Addr Base + 0x0000 GPRE Reset Reg Addr Base + 0x0000 Figure 17-2. eMIOS Module Configuration Register (EMIOS_MCR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-8 Freescale Semiconductor...
Page 648 Global prescaler. Selects the clock divider value for the global prescaler, as shown in [0:7] Table 17-7 below. 24–31 — Reserved. The GTBE signal is an inter-module signal, not an external pin on the device. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-9...
Page 649 The EMIOS_OUDR serves to disable transfers from the A2 to the A1 channel registers and from the B2 to the B1 channel registers when values are written to these registers, and the channel is running in modulus counter (MC) mode or an output mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-10 Freescale Semiconductor...
Page 650 Section 17.4.4.4, “Modes of Operation of the Unified Channels.” Reset Reg Addr UCn Base + 0x00 Reset Reg Addr UCn Base + 0x00 Figure 17-5. eMIOS Channel A Data Register (EMIOS_CADRn) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-11...
Page 651 Figure 17-6. eMIOS Channel B Data Register (EMIOS_CBDRn) Table 17-9. EMIOS_CADRn and EMIOS_CBDRn Value Assignments Register Access Operating Mode Write Read Write Read GPIO A1, A2 B1,B2 SAIC — SAOC IPWM — — — — DAOC — QDEC MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-12 Freescale Semiconductor...
Page 652 The eMIOS_CCRn enables the setting of several control parameters for a unified channel. Among these controls are the setting of a channel prescaler, channel mode selection, input trigger sensitivity and filtering, interrupt and DMA request enabling, and output mode control. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-13...
Page 653 10 output disable input 2 11 output disable input 3 4–5 UCPRE Prescaler. Selects the clock divider value for the unified channel internal prescaler, as [0:1] shown below. UCPRE[0:1] Divide Ratio MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-14 Freescale Semiconductor...
Page 654 Interrupt DMA request Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt DMA request Interrupt DMA request Interrupt DMA request Interrupt DMA request Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt Reserved MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-15...
Page 655 B, otherwise it has no effect. 0 Has no effect 1 Force a match at comparator B For input modes, the FORCMB bit is not used and writing to it has no effect. — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-16 Freescale Semiconductor...
Page 656 For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 0 The EDPOL value is transferred to the output flip-flop 1 The output flip-flop is toggled MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-17...
Page 657 0000000 General purpose input/output mode (input) 0000001 General purpose input/output mode (output) 0000010 Single action input capture 0000011 Single action output compare 0000100 Input pulse width measurement 0000101 Input period measurement MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-18 Freescale Semiconductor...
Page 658 (FLAG set at match of internal counter and comparator A or comparator B, immediate update) 0011011 Output pulse width and frequency modulation (FLAG set at match of internal counter and comparator A or comparator B, next period update) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-19...
Page 659 Center aligned output pulse width modulation, buffered (FLAG set on trailing edge, trailing edge dead-time) 1011101 Center aligned output pulse width modulation, buffered (FLAG set on trailing edge, leading edge dead-time) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-20 Freescale Semiconductor...
Page 660 Overflow. Indicates that an overflow has occurred in the internal counter. OVFL is cleared by writing a 1 to it. 0 No overflow 1 An overflow had occurred 17–28 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-21...
Page 661: Functional Description
The eMIOS provides independent channels (UC) that can be configured and accessed by the MPC5553/MPC5554. Four time bases can be shared by the channels through four counter buses and each unified channel can generate its own time base. Optionally, the counter A bus can be driven by an external time base from the eTPU imported through the STAC interface.
Page 662 STAC client. There are restrictions on engine export/import targets: one engine cannot export from or import to itself, nor can it import time base and/or angle count if in angle mode. The MPC5553/MPC5554 STAC server identification assignment is shown in Table 17-13.
Page 663: Global Clock Prescaler Submodule (Gcp)
Output disable input selector that selects the output disable input signal to be used as the unified channel output disable • Control state machine (FSM) The major components and functions of the MPC5553/MPC5554 unified channels are discussed in Section 17.4.4.1, “Programmable Input Filter (PIF) through Section 17.4.4.4, “Modes of Operation of the Unified Channels.”...
Page 664 The PIF is a 5-bit programmable up counter that is incremented by the selected clock source, according to bits IF[0:3] in EMIOS_CCRn. The clock source is selected by the EMIOS_CCRn[FCK] bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-25...
Page 665 During freeze, all registers are accessible. When the unified channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-26...
Page 666 UC operation, the double-buffered modes MCB, OPWFMB, OPWMB, and OPWMCB are provided (beginning at Section 17.4.4.4.15, “Modulus Counter, Buffered Mode (MCB) (MPC5553 Only)”). In these modes the A and B registers are double buffered. Descriptions of the double-buffered modes are presented separately, because there are several basic differences from the single-buffered MC, OPWFM, OPWM, and OPWMC modes.
Page 667 EDPOL is transferred to it. At the same time, the FLAG bit is set to indicate that the output compare match has occurred. Writing to register EMIOS_CADRn stores the value in register A2 and reading to register EMIOS_CADRn returns the value of register A1. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-28 Freescale Semiconductor...
Page 668 The leading edge sensitivity (that is, pulse polarity) is selected by EDPOL bit in the EMIOS_CCRn. Registers EMIOS_CADRn and EMIOS_CBDRn return the values in register A2 and B1, respectively. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-29...
Page 669 When the second edge of the same polarity is detected, the counter bus value is latched into registers A2 and B2, the data previously held in register B2 is transferred to data register B1, and the FLAG bit is set MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-30...
Page 670 MODE[6] controls if the EMIOS_CSRn[FLAG] is set on both matches or just on the second match (see Table 17-11 for details). If subsequent enabled output compares occur on registers A1 and B1, pulses will continue to be generated, regardless of the state of the FLAG bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-31...
Page 671 Writing EMIOS_CBDRn writes to B1. A2value transferred to A1 according to OUn bit. B2value transferred to B1 according to OUn bit. Figure 17-21. Double Action Output Compare with FLAG Set on Both Matches MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-32 Freescale Semiconductor...
Page 672 The FORCMA and FORCMB bits have no effect when the unified channel is configured for PEA mode. Figure 17-22 Figure 17-23 show how the unified channel can be used for continuous and single shot pulse/edge accumulation mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-33...
Page 673 Cleared on the first input event after writing to register A1. After input filter. Writing EMIOS_CADRn writes to A1. Reading EMIOS_CADRn returns the value of A2. Reading EMIOS_CBDRn returns the value of B1. Figure 17-22. Pulse/Edge Accumulation Continuous Mode Example MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-34 Freescale Semiconductor...
Page 674 For continuous operation (MODE[6] cleared), the next match between comparator A and the selected time base clears the internal counter and counting is enabled again. In order to guarantee the accuracy when MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 675 0x000303 Counter Bus A1 Value 0x000090 0x000090 0x000090 B1 Value 0x000303 0x000303 0x000303 Notes: Writing EMIOS_CADRn writes to A1. Writing EMIOS_CBDRn writes to B1. Figure 17-24. Pulse/Edge Counting Continuous Mode Example MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-36 Freescale Semiconductor...
Page 676 EDPOL bit selects the count direction according to the phase difference between phase_A and phase_B signals. Figure 17-26 Figure 17-27 show two unified channels configured to quadrature decode mode for count and direction encoder and phase_A and phase_B encoders, respectively. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-37...
Page 677 Register A1 holds the start time and register B1 holds the stop time of the programmable time interval. When a match occurs between register A and the selected timebase, the internal counter is cleared and it MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-38...
Page 678 Modulus counter (up counter, external clock source) 0b0010010– Reserved 0b0010011 0b0010100 Modulus counter (up/down counter, no change in counter direction upon match of input counter and register B1, internal clock source) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-39...
Page 679 Figure 17-29 Figure 17-30 shows how the unified channel can be used as modulus counter in up mode and up/down mode, respectively. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-40 Freescale Semiconductor...
Page 680 (FLAG set at match of internal counter and comparator A or comparator B, immediate update) 0b0011011 Output pulse width and frequency modulation (FLAG set at match of internal counter and comparator A or comparator B, next period update) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-41...
Page 681 OPFWM mode with next period update PFWM mode. In both figures EDPOL = 1, so the output is low during the duty cycle. Table 17-25 has additional illustrative examples. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-42 Freescale Semiconductor...
Page 682 Writing EMIOS_An writes to A2. Writing EMIOS_Bn writes to B2. A2value transferred to A1 according to OUn bit. B2value transferred to B1 according to OUn bit. Figure 17-32. OPWFM with Next Period Update MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-43...
Page 683 Unified Channel Mode of Operation 0b0011100 Center aligned output pulse width modulation (FLAG set in trailing edge, trailing edge dead-time) 0b0011101 Center aligned output pulse width modulation (FLAG set in trailing edge, leading edge dead-time) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-44 Freescale Semiconductor...
Page 684 A or B respectively. If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated, regardless of the state of the FLAG bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-45...
Page 685 Writing EMIOS_An writes to A2. Writing EMIOS_Bn writes to B1. A2value transferred to A1 according to OUn bit. B2value transferred to B1 according to OUn bit. Figure 17-33. Output PWMC with Leading Dead-time Insertion MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-46 Freescale Semiconductor...
Page 686 MODE[6] bit controls the transfer from register B2 to B1, which can be done either immediately (MODE[6] cleared), providing the fastest change in the duty cycle, or at every match of register A1 (MODE[6] set). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-47...
Page 687 Notes: 1 Writing EMIOS_An writes to A2. 2 Writing EMIOS_Bn writes to B2. A2value transferred to A1 according to OUn bit. B2value transferred to B1 according to OUn bit. Figure 17-35. Output PWM with Immediate Update MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-48 Freescale Semiconductor...
Page 688 A2value transferred to A1 according to OUn bit. B2value transferred to B1 according to OUn bit. Figure 17-36. Output PWM with Next Period Update 17.4.4.4.15 Modulus Counter, Buffered Mode (MCB) (MPC5553 Only) Table 17-28. Mode of Operation: MCB Mode MODE[0:6]...
Page 689 MCB up/down counter mode. The A1 register is updated at the cycle boundary. If A2 is written in cycle (n), this new value will be used in cycle (n+1) for the next A1 match. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-50...
Page 690 (n) in order to be used in cycle (n+1). Thus A1 receives the new value at the next cycle boundary. The EMIOS_OUDR[n] bits can be used to disable the update of A1 register. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 691 Note that in the example shown in Figure 17-41 prescaler ratio is set to two (refer to Section 17.5.3, “Time Base Generation). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-52 Freescale Semiconductor...
Page 692 B1 match negative edge from cycle (n). This allows the use of the A1 match positive edge to mask the B1 match negative edge when they occur at the same time. The result is that no transition occurs on the output flip-flop, and a 0% duty cycle is generated. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-53...
Page 693 A2 or B2 data written on cycle (n) were loaded to A1 or B1, respectively, thus generating matches in cycle (n+1). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-54 Freescale Semiconductor...
Page 694 A1/B1 Load Signal 0x000004 0x000006 0x000002 A1 Value 0x000002 0x000004 0x000006 A2 Value B1 Value 0x000008 0x000006 B2 Value 0x000008 0x000006 Figure 17-44. eMIOS OPWFMB Mode Example — Active Output Disable MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-55...
Page 695 Center aligned output pulse width modulation, buffered (FLAG set on trailing edge, trailing edge dead-time) 0b1011101 Center aligned output pulse width modulation, buffered (FLAG set on trailing edge, leading edge dead-time) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-56 Freescale Semiconductor...
Page 696 A1/B1 Load Signal A1 Value 0x000020 0x000015 0x000016 A2 Value 0x000020 0x000015 0x000016 B1 Value 0x000004 0x000005 0x000006 B2 Value 0x000004 0x000005 0x000006 Figure 17-46. eMIOS OPWMCB Mode Example — A1/B1 Register Loading MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-57...
Page 697 0x000001 and B1 matches are enabled. When the match between register B1 and the selected time base occurs the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-58 Freescale Semiconductor...
Page 698 The FLAG bit is not set in the case of the FORCMA, FORCMB or both bits being set at the same time. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-59...
Page 699 When the output disable is negated, the channel output flip-flop is again controlled by A1 and B1 matches. This process is synchronous, meaning that the output channel pin transitions only occur on system clock edges. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-60 Freescale Semiconductor...
Page 700 A1 or B1. Refer to Figure 17-41, which illustrates the delay from matches to output flip-flop transition in OPWFMB mode. 17.4.4.4.18 Output Pulse Width Modulation, Buffered Mode (OPWMB) (MPC5553 Only) Table 17-31. Mode of Operation: OPWMB Mode MODE[0:6] Unified Channel Mode of Operation...
Page 701 B1 = 8 signal negative edge. In this case the A1 match has precedence over the B1 match, causing the output flip-flop to remain at the EDPOL value, thus generating a 0% duty cycle. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-62 Freescale Semiconductor...
Page 702 A1 or B1 match. The output disable does not modify the flag bit behavior. Note that there is one system clock delay between the assertion of the output disable signal and the transition of the output flip-flop. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 17-63...
Page 703 EDPOL at B1 matches. In this example, if B1 = 0x000009, a B1 match does not occur, and thus a 0% duty cycle signal is generated. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-64 Freescale Semiconductor...
Page 704: Initialization / Application Information
Note that for the same programmed match value, the period is shorter when using a prescaler ratio greater than one. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 705 NOTE: The period of the time base does not include the match value. When a match occurs, the first clock cycle is used to clear the internal counter, starting another period Figure 17-56. eMIOS Time Base Example — Prescale Ratio = 3, Match Value = 3 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-66 Freescale Semiconductor...
Page 706: Revision History
Figure 17-57. eMIOS Time Base Example — Prescale Ratio = 2, Match Value = 5 17.6 Revision History Table 17-32. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Added Table 17-14 Mode of Operation: GPIO Mode to the section titled General Purpose Input/Output Mode.
Page 707 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 17-68 Freescale Semiconductor...
Page 708: Introduction
• 16 Kbytes (MPC5554) or 12 Kbytes (MPC5553) of shared code memory (SCM). • For the MPC5553, only one eTPU engine: eTPU A in the eTPU reference manual. Ignore any references to eTPU B. • The eTPU debug interface is built into the MPC5553/MPC5554’s debug module. Refer to Section 10.2.1 of the eTPU reference manual for details on eTPU debug.
Page 709: Block Diagram
Chapter 6, “System Integration Unit (SIU).” Because of the above differences between the MPC5553/MPC5554’s implementation of the eTPU and the full eTPU, full register bit descriptions are included within this chapter as well as in the Enhanced Time Processing (eTPU) Reference Manual.
Page 710: Etpu Operation Overview
MPC5553/MPC5554 core requests, or inter-channel requests. Events that call for local eTPU processing activate the microengine by issuing a service request. The service request microcode may send an interrupt to the MPC5553/MPC5554 core, but the core cannot be directly interrupted by I/O channel events.
Page 711 32-bit shared data memory (SDM), which is also used for passing information between the MPC5553/MPC5554’s core and both (or one) The bus interface unit (BIU) allows the core to access eTPU microengines.
Page 712 SCM (which also disables host access). 18.1.3.1.4 Shared Data Memory (SDM) The SDM works as data RAM that can be accessed by the MPC5553/MPC5554 core and up to two eTPU engines. This memory is used for either: •...
Page 713 The host can also access the SDM space mirrored in an alternate area with parameter sign extension (PSE). PSE allows for 24-bit data to be accessed as 32 bit sign-extended data without using the MPC5553/MPC5554’s bandwidth to extend the data. Parameter signal extension accesses differ from the usual host accesses to the original SDM area as follows: •...
Page 714 Out of reset, all channels are disabled. The MPC5553/MPC5554 core makes a channel active by assigning it one of three priorities: high, middle, or low. The scheduler determines the order in which channels are serviced based on channel number and assigned priority.
Page 715: Features
— A link service request allows activation of a channel thread by request of another channel, even between eTPU engines. — A host service request allows activation of a channel thread by the MPC5553/MPC5554 core request. — Each channel has an event mechanism that supports single and double action functionality in various combinations.
Page 716 — Interleaved SCM access in dual-engine eTPU (MPC5554) avoids contention in time for instruction memory. — 3 (MPC5554) or 2.5 (MPC5553) Kbytes of shared data memory (SDM) with interleaved access in dual (MPC5554) eTPU engine avoids contention for data memory.
Page 717: Modes Of Operation
TCRCLK clock input, totalling 130 in a dual engine system, or 65 in a single engine system. There are also 4 internal output disable signals that implement the output disable feature needed MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-10...
Page 718: Detailed Signal Description
Signals,” for more information. 18.3.2 Detailed Signal Description 18.3.2.1 Output and Input Channel Signals The channel signal connections for eTPU engine A (in both the MPC5553 and the MPC5554) and eTPU engine B (only in the MPC5554) are described in Table 18-1 Table 18-2, respectively.
Page 719 Table 18-1. eTPU A Channel Connection Table (both MPC5553 and MPC5554) (Continued) eTPU DSPI Serial Signals with eTPU Channel eTPU A Channel Pin Number Channel Which eTPU Connections Signal Number Connections Signal is Shared: 16–19 not connected GPIO[130:133] H4–H2 17–19...
Page 720 Refer to Section 17.2.1.2, “Output Disable Input—eMIOS Output Disable Input Signals for more information on the output disable signals. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-13...
Page 721: Memory Map/Register Definition
Base + 0x0_02FF Base + 0x0_0300– Reserved Base + 0x0_03FF Base + 0x0_0400– eTPU A channel registers Base + 0x0_07FF Base + 0x0_0800– eTPU B channel registers Base + 0x0_0BFF MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-14 Freescale Semiconductor...
Page 722: Register Description
A time base 1 Base + 0x0_0028 ETPU_TB2R_A eTPU A time base 2 Base + 0x0_002C ETPU_REDCR_A eTPU A STAC bus interface configuration register Base + 0x0_0030– — Reserved — Base + 0x0_003F MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-15...
Page 723 Base + 0x0_027F Base + 0x0_0280 ETPU_CPSSR_A eTPU A channel pending service status register Base + 0x0_0284 ETPU_CPSSR_B eTPU B channel pending service status register Base + 0x0_0288 — Reserved — MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-16 Freescale Semiconductor...
Page 724 ETPU_C31CR_B eTPU B channel 31 configuration register Base + 0x0_09F4 ETPU_C31SCR_B eTPU B channel 31 status and control register Base + 0x0_09F8 ETPU_C31HSRR_B eTPU B Channel 31 host service request register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-17...
Page 725 — Base + 0x1_FFFF The register at this address is available only on the MPC5554, not on the MPC5553. Parameter sign extension access area. See the eTPU reference manual. SCM access is only available under certain conditions when ETPU_MCR[VIS] = 1. The SCM can only be written in 32-bit accesses.
Page 726 0 Signature mismatch not detected. 1 MISC has read entire SCM array and the expected signature in ETPU_MISCCMPR does not match the value calculated. This bit is cleared by writing 1 to GEC. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-19...
Page 727 The eMIOS also has an GTBE bit. Assertion of either the eMIOS or eTPU GTBE bit starts time bases for the eMIOS and eTPU, see the eTPU reference manual. 18.4.2.1.2 eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR) ETPU_CDCR configures and controls dual-parameter coherent transfers. For more information, refer to the eTPU reference manual. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-20 Freescale Semiconductor...
Page 728 (from the SDM base address) of the parameter which is the destination or source (defined by WR) of the coherent transfer. The SDM address offset of the parameter is {CTBASE, PARM0}*4.Note that PARM0 allows non-contiguous parameters to be transferred coherently MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-21...
Page 729 This register can be written by the host with the 32-bit instruction to be executed by the microengine to recover from runaway code. This register is global to both ETPU engines. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-22 Freescale Semiconductor...
Page 730 A: Base + 0x0_0014 / eTPU B: Base + 0x0_0018 CDFC Reset Reg Addr eTPU A: Base + 0x0_0014 / eTPU B: Base + 0x0_0018 Figure 18-9. eTPU Engine Configuration Register (ETPU_ECR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-23...
Page 731 Refer to the eTPU reference manual for further details about entering halt mode. 0 eTPU engine is not halted. 1 eTPU engine is halted 9–12 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-24 Freescale Semiconductor...
Page 732 For more information on filtering, refer to the eTPU reference manual. Changing CDFC during eTPU normal input channel operation is not recommended because it changes the behavior of the transition detection logic while executing its operation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-25...
Page 733 Writes to this register issue a bus error and are ineffective when MDIS=1. Reads are always allowed. 18.4.2.2.1 eTPU Time Base Configuration Register (ETPU_TBCR) This register configures several time base options. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-26 Freescale Semiconductor...
Page 734 A: Base + 0x0_0020 / eTPU B: Base + 0x0_0040 Figure 18-10. eTPU Time Base Configuration Register (ETPU_TBCR) NOTE The MPC5554 has two eTPU engines, where the MPC5553 only has one. So for MPC5554, there are 2 TCRCLK signals, one for each eTPU engine: TCRCLKA and TCRCLKB MPC5553/MPC5554 Microcontroller Reference Manual, Rev.
Page 735 DIV8 clock (system clock / 8) See Note Reserved Reserved TCR2CTL shuts down TCR2 clocking, except on Angle Mode. TCR2 can also change as STAC client. These selections must not be used with AM=1 (Angle Mode). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-28 Freescale Semiconductor...
Page 736 Internal Timebase input, or TCRCLK filtered input. This field has no effect on TCCR2 in Angle Mode. For more information on TCR2, refer to the eTPU User’s Manual. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-29...
Page 737 A: Base + 0x0_0024 / eTPU B: Base + 0x0_0044 TCR1 Reset Reg Addr eTPU A: Base + 0x0_0024 / eTPU B: Base + 0x0_0044 Figure 18-11. eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-30 Freescale Semiconductor...
Page 738 18.4.2.2.4 STAC Bus Configuration Register (ETPU_REDCR) This register configures the eTPU STAC bus interface module and operation. For more information on the STAC interface, refer to the eTPU reference manual. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-31...
Page 739 TCR. For a client mode, the SRV2 field determines the Server address to which the client listens. 0 Resource Client operation. 1 Resource Server operation. 18–19 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-32 Freescale Semiconductor...
Page 740 R CIS15 CIS14 CIS13 CIS12 CIS11 CIS10 CIS9 CIS8 CIS7 CIS6 CIS5 CIS4 CIS3 CIS2 CIS1 CIS0 W w1c Reset Reg Addr eTPU A: Base + 0x0_0200 / eTPU B: Base + 0x0_0204 Figure 18-14. eTPU Channel Interrupt Status Register (ETPU_CISR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-33...
Page 741 In the MPC5554, eTPU A channels [0:2,12:15,28:29] and eTPU B channels [0:3,12:15,28:31] are connected to the DMA; in the MPC5553, eTPU channels [0:2, 14:15] are DMA connected. The data transfer request lines that are not connected to the DMA controller are left disconnected and do not generate transfer requests, even if their request status bits are asserted in registers ETPU_CDTRSR and ETPU_CnSCR.
Page 742 1 indicates that an interrupt overflow occurred in the channel. To clear a status bit, the host must write 1 to it. For details about interrupts refer to the eTPU reference manual. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-35...
Page 743 The host interrupt enable bits for all 32 channels are grouped in ETPU_CIER. The bits are mirrored by the channel configuration registers. For more information on channel configuration registers and interrupt enable, refer to Section 18.4.2.4.2, “eTPU Channel n Configuration Register (ETPU_CnCR),” and the eTPU reference manual. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-36 Freescale Semiconductor...
Page 744 DTRE DTRE DTRE DTRE DTRE DTRE DTRE Reset Reg Addr eTPU A: Base + 0x0_0250 / eTPU B: Base + 0x0_0254 Figure 18-19. eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-37...
Page 745 1 pending service request for channel n NOTE The pending service status bit for a channel is set when a service request is pending, even if the Channel is disabled (CPRn = 0). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-38 Freescale Semiconductor...
Page 746 18.4.2.4 Channel Configuration and Control Registers Each channel, for both eTPU engines, has a group of three registers used to control, configure and check status of that channel as shown in Table 18-24. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 18-39...
Page 747 Reserved In the MPC5554, eTPU A channels [0:2,12:15,28:29] and eTPU B channels [0:3,12:15,28:31] are connected to the DMA; in the MPC5553, eTPU A channels [0:2, 14:15] are connected. The data transfer request lines that are not connected to the DMA controller are left disconnected and do not generate interrupt requests,...
Page 748 CPBA Reset Reg Addr Channel_Register_Base + 0x00 Figure 18-22. TPU Channel n Configuration Register (ETPU_CnCR ETPD is only offered in the MPC5553. Table 18-26. ETPU_CnCR Field Descriptions Bits Name Description Channel interrupt enable. This bit is mirrored from the ETPU_CIER 0 Disable interrupt for this channel.For more information, refer to the eTPU reference...
Page 749 The ETPD value has to be compatible with the function chosen for the channel, selected in the field CFS. For details about entry table and condition encoding schemes, refer to the eTPU reference manual. The ETPD bit is only present in the MPC5553. 1 = Use PSTO for entry point selection.
Page 750 ETPU_CISR, ETPU_CIOSR, ETPU_CDTRSR, and ETPU_CDTROSR respectively. For more information on the three previously mentioned registers, refer to the eTPU reference manual. NOTE The MPC5553/MPC5554 core must write 1 to clear a status bit. NOTE In the MPC5554, eTPU A channels [0:2,12:15,28:29] and eTPU B channels [0:3,12:15,28:31] are connected to the DMA;...
Page 751 Bits Name Description Channel interrupt status. 0 Channel has no pending interrupt to the MPC5553 MPC5554 core. 1 Channel has a pending interrupt to the MPC5553 MPC5554 core. CIS is mirrored in the ETPU_CISR. For more information on ETPU_CISR and interrupts, Section 18.4.2.3.1, “eTPU Channel Interrupt Status Register...
Page 752: Functional Description
These bits are equivalent to the TPU/TPU2/TPU3 host sequence (HSQ) bits. 18.4.2.4.4 eTPU Channel n Host Service Request Register (ETPU_CnHSRR) ETPU_CnHSRR is used by the MPC5553/MPC5554 core to issue service requests to the channel. Reset Reg Addr Channel_Register_Base + 0x08...
Page 753: Initialization/Application Information
In addition, the SCM should be initialized with the eTPU application prior to configuring the eTPU. 18.7 Revision History Table 18-29. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • In Section 18.1.3, “eTPU Operation Overview”, changed:...
Page 754 Table 18-30. Changes to MPC5553/5554 RM for Rev. 5.0 Release Description of Change • In Section 18.4.2.2.4, “STAC Bus Configuration Register (ETPU_REDCR)” changed SERVER_ID1 and SERVER_ID2 fields to read-only and SRV1 and SRV2 fields to read-write. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 755 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 18-48 Freescale Semiconductor...
Page 756: Introduction
19.1 Introduction The enhanced queued analog-to-digital converter (eQADC) of the MPC5553/MPC5554 provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog-to-digital converters (ADCs), and a single master to single slave serial interface to an off-chip external device.
Page 757: Overview
RFIFO by the host CPU or by eDMA. Accordingly, the eQADC generates eDMA or interrupt requests to control data movement between the FIFOs and the system memory, which is external to the eQADC. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-2 Freescale Semiconductor...
Page 758: Features
— Differential conversions (range -2.5V to +2.5V). — Single-ended signal range from 0 to 5V. — Sample times of 2 (default), 8, 64, or 128 ADC clock cycles. — Provides sample time stamp information when requested. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-3...
Page 759: Modes Of Operation
Access to eQADC registers implies that CFIFOs can still be triggered using software triggers, because no scheme is implemented to 1. VREF=VRH-VRL. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-4 Freescale Semiconductor...
Page 760 In stop mode, the free running clock (FCK) output to external device will stop during its low phase if the eQADC SSI is MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 761: External Signals
The following is a list of external signals. These signals are external to the eQADC module, but may or may not be physical pins. See Chapter 2, “Signal Description” for a complete list of all physical pins and signals. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-6 Freescale Semiconductor...
Page 762 Mux Address 0 Digital/ eQADC SSI Serial Data Select Digital AN13 Single Ended Analog Input 13 I / — AN13/ — Analog/ Mux Address 1 Digital/ eQADC SSI Serial Data Out Digital MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-7...
Page 763 Single Ended Analog Input AN[37:39] Single Ended Analog I / — AN[37:39] / Analog Input 37-39 — ETRIG0/ External trigger for CFIFO0, — / Up — / Up Digital GPIO111 CFIFO2, and CFIFO4/ GPIO MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-8 Freescale Semiconductor...
Page 764: Memory Map/Register Definition
Table 19-2. eQADC Memory Map Address Register Name Register Description Size (bits) Base (0xFFF8_0000) EQADC_MCR EQADC module configuration register Base + 0x0004 — Reserved — Base + 0x0008 EQADC_NMSFR eQADC null message send format register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-9...
Page 765 5 Base + 0x006C — Reserved — Base + 0x0070 EQADC_FISR0 eQADC FIFO and interrupt status register 0 Base + 0x0074 EQADC_FISR1 eQADC FIFO and interrupt status register 1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-10 Freescale Semiconductor...
Page 766 Base + 0x014C Base + 0x0150– — Reserved — Base + 0x017C Base + 0x0180– EQADC_CF2Rn eQADC CFIFO2 registers 0–3 Base + 0x018C Base + 0x0190– — Reserved — Base + 0x01BC MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-11...
Page 767 Base + 0x040C Base + 0x0410– — Reserved — Base + 0x043C Base + 0x0440– EQADC_RF5Rn eQADC RFIFO5 registers 0–3 Base + 0x044C Base + 0x0450– — Reserved — Base + 0x07FC MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-12 Freescale Semiconductor...
Page 768: Eqadc Register Descriptions
Disabling the eQADC SSI (0b00 write to ESSIE) or serial transmissions from the eQADC SSI (0b10 write to ESSIE) while a serial transmission is in progress results in the abort of that transmission. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-13...
Page 769 Table 19-34 more information on the MESSAGE_TAG field. NOTE Writing to the eQADC null message send format register while serial transmissions are enabled is not recommended (See EQADC_MCR[ESSIE] field in Section 19.3.2.1). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-14 Freescale Semiconductor...
Page 770 Table 19-6. Minimum Required Time to Valid ETRIG Minimum Time (ns) DFL[0:3] Minimum Clock Count (System Clock = 120MHz) 0b0000 16.67 0b0001 25.00 0b0010 41.67 0b0011 75.00 0b0100 141.67 0b0101 275.00 0b0110 541.67 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-15...
Page 771 Base + 0x0010 (EQADC_CFPR0); Base + 0x0014 (EQADC_CFPR1); Base + 0x0018 (EQADC_CFPR2); Addr Base + 0x001C (EQADC_CFPR3); Base + 0x0020 (EQADC_CFPR4); Base + 0x0024 (EQADC_CFPR5) Figure 19-5. eQADC CFIFO Push Registers (EQADC_CFPRn) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-16 Freescale Semiconductor...
Page 772 Base + 0x0030 (EQADC_RFPR0); Base + 0x0034 (EQADC_RFPR1); Base + 0x0038 (EQADC_RFPR2); Addr Base + 0x003C (EQADC_RFPR3); Base + 0x0040 (EQADC_RFPR4); Base + 0x0044 (EQADC_RFPR5) Figure 19-6. eQADC RFIFO Pop Registers (EQADC_RFPRn) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-17...
Page 773 1 to SSEn will not set SSSn. Writing a 0 to SSEn has no effect. SSEn always is read as 0. 0 No effect. 1 Set the SSSn bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-18 Freescale Semiconductor...
Page 774 High level gated external trigger, continuous scan 0b1100 Falling edge external trigger, continuous scan 0b1101 Rising edge external trigger, continuous scan 0b1110 Falling or rising edge external trigger, continuous scan 0b1111 Reserved MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-19...
Page 775 18 flags becomes asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are enabled). See Section 19.4.7, “eQADC eDMA/Interrupt Request,” for details. 0 Disable underflow interrupt request 1 Enable underflow interrupt request MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-20 Freescale Semiconductor...
Page 776 The EQADC_FISRs contain flag and status bits for each CFIFO and RFIFO pair. Writing 1 to a flag bit clears it. Writing 0 has no effect. Status bits are read only. These bits indicate the status of the FIFO itself. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 777 Write 1 to clear the TORFn bit. Writing 0 has no effect. 0 No trigger overrun occurred 1 Trigger overrun occurred Note: The trigger overrun flag will not set for CFIFOs configured for software trigger mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-22 Freescale Semiconductor...
Page 778 EOQ bit from CFIFOn. It does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate RFIFO. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-23...
Page 779 Note: When generation of interrupt requests is selected (CFFSn=0), CFFFn must only be cleared in the ISR after the CFIFOn push register is accessed. Note: CFFFn should not be cleared when CFFSn is asserted (eDMA requests selected). 7–11 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-24 Freescale Semiconductor...
Page 780 If the maximum index number (CFIFO depth minus 1) is reached, TNXTPTRn is wrapped to 0, else, it is incremented by 1. For details refer to Section 19.4.3.1, “CFIFO Basic Functionality.” Writing any value to TNXTPTRn has no effect. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-25...
Page 781 CFIFO until that point (TC_CFn) is only known after the CFIFO status changes to IDLE, as indicated by CFSn. For details refer to Section 19.4.3.5.1, “Disabled Mode.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-26 Freescale Semiconductor...
Page 782 ADCn command buffer is initiated. CFSn_T0 is a copy of the corresponding CFSn in EQADC_CFSR (see Section 19.3.2.11) captured at the time a command transfer to buffern is initiated. 12–16 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-27...
Page 783 LCFT0 is 0b1111. CFS0_T1 CFS1_T1 CFS2_T1 CFS3_T1 CFS4_T1 CFS5_T1 Reset Base + 0x00A4 (EQADC_CFSSR1) Addr LCFT1 TC_LCFT1 Reset Base + 0x00A4 (EQADC_CFSSR1) Addr Figure 19-12. eQADC CFIFO Status Snapshot Register 1 (EQADC_CFSSR1) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-28 Freescale Semiconductor...
Page 784 CFIFOn to ADCn command buffer is initiated. This field has no meaning when LCFT1 is 0b1111. The third eQADC CFIFO status snapshot register is displayed in Figure 19-13. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-29...
Page 785 External command buffer number Indicator. Indicates to which external command buffer the last command was transmitted. 0 Last command was transferred to command buffer 2. 1 Last command was transferred to command buffer 3. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-30 Freescale Semiconductor...
Page 786 The EQADC_CFSR contains the current CFIFO status. The EQADC_CFSRs are read only. Writing to the EQADC_CFSR has no effect. CFS0 CFS1 CFS2 CFS3 CFS4 CFS5 Reset Reg Addr Base + 0x00AC Reset Reg Addr Base + 0x00AC Figure 19-14. eQADC CFIFO Status Register (EQADC_CFSR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-31...
Page 787 19.3.2.12 eQADC SSI Control Register (EQADC_SSICR) The EQADC_SSICR configures the SSI submodule. Reset Reg Addr Base + 0x00B4 Reset Reg Addr Base + 0x00B4 Figure 19-15. eQADC SSI Control Register (EQADC_SSICR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-32 Freescale Semiconductor...
Page 788 0b000 0b001 0b010 0b011 0b100 0b101 0b110 0b111 Table 19-21. System Clock Divide Factor for Baud Clock BR[0:3] System Clock Divide Factor 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-33...
Page 789 DATA. Contains the last result message that was shifted in. Writes to the [0:25] R_DATA have no effect. Messages that were not completely received due to a transmission abort will not be copied into EQADC_SSIRDR. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-34 Freescale Semiconductor...
Page 790 16-bit entries. Refer to Section 19.4.4, “Result FIFOs,” for more information on RFIFOs. These registers are read only. Data written to these registers is ignored. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-35...
Page 791: On-Chip Adc Registers
Registers ADC_TSCR and ADC_TBCR can be accessed by configuration commands sent to the ADC0 command buffer or to the ADC1 command buffer. A data write to ADC_TSCR through a configuration command sent to the ADC0 command buffer will write the same memory location MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-36 Freescale Semiconductor...
Page 792 This register is also accessible by configuration commands sent to the ADC0 command buffer. 19.3.3.1 ADCn Control Registers (ADC0_CR and ADC1_CR) The ADCn control registers (ADCn_CR) are used to configure the on-chip ADCs. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-37...
Page 793 Speed,” for details about how to set ADC0/1_CLK_PS. The ADCn_CLK_PS field must only be written when the ADCn_EN bit is negated. This field can be configured during the same write cycle used to set ADCn_EN. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-38 Freescale Semiconductor...
Page 794 0b00001 0b00010 0b00011 0b00100 0b00101 0b00110 0b00111 0b01000 0b01001 0b01010 0b01011 0b01100 0b01101 0b01110 0b01111 0b10000 0b10001 0b10010 0b10011 0b10100 0b10101 0b10110 0b10111 0b11000 0b11001 0b11010 0b11011 0b11100 0b11101 0b11110 0b11111 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-39...
Page 795 Clock to Time Stamp System Clock Divide TBC_CLK_PS[0:3] Counter for a 120 MHz Factor System Clock (MHz) 0b0000 Disabled Disabled 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 3.75 0b1010 1.88 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-40 Freescale Semiconductor...
Page 796 TBC_VALUE returns the current value of time base counter. Writes to TBC_VALUE register load the written data to the counter. The time base counter counts from 0x0000 to 0xFFFF and wraps when reaching 0xFFFF. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-41...
Page 797 The ADCn_OCCR contains the offset calibration constant used to fine-tune of ADC0/1 conversion results. The offset constant is a signed 14-bit integer value. Refer to Section 19.4.5.4, “ADC Calibration Feature,” for details about the calibration scheme used in the eQADC. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-42 Freescale Semiconductor...
Page 798: Functional Description
The eQADC can also in parallel and independently of the CFIFOs receive data from the on-chip ADCs or from off-chip external device into multiple RFIFOs. Result data is moved from the RFIFOs to the user-defined result queues in system memory by the host CPU or by the eDMA. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-43...
Page 799: Data Flow In The Eqadc
While conversion results are returned, the eQADC is checking the number of entries in the RFIFO and generating requests to empty it. The process of pushing and popping ADC results to and from an RFIFO can occur simultaneously. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-44 Freescale Semiconductor...
Page 800 SSI NOTES: External Device eQADC SSI n = 0, 1, 2, 3, 4, 5 RFIFO Header Logic ADC Result & Result Buffers Message Figure 19-25. Result Flow During eQADC Operation MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-45...
Page 801 2, then the BUSY0 field, that is to be sent to the eQADC on the next serial transmission, should be encoded assuming that the external command buffer has one entry. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-46 Freescale Semiconductor...
Page 802 The lower byte of conversion commands is always set to 0 to distinguish it from configuration commands. EOQ PAUSE Reserved MESSAGE_TAG (0b0) CFIFO Header ADC Command CHANNEL_NUMBER ADC Command Figure 19-26. Conversion Command Message Format for On-Chip ADC Operation MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-47...
Page 803 0 Message sent to ADC 0. 1 Message sent to ADC 1. Calibration. Indicates if the returning conversion result must be calibrated. 0 Do not calibrate conversion result. 1 Calibrate conversion result. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-48 Freescale Semiconductor...
Page 804 RFIFOs. See Section 19.4.5.3, “Time Stamp Feature,” for details. 0 Return conversion result only. 1 Return conversion time stamp after the conversion result. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-49...
Page 805 R/W bit. PAUSE Reserved ADC_REGISTER HIGH BYTE (0b0) (0b0) CFIFO Header ADC Command ADC_REGISTER LOW BYTE ADC_REG_ADDRESS ADC Command Figure 19-27. Write Configuration Command Message Format for On-chip ADC Operation MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-50 Freescale Semiconductor...
Page 806 ADC register address. Selects a register on the ADC register set to be written or read. Only ADDRESS halfword addresses can be used. See Table 19-25. [0:7] Read Configuration Command Message Format for On-Chip ADC Operation MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-51...
Page 807 External buffer bit. This bit should always be cleared for messages sent to an on-chip ADC. 0 Command is sent to an internal command buffer. 1 Command is sent to an external command buffer. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-52 Freescale Semiconductor...
Page 808 A time stamp. In this case, the stored 16-bit data is the value of the time base counter latched when the eQADC detects the end of the analog input voltage sampling. For details see Section 19.4.5.3, “Time Stamp Feature.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-53...
Page 809 CONVERSION_RESULT is positive, and 0b11 when CONVERSION_RESULT is negative. 2–15 CONVERSION Conversion result. A digital value corresponding to the analog input voltage in a channel _RESULT when the conversion command was initiated. [0:13] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-54 Freescale Semiconductor...
Page 810 FIFO control unit/external device to which external command buffer the corresponding command should be sent. The remaining 25 bits can be anything decodable by the external device. Only the ADC command portion of a command message is transferred to the external device. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-55...
Page 811 External buffer. This bit should always be set for messages sent to an external ADC. Command is sent to an internal command buffer. 1 Command is sent to an external command buffer. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-56 Freescale Semiconductor...
Page 812 Table 19-41. Result Message Format for External Device Operation Bits Name Description 6–7 — Reserved. 8–11 MESSAGE_TAG MESSAGE_TAG Field. Refer to Section , “ Conversion Command Message Format for [0:3] On-Chip ADC Operation.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-57...
Page 813 Operation,” for more information. The MESSAGE_TAG field must be set to the null message tag (0b1000). The eQADC does not store into an RFIFO any incoming message with a null message tag. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-58 Freescale Semiconductor...
Page 814: Command/Result Queues
Operation,” for a description of the message formats and their flow in eQADC. Refer to Section 19.5.5, “Command Queue and Result Queue Usage,” for examples of how command queues and result queues can be used. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-59...
Page 815: Eqadc Command Fifos
CFCTRn is 0. CFIFOn is full when the transfer next data pointer n equals the push next data pointer n and CFCTRn is not 0. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-60...
Page 816 CFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, CFIFOn with 16 entries is shown in sequence after pushing and transferring entries. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-61...
Page 817 • Its commands are bound for an internal command buffer that is not full, and it is the highest priority triggered CFIFO sending commands to that buffer. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-62 Freescale Semiconductor...
Page 818 BUSY fields of the incoming result messages from the external device (see Section , “ Result Message Format for External Device Operation,” for details). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-63...
Page 819 1. A CFIFO0 command is scheduled for the next transmission independently of the type of data that was previously scheduled. The time during which SDS is negated is stretched in order to allow the eQADC to load the CFIFO0 command and start its transmission. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-64 Freescale Semiconductor...
Page 820 (SIU_ETISR) in the SIU block. The eQADC trigger numbers specified by SIU_ETISR[TSEL(0-5)] correspond to CFIFO numbers 0-5. To calculate the CFIFO number that each trigger is connected to, divide the eDMA channel number by 2. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-65...
Page 821 CFIFO after detecting the EOQ bit set in the last transfer. After a EOQ bit is detected, software involvement is required to rearm the CFIFO so that it can detect new trigger events. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-66...
Page 822 The trigger detection hardware is reset. If MODEn is changed from disabled to an edge trigger mode, a new edge, matching that edge trigger mode, is needed to trigger the command transfers from the CFIFO. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-67...
Page 823 If the corresponding level is already present, setting the SSS bit triggers the CFIFO. The CFIFO commands start to be transferred MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-68...
Page 824 CFIFO in a TRIGGERED state. When high-level gated trigger is selected, a high-level signal opens the gate, and a low level closes the gate. The CFIFO commands start to be transferred when the MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 825 The pause bit has no effect in continuous-scan level-trigger mode. 19.4.3.5.4 CFIFO Scan Trigger Mode Start/Stop Summary Table 19-44 summarizes the start and stop conditions of command transfers from CFIFOs for all of the single-scan and continuous-scan trigger modes. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-70 Freescale Semiconductor...
Page 826 (EQADC_CFSSRn).” The last CFIFO to transfer a command to a specific external command buffer can be identified by reading the EQADC_CFSSRn[LCFTSSI] and EQADC_CFSSRn[ENI] fields (see Section 19.3.2.10, “eQADC CFIFO Status Snapshot Registers 0–2 (EQADC_CFSSRn).” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-71...
Page 827 • No trigger occurred. TRIGGER (0b10) TRIGGERED • Appropriate edge or level trigger occurred, OR (0b11) • CFIFO mode is programmed to single-scan software trigger mode and SSS bit is asserted. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-72 Freescale Semiconductor...
Page 828 In single-scan modes, command transfers from the corresponding CFIFO will cease when the eQADC completes the transfer of a entry with an asserted EOQ. Software involvement is required to rearm the CFIFO so that it can detect new trigger events. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-73...
Page 829 For CFIFOs configured for level-trigger mode, a trigger overrun event is only detected when the gate closes and reopens during a single serial command transmission as shown in Figure 19-40. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-74 Freescale Semiconductor...
Page 830 CFIFO. The smallest possible command sequence can have a single command as shown in example 3 of Figure 19-41. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-75...
Page 831 This case happens when different CFIFOs attempt to use different external command buffers and the higher priority CFIFO bars the lower priority one from MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-76 Freescale Semiconductor...
Page 832 • The command sequence became non-coherent. • The CFIFO status changed from the TRIGGERED state. • The CFIFO had underflow. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-77...
Page 833 When the eQADC enters debug or stop mode while a command sequence is being executed, the NCF will become asserted if an empty external command buffer is detected after debug/stop mode is exited. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-78 Freescale Semiconductor...
Page 834 CFIFO5 becomes non-coherent. CF5_ADC1_CM3 TNXTPTR – Transfer Next Data Pointer. CFx_ADCa_CMn – Command n in CFIFOx bound for ADCa. Figure 19-43. Non-Coherency Event When Different CFIFOs Use the Same Buffer MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-79...
Page 835 TNXTPTR – Transfer Next Data Pointer. CFx_ADCa_CMn – Command n in CFIFOx bound for external command buffer a. Figure 19-44. Non-Coherency Event When Different CFIFOs Are Using Different External Command Buffers MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-80 Freescale Semiconductor...
Page 836: Result Fifos
RFIFO and generates interrupt or eDMA requests to drain the RFIFO. EQADC_FISRn[POPNXTPTR] (see Section 19.3.2.8) indicates which entry is currently being addressed by the pop next data pointer, and EQADC_FISRn[RFCTR] provides the number of entries stored in the MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-81...
Page 837 The detailed behavior of the pop next data pointer and receive next data pointer is described in the example shown in Figure 19-47 where an RFIFO with 16 entries is shown for clarity of explanation, the actual MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-82 Freescale Semiconductor...
Page 838 All result data comes with a MESSAGE_TAG field defining what should be done with the received data. The FIFO control unit decodes the MESSAGE_TAG field and: • Stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO number or MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-83...
Page 839: On-Chip Adc Configuration And Control
ADC1_CR[ADC1_CLK_PS] fields (see Section 19.3.3.1) The ADC0/1_CLK_PS field selects the clock divide factor by which the system clock will be divided as showed in Table 19-28. The ADC clock frequency is calculated as below and it must not exceed 12 MHz. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-84 Freescale Semiconductor...
Page 840 ADC clock frequency higher than the maximum one supported by the ADC. ADC clock frequency must not exceed 12 Mhz. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 841 0b01011 0b01100 4.62 0b01101 4.29 0b01110 0b01111 3.75 0b10000 3.53 0b10001 3.33 0b10010 3.16 0b10011 0b10100 2.86 0b10101 2.73 0b10110 2.61 0b10111 0b11000 0b11001 2.31 0b11010 2.22 0b11011 2.14 0b11100 2.07 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-86 Freescale Semiconductor...
Page 842 RAW_RES is the raw, uncalibrated result corresponding to an specific input voltage V • OCC is the offset calibration constant. • The addition of two reduces the maximum quantization error of the ADC. See Section 19.5.6.3, “Quantization Error Reduction During Calibration.” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-87...
Page 843 Calibration. CAL_RES output is the calibrated result, and it is a 14-bit unsigned value. CAL_RES is truncated to 0x3FFF, in case of a overflow, and to 0x0000, in case of an underflow. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-88 Freescale Semiconductor...
Page 844 The FIFO control unit decodes these bits and sends the ADC command to the proper ADC. Other blocks of logic are the result format and calibration submodule, the time stamp logic, and the MUX control logic. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-89...
Page 845 The second advantage of pipelining conversion commands is to provide equal conversion intervals even though the sample time increases on second and subsequent conversions. See Figure 19-52. This is important for any digital signal process application. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-90 Freescale Semiconductor...
Page 846 Result Format Stamp ADC0_Result0 & Logic ADC1_Result1 Time Stamp0 Calibration Time Stamp1 Submodule TBC_CLK_PS Configuration Register Fields NOTE: n = 0, 1, 2, 3, 4, 5 Figure 19-51. On-Chip ADC Control Scheme MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-91...
Page 847: Internal/External Multiplexing
ADC. The differential conversions can only be initiated on four channels: DAN0, DAN1, DAN2, and DAN3. Refer to Table 19-51 Figure 19-52 for the channel numbers used to select differential conversions. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-92 Freescale Semiconductor...
Page 848 ADCn_EMUX bit asserted can access 4 differential pairs, 39 single-ended, and, at most, 32 externally multiplexed channels. Refer to Section 19.4.6.2, “External Multiplexing,” for a detailed explanation about how external multiplexing can be achieved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-93...
Page 849 The analog output of the four multiplex chips are each connected to four separate eQADC inputs, ANW, ANX, ANY, and ANZ. The MA pins correspond to the MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-94...
Page 850 (ANW, ANX, ANY, and ANZ) by interpreting the CHANNEL_NUMBER field. As a result, up to 32 externally multiplexed channels appear to the conversion queues as directly connected signals. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-95...
Page 851: Eqadc Edma/Interrupt Request
(EQADC_IDCRn),” and the interrupt flag bits are described in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).” Table 19-54 depicts all interrupts and eDMA requests generated by the eQADC. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-96 Freescale Semiconductor...
Page 852 Writing 1 to the CFFFn bit is not allowed while CFDS = 1. CFFFn = 1 For details refer to Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn),” and Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn).” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-97...
Page 853 End of Queue Interrupt Request EOQFn TORIEn Trigger Overrun Interrupt Request TORFn CFUIEn CFIFO Underflow Interrupt Request CFUFn RFOIEn RFIFO Overflow Interrupt Request RFOFn Combined Interrupt Request Figure 19-54. eQADC eDMA and Interrupt Requests MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-98 Freescale Semiconductor...
Page 854: Eqadc Synchronous Serial Interface (Ssi) Submodule
FCK clock from the master; data is exchanged between the master and the slave. Data in the master transmit shift register in the beginning of MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 855 FCK until it detects an asserted SDS on the immediately next FCK negative edge. See Figure 19-58 for three situations showing how the slave should behave according to when SDS is asserted. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-100 Freescale Semiconductor...
Page 856 Section 18.3.2.12, ‘eQADC SSI Control Register (EQADC_SSICR).’ Figure 19-57. Synchronous Serial Interface Protocol Timing 1.Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-101...
Page 857 Slave drives msb bit again due to detection of a negated SDS on the negative edge of FCK. Figure 19-58. Slave Driving the msb and Consecutive Bits in a Data Transmission MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-102 Freescale Semiconductor...
Page 858: Analog Submodule
The digital module also saves each successive sample and adds them according to the RSD algorithm at the end of the entire conversion cycle. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-103...
Page 859 For the 12-bit ADC, the input signal is sampled during the input phase, and after each of the 12 passes through the RSD stage. Thus, 13 total a and b values are collected. Upon MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-104...
Page 860: Initialization/Application Information
3.9 ms Command triggered by queue software strategy Repetitive every 625 us Airflow read every 30 angle-based queue degrees at 8000 RPM Slow repetitive every 100 ms Temperature sensors time-based queue MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-105...
Page 861 Configuration Command to ADC0—Ex: Write ADC_TSCR Command Address Configuration Command to ADC1—Ex: Write ADC1_CR Configuration Command to ADC2—Ex: Write to external device configuration register Figure 19-64. Example of a Command Queue Configuring the On-Chip ADCs/External Device MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-106 Freescale Semiconductor...
Page 862 0 0 1 0 0b0011 Conversion Command CMD7 0 0 1 0 0b0011 Conversion Command CMD8 0 0 1 0 0b0011 Configure peripheral device for next conversion sequence .... CFIFO Header ADC Command MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-107...
Page 863 CFIFO1 when it becomes the highest priority CFIFO trying to send commands to ADC1. The received results will be placed in RFIFO3 and then moved to result queue 1 by the eDMA. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-108 Freescale Semiconductor...
Page 864: Eqadc/Edma Controller Interface
When the last expected result is written to the receive queue, one of the following actions is recommended. Refer to Chapter 9, “Enhanced Direct Memory Access (eDMA)” for details about how this functionality is supported. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-109...
Page 865: Sending Immediate Command Setup Example
5. When the eQADC receives a conversion result for RFIFO5, it generates an interrupt request. RFIFO pop register 5 (EQADC_RFPR5) can be popped to read the result. Refer to Section 19.3.2.5, “eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn).” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-110 Freescale Semiconductor...
Page 866: Modifying Queues
0 command was sent to result queue 1. This happens because the system can be configured so that several command queues can have results sent to a single result queue. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-111...
Page 867: Adc Result Calibration
The eQADC provides these voltages via channel numbers 43 and 44. The raw, uncalibrated results for these input voltages are obtained by converting these channels with conversion commands that have the CAL bit negated. 1.VREF=V MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-112 Freescale Semiconductor...
Page 868 4096 and 12288. Therefore, using equations (5.5.d) and (5.5.e), the gain and offset calibration constants are: GCC=(12288-4096)/(11592-3798) = 1.05106492-> 1.05102539 = 0x4344 OCC=12288-1.05106492*11592 -2 = 102.06-> 102 = 0x0066 1. This calculation is rounded down due to binary approximation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-113...
Page 869: Eqadc Versus Qadc
QADC in terms of their functionality. This section targets users familiar with terminology in QADC. Figure 19-69 is an overview of a QADC. Figure 19-70 is an overview of the eQADC system. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-114 Freescale Semiconductor...
Page 870 FIFO instead of queue. These register names, register contents, and signals are functionally equivalent to the queue counterparts in the QADC. Table 19-59 lists how the eQADC register, register contents, and signals are related to QADC. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 19-115...
Page 871 Write to the eQADC SSI registers. Queue Execution Require software or external trigger Require software or external trigger events to start queue execution. events to start command transfers from a CFIFO. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-116 Freescale Semiconductor...
Page 872: Revision History
19.6 Revision History Table 19-61. Changes to MPC5553/5554 RM for Rev. 4.0 Release Description of Change • Removed section 9.2 “Detailed Signals” from this chapter because this information is contained in the Signals chapter of the Reference Manual. • Added this cross reference to the EQADC_NMSFR[NMF] bit: “Refer to the section “Null Message Format for External Device Operation”...
Page 873 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 19-118 Freescale Semiconductor...
Page 874: Introduction
Deserial Serial Peripheral Interface (DSPI) 20.1 Introduction This chapter describes the deserial serial peripheral interface (DSPI), which provides a synchronous serial bus for communication between the MPC5553/MPC5554 and an external peripheral device. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-1...
Page 875: Block Diagram
DSPI deserialized output connections to the SIU. The channels and register content are transmitted using an SPI-like protocol. There are four identical DSPI modules (DSPI_A, DSPI_B, DSPI_C, and DSPI_D) on the MPC5554, and three DSPI modules on the MPC5553 (DSPI_B, DSPI_C, and DSPI_D). The DSPI has three configurations: •...
Page 876: Features
— RX FIFO is not empty (RFDF) • Six interrupt conditions – End of queue reached (EOQF) – TX FIFO is not full (TFFF) – Transfer of current frame complete (TCF) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-3...
Page 877: Modes Of Operation
The module-specific modes are entered by host software writing to a register. The MCU-specific mode is controlled by signals external to the DSPI. The MCU-specific mode is a mode that the entire MPC5553/MPC5554 may enter, in parallel to the DSPI being in one of its module-specific modes. 20.1.4.1 Master Mode Master mode allows the DSPI to initiate and control serial communication.
Page 878: External Signal Description
Serial data out Output / Input Serial clock (output) Serial clock (input) In the SIU the user can select alternate pin functions for the MPC5553/MPC5554. 20.2.2 Signal Names and Descriptions 20.2.2.1 Peripheral Chip Select / Slave Select (PCS0/SS) In master mode, the PCS0 signal is a peripheral chip select output that selects the slave device to which the current transmission is intended.
Page 879: Memory Map/Register Definition
SCK is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode, SCK is an input from an external bus master. 20.3 Memory Map/Register Definition 20.3.1 Memory Map Table 20-2 shows the DSPI memory map. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-6 Freescale Semiconductor...
Page 880 — Base + 0x00B8 Base + 0x00BC DSPIx_DSICR DSPI DSI configuration register Base + 0x00C0 DSPIx_SDR DSPI DSI serialization data register Base + 0x00C4 DSPIx_ASDR DSPI DSI alternate serialization data register MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-7...
Page 881: Register Descriptions
1 DSPI is in master mode CONT_SCKE Continuous SCK enable. Enables the serial communication clock (SCK) to run continuously. Section 20.4.8, “Continuous Serial Communications Clock,” for details. 0 Continuous SCK disabled 1 Continuous SCK enabled MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-8 Freescale Semiconductor...
Page 882 The reset value of the MDIS bit is parameterized, with a default reset value of 0. 0 Enable DSPI clocks 1 Allow external logic to disable DSPI clocks MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-9...
Page 883 Halt. Provides a mechanism for software to start and stop DSPI transfers. See Section 20.4.2, “Start and Stop of DSPI Transfers,” for details on the operation of this bit. 0 Start transfers 1 Stop transfers MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-10 Freescale Semiconductor...
Page 884 16–31 — Reserved. 20.3.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) The MPC5553/MPC5554 DSPI modules each contain eight clock and transfer attribute registers (DSPIx_CTARn) which are used to define different transfer attribute configurations. Each DSPIx_CTAR controls: • Frame size •...
Page 885 CSSCK Reset Base + 0x000C (DSPIx_CTAR0); 0x0010 (DSPIx_CTAR1); 0x0014 (DSPIx_CTAR2); 0x0018 (DSPIx_CTAR3); Addr 0x001C (DSPIx_CTAR4); 0x0020 (DSPIx_CTAR5); 0x0024 (DSPIx_CTAR6); 0x0028 (DSPIx_CTAR7) Figure 20-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-12 Freescale Semiconductor...
Page 886 The table below lists the frame sizes. FMSZ Framesize FMSZ Framesize 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-13...
Page 887 SCK and the negation of PCS. This field is only used in master mode. The table below lists the prescaler values. The description for bitfeild ASC in Table 20-5 details how to compute the after SCK delay. After SCK Delay PASC Prescaler Value MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-14 Freescale Semiconductor...
Page 888 The baud rate prescaler values are listed in the table below. The description for Section 20.4.6.1, “Baud Rate Generator” details how to compute the baud rate. Baud Rate Prescaler Value MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-15...
Page 889 The PCS to SCK delay is a multiple of the system clock period and it is computed according to the following equation:   ----------- PCSSCK Prescaler value CSSCK Scaler value Note: See Section 20.4.6.2, “PCS to SCK Delay (tCSC),” for more details. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-16 Freescale Semiconductor...
Page 890 The after SCK delay is a multiple of the system clock period, and it is computed according to the following equation:   ----------- PASC Prescaler value ASC Scaler value Note: See Section 20.4.6.3, “After SCK Delay (tASC),” for more details. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-17...
Page 891 The delay after transfer is a multiple of the system clock period and it is computed according to the following equation:   ----------- PDT Prescaler value DT Scaler value Note: See Section 20.4.6.4, “Delay after Transfer (tDT),” for more details MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-18 Freescale Semiconductor...
Page 892 R TCF TXRXS EOQF TFUF TFFF RFOF RFDF W w1c Reset Reg Addr Base + 0x002C TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Reg Addr Base + 0x002C Figure 20-6. DSPI Status Register (DSPIx_SR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-19...
Page 893 The bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-20 Freescale Semiconductor...
Page 894 The DSPIx_RSER also selects the type of request to be generated. See the individual bit descriptions for information on the types of requests the bits support. The user must not write to the DSPIx_RSER while the DSPI is running. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-21...
Page 895 TFFF_RE bit in the DSPIx_RSER is set, this bit selects between generating an interrupt request or a DMA request. 0 Interrupt request will be generated 1 DMA request will be generated 8–11 — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-22 Freescale Semiconductor...
Page 896 R CONT CTAS EOQ CTCNT PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 Reset Reg Addr Base + 0x0034 TXDATA Reset Reg Addr Base + 0x0034 Figure 20-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-23...
Page 897 SPI frame. In SPI slave mode DSPIx_CTAR0 is used. The table below shows how the CTAS values map to the DSPIx_CTARs. There are eight DSPIx_CTARs in the MPC5553/MPC5554 DSPI implementation. Note: The field is only used in SPI master mode.
Page 898 — Reserved, should be cleared. 16–31 RXDATA Received data. The RXDATA field contains the SPI data from the RX FIFO entry [0:15] pointed to by the pop next data pointer (POPNXTPTR). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-25...
Page 899 The DSPIx_RXFRn registers provide visibility into the RX FIFO for debugging purposes. Each register is an entry in the RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO. The MPC5553/MPC5554 uses four registers to implement the RX FIFO, that is DSPIx_RXFR0–DSPIx_RXFR3 are used.
Page 900 TXSS TPOL TRRE Reset Reg Addr Base + 0x00BC R DCONT DSICTAS DPCS DPCS DPCS DPCS DPCS DPCS Reset Reg Addr Base + 0x00BC Figure 20-12. DSPI DSI Configuration Register (DSPIx_DSICR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-27...
Page 901 Section 20.4.7.5, “Continuous Selection Format,” for details. 0 Return peripheral chip select signals to their inactive state after transfer is complete 1 Keep peripheral chip select signals asserted after transfer is complete MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-28 Freescale Semiconductor...
Page 902 DSPIx_SDR on the rising edge of every system clock. The DSPIx_SDR is read-only. When the TXSS bit in the DSPIx_DSICR is negated, the data in the DSPIx_SDR is the source of the serialized data. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-29...
Page 903 DSPIx_ASDR take effect on the next frame boundary. Reset Reg Addr Base + 0x00C4 ASER_DATA Reset Reg Addr Base + 0x00C4 Figure 20-14. DSPI DSI Alternate Serialization Data Register (DSPIx_ASDR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-30 Freescale Semiconductor...
Page 904 Figure 20-15. DSPI DSI Transmit Comparison Register (DSPIx_COMPR) Table 20-15. DSPIx_COMPR Field Description Bits Name Description 0–15 — Reserved. 16–31 COMP_DATA Compare data. The COMP_DATA field holds the last serialized DSI data. [0:15] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-31...
Page 905: Functional Description
20.4 Functional Description The DSPI supports full-duplex, synchronous serial communications between the MPC5553/MPC5554 and peripheral devices. The DSPI can also be used to reduce the number of pins required for I/O by serializing and deserializing up to 16 parallel input/output signals from the eTPU and eMIOS. All communications are through an SPI-like protocol.
Page 906: Modes Of Operation
Master, slave, and module disable modes are module-specific modes while debug mode is a MPC5553/MPC5554-specific mode. The module-specific modes are determined by bits in the DSPIx_MCR. Debug mode is a mode that the entire MPC5553/MPC5554 can enter in parallel with the DSPI being configured in one of its module-specific modes. 20.4.1.1 Master Mode In master mode the DSPI can initiate communications with peripheral devices.
Page 907: Start And Stop Of Dspi Transfers
FRZ bit in the DSPIx_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the MPC5553/MPC5554 enters debug mode while the FRZ bit is negated, the DSPI behavior is unaffected and remains dictated by the module-specific mode and configuration of the DSPI. The DSPI enters debug mode when a debug request is asserted by an external controller.
Page 908: Serial Peripheral Interface (Spi) Configuration
In slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI and the SPI command field of the TX FIFO entry is ignored. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-35...
Page 909 TXNXTPTR contains the positive offset from DSPIx_TXFR0 in number of 32-bit registers. For example, TXNXTPTR equal to two means that the DSPIx_TXFR2 contains the SPI data and command for the next MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-36 Freescale Semiconductor...
Page 910 For example, POPNXTPTR equal to two means that the DSPIx_RXFR2 contains the received SPI data that will be returned when DSPIx_POPR is read. The POPNXTPTR field is incremented every time the DSPIx_POPR is read. POPNXTPTR rolls over every four frames on the MPC5553/MPC5554. 20.4.3.5.1 Filling the RX FIFO The RX FIFO is filled with the received SPI data from the shift register.
Page 911: Deserial Serial Interface (Dsi) Configuration
The DSI frames can be from 4 to 16 bits long. With multiple transfer operation (MTO), the DSPI supports serial chaining of DSPI modules within the MPC5553/MPC5554 to create DSI frames consisting of concatenated bits from multiple DSPIs. The DSPI also supports parallel chaining allowing several DSPIs and off-chip SPI devices to share the same serial communications clock (SCK) and peripheral chip select (PCS) signals.
Page 912 Figure 20-20 shows the DSI deserialization logic. for more information on the DSPIx_DDR, refer to Section 20.3.2.14, “DSPI DSI Deserialization Data Register (DSPIx_DDR).” MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-39...
Page 913 For triggered control, initiation of a transfer is controlled by the internal hardware trigger signal (ht). The TPOL bit in the DSPIx_DSICR selects the active edge of ht. For ht to have any affect, the TRRE bit in the DSPIx_DSICR must be set. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-40 Freescale Semiconductor...
Page 914 20.4.4.6 DSPI Connections to eTPU_A, eTPU_B, EMIOS and SIU The four (MPC5554) or three (MPC5553) DSPI blocks connect to the input and output channels of the eTPUs and the EMIOS. The MPC5554 connects to eTPU_A, eTPU_B, EMIOS, and SIU. The MPC5553 connects to eTPU_A, EMIOS, and SIU.
Page 915 Input 1 on IMUX for External IRQ[8] eTPU_A Output Channel 28 eTPU_A Input Channel 28, Input 1 on IMUX for External IRQ[9] eTPU_A Output Channel 27 eTPU_A Input Channel 27, Input 1 on IMUX for External IRQ[10] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-42 Freescale Semiconductor...
Page 916 Output Channel 5 Input 2 on IMUX for External IRQ[8] eTPU_A Output Channel 6 Input 2 on IMUX for External IRQ[9] eTPU_A Output Channel 7 Input 2 on IMUX for External IRQ[10] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-43...
Page 917 EMIOS Output Channel 12 Input 3 on IMUX for External IRQ[7] eTPU_A Output Channel 29 Input 3 on IMUX for External IRQ[8] eTPU_A Output Channel 28 Input 3 on IMUX for External IRQ[9] MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-44 Freescale Semiconductor...
Page 918 Input 3 on IMUX for External IRQ[13] 20.4.4.7 Multiple Transfer Operation (MTO) In DSI configuration the MTO feature allows for multiple DSPIs within the MPC5553/MPC5554 to be chained together in a parallel or serial configuration. The parallel chaining allows multiple DSPIs internal to the MPC5553/MPC5554 and multiple SPI devices external to the MPC5553/MPC5554 to share SCK and PCS signals thereby saving pins.
Page 919 20.4.4.7.1 Internal Muxing/SIU Support for Serial and Parallel Chaining To support MTO, each DSPI in MPC5553/MPC5554 has multiplexers on the SIN, SS, SCK, and ht inputs. The internal multiplexers are controlled by registers in the SIU block. Figure 20-25 (MPC5553) shows DSPI_B and four of the multiplexers in the IMUX subblock of the SIU.
Page 920 The source for the SIN input of a DSPI can be a pin or the SOUT of any of the other three (for the MPC5554) DSPIS or two (for the MPC5553) DSPIs. The source for the SS input of a DSPI can be a pin or the PCS0 signal from any of the other DSPIs.
Page 921 DSPI slaves each have a trigger output signal MTRIG that indicates to DSPI_A that a trigger condition has occurred in the DSPI slaves. In the MPC5553, it is DSPI_B that controls and initiates all transfers, but the DSPI slaves each have a trigger output signal MTRIG that indicates to DSPI_B that a trigger condition has occurred in the DSPI slaves.
Page 922 SOUT of the DSPI_B (slave) is connected to the SIN input of the DSPI_C and so on (slave). In the MPC5553, the SOUT of the DSPI_C (slave) is connected to the SIN input of the DSPI_D and so on (slave).
Page 923: Combined Serial Interface (Csi) Configuration
(MPC5553) master that a trigger condition has occurred. When an on-chip DSPI slave has a change in data to be serialized it can assert the MTRIG signal to the DSPI master which initiates the transfer. When a DSPI slave has its ht signal asserted it will assert its MTRIG signal thereby propagating trigger signals from other DSPI slaves to the DSPI master.
Page 924 When DSI frames are transferred the returned frames are deserialized and latched into the DSPIx_DDR. When SPI frames are transferred the returned frames are deserialized and written to the RX FIFO. Figure 20-33 shows the CSI deserialization logic. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-51...
Page 925: Dspi Baud Rate And Clock Delay Generation
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge. See Figure 20-36 for an illustration of the PCS to SCK delay. The PCSSCK and CSSCK fields in the MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-52 Freescale Semiconductor...
Page 926 Table 20-26 shows an example of the computed delay after transfer. Table 20-26. Delay after Transfer Computation Example Prescaler Scaler Delay after Transfer Value Value 0b01 0b1110 32768 100 MHz 0.98 ms MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-53...
Page 927: Transfer Formats
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes registers (DSPIx_CTARn) select the polarity and phase of the serial clock, SCK. The polarity bit selects MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-54...
Page 928 In this format, the master and slave sample their SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered SCK edges. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-55...
Page 929 SCK edge before the first data bit becomes available on the slave SOUT pin. In this format the master and slave devices change the data on their SOUT pins on the odd-numbered SCK edges and sample the data on their SIN pins on the even-numbered SCK edges. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-56 Freescale Semiconductor...
Page 930 SCK delay has elapsed the first SCK edge is generated. The slave samples the master SOUT signal on every odd numbered SCK edge. The slave also places new data on the slave SOUT on every odd numbered clock edge. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-57...
Page 931 SCK. No clock edge will be visible on the master SCK pin during the sampling of the last bit. The SCK to PCS delay must be greater or equal to half of the SCK period. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-58...
Page 932 The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR. Figure 20-40 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-59...
Page 933 In Figure 20-42, time ‘A’ shows the one clock interval. Time ‘B’ is user programmable from a MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-60 Freescale Semiconductor...
Page 934: Continuous Serial Communications Clock
Enabling continuous SCK disables the PCS to SCK delay and the After SCK delay. The delay after transfer is fixed at one SCK cycle. Figure 20-43 shows timing diagram for continuous SCK format with continuous selection disabled. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-61...
Page 935: Interrupts/Dma Requests
Current frame transfer is complete TX FIFO underflow has occurred TFUF RX FIFO is not empty RFDF RX FIFO overflow has occurred RFOF A FIFO overrun has occurred TFUF OR RFOF MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-62 Freescale Semiconductor...
Page 936 FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is initiated. The RFOF_RE bit in the DSPIx_RSER must be set for the interrupt request to be generated. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 937: Power Saving Features
DSPI that this is the last entry in the queue. 2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ flag (EOQF) in the DSPIx_SR is set. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-64 Freescale Semiconductor...
Page 938: Baud Rate Settings
PBR and the baud rate scaler BR in the DSPIx_CTARs. The values calculated assume a 100 MHz system frequency. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 20-65...
Page 939: Delay Settings
) and CS to SCK delay (t ) that can be generated based on the prescaler values and the scaler values set in the DSPIx_CTARs. The values calculated assume a 100 MHz system frequency. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-66 Freescale Semiconductor...
Page 940: Mpc5Xx Qspi Compatibility With The Dspi
For DT = 0 --> 0.425s delay: For this value, the closest value in the DSPI is 0.480s For DSCK = 0 --> 1/2 SCK period: For this value, the value for the DSPI is 20ns MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 941: Calculation Of Fifo Pointer Addresses
Push TX FIFO Register Entry A (First In) Entry B Entry C Entry D (Last In) Shift Register SOUT – – TX FIFO Counter – 1 Figure 20-45. TX FIFO Pointers and Counter MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-68 Freescale Semiconductor...
Page 942: Revision History
RX FIFO depth: Receive FIFO depth, implementation specific 20.6 Revision History Table 20-34. Changes added to MPC5553/5554 for Rev. 4.0 Release Description of Change Added the following bullet to the Features List: • “Supports all functional modes from QSPI subblock of QSMCM (MPC500 family)”...
Page 943 Table 20-35. Changes added to MPC5553/5554 for Rev. 5.0 Release Description of Change No change for Rev. 5 release. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 20-70 Freescale Semiconductor...
Page 944: Introduction
Chapter 21 Enhanced Serial Communication Interface (eSCI) 21.1 Introduction This section gives an overview of the MPC5553/MPC5554’s eSCI module, and presents a block diagram, its features and its modes of operation. 21.1.1 Block Diagram LIN Hardware LIN Error Flags LIN Error Detection...
Page 945: Overview
• 1/16 bit-time noise detection • Two-channel DMA interface 21.1.4 Modes of Operation The eSCI functions the same in normal, special, and emulation modes. It has a low-power module disable mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-2 Freescale Semiconductor...
Page 946: External Signal Description
The total address for each register is the sum of the base address for the eSCI module (ESCIx_base) and the address offset for each register. There are two eSCI modules on the MPC5553/MPC5554: the base is 0xFFFB_0000 for eSCIA and 0xFFFB_4000 for eSCIB. Table 21-2. Module Memory Map...
Page 947: Register Definition
BR is the content of the eSCI control register 1 (ESCIx_CR1), bits SBR0–SBR12. SBR0–SBR12 can contain a value from 1 to 8191. Also refer to the ESCIx_LCR[WU] bit description on page 21-13. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-4 Freescale Semiconductor...
Page 948 During reception, the received parity bit will be verified in the most significant bit position. The received parity bit will not be masked out. 0 Parity function disabled 1 Parity function enabled MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-5...
Page 949 0 No break characters 1 Transmit break characters NOTES After reset, the baud rate generator is disabled until the TE bit or the RE bit is set for the first time. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-6 Freescale Semiconductor...
Page 950 Activate RX DMA channel. If this bit is enabled and the eSCI has received data, it will raise a DMA RX request. TXDMA Activate TX DMA channel. Whenever the eSCI is able to transmit data, it will raise a DMA TX request. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-7...
Page 951 Table 21-21. PFIE Parity flag interrupt enable. Generates an interrupt, when parity flag is set. For a list of interrupt enables and flags, see Table 21-21. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-8 Freescale Semiconductor...
Page 952 The ESCIx_SR indicates the current status. The status flags can be polled, and some can also be used to generate interrupts. All bits in ESCIx_SR except for RAF are cleared by writing 1 to them. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 953 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wake-up bit (RWU) is set, an idle line condition does not set the IDLE flag. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-10 Freescale Semiconductor...
Page 954 LWAKE will also be set if ESCI receives a LIN 2.0 wake-up signal (in which the baud rate is lower than 32K baud). See the WU bit. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-11...
Page 955 WUD0 WUD1 LDBG DSF PRTY RXIE TXIE WUIE STIE PBIE CIE CKIE FCIE Reset Reg Addr Base + 0x000C OFIE Reset Reg Addr Base + 0x000C Figure 21-6. LIN Control Register (ESCIx_LCR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-12 Freescale Semiconductor...
Page 956 Table 21-21. CRC error interrupt enable. Generates an Interrupt when a CRC error on a received extended frame is detected. For a list of interrupt enables and flags, see Table 21-21. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-13...
Page 957 Additionally it is possible to flush the ESCIx_LTR by setting the ESCIx_LCR[LRES] bit. NOTE Not all values written to the ESCIx_LTR will generate valid LIN frames. The values are determined according to the LIN specification. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-14 Freescale Semiconductor...
Page 958 TX (RX) T[11:8] 4th Write (Table 21-11) W T[7:0] 5th Write (Table 21-12) W D[7:0] Reset Reg Addr eSCI x Base + 0x000010 Figure 21-8. LIN Transmit Register (ESCIx_LTR) Alternate Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-15...
Page 959 Transmit direction. Indicates a TX frame; that is, the eSCI will transmit data to a slave. Otherwise, an RX frame is assumed, and the eSCI only transmits the header. The data bytes are received from the slave. 0 RX frame 1 TX frame MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-16 Freescale Semiconductor...
Page 960 ESCIx_LRR can be ready only when ESCIx_SR[RXRDY] is set. NOTE Application software must ensure that ESCIx_LRR be read before new data or checksum bytes or CRCs are received from the LIN bus. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-17...
Page 961 21.3.3.8 LIN CRC Polynomial Register (ESCIx_LPR) ESCIx_LPRn can be written when there are no ongoing transmissions. R P15 Reset Reset Reg Addr Base + 0x0018 Figure 21-10. LIN CRC Polynomial Register (ESCIx_LPR) MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-18 Freescale Semiconductor...
Page 962: Functional Description
The eSCI uses the standard NRZ mark/space data format. Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in eSCI control register 1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 963: Baud Rate Generation
Integer division of the system clock may not give the exact target frequency. Table 21-17 lists some examples of achieving target baud rates with a system clock frequency of 128 MHz. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-20 Freescale Semiconductor...
Page 964: Transmitter
LOOP Control Load from Shift Preamble Break ESCIx_DR Enable (All 1s) (All 0s) LOOPS Parity Generation RSRC Transmitter Control TDRE TDRE Interrupt Request Interrupt TCIE Request Figure 21-13. eSCI Transmitter Block Diagram MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-21...
Page 965 ESCIx_DR, which occurs approximately half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-22 Freescale Semiconductor...
Page 966 0 where the stop bit should be. Receiving a break character has the following effects on eSCI registers: • Sets the framing error flag, FE. • Sets the receive data register full flag, RDRF. • Clears the eSCI data register (ESCIx_DR). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-23...
Page 967 If SBSTP is 0, the remainder of the byte will be transmitted normally. • If SBSTP is 1, the remaining bits in the byte after the error bit are transmitted as 1s (idle). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-24 Freescale Semiconductor...
Page 968: Receiver
The eSCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in eSCI control register 1 (ESCIx_CR1) determines the length of data characters. When receiving 9-bit data, bit R8 in the eSCI data register (ESCIx_DR) is the ninth bit (bit 8). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-25...
Page 969 To verify the start bit and to detect noise, the eSCI data recovery logic takes samples at RT3, RT5, and RT7. Table 21-18 summarizes the results of the start bit verification samples. Table 21-18. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-26 Freescale Semiconductor...
Page 970 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 21-20 summarizes the results of the stop bit samples. Table 21-20. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-27...
Page 971 RT8, RT9, and RT10. STOP Receiver RT Clock RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Figure 21-19. Slow Data MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-28 Freescale Semiconductor...
Page 972 The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 3.40%, as is shown below: 160 – 154  ------------------------- - 3.40% MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-29...
Page 973 All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow. Any receiver for which a MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-30 Freescale Semiconductor...
Page 974: Single-Wire Operation
During transmission, the transmitter must be enabled (TE=1); the receiver may be enabled or disabled. If the receiver is enabled (RE=1), transmissions will be echoed back on the receiver. Set or clear open drain output enable depending on desired operation. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-31...
Page 975: Loop Operation
The module disable bit (ESCIx_CR2[MDIS]) in the eSCI control register 2 can be used to turn off the eSCI. This will save power by stopping the eSCI core from being clocked.By default the eSCI is enabled (ESCIx_CR2[MDIS]=0). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-32 Freescale Semiconductor...
Page 976: Interrupt Operation
MCU acknowledges that request. The eSCI only has a single interrupt line (eSCI interrupt signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-33...
Page 977 The interrupt is set when the stop bit is read as a 0; which violates the SCI protocol. FE is cleared by writing it with 1. 21.4.9.2.8 NF Description The NF interrupt is set when the eSCI detects noise on the receiver input. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-34 Freescale Semiconductor...
Page 978 RX frame is received. The FRC flag is cleared by writing a 1 to the bit. NOTE The last byte of a TX frame being sent or an RX frame being received indicates that the checksum comparison has taken place. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-35...
Page 979: Using The Lin Hardware
ID field should be calculated automatically and whether double stop flags should be inserted after a bit error. The BRK13 bit in ESCIx_CR2 decides whether to generate 10 or 13 bit break characters. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-36 Freescale Semiconductor...
Page 980 In contrast to the standard software implementation where each byte transmission requires several interrupts, the DMA controller and eSCI handle communication, bit error and physical bus error checking, checksum, and CRC generation (checking on the RX side). MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-37...
Page 981 RX frame has been stored, the DMA controller can indicate completion to the CPU. NOTE It is also possible to setup a whole sequence of RX and TX frames, and generate a single event at the end of that sequence. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-38 Freescale Semiconductor...
Page 982 31 RT clock cycles, after a transmission has started, the LIN hardware will set the PBERR flag in the LIN status register. In addition a bit error may be generated. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor...
Page 983: Revision History
21.5 Revision History Table 21-22. Changes to MPC5553/5554 for Rev. 4.0 Release Description of Change Added this note to the steps for initiating a character transmission: • “A single 32-bit write to ESCI_CR1 may be used in place of steps b–d above.”...
Page 984 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 21-41...
Page 985 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 21-42 Freescale Semiconductor...
Page 986: Introduction
22.1 Introduction The MPC5554 MCU contains three controller area network (FlexCAN2) modules; the MPC5553 contains two FlexCAN2 modules. Each FlexCAN2 module is a communication controller implementing the CAN protocol according to CAN Specification version 2.0B and ISO Standard 11898. Each FlexCAN2 module contains a 1024-byte embedded memory, capable of storing 64 message buffers (MBs).
Page 987: Block Diagram
CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. Sixty-four message buffers (MBs) are stored in an embedded 1024-byte RAM dedicated to the FlexCAN2 module. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 22-2 Freescale Semiconductor...
Page 988: Features
22.1.4.1 Normal Mode In normal mode, the module operates receiving and/or transmitting message frames, errors are handled normally and all the CAN protocol functions are enabled. In the MPC5553/MPC5554, there is no distinction between user and supervisor modes. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5...
Page 989: External Signal Description
Table 22-1. FlexCAN2 Signals Signal Name Direction Description CNRXx CAN receive CNTXx CAN transmit In the MPC5554, indicates FlexCAN2 module A, B or C, whereas in the MPC5553, indicates FlexCAN2 module A and C. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 22-4 Freescale Semiconductor...
Page 990: Detailed Signal Description
The complete memory map for a FlexCAN2 module with its 64 MBs is shown in Table 22-2. Except for the base addresses, the three (MPC5554) or two (MPC5553) FlexCAN2 modules have identical memory maps. Each individual register is identified by its complete name and the corresponding mnemonic. Table 22-2. Module Memory Map...
Page 991: Message Buffer Structure
Base + 0x047F per MB The MPC5554 has FlexCAN2 modules A, B, and C, whereas the MPC5553 only has FlexCAN2 modules A and C. The FlexCAN2 module stores CAN messages for transmission and reception using a message buffer structure. Each individual MB is formed by 16 bytes mapped in memory as described in Table 22-3.
Page 992 MB does not participate in the matching process. 0010 MB participates in the matching process. When a 0100 EMPTY: MB is active and empty. frame is received successfully, the code is automatically updated to FULL. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 22-7...
Page 993 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. 1100 0100 Transmit remote frame unconditionally once. After transmission, the MB automatically becomes and RX MB with the same ID. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 22-8 Freescale Semiconductor...
Page 994: Register Descriptions
22.3.3 Register Descriptions The FlexCAN2 registers are described in this section. Note that there are three (or two in the MPC5553) separate, identical FlexCAN2 modules. Each register in the following sections is denoted with an ‘x’ that represents the specified module, A, B, or C.
Page 995 FlexCAN2 has exited these modes. 0 FlexCAN2 module is either in normal mode, listen-only mode or loop-back mode 1 FlexCAN2 module is either disabled or freeze mode — Reserved. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 22-10 Freescale Semiconductor...
Page 996 Maximum MBs in use MAXMB Note: MAXMB has to be programmed with a value smaller or equal to the number of available message buffers, otherwise FlexCAN2 will not transmit or receive frames. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 22-11...
Page 997 Phase segment 1. Defines the length of phase buffer segment 1 in the bit time. The valid [0:2] programmable values are 0–7.   Time Quanta  Phase Buffer Segment 1 PSEG1 + 1 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 22-12 Freescale Semiconductor...
Page 998 0 Timer sync feature disabled 1 Timer sync feature enabled Note: There is a possibility of 4–5 ticks count skew between the different FlexCAN2 stations that would operate in this mode. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 22-13...
Page 999 If desired, software can poll the register to discover when the data was actually written. MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 22-14...
Page 1000 RX 14 Mask 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5 Freescale Semiconductor 22-15...

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Freescale Semiconductor MPC5553 Reference Manual

Overview

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Chapter 19

Chapter 2

Chapter 3 Microarchitecture Summary

Chapter 17

5.2 External Signal Description

Chapter 7

8.2.1 Register Descriptions

Table of Contents

Chapter 10

Chapter 11

Chapter 12

Chapter 14

Chapter 15

Chapter 16

Chapter 13

Chapter 18

Chapter 5

Chapter 6

Appendix C Revision History

Chapter 24

Chapter 25 Modes of Operation

Chapter 23 Detailed Signal Description

Chapter 22

Chapter 21

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