Freescale Semiconductor MPC564 MPC564MVR56 Manuals

Manuals and User Guides for Freescale Semiconductor MPC564 MPC564MVR56. We have 1 Freescale Semiconductor MPC564 MPC564MVR56 manual available for free PDF download: Reference Manual

Freescale Semiconductor MPC564 MPC564MVR56 Reference Manual

Freescale Semiconductor MPC564 MPC564MVR56 Reference Manual (1420 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 12 MB

Table of Contents

Section 1

3
- Table of Contents
  3
- Paragraph Number
  4
Section 2

13
- About this Book Lxxvii
  77
- Audience
  77
- Organization
  77
- Conventions and Nomenclature
  80
- Suggested Reading
  80
- Notational Conventions
  81
- Acronyms and Abbreviations
  82
- References
  83
- Chapter 1
  
  85
- Chapter 10 Memory Controller
  
  399
  - Overview
    399
  - Memory Controller Architecture
    401
  - Associated Registers
    402
  - Port Size Configuration
    402
  - Address and Address Space Checking
    403
  - Burst Support
    403
  - Write-Protect Configuration
    403
  - Case 1: Normal Setup Time
    404
  - Reduced Data Setup Time
    404
  - Case 2: Short Setup Time
    405
  - Summary of Short Setup Time
    406
  - Chip-Select Timing
    408
  - Memory Devices Interface Example
    410
  - Peripheral Devices Interface Example
    411
  - Relaxed Timing Examples
    412
  - Extended Hold Time on Read Accesses
    416
  - Summary of GPCM Timing Options
    420
  - Dual Mapping of the Internal Flash EEPROM Array
    422
  - Write and Byte Enable Signals
    422
  - Dual Mapping of an External Flash Region
    424
  - Global (Boot) Chip-Select Operation
    425
  - Memory Controller External Master Support
    426
  - General Memory Controller Programming Notes
    429
  - Programming Model
    429
  - Memory Controller Base Registers (BR0-BR3)
    430
  - Memory Controller Status Registers (MSTAT)
    430
  - Memory Controller Option Registers (OR0-OR3)
    432
  - Dual-Mapping Base Register (DMBR)
    434
  - Dual-Mapping Option Register (DMOR)
    435
- Chapter 11 L-Bus to U-Bus Interface (L2U)
  
  437
  - Data Memory Protection Unit Features
    437
  - General Features
    437
  - L2U Block Diagram
    438
  - Modes of Operation
    439
  - Normal Mode
    439
  - Data Memory Protection
    440
  - Factory Test Mode
    440
  - Peripheral Mode
    440
  - Reset Operation
    440
  - Functional Description
    441
  - Associated Registers
    442
  - L-Bus Memory Access Violations
    443
  - Reservation Support
    443
  - L2U Reservation Support
    444
  - Reservation Protocol
    444
  - L-Bus Show Cycle Support
    445
  - Reserved Location (Bus) and Possible Actions
    445
  - L-Bus Write Show Cycle Flow
    446
  - Performance Impact
    446
  - Programming Show Cycles
    446
  - Show Cycle Protocol
    446
  - L-Bus Read Show Cycle Flow
    447
  - Show Cycle Support Guidelines
    447
  - L2U Programming Model
    448
  - L2U Module Configuration Register (L2U_MCR)
    449
  - Transaction Size
    449
  - U-Bus Access
    449
  - Region Base Address Registers (L2U_Rbax)
    450
  - Region Attribute Registers (L2U_Rax)
    451
  - Global Region Attribute Register (L2U_GRA)
    452
- Chapter 12 U-Bus to IMB3 Bus Interface (UIMB)
  
  455
  - Features
    455
  - Clock Module
    456
  - UIMB Block Diagram
    456
  - Interrupt Operation
    457

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