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Freescale Semiconductor MPC500 Series Reference Manual

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Freescale Semiconductor, Inc.
MPC509RM/D
Revised 15 July 1999
MPC500 Family
MPC509
Reference Manual
PowerPC  Microcontrollers
For More Information On This Product,
Go to: www.freescale.com

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Summary of Contents for Freescale Semiconductor MPC500 Series

  • Page 1 Freescale Semiconductor, Inc. MPC509RM/D Revised 15 July 1999 MPC500 Family MPC509 Reference Manual PowerPC  Microcontrollers For More Information On This Product, Go to: www.freescale.com...
  • Page 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...

  • Page 3: Table Of Contents

    Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Page Number Number PREFACE Section 1 INTRODUCTION 1.1 Features ..............1-1 1.2 Block Diagram .
  • Page 4 Freescale Semiconductor, Inc. Page Paragraph Number Number 2.5.4.3 Development Port Serial Clock Input (DSCK) ......2-17 2.5.4.4 Instruction Fetch Visibility Signals (VF[0:2]) .
  • Page 5 Freescale Semiconductor, Inc. Page Paragraph Number Number 3.6 RCPU Programming Model ........... . 3-7 3.7 PowerPC UISA Register Set .
  • Page 6 Freescale Semiconductor, Inc. Page Paragraph Number Number Section 4 INSTRUCTION CACHE 4.1 Instruction Cache Features ........... . 4-1 4.2 Instruction Cache Organization .
  • Page 7 Freescale Semiconductor, Inc. Page Paragraph Number Number 5.4.9 Accesses to 16-Bit Ports ..........5-27 5.4.10 Address Retry.
  • Page 8 Freescale Semiconductor, Inc. Page Paragraph Number Number 5.5.16.2 Asynchronous Interface with Latch Enable ......5-63 5.5.16.3 Synchronous Interface with Asynchronous OE .
  • Page 9 Freescale Semiconductor, Inc. Page Paragraph Number Number 5.7.3.2 PIT Time-Out Period Selection........5-91 5.7.3.3 PIT Enable Bits.
  • Page 10 Freescale Semiconductor, Inc. Page Paragraph Number Number 6.5.3 Interrupt Controller Registers ..........6-8 6.5.3.1 Pending Interrupt Request Register .
  • Page 11 Freescale Semiconductor, Inc. Page Paragraph Number Number 8.2.1.6 Treating Floating-Point Numbers ........8-19 8.2.2 Internal Breakpoints .
  • Page 12 Freescale Semiconductor, Inc. Page Paragraph Number Number 8.8 Development Support Registers ..........8-45 8.8.1 Register Protection .
  • Page 13 Freescale Semiconductor, Inc. LIST OF FIGURES Figure Title Page MPC509 Block Diagram ................. 1-2 MPC509 Pin Assignments ................1-3 MPC509 Signals ..................... 1-4 MPC509 Memory Map ..................1-5 Output-Only and Three-State I/O Buffers ............2-2 RCPU Block Diagram ..................3-2 Sequencer Data Path ..................
  • Page 14 Freescale Semiconductor, Inc. Figure Title Page 5-27 Phase-Locked Loop Block Diagram ............. 5-74 5-28 Crystal Oscillator ..................5-75 5-29 Charge Pump with Loop Filter Schematic ............ 5-75 5-30 Periodic Interrupt Timer Block Diagram ............5-90 5-31 External Reset Request Flow ............... 5-97 5-32 Internal Reset Request Flow ................
  • Page 15 Freescale Semiconductor, Inc. LIST OF TABLES Table Title Page 2-1 MPC509 Pin List ....................2-1 2-2 EBI Pin Definitions ....................2-2 2-3 MPC509 Power Connections................. 2-4 2-4 Pins with Internal Pull-Ups/Pulldowns ..............2-4 2-5 Signal Descriptions ....................2-5 2-6 Byte Enable Encodings..................2-11 2-7 Address Type Definitions..................
  • Page 16 Freescale Semiconductor, Inc. Table Title Page 5-5 EBI Signal Descriptions ..................5-13 5-6 Address Type Encodings..................5-15 5-7 Byte Enable Encodings..................5-15 5-8 Signals Driven at Start of Address Phase............5-20 5-9 Burst Access Address Wrapping ................. 5-25 5-10 SPECADDR Bit Settings................... 5-26 5-11 SPECMASK Bit Settings...................
  • Page 17 Freescale Semiconductor, Inc. Table Title Page 5-46 Reset Status Register Bit Settings..............5-96 5-47 Reset Behavior for Different Clock Modes............5-101 5-48 Pin Configuration During Reset ............... 5-101 5-49 Data Bus Reset Configuration Word..............5-103 5-50 SIU Port Registers Address Map..............5-106 5-51 Port M Pin Assignments ..................
  • Page 18 Freescale Semiconductor, Inc. Table Title Page 8-17 Checkstop State and Debug Mode..............8-38 8-18 Debug Mode Development Port Usage ............. 8-39 8-19 Non-Debug Mode Development Port Usage ............. 8-41 8-20 Prologue Events ....................8-42 8-21 Epilogue Events....................8-42 8-22 Peek Instruction Sequence................8-43 8-23 Poke Instruction Sequence................
  • Page 19 Freescale Semiconductor, Inc. PREFACE This manual defines the functionality of the MPC509 for use by software and hardware developers. The MPC509 is a member of the PowerPC-based Motorola MPC500 fam- ily of microcontrollers. Audience This manual is intended for system software and hardware developers and appli- cations programmers.
  • Page 20 Freescale Semiconductor, Inc. text. Specific bit fields or ranges are shown in brackets. In certain contexts, such as a signal encoding, this indicates a don’t care. For example, if a field is binary encoded 0bx001, the state of the first bit is a don’t care.

  • Page 21: Features

    Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION The MPC509 is a member of the PowerPC Family of reduced instruction set computer (RISC) microcontrollers (MCUs). The MPC509 implements the 32-bit portion of the PowerPC™ architecture, which provides 32-bit effective addresses, integer data types of eight, 16, and 32 bits, and floating-point data types of 32 and 64 bits.
  • Page 22 Freescale Semiconductor, Inc. — Chip-select logic to reduce or eliminate external decoding logic — External bus interface (EBI) that supports synchronous, asynchronous, burst transfer, and pipeline transfer memory types — System protection features including bus monitor and periodic interrupt timer —...

  • Page 23: Block Diagram

    Freescale Semiconductor, Inc. 1.2 Block Diagram INTERMODULE BUS 2 (IMB2) PERIPHERAL CONTROL UNIT (PCU) SYSTEM INTERFACE UNIT RISC MCU (SIU) EXTERNAL PROCESSOR INTERNAL LOAD/STORE BUS (L-BUS) (RCPU) 28-KBYTE SRAM INTERNAL INSTRUCTION BUS (I-BUS) 4-KBYTE I-CACHE DEVELOPMENT DEVELOPMENT PORT SUPPORT Figure 1-1 MPC509 Block Diagram Notice in that the IMB2 connects the processor to any on-chip peripherals.

  • Page 24: Pin Connections

    Freescale Semiconductor, Inc. 1.3 Pin Connections VSSE9 VSSE0 DATA15 ADDR5/CS5 DATA14 ADDR4/CS4 DATA13 ADDR3/CS3 DATA12 ADDR2/CS2 DATA11 ADDR1/CS1 DATA10 ADDR0/CS0 DATA9 CSBOOT DATA8 DATA7 DATA6 DATA5 DATA4 VSSE1 VSSE8 VDDE1 VDDE8 DATA3 DATA2 DATA1 DATA0 VSSIL VSSIR VDDIL MPC509L3C25 VDDIR...
  • Page 25 Freescale Semiconductor, Inc. PERIPHERAL CONTROL IRQ[0:1] PQ[0:6]/IRQ[0:6] UNIT (PCU) CSBOOT CS[0:7]/ADDR[0:7]/PA[0:7] CS[0:11] CS[8:11]/ADDR[8:11]/PB[0:3] CHIP SELECTS ADDR[12:15]/PB[4:7] ADDR[0:29] ADDR[16:29] DATA[0:31] BURST BURST/PI0 TEA/PI1 AACK/PI2 AACK TA/PI3 BE[0:1]/PI[4:5] BE[0:3] EXTERNAL BUS BE[2:3]/PI[6:7] INTERFACE AT0/PJ1 AT[0:1] AT1/PJ2 TS/PJ3 CT[0:3] CT[0:3]/PJ[4:7] CR/DS BI/PM3 BR/PM4...

  • Page 26: Memory Map

    Freescale Semiconductor, Inc. 1.4 Memory Map VECTOR TABLE LOCATION 0x0000 0000 POSSIBLE SRAM (IP BIT = 0) LOCATION (28 KBYTES) 0x0000 6FFF EXTERNAL 0x000F E000 POSSIBLE SRAM ONE OF FOUR POSSIBLE LOCATIONS LOCATION SELECTED FOR SRAM (28 KBYTES) 0x000F EFFF...

  • Page 27: Signal Descriptions

    Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS This section describes the MPC509 signals and pins. For a more detailed discussion of a particular signal, refer to the section of the manual that discusses the function involved. 2.1 Pin List Table 2-1 MPC509 Pin List...

  • Page 28: Pin Characteristics

    Freescale Semiconductor, Inc. Table 2-1 MPC509 Pin List (Continued) Primary Function(s) Port Function — DDSN SSSN — — VDDKAP1, VDDKAP2 — 2.2 Pin Characteristics Table 2-2 shows the characteristics of the MPC509 pins. Assume the model for output only and three-state I/O buffers shown in Figure 2-1.
  • Page 29 Freescale Semiconductor, Inc. Table 2-2 EBI Pin Definitions (Continued) Buffer Weak When Bus is When Bus Is Not Mnemonic During Reset Type Pull-Up Granted Granted 3-state BURST 3-state Output unless Float unless BE[0:3] 3-state configured as input configured as output...

  • Page 30: Power Connections

    Freescale Semiconductor, Inc. 2.3 Power Connections Table 2-3 shows the MPC509 power connections. Table 2-3 MPC509 Power Connections Description External periphery power Internal module power Clock synthesizer power DDSN SSSN Keep-alive power for the internal oscillator, time VDDKAP1 base, and decrementer...

  • Page 31: Signal Descriptions

    Freescale Semiconductor, Inc. Table 2-4 Pins with Internal Pull-Ups/Pulldowns Pull-up/Pull-down DSCK Pull-down DSDI 2.5 Signal Descriptions MPC509 signals are summarized in Table 2-5 and described in the following subsec- tions. Since pins often have more than one function, more than one description may apply to a pin.
  • Page 32 Freescale Semiconductor, Inc. Table 2-5 Signal Descriptions (Continued) Mnemonic Module Direction Description Chip CSBOOT Output Chip select of system boot memory. Selects Chip CS[0:11] Output Chip-select signals for external memory devices. Selects Cycle type signals. Indicate what type of bus cycle the bus master is...

  • Page 33: Bus Arbitration And Reservation Support Signals

    Freescale Semiconductor, Inc. Table 2-5 Signal Descriptions (Continued) Mnemonic Module Direction Description Reset output signal. Asserted by MCU during reset. When asserted, RESETOUT Output instructs all devices monitoring this signal to reset all parts within them- selves that can be reset by software.

  • Page 34: Bus Request (Br)

    Freescale Semiconductor, Inc. The cancel reservation (CR) signal is used to indicate that the processor should not perform any stwcx. cycle to external memory. This signal is sampled at the same time the MCU samples the arbitration pins for a qualified bus grant.

  • Page 35: Bus Busy (Bb)

    Freescale Semiconductor, Inc. pleted (assuming it has another transaction to run). The MCU does not accept a BG in the cycles between the as- sertion of any TS and AACK. Negation — May occur at any time to indicate the MCU cannot use the bus.

  • Page 36: Address Phase Signals

    Freescale Semiconductor, Inc. 2.5.2 Address Phase Signals The address phase is the period of time from the assertion of transfer start (TS) until the address phase is terminated by one of the following signals: address acknowledge (AACK), address retry (ARETRY), or transfer error acknowledge (TEA). TS is valid for one clock cycle at the start of the address phase.

  • Page 37: Byte Enables (Be[0:3])

    Freescale Semiconductor, Inc. Timing Comments Assertion/Negation — BURST is an address attribute; it is updated at the start of the address phase and maintained until the start of the next address phase. High impedance — Coincides with negation of BB, provid- ed no qualified bus grant exists.

  • Page 38: Address Acknowledge (Aack)

    Freescale Semiconductor, Inc. 2.5.2.6 Address Acknowledge (AACK) Input only Module: EBI State Meaning Asserted — Indicates that the address phase of a transac- tion is complete. If the external access is to a chip-select region for which the chip select is programmed to return AACK and TA, then the external bus interface uses the logical OR of the external AACK pin and the AACK signal returned by the chip select.

  • Page 39: Address Retry (Aretry)

    Freescale Semiconductor, Inc. Timing Comments Assertion/Negation — Sampled when AACK is asserted. A burst transfer can only be burst-inhibited before the first TA assertion. Simple, asynchronous memory devices should keep AACK negated to keep the address valid. They can assert BI at the same time as or before AACK and at the same time as the first TA assertion.

  • Page 40: Cycle Types (Ct[0:3])

    Freescale Semiconductor, Inc. Table 2-7. Table 2-7 Address Type Definitions AT[0:1] Address Space Definition 0b00 User, data 0b01 User, instruction 0b10 Supervisor, data 0b11 Supervisor, instruction Timing Comments Assertion/Negation — The AT[0:1] signals are address at- tributes; they are updated at the start of the address phase and maintained until the start of the next address phase.

  • Page 41: Burst Data In Progress (Bdip)

    Freescale Semiconductor, Inc. read or write. 16-bit devices must reside on DATA[0:15]. 32-bit devices reside on DATA[0:31]. Timing Comments Assertion/negation — On write cycles, the SIU drives data one clock after driving TS. The data is available until the slave asserts TA.

  • Page 42: Transfer Error Acknowledge (Tea)

    Freescale Semiconductor, Inc. Negated — (While BB is asserted) indicates that, until TA is asserted, the MCU must continue to drive the data for the current write or must wait to sample the data for reads. Timing Comments Assertion — Must not occur before AACK is asserted for the current transaction.

  • Page 43: Development Support Signals

    Freescale Semiconductor, Inc. cycle). DS can be used to latch data for a bus analyzer. It can also aid in following the external bus pipeline. Timing Comments Assertion — Occurs after the chip-select unit asserts the in- ternal TA signal or the bus monitor timer asserts the inter- nal TEA signal.

  • Page 44: Instruction Fetch Visibility Signals (Vf[0:2])

    Freescale Semiconductor, Inc. SETOUT, debug mode is enabled when the reset state is exited. For normal operation, this pin should be pulled to ground through a resistor. Refer to 5.8.3 Configuration During Reset for more information. Timing Comments Refer to the...

  • Page 45: Chip-Select Signals

    Freescale Semiconductor, Inc. information on these signals. 2.5.5 Chip-Select Signals 2.5.5.1 Chip Select for System Boot Memory (CSBOOT) Input only Module: Chip selects State Meaning Asserted — Indicates the boot memory device is being se- lected. In systems that have no external boot device, this pin can be configured as a write enable or output enable of an external memory device.

  • Page 46: Engineering Clock Output (Ecrout)

    Freescale Semiconductor, Inc. to the rising edge of this clock. 2.5.6.2 Engineering Clock Output (ECROUT) Output only Module: Clocks State Meaning Asserted/Negated — Provides a buffered clock reference output with a frequency equal to the crystal oscillator fre- quency, taken from the PLL feedback signal.

  • Page 47: Reset Signals

    Freescale Semiconductor, Inc. serted when bit 0 of the decrementer register changes from zero to one and can also be asserted by software. See the RCPU Reference Manual (RCPURM/AD) for details on decrementer exceptions. Negated — (By software) indicates the event causing as- sertion of PDWU is not or is no longer occurring.

  • Page 48: Ports I, J, K, And L

    Freescale Semiconductor, Inc. (PORTA/PORTB) and pin assignment register (PAPAR/ PBPAR). Timing Comments Assertion/Negation — Accesses to these ports require three clock cycles, the same as for external accesses to port replacement logic if a port replacement unit (PRU) is used.

  • Page 49: Port Q (Pq[0:6])

    Freescale Semiconductor, Inc. ed level is being requested. 2.5.9.2 Port Q (PQ[0:6]) Input/Output Module: PCU State Meaning Asserted/Negated — Indicates the logic level of the data being transmitted. Timing Comments Assertion/Negation — Accesses to port Q require two clock cycles.

  • Page 50: Test Reset (Trst)

    Freescale Semiconductor, Inc. 2.5.10.5 Test Reset (TRST) Input only Module: JTAG State Meaning Asserted — Signals TAP controller to reset itself. Timing Comments Asynchronous. MPC509 SIGNAL DESCRIPTIONS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 2-24 For More Information On This Product,...

  • Page 51: Central Processing Unit

    Freescale Semiconductor, Inc. SECTION 3 CENTRAL PROCESSING UNIT The PowerPC-based RISC processor (RCPU) used in the MPC509 integrates four execution units: an integer unit (IU), a load/store unit (LSU), a branch processing unit (BPU), and a floating-point unit (FPU). The use of simple instructions with rapid exe- cution times yields high efficiency and throughput for MPC509-based systems.

  • Page 52: Instruction Sequencer

    Freescale Semiconductor, Inc. L-DATA L-ADDR I-DATA I-ADDR WRITE BACK BUS 2 SLOTS/CLOCK Figure 3-1 RCPU Block Diagram 3.3 Instruction Sequencer The instruction sequencer (see Figure 3-2) provides centralized control over data flow between execution units and register files. The sequencer implements the basic...
  • Page 53 Freescale Semiconductor, Inc. instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history so it can back the machine up in the event of an exception. The sequencer fetches the instructions from the instruction cache into the instruction pre-fetch queue.

  • Page 54: Independent Execution Units

    Freescale Semiconductor, Inc. 3.4 Independent Execution Units The PowerPC architecture supports independent floating-point, integer, load-store, and branch processing execution units, making it possible to implement advanced fea- tures such as look-ahead operations. For example, since branch instructions do not depend on GPRs or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches.

  • Page 55: Branch Processing Unit (Bpu)

    Freescale Semiconductor, Inc. Table 3-1 RCPU Execution Units Unit Description Branch processing Includes the implementation of all branch instructions. unit (BPU) Includes implementation of all load and store instructions, whether defined as part Load/store unit (LSU) of the integer processor or the floating-point processor.

  • Page 56: Load/Store Unit (Lsu)

    Freescale Semiconductor, Inc. • The ALU-BFU unit includes the implementation of all integer logic, add and sub- tract, and bit field instructions. The IU also includes the integer exception register (XER) and the general-purpose register file. IMUL-IDIV and ALU-BFU are implemented as separate execution units. The ALU-BFU unit can execute one instruction per clock cycle.

  • Page 57: Levels Of The Powerpc Architecture

    Freescale Semiconductor, Inc. to deliver results in hardware that are adequate for most applications, if not in strict conformance with IEEE standards. In this mode, denormalized numbers, NaNs, and IEEE invalid operations are treated as legitimate, returning default results rather than causing floating-point assist exceptions.
  • Page 58 Freescale Semiconductor, Inc. Registers such as the general-purpose registers (GPRs) and float- ing-point registers (FPRs) are accessed through operands that are part of the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as move...
  • Page 59 Freescale Semiconductor, Inc. SUPERVISOR MODEL OEA USER MODEL UISA Machine State Register FPR0 FPR1 Supervisor-Level SPRs FPR31 SPR18 DAE/Source Instruction Service Register (DSISR) SPR19 Data Address Register (DAR) Condition SPR22 Decrementer Register (DEC) GPR0 Register SPR26 Save and Restore Register 0 (SRR0)

  • Page 60: Powerpc Uisa Register Set

    Freescale Semiconductor, Inc. Where not otherwise noted, reserved fields in registers are ignored when written to and return zero when read. An exception to this rule is XER[16:23]. These bits are set to the value written to them and return that value when read.

  • Page 61: Floating-Point Status And Control Register (Fpscr)

    Freescale Semiconductor, Inc. FPRs — Floating-Point Registers FPR0 FPR1 ..FPR31 RESET: UNCHANGED 3.7.3 Floating-Point Status and Control Register (FPSCR) The FPSCR controls the handling of floating-point exceptions and records status resulting from the floating-point operations. FPSCR[0:23] are status bits, while FPSCR[24:31] are control bits.
  • Page 62 Freescale Semiconductor, Inc. A listing of FPSCR bit settings is shown in Table 3-3. Table 3-3 FPSCR Bit Settings Bit(s) Name Description Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if that instruction causes any of the floating-point exception bits in the FPSCR to change from zero to one.

  • Page 63: Condition Register (Cr)

    Freescale Semiconductor, Inc. Table 3-3 FPSCR Bit Settings (Continued) Bit(s) Name Description Floating-point invalid operation exception for software request. This bit can be altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow soft-...

  • Page 64: Condition Register Cr0 Field Definition

    Freescale Semiconductor, Inc. CR — Condition Register 11 12 15 16 19 20 23 24 27 28 RESET: UNCHANGED The CR fields can be set in the following ways: • Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from a GPR.

  • Page 65: Condition Register Cr1 Field Definition

    Freescale Semiconductor, Inc. 3.7.4.2 Condition Register CR1 Field Definition In all floating-point instructions when the CR is set to reflect the result of the operation (that is, when Rc = 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3] to indicate the floating-point exception status.

  • Page 66: Integer Exception Register (Xer)

    Freescale Semiconductor, Inc. 3.7.5 Integer Exception Register (XER) The integer exception register (XER) is a user-level, 32-bit register. XER — Integer Exception Register SPR 1 24 25 26 27 28 29 30 31 BYTES RESET: UNCHANGED The bit definitions for XER, shown in...

  • Page 67: Count Register (Ctr)

    Freescale Semiconductor, Inc. Both conditional and unconditional branch instructions include the option of placing the effective address of the instruction following the branch instruction in the LR. This is done regardless of whether the branch is taken. LR — Link Register...

  • Page 68: Powerpc Oea Register Set

    Freescale Semiconductor, Inc. Table 3-9 Time Base Field Definitions Bits Name Description 0:31 Time base (upper) — The high-order 32 bits of the time base 32:63 Time base (lower) — The low-order 32 bits of the time base In 32-bit PowerPC implementations such as the RCPU, it is not possible to read the entire 64-bit time base in a single instruction.
  • Page 69 Freescale Semiconductor, Inc. Table 3-10 Machine State Register Bit Settings Bit(s) Name Description 0:14 — Reserved Exception little endian mode. When an exception occurs, this bit is copied into MSR[LE] to select the endian mode for the context established by the exception.

  • Page 70: Dae/Source Instruction Service Register (Dsisr)

    Freescale Semiconductor, Inc. Table 3-11 Floating-Point Exception Mode Bits FE[0:1] Mode Ignore exceptions mode — Floating-point exceptions do not cause the floating-point assist error handler to be invoked. Floating-point precise mode — The system floating-point assist error 01, 10, 11 handler is invoked precisely at the instruction that caused the enabled exception.

  • Page 71: Decrementer Register (Dec)

    Freescale Semiconductor, Inc. Table 3-12 Time Base Field Definitions Bits Name Description 0:31 Time base (upper) — The high-order 32 bits of the time base 32:63 Time base (lower) — The low-order 32 bits of the time base The TB can be written at the supervisor privilege level only. The mttbl and mttbu sim- plified mnemonics write the lower and upper halves of the TB, respectively.

  • Page 72: Machine Status Save/Restore Register 0 (Srr0)

    Freescale Semiconductor, Inc. DEC — Decrementer Register SPR 22 Decrementing Counter RESET: UNCHANGED 3.9.6 Machine Status Save/Restore Register 0 (SRR0) The machine status save/restore register 0 (SRR0) is a 32-bit register that identifies where instruction execution should resume when an rfi instruction is executed follow- ing an exception.

  • Page 73: Processor Version Register (Pvr)

    Freescale Semiconductor, Inc. SPRG0–SPRG3 — General Special-Purpose Registers 0–3 SPR 272 – SPR 275 SPRG0 SPRG1 SPRG2 SPRG3 RESET: UNCHANGED Uses for SPRG0–SPRG3 are shown in Table 3-13. Table 3-13 Uses of SPRG0–SPRG3 Register Description Software may load a unique physical address in this register to identify an area of memory reserved for SPRG0 use by the exception handler.

  • Page 74: Eie, Eid, And Nri Special-Purpose Registers

    Freescale Semiconductor, Inc. 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers The RCPU includes three implementation-specific SPRs to facilitate the software manipulation of the MSR[RI] and MSR[EE] bits. Issuing the mtspr instruction with one of these registers as an operand causes the RI and EE bits to be set or cleared as...

  • Page 75: Floating-Point Exception Cause Register (Fpecr)

    Freescale Semiconductor, Inc. Table 3-17 Development Support Registers SPR Number Mnemonic Name (Decimal) CMPA Comparator A value register CMPB Comparator B value register CMPC Comparator C value register CMPD Comparator D value register Exception cause register Debug enable register COUNTA...
  • Page 76 Freescale Semiconductor, Inc. — Floating-point arithmetic instructions — Floating-point multiply/add instructions — Floating-point rounding and conversion instructions — Floating-point compare instructions — Floating-point status and control instructions • Load/store instructions. These include integer and floating-point load and store instructions. — Integer load and store instructions —...

  • Page 77: Instruction Set Summary

    Freescale Semiconductor, Inc. an instruction or by an asynchronous event. Either kind of exception may cause one of several components of the system software to be invoked. 3.10.1 Instruction Set Summary Table 3-18 provides a summary of RCPU instructions. Refer to the...
  • Page 78 Freescale Semiconductor, Inc. Table 3-18 Instruction Set Summary (Continued) Mnemonic Operand Syntax Name extsb (extsb.) rA,rS Extend sign byte extsh (extsh.) rA,rS Extend sign half-word fabs (fabs.) frD,frB Floating absolute value fadd (fadd.) frD,frA,frB Floating add (double-precision) fadds (fadds.) frD,frA,frB...
  • Page 79 Freescale Semiconductor, Inc. Table 3-18 Instruction Set Summary (Continued) Mnemonic Operand Syntax Name lfsux frD,rA,rB Load floating-point single with update indexed lfsx frD,rA,rB Load floating-point single indexed rD,d(rA) Load half-word algebraic lhau rD,d(rA) Load half-word algebraic with update lhaux rD,rA,rB...
  • Page 80 Freescale Semiconductor, Inc. Table 3-18 Instruction Set Summary (Continued) Mnemonic Operand Syntax Name or (or.) rA,rS,rB (orc.) rA,rS,rB OR with complement rA,rS,UIMM OR immediate oris rA,rS,UIMM OR immediate shifted — Return from interrupt rlwimi (rlwimi.) rA,rS,SH,MB,ME Rotate left word immediate then mask insert rlwinm (rlwinm.)

  • Page 81: Recommended Simplified Mnemonics

    Freescale Semiconductor, Inc. Table 3-18 Instruction Set Summary (Continued) Mnemonic Operand Syntax Name subfe (subfe. subfeo subfeo.) rD,rA,rB Subtract from extended subfic rD,rA,SIMM Subtract from immediate carrying subfme (subfme. subfmeo subfmeo.) rD,rA Subtract from minus one extended subfze (subfze. subfzeo subfzeo.)

  • Page 82: Exception Model

    Freescale Semiconductor, Inc. 3.11 Exception Model The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execu- tion of instructions. When exceptions occur, information about the state of the processor is saved to certain registers, and the processor begins execution at an address (exception vector) predetermined for each exception.

  • Page 83: Precise Exceptions

    Freescale Semiconductor, Inc. (and, in some cases, the DAR and DSISR) may not be recoverable; the processor may be in the process of saving or restoring these registers. To determine whether the machine state is recoverable, the user can read the RI (recoverable exception) bit in SRR1.

  • Page 84: Instruction Timing

    Freescale Semiconductor, Inc. Table 3-20 Exception Vector Offset Table Vector Offset Exception Type (Hexadecimal) 00000 Reserved 00100 System reset 00200 Machine check 00300 Data access 00400 Instruction access 00500 External interrupt 00600 Alignment 00700 Program 00800 Floating-point unavailable 00900 Decrementer...
  • Page 85 Freescale Semiconductor, Inc. 4. In the retirement stage, the history buffer retires instructions in architectural order. An instruction retires from the machine if it completes execution with no exceptions and if all instructions preceding it in the instruction stream have finished execution with no exceptions. As many as six instructions can be retired in one clock.
  • Page 86 Freescale Semiconductor, Inc. Table 3-21 Instruction Latency and Blockage Instruction Type Precision Latency Blockage Floating-point Double multiply-add Single Floating-point Double add or subtract Single Double Floating-point multiply Single Double Floating-point divide Single Integer multiply — 1 or 2 Integer divide —...

  • Page 87: Instruction Cache

    Freescale Semiconductor, Inc. SECTION 4 INSTRUCTION CACHE The MPC509 instruction cache (I-cache) is a 4-Kbyte, two-way set associative cache. The cache is organized into 128 sets, with two lines per set and four words per line. Cache lines are aligned on four-word boundaries in memory.

  • Page 88: Instruction Cache Organization

    Freescale Semiconductor, Inc. 4.2 Instruction Cache Organization Figure 4-1 illustrates the I-cache organization. INSTRUCTION POINTER WORD SELECT WAY0 WAY1 SET0 TAG0 W0 W1 W2 W3 TAG0 W0 W1 W2 W3 SET1 TAG1 W0 W1 W2 W3 TAG1 W0 W1 W2 W3...

  • Page 89: Instruction Cache Programming Model

    Freescale Semiconductor, Inc. ADDR[21:27] 4-KBYTE DECODER CACHE ARRAY ADDR[28:29] 4-WORD LINE BUFFER WORD STREAM 4-WORD SELECT BURST BUFFER DATA INSTRUCTION BYPASS I-BUS TO CPU DATA Figure 4-2 Instruction Cache Data Path 4.3 Instruction Cache Programming Model Three special purpose registers (SPRs) control the I-cache:...
  • Page 90 Freescale Semiconductor, Inc. RESERVED RESET: Table 4-2 ICCST Bit Settings Bits Mnemonic Description I-cache enable status bit. This bit is a read-only bit. Any attempt to write it is ignored. 0 = I-cache is disabled 1 = I-cache is enabled —...

  • Page 91: Cache Operation

    Freescale Semiconductor, Inc. Table 4-3 I-Cache Address Register (ICADR) Bits Mnemonic Description The address to be used in the command programmed in the control and status 0:31 register ICSDAT — I-Cache Data Register SPR 562 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

  • Page 92: Cache Commands

    Freescale Semiconductor, Inc. lines. If neither of the two candidate lines in the selected set are invalid, then the least recently used line is selected for replacement. Locked lines are never replaced. The transfer begins with the word requested by the instruction unit (critical word first), followed by any remaining words of the line, then by any remaining words at the begin- ning of the line (wrap around).
  • Page 93 Freescale Semiconductor, Inc. the external bus and the CPU does not snoop this instruction if broadcast by other masters. This command is not privileged and has no error cases that the user needs to check. 4.5.2 Invalidate All To invalidate the whole cache, set the invalidate all command in the ICCST. This command has no error cases that the user needs to check.
  • Page 94 Freescale Semiconductor, Inc. 4.5.6 Cache Enable To enable the cache, set the cache enable command in the ICCST. This operation can be performed only at the supervisor privilege level. The cache enable command has no error cases that the user needs to check.
  • Page 95 Freescale Semiconductor, Inc. Table 4-6 ICDAT Layout During a Tag Read 0:20 25:31 0 = not valid 0 = not locked Tag value Reserved LRU bit Reserved 1 = valid 1 = locked MPC509 INSTRUCTION CACHE MOTOROLA REFERENCE MANUAL Revised 15 July 1999 For More Information On This Product, Go to: www.freescale.com...
  • Page 96 Freescale Semiconductor, Inc. MPC509 INSTRUCTION CACHE MOTOROLA REFERENCE MANUAL Revised 15 July 1999 4-10 For More Information On This Product, Go to: www.freescale.com...

  • Page 97: System Interface Unit

    Freescale Semiconductor, Inc. SECTION 5 SYSTEM INTERFACE UNIT The system interface unit (SIU) consists of modules that control the buses of the chip, provide the clocks, and provide miscellaneous functions for the system, such as chip selects, test control, reset control, and I/O ports.

  • Page 98: Siu Address Map

    Freescale Semiconductor, Inc. CHIP SELECTS L-DATA L-BUS L-BUS L-ADDR E-BUS E-BUS ADDRESS INTERFACE CROSS-BUS ARB & CNTL ADDRESS DECODE DATA I-BUS I-ADDR I-BUS SUBBUS DEBUG INTERFACE I-DATA RESET CLOCKS MONITOR POWER-PC TIMER & PORTS DECREMENTER Figure 5-1 SIU Block Diagram 5.2 SIU Address Map...
  • Page 99 Freescale Semiconductor, Inc. Table 5-1 SIU Address Map Access Address Register 0x8007 FC00 SIU module configuration register (SIUMCR) Test 0x8007 FC04 SIU test register 1 (SIUTEST1) 0x8007 FC08 – — Reserved 0x8007 FC1C 0x8007 FC20 Memory mapping (MEMMAP) 0x8007 FC24...

  • Page 100: Siu Module Configuration

    Freescale Semiconductor, Inc. Table 5-1 SIU Address Map (Continued) Access Address Register 0x8007 FD9C CS10 option register (CSOR10) 0x8007 FDA0 Reserved 0x8007 FDA4 CS9 option register (CSOR9) 0x8007 FDA8 Reserved 0x8007 FDAC CS8 option register (CSOR8) 0x8007 FDB0 Reserved 0x8007 FDB4...
  • Page 101 Freescale Semiconductor, Inc. SIUMCR — SIU Module Configuration Register 0x8007 FC00 SIU- RESERVED RESERVED LSHOW RESET: PARTNUM MASKNUM RESET: Read-Only Fixed Value Read-Only Fixed Value Table 5-2 SIUMCR Bit Settings Bit(s) Name Description SIU freeze 0 = Decrementer and time base registers and the periodic interrupt timer continue to run while internal freeze signal is asserted (reset value).
  • Page 102 Freescale Semiconductor, Inc. Table 5-2 SIUMCR Bit Settings (Continued) Bit(s) Name Description Debug register lock. This bit can be written only when internal freeze signal is asserted. DLK allows development software to configure show cycles and prevent normal software from sub- sequently changing this configuration.
  • Page 103 Freescale Semiconductor, Inc. Table 5-3 MEMMAP Bit Settings Bit(s) Name Description L-bus memory enable 0 = L-bus memory disabled 1 = L-bus memory enabled Reset state depends on the value of the data bus configuration word. — Reserved Base address of the L-bus memory block...
  • Page 104 Freescale Semiconductor, Inc. Capability is provided to allow masters on one bus to access slaves on the opposite bus. L-bus masters must be able to access peripherals on the I-bus to program their control registers or to program flash memory arrays. This is because the CPU instruc- tion fetch unit can only run read cycles.

  • Page 105: Memory Mapping Register

    Freescale Semiconductor, Inc. 5.3.3.1 Memory Block Mapping The SRAM array can be mapped to one of four locations. These locations are at the top and bottom of the 4-Gbyte address range. They include the two alternatives for the PowerPC vector map (0x0000 0100 and 0xFFFF 0100). The LMEMBASE field in the memory mapping register (MEMMAP) determine the locations of the SRAM array.

  • Page 106: Accesses To Unimplemented Internal Memory Locations

    Freescale Semiconductor, Inc. 5.3.3.2 Accesses to Unimplemented Internal Memory Locations If an access is made to a location within the 2 -sized memory block that is not imple- mented in any memory module on the chip, then the CPU takes a machine check exception.

  • Page 107: Internal Cross-Bus Accesses

    Freescale Semiconductor, Inc. 5.3.4 Internal Cross-Bus Accesses Each internal bus (I-bus and L-bus) has a master/slave interface in the SIU. The slave interface is used for accesses by the internal master (RCPU) to the external bus, to memory on the opposite bus (e.g., L-bus to I-bus access), or to SIU registers.

  • Page 108: Effects Of Freeze On The Programmable Interrupt Timer (Pit)

    Freescale Semiconductor, Inc. In addition, if the processor is executing normally and runs a bus cycle that is not ter- minated, a non-maskable breakpoint always gains control of the processor by terminating the bus cycle with the bus monitor so the processor can enter debug mode.

  • Page 109: External Bus Signals

    Freescale Semiconductor, Inc. 5.4.2 External Bus Signals Table 5-5 summarizes the E-bus signals. The following abbreviations are used in this table: M = Bus master S = Slave device A = Central bus arbiter T = Bus watchdog timer X = Any device on the system...
  • Page 110 Freescale Semiconductor, Inc. Table 5-5 EBI Signal Descriptions (Continued) Mnemonic Direction Description Address retry. This is an address phase termination signal. It is de- signed to resolve deadlock cases on hierarchical bus structures or for S, A → M ARETRY error-correcting memories.

  • Page 111: Basic Bus Cycle

    Freescale Semiconductor, Inc. Table 5-5 EBI Signal Descriptions (Continued) Mnemonic Direction Description This input-only signal resets the entire MCU. While RESET is assert- Source → M RESET ed, the MCU asserts the RESETOUT signal. Reset output. This output-only signal indicates that the MCU is in reset.
  • Page 112 Freescale Semiconductor, Inc. MASTER SLAVE RECEIVE ADDRESS IS BUS GRANTED? CAN SLAVE PIPELINE? REQUEST BUS BUS GRANT RECEIVED ASSERT ADDRESS ACKNOWLEDGE BUS BEING RETURN DATA DRIVEN BY ANOTHER MASTER? ASSERT TRANSFER ACKNOWLEDGE ASSERT BUS BUSY ASSERT TRANSFER ADDRESS START ACKNOWLEDGE...

  • Page 113: Write Cycle Flow

    Freescale Semiconductor, Inc. CLKOUT REQUEST BUS & RECEIVE GRANT BEGIN DRIVING ADDRESS AND ASSERT TS ADDR & PIPELINED ADDRESS ATTRIBUTES AACK RECEIVE AACK (COULD STOP DRIVING ADDRESS HERE) WAIT ONE CLOCK DATA RETURN FOR THE READ DATA Figure 5-5 Example of a Read Cycle 5.4.3.2 Write Cycle Flow...

  • Page 114: Basic Pipeline

    Freescale Semiconductor, Inc. MASTER SLAVE IS BUS GRANTED? REQUEST BUS RECEIVE ADDRESS BUS GRANT RECEIVED CAN SLAVE PIPELINE? BUS BEING DRIVEN BY ANOTHER MASTER? ASSERT ADDRESS ACKNOWLEDGE ASSERT BUS BUSY LATCH DATA ASSERT TRANSFER START ASSERT TRANSFER ACKNOWLEDGE DRIVE ADDRESS...
  • Page 115 Freescale Semiconductor, Inc. CLKOUT ADDRESS PHASE DATA PHASE PIPE DEPTH Figure 5-7 Example of Pipelined Bus Figure 5-8 illustrates a write access followed by two read accesses on the external bus. CLKOUT ADDR DATA AACK ADDR-PHASE DATA-PHASE EBI-PIPE- DEPTH Figure 5-8 Write Followed by Two Reads on the E-Bus (Using Chip Selects)

  • Page 116: Bus Cycle Phases

    Freescale Semiconductor, Inc. 5.4.5 Bus Cycle Phases The following paragraphs describe the three bus cycle phases: arbitration phase, address phase, and data phase. NOTE There is no separate arbitration for the address and data buses. 5.4.5.1 Arbitration Phase The SIU supports multiple masters but is optimized for single-master systems. Each master must have bus request, bus grant, and bus busy signals.

  • Page 117: Data Phase

    Freescale Semiconductor, Inc. TS is a control signal that is valid for only one clock cycle at the start of the address phase. The address attributes listed in Table 5-8 are updated at the start of the address phase and are maintained until the start of the next address phase.

  • Page 118: Burst Cycles

    Freescale Semiconductor, Inc. chip select module accepts the external pin information and does not generate TA internally. A bus timer or system address protection mechanism can assert transfer error acknowledge (TEA) to terminate the data phase when a bus error condition is encoun- tered.

  • Page 119: Termination Of Burst Cycles

    Freescale Semiconductor, Inc. CLKOUT ADDR PIPELINED ADDRESS Burst AACK DATA WAIT STATE LAST DATA NEXT DATA BDIP ADDR PHASE DATA PHASE Figure 5-9 External Burst Read Cycle 5.4.6.1 Termination of Burst Cycles During the data phase of a burst read cycle, the master receives data from the addressed slave.

  • Page 120: Decomposed Cycles And Address Wrapping

    Freescale Semiconductor, Inc. A burst can only be burst inhibited until the first data is acknowledged (TA asserted). Since BI is not sampled until AACK is asserted, AACK must be asserted before or at the same time as TA. Otherwise, the BI pin is never sampled.

  • Page 121: Preventing Speculative Loads

    Freescale Semiconductor, Inc. Table 5-9 Burst Access Address Wrapping Starting Ad- Burst Address Wrapping Port Size dress Half-Word/Word Boundary Address ADDR[28:30] ADDR[28:30] 000 (Starting address) Double word boundary, 16 bit Two bursts of four beats each 010 (Starting address) Odd word boundary,...
  • Page 122 Freescale Semiconductor, Inc. However, if the address of the speculative load represents a FIFO device, the specu- latively loaded data is lost when the exception is processed, and the re-issued load instruction loads the next data item in the queue. Preventing speculative loads is nec- essary to prevent this scenario from occurring.

  • Page 123: Accesses To 16-Bit Ports

    Freescale Semiconductor, Inc. Table 5-11 SPECMASK Bit Settings Bit(s) Name Description 0:15 — Reserved Six-bit mask that specifies which block or blocks within region specified in SPECMASK reg- 16:21 MASK ister are actually protected from speculative accesses. 22:31 — Reserved...

  • Page 124: Address Retry

    Freescale Semiconductor, Inc. nal L-data bus), the table shows the values of BE[0:3] and indicates which bytes of the operand are accessed and where these bytes are placed on the E-bus. Table 5-13 EBI Read and Write Access to 16-Bit Ports...

  • Page 125: Transfer Error Acknowledge Cycles

    Freescale Semiconductor, Inc. must not be asserted at any time during the cycle; if ARETRY is as- serted during a burst cycle, it must be asserted before the first beat is terminated with TA. 5.4.11 Transfer Error Acknowledge Cycles A bus timer or system address protection mechanism can assert transfer error...
  • Page 126 Freescale Semiconductor, Inc. Table 5-14 Cycle Type Encodings CT[0:3] Cycle Type Description This is a normal external bus cycle. Both the address and data phase are seen on the external bus. This cycle requires an AACK and a TA signal. This cycle type is used for sequential fetches and for prefetches...

  • Page 127: Show Cycles

    Freescale Semiconductor, Inc. Table 5-14 Cycle Type Encodings (Continued) CT[0:3] Cycle Type Description E-Mem cache hit 1000 to CSBOOT region E-Mem cache 1001 These are internal visibility cycles. They always have an address hit to CS1 region phase and include a data phase for data accesses. These cycles are E-Mem cache self-terminating and do not require AACK and TA signals.

  • Page 128: Storage Reservation Support

    Freescale Semiconductor, Inc. show cycles (I-bus show cycles are address only), the data phase always follows the address phase by one clock cycle. The L-bus show cycle does not start until the inter- nal cycle completes. This allows all show cycles to complete in two clock cycles.

  • Page 129: Powerpc Architecture Reservation Requirements

    Freescale Semiconductor, Inc. MASTER CT[0:3] CT[0:3] E-BUS SNOOP NON-LOCAL LOGIC ARETRY ARETRY NON-LOCAL INTERFACE E-BUS Figure 5-10 Storage Reservation Signaling 5.4.14.1 PowerPC Architecture Reservation Requirements The PowerPC architecture requires that the reservation protocol meets the following requirements: • Each PowerPC processor has at most one reservation.

  • Page 130: Reservation Storage Signals

    Freescale Semiconductor, Inc. • Snoop accesses to all local bus slaves. • Hold one reservation for each local master capable of storage reservations. • Set the reservation when that master issues a load with reservation. • Clear the reservation when some other master issues a store to the reservation address.

  • Page 131: Chip Selects

    Freescale Semiconductor, Inc. Table 5-15 EBI Storage Reservation Interface Signals Name Direction Description Snoop logic ⇒ SIU Cancel reservation. Each PowerPC CPU has its own CR signal. This signal shows the status of any outstanding reservation on the external bus. When asserted, CR indicates that there is no outstanding reservation.

  • Page 132: Chip-Select Features

    Freescale Semiconductor, Inc. The chip-select module provides the necessary control signals, such as the chip enable (CE), write enable (WE), and output enable (OE), for the external memory and peripheral devices. In addition, the chip-select module provides some handshakes for the external bus and some limited protection mechanisms for the system.

  • Page 133: Chip-Select Pins

    Freescale Semiconductor, Inc. DECODE TIMING ADDRESS DECODER PIN CONFIGURATION PIN 0 LOGIC CIRCUIT BASE OPTION ADDRESS REGISTER CONTROL REGISTER UNIT ADDRESS DECODER PIN CONFIGURATION PIN 1 LOGIC CIRCUIT BASE OPTION ADDRESS REGISTER CONTROL REGISTER UNIT ADDRESS DECODER PIN CONFIGURATION PIN N...

  • Page 134: Chip-Select Registers And Address Map

    Freescale Semiconductor, Inc. Table 5-16 Chip-Select Pin Functions (Continued) Alternate Chip-Select Function Pin Function in Chip-Select Mode Function ADDR3/PA3 Can be CE, WE, or OE of EPROMs or SRAMs. ADDR4/PA4 Can be CE, WE, or OE of EPROMs or SRAMs.
  • Page 135 Freescale Semiconductor, Inc. Table 5-17 is an address map of the chip-select module. As the entries in the Access column indicate, all chip-select registers are accessible at the supervisor privilege level only. When set, the LOK bit in the SIU module configuration register (SIUMCR) locks all chip-select registers to prevent software from changing the chip-select configuration inadvertently.
  • Page 136 Freescale Semiconductor, Inc. Table 5-17 Chip-Select Module Address Map Access Address Register 0x8007 FD00 – — Reserved 0x8007 FD90 0x8007 FD94 CS11 option register (CSOR11) 0x8007 FD98 Reserved 0x8007 FD9C CS10 option register (CSOR10) 0x8007 FDA0 Reserved 0x8007 FDA4 CS9 option register (CSOR9)

  • Page 137: Chip-Select Base Address Registers

    Freescale Semiconductor, Inc. 5.5.4.1 Chip-Select Base Address Registers Base address registers contain the base address of the range of memory to which the chip select circuit responds. All base address registers contain the same fields but have different reset values.
  • Page 138 Freescale Semiconductor, Inc. registers for CS[0:11] depends on the value of internal DATA0 at reset. If DATA0 = 1, the CS[0:11]/ADDR[0:11] pins are configured as chip selects, and the PCON field at reset is 0b10 (output enable) for CS0 and 0b00 (chip enable) for CS[0:11]. If internal DATA0 = 0 at reset, the pins are configured as address pins, and the PCON field val- ues for all option registers are 0b11 (non-chip-select function).
  • Page 139 Freescale Semiconductor, Inc. CSOR0 — CS0 Option Register 0x8007 FDEC RESERVED RESET: RESERVED PCON BYTE REGION RESERVED RESET: *0b10 if pins are configured as chip selects at reset, otherwise 0b11 CSOR1 — CS1 Option Register 0x8007 FDE4 CSOR2 — CS2 Option Register 0x8007 FDDC CSOR3 —...
  • Page 140 Freescale Semiconductor, Inc. CSOR6 — CS6 Option Register 0x8007 FDBC CSOR7 — CS7 Option Register 0x8007 FDB4 CSOR8 — CS8 Option Register 0x8007 FDAC CSOR9 — CS9 Option Register 0x8007 FDA4 CSOR10 — CS10 Option Register 0x8007 FD9C CSOR11 — CS11 Option Register...
  • Page 141 Freescale Semiconductor, Inc. Table 5-19 Chip-Select Option Register Bit Settings Bit(s) Name Description Block size. This field determines the size of the block associated with the base address. 0000 = Disables corresponding region 0001 = 4 Kbytes 0010 = 8 Kbytes...

  • Page 142: Chip-Select Regions

    Freescale Semiconductor, Inc. Table 5-19 Chip-Select Option Register Bit Settings (Continued) Bit(s) Name Description TA delay. Indicates the latency of the device for the first TA returned. Up to seven wait states are allowed. 000 = 0 wait states 001 = 1 wait state...
  • Page 143 Freescale Semiconductor, Inc. Each chip-select pin that is programmed as a chip enable defines a separate region. Only the CSBOOT and CS[1:5] pins can serve as chip enables. All chips within a region have a common chip enable signal. Each chip select that can be programmed as a chip enable has an associated base address register.

  • Page 144: Multi-Level Protection

    Freescale Semiconductor, Inc. Since the address decode logic of the chip select uses only the most significant address bits to determine an address match within its block size, the value of the base address must be a multiple of the corresponding block size.

  • Page 145: Main Block And Sub-Block Pairings

    Freescale Semiconductor, Inc. 5.5.6.1 Main Block and Sub-Block Pairings Multi-level protection is accomplished using a paired set of chip-select decoding cir- cuits. The decoding pairs are specified in Table 5-21. Table 5-21 Main Block and Sub-Block Pairings Main Block Sub-Block...

  • Page 146: Access Protection

    Freescale Semiconductor, Inc. If an address is contained in the dedicated sub-block (and the CSBOOT main block) but not the CS1 sub-block, the protections specified in the CSBOOT sub-block option register are used. The SBLK bit of the dedicated sub-block option register is cleared at power-on. The bit can be modified after reset if needed.

  • Page 147: Write Protection

    Freescale Semiconductor, Inc. lation (DSP = 1 and AT1 = 1), it asserts the internal TEA signal and does not assert the external chip enable signal. 5.5.7.3 Write Protection The WP bit in the option registers for CSBOOT, the CSBOOT sub-block, and CS[1:5] controls whether the address block is write-protected.

  • Page 148: Port Size

    Freescale Semiconductor, Inc. Table 5-22 TADLY and Wait State Control TADLY Wait States 0b000 0b001 0b010 0b011 0b100 0b101 0b110 0b111 Note this field is used only when the chip-select logic returns the handshaking signals (ACKEN = 1). Note that the user does not program the number of wait states prior to AACK assertion.

  • Page 149: Chip-Select Pin Control

    Freescale Semiconductor, Inc. 5.5.12 Chip-Select Pin Control The PCON, BYTE, and REGION fields of each chip-select option register control how the associated pin is used. The PCON field determines pin function (CE, OE, WE, or alternate function). The BYTE field determines which byte enable a WE pin corre- sponds to.

  • Page 150: Region Control

    Freescale Semiconductor, Inc. Table 5-25 BYTE Field Encodings BYTE Byte Enabled 0b00 Byte enable 0 0b01 Byte enable 1 0b10 Byte enable 2 0b11 Byte enable 3 If the pin is configured as an OE, this field is not used. (It is assumed the OE pin enables the outputs of all four bytes of the region onto the 32-bit E-bus.) Thus, typically...

  • Page 151: Interface Type Descriptions

    Freescale Semiconductor, Inc. • Has a synchronous OE, an asynchronous OE, or no OE • Is burstable or non-burstable • Uses the LAST or BDIP protocol for ending a burst transmission The following paragraphs define these concepts. A burstable device can accept one address and drive out multiple data beats. A burst- able device must be synchronous.
  • Page 152 Freescale Semiconductor, Inc. Table 5-27 Interface Types ITYPE Interface Type (Binary) Generic asynchronous region with output buffer turn-off time of less than or equal to one clock period (see 5.5.13.2 Turn-Off Times for Different Interface 0000 Types). A device of this type cannot be pipelined. Refer to...

  • Page 153: Turn-Off Times For Different Interface Types

    Freescale Semiconductor, Inc. Table 5-27 Interface Types (Continued) ITYPE Interface Type (Binary) Region with fixed burst access capability (burst type 2). Refer to Figure 5-25. This interface type uses the LAST timing protocol. Typically, this ITYPE is used for burst accesses to DRAM.

  • Page 154: Chip-Select Operation Flowchart

    Freescale Semiconductor, Inc. CAUTION It is recommended that the BI pin not be asserted during accesses to memory regions controlled by chip selects; instead, the chip-select unit will generate the BI signal internally when appropriate. 5.5.14 Chip-Select Operation Flowchart Figure 5-14 illustrates the operation of the chip-select logic for external accesses.

  • Page 155: Pipelined Accesses To The Same Region

    Freescale Semiconductor, Inc. Table 5-28 Pipelined Reads and Writes Pipelining First Access Second Access Supported Read Read Write Read Read Write Write Write The following subsections explain which types of interfaces permit pipelining of read accesses. Pipelining of consecutive accesses to the same region is discussed first, fol- lowed by pipelining of consecutive accesses to different regions.

  • Page 156: Pipelined Accesses To Different Regions

    Freescale Semiconductor, Inc. NOTE If the region is programmed to return its own handshaking signals (ACKEN = 0), the chip-select logic does not know whether the device has an address latch (hence, whether the device is programmable). The chip-select control logic takes this into account and asserts the CE of the second access only after AACK has been asserted for the first access.
  • Page 157 Freescale Semiconductor, Inc. 1. If both regions are under chip-select control, the delays of both regions are known to the chip-select logic, and the interface type of the first region supports pipelining, then the second access (if a read) can be pipelined with the first.

  • Page 158: Chip-Select Timing Diagrams

    Freescale Semiconductor, Inc. 5.5.16 Chip-Select Timing Diagrams The diagrams in this section show the different device interfaces that the chip-select module supports. Where applicable, the diagrams indicate how the various signals (address, data, and chip-select signals) are correlated. CAUTION The user must not assume that CE is always asserted simultaneous- ly with TS.

  • Page 159: Asynchronous Interface With Latch Enable

    Freescale Semiconductor, Inc. CLKOUT ADDR POSSIBLE A2 OUTPUT BUFFERS CORRELATION STROBE IN DATA DATA Figure 5-18 Asynchronous Write (Zero Wait States) 5.5.16.2 Asynchronous Interface with Latch Enable Devices with an address latch enable signal, such as the Motorola MCM62995A mem-...

  • Page 160: Synchronous Interface With Early Synchronous Oe

    Freescale Semiconductor, Inc. CLKOUT ADDR OVERLAP ACCESS CLOCK IN ADDRESS FOR READ ENABLE DATA OUTPUT (ASYNCHRONOUS) DATA = UNDEFINED = DON’T CARE AACK Figure 5-19 Synchronous Read with Asynchronous OE (Zero Wait States) CLKOUT ADDR OVERLAP ACCESS CLOCK IN ADDRESS FOR WRITE...

  • Page 161: Synchronous Interface With Synchronous Oe, Early Overlap

    Freescale Semiconductor, Inc. CLKOUT ADDR OVERLAP ACCESS = UNDEFINED = DON’T CARE CLOCK IN ADDRESS FOR READ NEXT POSSIBLE CE (SYNCHRONOUS) ENABLE DATA OUTPUT DATA DEVICE CAN 3-STATE IT AACK DRIVERS FROM CLOCK EDGE ONE WAIT STATE Figure 5-21 Synchronous Read with Early OE (One Wait State) 5.5.16.5 Synchronous Interface with Synchronous OE, Early Overlap...

  • Page 162: Synchronous Burst Interface

    Freescale Semiconductor, Inc. 5.5.16.6 Synchronous Burst Interface The chip-select module supports two types of burst interfaces. The type 1 burst inter- face uses the output enable and the write enable to control the data being driven out or received. The type 1 burst interface also requires a BDIP signal to control when the region should output the next beat of the burst.
  • Page 163 Freescale Semiconductor, Inc. CLKOUT POSSIBLE A2 ADDR LAST DATA BDIP NEXT DATA (ASYNCHRONOUS) TURN OFF ENABLE DATA OUT DATA WAIT STATE AACK = UNDEFINED = DON’T CARE Figure 5-23 Type 1 Synchronous Burst Read Interface CLOCK POSSIBLE A2 ADDR CLOCK IN DATA...

  • Page 164: Burst Handling

    Freescale Semiconductor, Inc. Figure 5-25 shows a read access to a type 2 burst interface (ITYPE = 8). Note that an output enable signal is not required for this type of interface. Instead, the interface uses the LAST signal. CLKOUT...

  • Page 165: Chip-Select Reset Operation

    Freescale Semiconductor, Inc. that the device has a 16-bit port. If more data is needed, the EBI requests the chip selects to perform another access to the device to complete the transfer. 5.5.18 Chip-Select Reset Operation The data bus configuration word specifies how the MCU is configured at reset.

  • Page 166: Clock Submodule

    Freescale Semiconductor, Inc. 5.6 Clock Submodule The system clock provides timing signals for the IMB2 and for an external peripheral bus. The MCU drives the system clock onto the external bus on the CLKOUT pin. The main timing reference for the MPC500 family is a 4-MHz crystal. The system operating frequency is generated through a programmable phase-locked loop.

  • Page 167: Clock Submodule Signal Descriptions

    Freescale Semiconductor, Inc. OSCCLK LPM3 RFD[0:3] VCOOUT LPM3 SPLL MF[0:3] ECROUT LPM1 XTAL 2:1 MUX EXTAL (÷4) VDDSN SI_S_FREEZE MODCLK LPM2 LPM1 TB, DEC SYSTEM CLKOUT CLOCKS SIU CLOCK BLOCK Figure 5-26 SIU Clock Module Block Diagram 5.6.1 Clock Submodule Signal Descriptions Table 5-30 describes the signals used by the clock module.

  • Page 168: Clock Power Supplies

    Freescale Semiconductor, Inc. Table 5-30 Clocks Module Signal Descriptions Mnemonic Name Direction Description System clock. Used as the bus timing reference by CLKOUT System clock out external devices. Connections for external crystal to the internal oscil- EXTAL, XTAL Crystal oscillator lator circuit.

  • Page 169: System Clock Sources

    Freescale Semiconductor, Inc. The oscillator, system clock control register, and system clock control and status reg- ister are powered from the keep alive power supply (VDDKAP1) and V . In addition, VDDKAP1 powers the PowerPC time base and decrementer. This allows the time base to continue incrementing at 1 MHz even when the main power to the MCU is off.

  • Page 170: Phase-Locked Loop

    Freescale Semiconductor, Inc. 5.6.4 Phase-Locked Loop The phase-locked loop (PLL) is a frequency synthesis PLL that can multiply the refer- ence clock frequency by a factor from 4 to 11, provided the system clock (CLKOUT) frequency (when RFD = 0b000) remains within the specified limits. With a reference frequency of 4 MHz, the PLL can synthesize frequencies from 16 MHz to 44 MHz.

  • Page 171: Phase Detector

    Freescale Semiconductor, Inc. 36 pF 4 MHz EXTAL 10 MΩ XTAL 36 pF Figure 5-28 Crystal Oscillator 5.6.4.2 Phase Detector The phase detector compares both the phase and frequency of the reference clock (oscclk in Figure 5-27) and the feedback clock. The reference clock comes from either the crystal oscillator or an external clock source.

  • Page 172: Vco

    Freescale Semiconductor, Inc. 5.6.4.4 VCO The VCO uses a single-ended design with an external capacitor to increase noise immunity. The voltage on XFCP controls the VCO output frequency. The frequency- to-voltage relationship (VCO gain) is positive, and the output frequency is twice the maximum target system frequency.

  • Page 173: Multiplication Factor (Mf) Bits

    Freescale Semiconductor, Inc. Table 5-33 CLKOUT Frequencies with a 4-MHz Crystal CLKOUT (Hz) RFD[0:3] MF = MF = MF = MF = MF = MF = MF = MF = X000 X001 X010 X011 X100 X101 X110 X111 (x4) (x5)
  • Page 174 Freescale Semiconductor, Inc. Table 5-34 Multiplication Factor Bits Multiplication Fac- PLL Frequency MF Field (Binary) (with 4-MHz Reference) x000 16 MHz x001 20 MHz x010 24 MHz x011 28 MHz x100 32 MHz x101 36 MHz x110 40 MHz x111...

  • Page 175: Reduced Frequency Divider (Rfd[0:3])

    Freescale Semiconductor, Inc. When the PLL is operating in one-to-one mode, the multiplication factor is set to one and MF is ignored. Figure 5-27 shows how the PLL uses the MF bits to multiply the input crystal fre- quency. The output of the VCO is divided down to generate the feedback signal to the phase comparator.

  • Page 176: Low-Power Modes

    Freescale Semiconductor, Inc. These bits can be read at any time. They should be written only when the system PLL lock status bit (SPLS) is set. Writing the RFD bits, especially to 0x0, when the PLL is not locked can cause the clock frequency to surpass the system operating frequency.

  • Page 177: Doze Mode

    Freescale Semiconductor, Inc. Since the oscillator and PLL are still running and locked, the low-power mode exit sig- nal must be a minimum of two system clock cycles and exiting this state does not incur a PLL lock time. 5.6.6.3 Doze Mode Mode 0x2 is doze mode.

  • Page 178: System Clock Lock Bits

    Freescale Semiconductor, Inc. up is two clock cycles of the frequency that the VCO was programmed to generate. The delay for mode 3 is the crystal start-up time plus the VCO lock time. The LPMM bit can be read or written any time.

  • Page 179: Time Base And Decrementer Support

    Freescale Semiconductor, Inc. 5.6.9 Time Base and Decrementer Support The time base is a timer facility defined by the PowerPC architecture. It is a 64-bit free- running binary counter which is incremented at a frequency determined by each imple- mentation of the time base. There is no interrupt or other indication generated when the count rolls over.

  • Page 180: Decrementer Clock Enable (Dce) Bit

    Freescale Semiconductor, Inc. 5.6.9.3 Decrementer Clock Enable (DCE) Bit The decrementer clock enable (DCE) bit in the SCCR enables or disables the clock source to the decrementer. The default state is to have the clock enabled. The actual clock source is determined by the TBS bit. The DCE bit does not affect the decre- menter until after the next increment time, as determined by the clock source.

  • Page 181: System Clock Control Register (Sccr)

    Freescale Semiconductor, Inc. circuitry to assert the LOO bit and force the PLL into self-clocked mode. A frequency above 500 kHz causes the loss-of-oscillator circuitry to negate the LOO bit, and the PLL operates normally. The LOO bit can be read any time. It can be written only in spe- cial test mode.
  • Page 182 Freescale Semiconductor, Inc. Table 5-38 SCCR Bit Settings Bit(s) Name Description — Reserved Low-power mode mask LPMM 0 = IRQ[0:1] pins cannot be used to wake up from LPM 1 = IRQ[0:1] pins can be used to wake up from LPM —...

  • Page 183: System Clock Lock And Status Register (Sclsr)

    Freescale Semiconductor, Inc. Table 5-38 SCCR Bit Settings (Continued) Bit(s) Name Description Reduced-frequency divider. The RFD field controls a prescaler at the output of the PLL. In nor- mal mode, the MF and RFD fields determine the CLKOUT frequency. (In bypass mode, only this field, and not the MF field, affects CLKOUT frequency.

  • Page 184: System Protection

    Freescale Semiconductor, Inc. Table 5-39 SCLSR Bit Settings Bit(s) Name Description — Reserved System PLL test mode enable STME 0 = Test mode disabled 1 = Test mode enabled MF lock 0 = Writes to MF field (in SCCR) allowed...

  • Page 185: System Protection Registers

    Freescale Semiconductor, Inc. • The periodic interrupt timer generates an interrupt after a period specified by the user. 5.7.2 System Protection Registers Table 5-40 shows the SIU system protection registers. Table 5-40 System Protection Address Map Access Address Register 0x8007 FC40...

  • Page 186: Pit Clock Frequency Selection

    Freescale Semiconductor, Inc. CLOCKS PITC EXTAL DIVIDE PCFS CLOCK BY 4 16-BIT FREEZE DIVIDE LOGIC DISABLE LOGIC MODULUS PIT INTERRUPT COUNTER PCFS[2:0] FREEZE Figure 5-30 Periodic Interrupt Timer Block Diagram 5.7.3.1 PIT Clock Frequency Selection The PIT clock frequency select (PCFS) field in the PICSR selects the appropriate fre- quency for the PIT clock source over a range of external clock or crystal frequencies.

  • Page 187: Pit Time-Out Period Selection

    Freescale Semiconductor, Inc. Table 5-42 Recommended Settings for PCFS[0:2] Input Frequency Range PCFS[0:2] 16 MHz < FREQ ≤ 32 MHz 0b011 32 MHz < FREQ ≤ 64 MHz 0b100 Reserved 0b101 Reserved 0b110 Reserved 0b111 5.7.3.2 PIT Time-Out Period Selection The PIT time-out period is determined by the input clock frequency, the divider speci- fied in the PCFS field, and the timing count specified in the PITC field of the PICSR.

  • Page 188: Pit Enable Bits

    Freescale Semiconductor, Inc. 5.7.3.3 PIT Enable Bits The PIT enable (PTE) bit in the PICSR enables or disables the timer. When the timer is disabled, it retains its current value. When the timer is enabled, it resumes counting starting with the current value.

  • Page 189: Periodic Interrupt Timer Register

    Freescale Semiconductor, Inc. Table 5-44 PICSR Bit Settings Bit(s) Name Description — Reserved Periodic timer enable 0 = Disable decrementer counter 1 = Enable decrementer counter Periodic interrupt enable 0 = Disable periodic interrupt 1 = Enable periodic interrupt Caution: Be sure the EE (external interrupts enable) bit in the MSR is cleared before changing the value of this bit.

  • Page 190: Bus Monitor Timing

    Freescale Semiconductor, Inc. 5.7.4.1 Bus Monitor Timing The bus monitor timing (BMT) field in the BMCR allows the user to select one of four selectable response time periods. Periods range from 16 to 256 system clock cycles. The programmability of the time-out allows for a variation in system peripheral response time.

  • Page 191: Reset Operation

    Freescale Semiconductor, Inc. Table 5-45 BMCR Bit Settings Bit(s) Name Description — Reserved Bus monitor lock BMLK 0 = Enable changes to BMLK, BME, BMT 1 = Ignore writes to BMLK, BME, BMT Bus monitor enable 0 = Disable bus monitor 1 = Enable bus monitor Bus monitor timing.

  • Page 192: Reset Flow

    Freescale Semiconductor, Inc. Individual bits in the RSR can be cleared by writing them as zeros after reading them as ones. (Writing individual bits as ones has no effect.) The register can be read at all times. Assertion of the RESET pin clears all bits except the RESET bit.
  • Page 193 Freescale Semiconductor, Inc. IDLE FROM INTERNAL RESET FLOW RESET = ASSERT RESETOUT AND INTERNAL RESET. REQUEST INTERNAL BUSES RESET START THE COUNTER RESET WAIT FOR CNT = 17 WAIT FOR PLL TO LOCK THIS STATE DEPENDS ON PLL MODE AND RESET CONFIG...

  • Page 194: Internal Reset Request Flow

    Freescale Semiconductor, Inc. (synchronous or asynchronous) before getting to the reset control logic. The external reset request follows the asynchronous path in the case of power-on reset or in case of loss of oscillator. Under all remaining conditions the reset request goes through the synchronous path, in which the reset request is synchronized with the system clock.
  • Page 195 Freescale Semiconductor, Inc. NOTE: IDLE INT_RST IS EITHER LOO OR LOL OR JTAG OR TO EXTERNAL RESET FLOW SWDOG TIMER OR CHECKSTOP RESET REQUEST INT_RST = 1 RESET CLOCKS AND PLL LOO/LOL RST IF RESET = 0 REQUEST THE INTERNAL BUSES.

  • Page 196: Reset Behavior For Different Clock Modes

    Freescale Semiconductor, Inc. The SIU enters internal reset flow when an internal reset request is issued due to one of the following causes: loss of clock, loss of PLL lock, software watchdog time-out, entry into checkstop state, or assertion of a JTAG reset request. If the source of reset is either loss of oscillator or loss of clock, the SIU resets the clocks and the PLL imme- diately.

  • Page 197: Configuration During Reset

    Freescale Semiconductor, Inc. Table 5-47 Reset Behavior for Different Clock Modes Clock Mode MODCLK Internal DATA19 = 1 at Reset Internal DATA19 = 0 at Reset DDSN Release internal reset when PLL is locked and 17 clocks af- Normal Release internal reset 17...

  • Page 198: Data Bus Configuration Mode

    Freescale Semiconductor, Inc. This scheme allows users of the internal default mode to limit their required external configuration hardware to two pull-down resistors (DSDI and DSCK). It also allows many options to be configured with a single three-state octal buffer.
  • Page 199 Freescale Semiconductor, Inc. Table 5-49 Data Bus Reset Configuration Word Internal Default Data Configuration Effect of Mode Select = 1 Effect of Mode Select = 0 Mode Function Affected During Reset During Reset 3 V I/O TTL I/O Minimum bus mode...

  • Page 200: Power-On Reset

    Freescale Semiconductor, Inc. Table 5-49 Data Bus Reset Configuration Word (Continued) Internal Default Data Configuration Effect of Mode Select = 1 Effect of Mode Select = 0 Mode Function Affected During Reset During Reset 3 V I/O TTL I/O BURST, TEA, AACK, TA,...

  • Page 201: General-Purpose I/O

    Freescale Semiconductor, Inc. 5.9 General-Purpose I/O Many of the pins associated with the SIU can be used for more than one function. The primary function of these pins is to provide an external bus interface. When not used for their primary function, many of these pins can be used as digital I/O pins.
  • Page 202 Freescale Semiconductor, Inc. Table 5-50 SIU Port Registers Address Map Access Address Register 0x8007 FC60 Port M data direction (DDRM) 0x8007 FC64 Port M pin assignment (PMPAR) 0x8007 FC68 Port M data (PORTM) 0x8007 FC6C – — Reserved 0x8007 FC80...

  • Page 203: Port M

    Freescale Semiconductor, Inc. 5.9.2 Port M PORTM — Port M Data Register 0x8007 FC68 RESERVED RESET: RESERVED RESET: U = Unaffected by reset Writes to PORTM are stored in internal data latches. If any bit of the port is configured as an output, the value latched for that bit is driven onto the pin.

  • Page 204: Ports A And B

    Freescale Semiconductor, Inc. PMPAR — Port M Pin Assignment Register 0x8007 FC64 PMPA PMPA PMPA PMPA PMPA PMPA RESERVED RESET: RESERVED RESET: * Reset setting depends on the value of the configuration word at reset. The bits in this register control the function of the associated pins. Setting a bit in this register to one configures the corresponding pin as a bus control signal;...
  • Page 205 Freescale Semiconductor, Inc. PORTA, PORTB — Port A, B Data Registers 0x8007 FC88 RESET: RESERVED RESET: U = Unaffected by reset When a port A or port B pin is configured as a general-purpose output, the value in the port A or port B data register is driven onto the pin. PORTA and PORTB are unaffected by reset.

  • Page 206: Ports I, J, K, And L

    Freescale Semiconductor, Inc. Table 5-52 Port A Pin Assignments PMPAR Bit Port A Signal Bus Control Signal PAPA0 ADDR0 PAPA1 ADDR1 PAPA2 ADDR2 PAPA3 ADDR3 PAPA4 ADDR4 PAPA5 ADDR5 PAPA6 ADDR6 PAPA7 ADDR7 Table 5-53 Port B Pin Assignments PMPAR Bit...
  • Page 207 Freescale Semiconductor, Inc. Writes to port I, J, K, and L data registers are stored in internal data latches. If any pin in one of these ports is configured as an output, the value latched for the correspond- ing data register bit is driven onto the pin. A read of one of these data registers returns the value at the pin only if the pin is configured as a discrete input.
  • Page 208 Freescale Semiconductor, Inc. Table 5-54 Port I Pin Assignments PIPAR Bit Port I Signal Bus Control Signal PIPA0 BURST PIPA1 PIPA2 AACK PIPA3 PIPA4 PIPA5 PIPA6 PIPA7 Table 5-55 Port J Pin Assignments PJPAR Bit Port J Signal Bus Control Signal...

  • Page 209: Port Replacement Unit (Pru) Mode

    Freescale Semiconductor, Inc. Table 5-57 Port L Pin Assignments PLPAR Bit Port L Signal Bus Control Signal PLPA2 PLPA3 PLPA4 PLPA5 PLPA6 PLPA7 5.9.5 Port Replacement Unit (PRU) Mode The entire external bus interface must be supported in order to build an emulator for an MCU.
  • Page 210 Freescale Semiconductor, Inc. MPC509 SYSTEM INTERFACE UNIT MOTOROLA REFERENCE MANUAL Revised 15 July 1999 5-114 For More Information On This Product, Go to: www.freescale.com...

  • Page 211: Peripheral Control Unit

    Freescale Semiconductor, Inc. SECTION 6 PERIPHERAL CONTROL UNIT The peripheral control unit (PCU) consists of the following submodules: • Software watchdog — provides system protection. • Interrupt controller — controls the interrupts that external peripherals and internal modules send to the CPU.

  • Page 212: Pcu Address Map

    Freescale Semiconductor, Inc. 6.2 PCU Address Map Table 6-1 shows the address map for the PCU. An entry of “S” in the Access column indicates that the register is accessible in supervisor mode only. “S/U” indicates that the register can be programmed to the desired privilege level. “Test” indicates that the register is accessible in test mode only.

  • Page 213: Software Watchdog

    Freescale Semiconductor, Inc. PCUMCR — Peripheral Control Unit Module Configuration Register 0x8007 EF80 STOP IRQMUX RESERVED SUPV RESERVED RESET: RESERVED RESET: Table 6-2 PCUMCR Bit Settings Bit(s) Name Description Stop system clock to peripherals controller STOP 0 = Enable system clock to IMB2 modules...

  • Page 214: Software Watchdog Service Register

    Freescale Semiconductor, Inc. Any number of instructions may occur between the two writes to the SWSR. If any value other than 0x556C or 0xAA39 is written to the SWSR, however, the entire sequence must start over. 6.4.1 Software Watchdog Service Register...

  • Page 215: Software Watchdog Register

    Freescale Semiconductor, Inc. Table 6-3 SWCR/SWTC Bit Settings Bit(s) Name Description — Reserved Software watchdog enable 0 = Disable watchdog counter 1 = Enable watchdog counter Software watchdog lock SWLK 0 = Enable changes to SWLK, SWE, SWTC 1 = Ignore writes to SWLK, SWE, SWTC Software watchdog timing count.
  • Page 216 Freescale Semiconductor, Inc. • The pending interrupt request register (IRQPEND) contains a status bit for each of the 32 interrupt levels. • The interrupt enable register (IRQENABLE) contains an enable bit for each of the 32 interrupt levels. • The interrupt request levels register (PITQIL) determines the interrupt request level assigned to each interrupt source.

  • Page 217: Interrupt Sources

    Freescale Semiconductor, Inc. interrupts to be structured in a cascade, where an interrupt controller on an external chip is read only if a certain interrupt on the MCU is serviced, or in parallel, where all interrupt controllers in the system are read and combined before it is determined which interrupt in the system needs servicing.

  • Page 218: Interrupt Controller Registers

    Freescale Semiconductor, Inc. IMB2 CLOCK IMB2 IRQ[0:7] [0:7] [8:15] [16:23] [24:31] [0:7] Figure 6-3 Time-Multiplexing Protocol For IRQ Pins The IRQMUX field in the PCU module configuration register (PCUMCR) selects the type of multiplexing the interrupt controller performs. Refer to Table 6-4.

  • Page 219: Pending Interrupt Request Register

    Freescale Semiconductor, Inc. Table 6-5 Interrupt Controller Registers Register Description Contains a status bit for each of the 32 interrupt levels. Each bit of Pending Interrupt IRQPEND is a read-only status bit that reflects the current state of the Request Register (IRQPEND) corresponding interrupt signal.

  • Page 220: Interrupt Enable Register

    Freescale Semiconductor, Inc. IRQAND — Enabled Active Interrupt Requests Register 0x8007 EFA4 RESET: RESET: 6.5.3.3 Interrupt Enable Register The interrupt enable register (IRQENABLE) is a read/write register. The bits in this reg- ister are affected only by writes from the CPU (or other bus master) and by reset.

  • Page 221: Port Q

    Freescale Semiconductor, Inc. PITQIL — PIT/Port Q Interrupt Levels Register 0x8007 EFAC IRQ0L IRQ1L IRQ2L RESET: RESERVED PITIRQL RESET: Table 6-6 PITQIL Bit Settings Bit(s) Name Description — Reserved IRQ0L Interrupt request level for the IRQ0 pin 6:10 IRQ1L Interrupt request level for the IRQ1 pin...

  • Page 222: Port Q Pin Assignment Register

    Freescale Semiconductor, Inc. is configured in the PQPAR as an edge-sensitive interrupt request pin, then the PQE bit acts as a status bit that indicates whether the corresponding interrupt request line is asserted. The bit also acts as a status bit if the pins are configured as general-pur- pose inputs or outputs.

  • Page 223: Port Q Pin Assignment Fields

    Freescale Semiconductor, Inc. 6.6.2.1 Port Q Pin Assignment Fields The port Q pin assignment fields (PQPA[0:6]) select the basic function of each port Q pin, as shown in Table 6-7. Table 6-7 Port Q Pin Assignments PQPA Pin Function PORTQ (Port Q Data Field)
  • Page 224 Freescale Semiconductor, Inc. MPC509 PERIPHERAL CONTROL UNIT MOTOROLA REFERENCE MANUAL Revised 15 July 1999 6-14 For More Information On This Product, Go to: www.freescale.com...

  • Page 225: Static Ram Module

    Freescale Semiconductor, Inc. SECTION 7 STATIC RAM MODULE The static RAM (SRAM) module consists of a 28-Kbyte block of static RAM. The pri- mary function of this module is to serve as fast (one-cycle access), general-purpose RAM for the MCU. The SRAM can be read or written as either bytes, half-words or words.
  • Page 226 Freescale Semiconductor, Inc. Table 7-1 MPC509 SRAM Module Addresses LMEMBASE SRAM Location Reserved Location 0x0000 0000 – 0x0000 6FFF 0x0000 7FFF – 0x0000 7FFF 0x000F 8000 – 0x000F EFFF 0x000F F000 – 0x000F FFFF 0xFFF0 0000 – 0xFFF0 6FFF 0xFFF0 7FFC – 0xFFF0 7FFF 0xFFFF 8000 –...

  • Page 227: Sram Registers

    Freescale Semiconductor, Inc. VECTOR TABLE LOCATION 0x0000 0000 POSSIBLE SRAM (IP BIT = 0) LOCATION (28 KBYTES) 0x0000 6FFF EXTERNAL 0x000F 8000 POSSIBLE SRAM ONE OF FOUR POSSIBLE LOCATIONS LOCATION SELECTED FOR SRAM (28 KBYTES) 0x000F EFFF EXTERNAL 0x8000 0000...
  • Page 228 Freescale Semiconductor, Inc. RESERVED RESERVED RESET: Each SRAM module configuration register contains bits for setting access rights to the array. Table 7-2 provides definitions for the bits. Table 7-2 SRAMMCR Bit Settings Bit(s) Name Description Lock bit 0 = Writes to the SRAMMCR are accepted.

  • Page 229: Development Support

    Freescale Semiconductor, Inc. SECTION 8 DEVELOPMENT SUPPORT Development tools are used by a microcomputer system developer to debug the hard- ware and software of a target system. These tools are used to give the developer some control over the execution of the target program. In-circuit emulators and bus state analyzers are the most frequently used debugging tools.

  • Page 230: Indirect Change-Of-Flow Cycles

    Freescale Semiconductor, Inc. serialized, and all internal fetch cycles appear on the external bus. Processor perfor- mance is therefore much lower than when working in regular mode. The mechanism described below allows tracking of the program instructions flow with almost no performance degradation. The information provided externally may be cap- tured and compressed and then parsed by a post-processing program using the microarchitecture defined below.

  • Page 231: Marking The Indirect Change-Of-Flow Attribute

    Freescale Semiconductor, Inc. • Assertion or negation of VSYNC • Exception taken • Indirect branch taken • Execution of the following sequential instructions: rfi, isync, mtmsr, and mtspr to CMPA–CMPF, ICTRL, ECR, and DER When a program trace recording is needed, the user can ensure that cycles which result from an indirect change-of-flow are visible on the external bus.

  • Page 232: Instruction Fetch Show Cycle Control

    Freescale Semiconductor, Inc. tions (VF = 101, see Table 8-3) and marks the subsequent instruction address with the indirect change-of-flow attribute, as if it were an indirect branch target. Therefore, when the processor detects one of these instructions, the address of the following instruction is visible externally.

  • Page 233: Program Flow-Tracking Pins

    Freescale Semiconductor, Inc. 8.1.3 Program Flow-Tracking Pins The following sets of pins are used in program flow tracking: • Instruction queue status pins (VF[0:2]) denote the type of the last fetched instruc- tion or how many instructions were flushed from the instruction queue.

  • Page 234: History Buffer Flush Status Pins

    Freescale Semiconductor, Inc. Table 8-4 VF Pins Queue Flush Encodings VF[0:2] Queue Flush Information 0 instructions flushed from instruction queue 1 instruction flushed from instruction queue 2 instructions flushed from instruction queue 3 instructions flushed from instruction queue 4 instructions flushed from instruction queue...

  • Page 235: Cycle Type, Write/Read, And Address Type Pins

    Freescale Semiconductor, Inc. is of an indirect branch taken (VF[0:2] = 101), appropriate for the rfi instruction that is being issued. In both cases, the first instruction fetch after debug mode is marked with the program trace cycle attribute and therefore is visible externally.

  • Page 236: External Hardware During Program Trace

    Freescale Semiconductor, Inc. Notice in Table 8-6 that during an instruction fetch (AT1 = 1) to internal memory or to external memory resulting in a cache hit, a logic level of zero on the WR pin indicates that the cycle is the result of an indirect change-of-flow. The indirect change-of-flow attribute is also indicated by a cycle type encoding of 0001 when AT1 = 1.
  • Page 237 Freescale Semiconductor, Inc. The following steps enable the user to synchronize the trace window to events in- ternal to the processor: 1. Enter debug mode, either immediately out of reset or using the debug mode re- quest. 2. Program the hardware to break on the event that marks the start of the trace window using the control registers defined in 8.8 Development Support Reg-...

  • Page 238: Detecting The Trace Window Starting Address

    Freescale Semiconductor, Inc. mation upon the report on the VF pins of VSYNC. 8. The watchpoint logic signals the ending event by asserting the appropriate watchpoint pin. 9. Upon detecting the second watchpoint, negate VSYNC using the development port serial interface.

  • Page 239: Detecting The Trace Window Ending Address

    Freescale Semiconductor, Inc. negation of VSYNC. A VF[0:2] encoding of 011 indicates the assertion or negation of VSYNC only if the previous VF[0:2] pin values were 000, 001, or 010. 8.1.4.6 Detecting the Trace Window Ending Address The information on the VF and VFLS status pins changes every clock. Cycles marked with the indirect change-of-flow are generated on the external bus only when possible (when the SIU wins the arbitration over the external bus).
  • Page 240 Freescale Semiconductor, Inc. monitor or by using the development port serial interface. A watchpoint output may also be counted. When the counter reaches zero, an internal breakpoint is generated. An external breakpoint occurs when a development system or external peripheral requests a breakpoint through the development port serial interface.

  • Page 241: Watchpoints

    Freescale Semiconductor, Inc. 8.2.1 Watchpoints Watchpoints are based on eight comparators on the I-bus and L-bus, two counters, and two AND-OR logic structures. There are four comparators on the instruction address bus (I-address), two comparators on the load/store address bus (L-address), and two comparators on the load/store data bus (L-data).

  • Page 242: Byte And Half-Word Working Modes

    Freescale Semiconductor, Inc. Since watchpoint events are reported upon the retirement of the instruction that caused the event, and more than one instruction can retire from the machine in one clock, separate watchpoint events may be reported in the same clock. Moreover, the same event, if detected on more than one instruction (e.g., tight loops, range detec-...

  • Page 243: Generating Six Compare Types

    Freescale Semiconductor, Inc. — One L-address comparator = 0x0000 000C and program for less than — One L-data comparator = 0x4E20 4E20 and program for greater than — One L-data comparator = 0x9C40 9C40 and program for less than — Both byte masks = 0b1111 —...

  • Page 244: I-Bus Support Detailed Description

    Freescale Semiconductor, Inc. • Less than or equal of the largest unsigned number (1111...1) • Greater than or equal of the smallest unsigned number (0000...0) • Less than or equal of the maximum positive number when in signed mode (0111...1) •...

  • Page 245: L-Bus Support Detailed Description

    Freescale Semiconductor, Inc. The I-bus watchpoints and breakpoint are generated using these events and accord- ing to the user’s programming of the CMPA, CMPB, CMPC, CMPD, and ICTRL registers. Table 8-8 shows how watchpoints are determined from the programming options. Note that using the OR option enables “out of range” detection.
  • Page 246 Freescale Semiconductor, Inc. Figure 8-4 shows the general structure of L-bus support. COMPARATOR E COMPARATOR F COMPARE TYPE BYTE MASK COMPARE SIZECOMPARE TYPE TYPE LOGIC TYPE LOGIC COMPARATOR G BYTE 0 SIZE COMPARE BYTE LOGIC TYPE QUALIFIER BYTE 1 LOGIC...

  • Page 247: Treating Floating-Point Numbers

    Freescale Semiconductor, Inc. Table 8-9 L-Bus Data Events Event Name Event Function (Gmatch0 | Gmatch1 | Gmatch2 | Gmatch3) (Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3) ((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 &...

  • Page 248: Internal Breakpoints

    Freescale Semiconductor, Inc. 8.2.2 Internal Breakpoints Internal breakpoints are generated from the watchpoints. The user may enable a watchpoint to create a breakpoint by setting the associated software trap enable bit in the ICTRL or LCTRL2 register. This can be done by a software monitor program exe- cuted by the MCU.

  • Page 249: Ignore First Match

    Freescale Semiconductor, Inc. All bits, the software trap-enable bits and the development port trap enable bits, can be read from ICTRL and the LCTRL2 using mfspr. For the exact bits placement refer Table 8-30 Table 8-32. 8.2.2.3 Ignore First Match In order to facilitate the debugger utilities of “continue”...

  • Page 250: Development Port

    Freescale Semiconductor, Inc. Non-maskable breakpoints cause the processor to stop without regard to the state of the MSR[RI] bit. If the processor is in a non-recoverable state when the breakpoint occurs, the state of the SRR0, SRR1, and the DAR may have been overwritten by the breakpoint.

  • Page 251: Development Port Signals

    Freescale Semiconductor, Inc. L-BUS SIU/ RCPU DEV SUPPORT SPRs I-BUS BREAKPOINT LOGIC I-CACHE PORT SIU BUS DEVELOPMENT PORT CONTROL LOGIC BKPT, TE, TECR VSYNC DSCK DEVELOPMENT PORT PLLL/ SHIFT REGISTER DSDO DSDI VFLS (FRZ) Figure 8-5 Development Port Support Logic 8.3.1 Development Port Signals...
  • Page 252 Freescale Semiconductor, Inc. In clocked mode, detection of the rising edge of the synchronized clock causes the synchronized data from the DSDI pin to be loaded into the least significant bit of the shift register. This transfer occurs one quarter clock after the next rising edge of the system clock.

  • Page 253: Development Port Registers

    Freescale Semiconductor, Inc. 8.3.2 Development Port Registers The development port consists of two registers: the development port shift register and the trap enable control register. These registers are described in the following paragraphs. Figure 8-6 illustrates the development port registers and data paths.

  • Page 254: Trap Enable Control Register

    Freescale Semiconductor, Inc. When the processor is in debug mode, data is transferred to the CPU by shifting it into the shift register. The processor then reads the data as the result of executing a “move from special-purpose register DPDR” (development port data register) instruction.
  • Page 255 Freescale Semiconductor, Inc. data rate for this mode is always the same as the system clock rate, which is at least twice as fast as in synchronous clocked mode. In this mode, an undelayed CLKOUT signal must be available to the development tool, and extra care must be taken to avoid noise and crosstalk on the serial lines.
  • Page 256 Freescale Semiconductor, Inc. DSCK SYNC DSCK START LENGTH CNTRL DI<0> DSDI <N-2> <N-1> <N> SYNC START CNTRL DI<0> LENGTH <N-2> <N-1> <N> DSDI PLLL/ S<0> S<1> DO<0> READY <N-2> <N-1> <N> DSDO INT S/R DEBUG PORT DETECTS THE “START” BIT ON DSDI AND FOLLOWS THE “READY”...
  • Page 257 Freescale Semiconductor, Inc. DSCK SYNC DSCK DSDI START LENGTH CNTRL DI<0> DI<1> <-3> <N-2> <N-1> <N> SYNC START LENGTH CNTRL DI<0> DI<1> <N-3> <N-2> <N-1> <N> DSDI PLLL/ S<0> S<1> DO<0> DO<1> READY <N-2> <N-1> <N> <N-3> DSDO INT S/R DEBUG PORT DETECTS THE “START”...

  • Page 258: Development Port Transmissions

    Freescale Semiconductor, Inc. 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3...

  • Page 259: Cpu Input Transmissions

    Freescale Semiconductor, Inc. register. These seven bits are then latched into the TECR. The control bit determines whether the data is latched into the trap enable and VSYNC bits of the TECR or into the breakpoints bits of the TECR, as shown in...

  • Page 260: Serial Data Out Of Development Port - Debug Mode

    Freescale Semiconductor, Inc. Table 8-14 Status Shifted Out of Shift Register — Non-Debug Mode Ready Status [0:1] Data (7 or 32 Bits Indication Ones Sequencing Error Ones Null NOTES: 1. Depending on input mode. When the processor is not in debug mode, the sequencing error encoding indicates that the transmission from the external development tool was a transmission to the CPU (length = 0).

  • Page 261: Sequencing Error Output

    Freescale Semiconductor, Inc. fore, a status of valid data is output and the CPU exception status is saved for the next transmission. Since it is not possible for a sequencing error to occur and for valid data to be received on the same transmission, there is no conflict between a valid data sta- tus and the sequencing error status.

  • Page 262: Cpu Exception Output

    Freescale Semiconductor, Inc. 8.3.8.3 CPU Exception Output The CPU exception encoding is used to indicate that the CPU encountered an excep- tion during the execution of the previous instruction in debug mode. Exceptions may occur as the result of instruction execution (such as unimplemented opcode or arith- metic error), because of a memory access fault, or from an external interrupt.

  • Page 263: Debug Mode Functions

    Freescale Semiconductor, Inc. 8.4 Debug Mode Functions In debug mode, the CPU fetches all instructions from the development port. In addi- tion, data can be read from and written to the development port. This allows memory and registers to be read and modified by an external development tool (emulator) con- nected to the development port.

  • Page 264: Entering Debug Mode

    Freescale Semiconductor, Inc. 8.4.2 Entering Debug Mode Debug mode is entered whenever debug mode is enabled, an exception occurs, and the corresponding bit is set in the debug enable register (DER). The processor per- forms normal exception processing, (i.e., saving the next instruction address and the current state of MSR in SRR0 and SRR1 and modifying the contents of the MSR).

  • Page 265: Freeze Function

    Freescale Semiconductor, Inc. in the CPU is disabled. This forces all data accesses to the development port to occur immediately following the fetch of the associated instruction. In debug mode, if an exception occurs during the execution of an instruction, normal exception processing does not result.

  • Page 266: Development Port Transmission Sequence

    Freescale Semiconductor, Inc. Table 8-17 Checkstop State and Debug Mode Debug Action Performed MSR[ME] Mode CHSTPE MCIE when CPU Detects a ECR Value Enable Machine Check Interrupt Enter the checkstop state 0x2000 0000 Enter the checkstop state 0x2000 0000 Enter debug mode...
  • Page 267 Freescale Semiconductor, Inc. Table 8-18 Debug Mode Development Port Usage Serial Data Shifted In Shifted Out Development Port Activity; This Next (DSDO Indicates This Step Step Processor Activity “READY”) Transmission Port transfers instruction to CPU; CPU instruction CPU executes instruction, fetches next...

  • Page 268: Debug Mode Sequence Diagram

    Freescale Semiconductor, Inc. Table 8-18 Debug Mode Development Port Usage (Continued) Serial Data Shifted In Shifted Out Development Port Activity; This Next (DSDO Indicates This Step Step Processor Activity “READY”) Transmission Port transfers instruction to CPU; CPU instruction CPU executes instruction, fetches next...

  • Page 269: Port Usage In Normal (Non-Debug) Mode

    Freescale Semiconductor, Inc. CPU DATA TRAP ENABLE INSTRUCTION DATA NON DPDR INSTRUCTION DPDR WRITE INSTRUCTION ANY INSTRUCTION DPDR READ WITH EXCEPTION INSTRUCTION INSTR TRAP TRAP ENABLE ENABLE DATA DATA INSTR DATA DATA N - SHIFT OUT NULL STATUS X - SHIFT OUT EXCEPTION STATUS...

  • Page 270: Examples Of Debug Mode Sequences

    Freescale Semiconductor, Inc. 8.6 Examples of Debug Mode Sequences The tables that follow show typical sequences of instructions that are used in a devel- opment activity. They assume that no bus errors or sequence errors occur and that no writes occur to the trap enable control register.

  • Page 271: Peek Instruction Sequence

    Freescale Semiconductor, Inc. 8.6.3 Peek Instruction Sequence The peek sequence of instructions is used to read a memory location and transfer the data to the development port. It starts by moving the memory address into R1 from the development port. Next the location is read and the data loaded into R0. Finally, R0 is transferred to the development port.
  • Page 272 Freescale Semiconductor, Inc. signal. In order to enable a software monitor debugger to broadcast the fact that the debug software is now executing, it is possible to assert and negate the internal freeze signal when debug mode is disabled. (The freeze signal can be asserted externally only when the processor enters debug mode.)

  • Page 273: Development Support Registers

    Freescale Semiconductor, Inc. EVENT DECODER EVENT VALID EXCEPTION CAUSE REGISTER (ECR) DEBUG ENABLE REGISTER (DER) RESET FREEZE INTERNAL DEBUG DEBUG MODE ENABLE MODE SIGNAL Figure 8-14 Debug Mode Logic 8.8 Development Support Registers Table 8-24 lists the registers used for development support. The registers are accessed with the mtspr and mfspr instructions.

  • Page 274: Register Protection

    Freescale Semiconductor, Inc. Table 8-24 Development Support Programming Model SPR Number Mnemonic Name (Decimal) CMPA Comparator A value register CMPB Comparator B value register CMPC Comparator C value register CMPD Comparator D value register Exception cause register Debug enable register...
  • Page 275 Freescale Semiconductor, Inc. Table 8-25 Development Support Registers Read Access Protection Debug In Debug MSR[PR] Mode Result Mode Enable Read is performed. ECR is cleared when read. Reading DPDR yields indeterminate data. Read is performed. ECR is not cleared when read.

  • Page 276: Comparator A-D Value Registers (Cmpa-Cmpd)

    Freescale Semiconductor, Inc. 8.8.2 Comparator A–D Value Registers (CMPA–CMPD) CMPA–CMPD — Comparator A–D Value Register SPR 144 – SPR 147 CMPAD RESET: UNDEFINED CMPAD RESERVED RESET: UNDEFINED Table 8-27 CMPA–CMPD Bit Settings Bits Mnemonic Description 0:29 CMPAD Address bits to be compared 30:31 —...

  • Page 277: Comparator G-H Value Registers (Cmpg-Cmph)

    Freescale Semiconductor, Inc. 8.8.4 Comparator G–H Value Registers (CMPG–CMPH) CMPG–CMPH — Comparator G–H Value Registers SPR 154, 155 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
  • Page 278 Freescale Semiconductor, Inc. Table 8-30 ICTRL Bit Settings Bits Mnemonic Description Function Compare type of comparator A 0xx - not active (reset value) 100 - equal Compare type of comparator B 101 - less than Compare type of comparator C...

  • Page 279: L-Bus Support Control Register 1

    Freescale Semiconductor, Inc. Table 8-30 ICTRL Bit Settings (Continued) Bits Mnemonic Description Function 000 - RCPU is fully serialized and show cycle will be performed for all fetched instructions (reset value). 001 - RCPU is fully serialized and show cycle...
  • Page 280 Freescale Semiconductor, Inc. Table 8-31 LCTRL1 Bit Settings Bits Mnemonic Description Function Compare type, comparator E 0xx - not active (reset value) 100 - equal Compare type, comparator F 101 - less than Compare type, comparator G 110 - greater than...

  • Page 281: L-Bus Support Control Register 2

    Freescale Semiconductor, Inc. 8.8.7 L-Bus Support Control Register 2 LCTRL2 — L-Bus Support Control Register 2 SPR 157 LW0E LW0IA LW0LA LW0LD LW1E LW1IA LW1LA IADC LADC LDDC IADC RESET: LW1LD RESERVED DLW0 DLW1 SLW0 SLW1 LADC LDDC NOM- RESET:...
  • Page 282 Freescale Semiconductor, Inc. Table 8-32 LCTRL2 Bit Settings (Continued) Bits Mnemonic Description Function 2nd L-bus watchpoint 0 - don’t care LW1IADC care/don’t care I-addr events 1 - care 00 - match from comparator E 2nd L-bus watchpoint 01 - match from comparator F...

  • Page 283: Breakpoint Counter A Value And Control Register

    Freescale Semiconductor, Inc. 8.8.8 Breakpoint Counter A Value and Control Register COUNTA — Breakpoint Counter A Value and Control Register SPR 150 CNTV RESET: UNDEFINED RESERVED CNTC RESET: Table 8-33 Breakpoint Counter A Value and Control Register (COUNTA) Bit(s) Name...

  • Page 284: Exception Cause Register (Ecr)

    Freescale Semiconductor, Inc. Table 8-34 Breakpoint Counter B Value and Control Register (COUNTB) Bit(s) Name Description 0:15 CNTV Counter preset value 16:29 — Reserved Counter source select 00 - not active (reset value) 30:31 CNTC 01 - I-bus second watchpoint...

  • Page 285: Debug Enable Register (Der)

    Freescale Semiconductor, Inc. Table 8-35 ECR Bit Settings Bit(s) Name Description — Reserved CHSTP Checkstop bit. Set when the processor enters checkstop state. Machine check interrupt bit. Set when a machine check exception (other than one caused by a data storage or instruction storage error) is asserted.
  • Page 286 Freescale Semiconductor, Inc. DER — Debug Enable Register SPR 149 RESERVED MCEE DSEE ISEE EXTIE ALEE PREE FPU- RESERVED FPA- STPE RESET: SEEE RESERVED LBRK IBRKE EBRK DPIE RESET: Table 8-36 DER Bit Settings Bit(s) Name Description — Reserved Checkstop enable bit...
  • Page 287 Freescale Semiconductor, Inc. Table 8-36 DER Bit Settings (Continued) Bit(s) Name Description 11:12 — Reserved System call exception enable bit SYSEE 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Trace exception enable bit 0 = Debug mode entry disabled...
  • Page 288 Freescale Semiconductor, Inc. MPC509 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL Revised 15 July 1999 8-60 For More Information On This Product, Go to: www.freescale.com...

  • Page 289: Ieee 1149.1-Compliant Interface

    Freescale Semiconductor, Inc. SECTION 9 IEEE 1149.1-COMPLIANT INTERFACE The MPC509 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).

  • Page 290: Jtag Signal Descriptions

    Freescale Semiconductor, Inc. CLOCK-IR SHIFT-IR UPDATE-IR RESET TRST INSTRUCTION REGISTER [4 BITS] IR DECODER BOUNDARY SCAN REGISTER [TBD BITS] DEVICE ID REGISTER [32 BITS] BYPASS REGISTER [1 BIT] TEST DATA REGISTERS Figure 9-2 Test Logic Block Diagram 9.2 JTAG Signal Descriptions...

  • Page 291: Operating Frequency

    Freescale Semiconductor, Inc. Table 9-1 JTAG Interface Pin Descriptions Internal Pull-Up/ Signal Name Input/Output Pulldown Provid- Description Test data input pin. Sampled on the rising edge of TCK. Input Pull-up Has pull-up resistor. Test data output pin. Actively driven during the shift-IR...

  • Page 292: Extest (0000)

    Freescale Semiconductor, Inc. Table 9-2 Instruction Register Encoding Code Instruction BYPASS SAMPLE/PRELOAD IDCODE TMSCAN Reserved Reserved CLAMP HIGHZ EXTEST_PULLUP EXTEST The parallel output of the instruction register is reset to 1101 in the test-logic-reset con- troller state. NOTE This preset state is equivalent to the IDCODE instruction. In the cap- ture-IR state, 1101 is loaded into the instruction shift register stage.

  • Page 293: Bypass (1111)

    Freescale Semiconductor, Inc. CHIP 2 CHIP 1 EXTEST INSTR. SAMPLE INSTR. Figure 9-3 Sample EXTEST Connection The following steps show an example of how the EXTEST instruction is initialized and invoked for board interconnection test. 1. Shift in the PRELOAD instruction in chip 1.

  • Page 294: Sample/Preload (1110)

    Freescale Semiconductor, Inc. 9.5.3 SAMPLE/PRELOAD (1110) The SAMPLE/PRELOAD instruction enables the boundary scan register between TDI and TDO as test data register. When this instruction is selected, the operation of the test logic shall have no effect on the operation of the on-chip system logic or on the flow of signal between the system pin and the on-chip system logic as required in the 1149.1 specification.

  • Page 295: Highz (0010)

    Freescale Semiconductor, Inc. The CLAMP instruction performs the same task as the EXTEST instruction. Unlike the EXTEST instruction, however, once the data in the boundary scan cell is updated, it remains unchanged until a new instruction is shifted in or reset.

  • Page 296: Idcode (1101)

    Freescale Semiconductor, Inc. • Traverse into the Run-Test/Idle state for extra TCK periods of charging delay; or • Limit the maximum TCK frequency (slow down the TCK) so that two TCK periods are adequate 9.5.7 IDCODE (1101) The IDCODE enables the IDREGISTER between TDI and TDO as test data register.

  • Page 297: Non-Ieee 1149.1-1990 Operation

    Freescale Semiconductor, Inc. ment to avoid device-destructive configurations. The user must avoid situations in which the MPC509 output drivers are enabled into actively driven networks. 9.7 Non-IEEE 1149.1-1990 Operation In non-IEEE 1149.1-1990 operation, the IEEE 1149.1-1990 test logic must be kept transparent to the system logic by forcing the TAP controller into the Test-Logic-Reset controller state and keeping it there.
  • Page 298 Freescale Semiconductor, Inc. BDIP_L: inout bit; ARETRY_L: inout bit; CR_L: inout bit; ECROUT: buffer bit; CLKOUT: buffer bit; SRESET_L: buffer bit; RESET_L: bit; IRQ_L: inout bit_vector(0 to 6); DSCK: bit; DSDI: bit; MODCK: bit; inout bit_vector(0 to 5); VFLS: inout bit_vector(0 to 1);...
  • Page 299 Freescale Semiconductor, Inc. constant XX_Package : PIN_MAP_STRING := “VSSE: ( 1, 13, 29, 60, 74, 81, 95, 107, 120, 127, 137, 153 ), “ & “VDDE: ( 160, 14, 26, 61, 75, 80, 94, 106, 121, 126, 136, 152 ), “...
  • Page 300 Freescale Semiconductor, Inc. 115, 116, 117, “ & “ 118, 119, 122, 123, 124, 125, 128, 129, 130, 131, 132, 133, 134, 135, “ & “ 138, 139, 140, 141 ), “ & “BB_L: 144, “ & “BG_L: 145, “...
  • Page 301 Freescale Semiconductor, Inc. -- cell = BC_4 for inputs, BC_6 for bidirectionals, BC_2 all other -- function = input = input only bidir = directional controlr = control with jtag_reset output2 = output two state (0 1) -- safe =...
  • Page 302 Freescale Semiconductor, Inc. “38 (BC_2, CSBOOT_L, output2, X), “ & “39 (BC_6, CS(0), bidir, Z), “ & --num cell port function safe ccell dsval rslt “40 (BC_2, *, controlr, 0), “ & “41 (BC_6, CS(1), bidir, Z), “ & “42 (BC_2, *, controlr, 0), “...
  • Page 303 Freescale Semiconductor, Inc. “90 (BC_2, *, controlr, 0), “ & “91 (BC_6, D(25), bidir, Z), “ & “92 (BC_2, *, controlr, 0), “ & “93 (BC_6, D(24), bidir, Z), “ & “94 (BC_2, *, controlr, 0), “ & “95 (BC_6, D(23), bidir, Z), “...
  • Page 304 Freescale Semiconductor, Inc. “142 (BC_2, *, controlr, 0), “ & “143 (BC_6, A(29), bidir, 144, Z), “ & “144 (BC_2, *, controlr, 0), “ & “145 (BC_6, A(28), bidir, 146, Z), “ & “146 (BC_2, *, controlr, 0), “ &...
  • Page 305 Freescale Semiconductor, Inc. “195 (BC_6, WP(0), bidir, 196, Z), “ & “196 (BC_2, *, controlr, 0), “ & “197 (BC_6, WP(1), bidir, 198, Z), “ & “198 (BC_2, *, controlr, 0), “ & “199 (BC_6, WP(2), bidir, 200, Z), “...
  • Page 306 Freescale Semiconductor, Inc. MPC509 IEEE 1149.1-COMPLIANT INTERFACE MOTOROLA REFERENCE MANUAL Revised 15 July 1999 9-18 For More Information On This Product, Go to: www.freescale.com...

  • Page 307: Mpc509 Electrical Characteristics

    Freescale Semiconductor, Inc. APPENDIX A MPC509 ELECTRICAL CHARACTERISTICS Click here for the MPC509L3C25 electrical characteristics. Click here for the MPC509L3M25 electrical characteristics. MPC509 MPC509 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 For More Information On This Product, Go to: www.freescale.com...
  • Page 308 Freescale Semiconductor, Inc. MPC509 MPC509 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 For More Information On This Product, Go to: www.freescale.com...
  • Page 309 Freescale Semiconductor, Inc. APPENDIX A MPC509L3C25 ELECTRICAL CHARACTERISTICS The MPC509L3C25 is the first implementation of the PowerPC™ family of reduced instruction set computer (RISC) microprocessors designed for embedded control. This document contains pertinent physical characteristics of the MPC509L3C25. For func-...
  • Page 310 Freescale Semiconductor, Inc. A.2 MPC509L3C25 Features Major features of the MPC509L3C25 are as follows: • High-performance, embedded control microprocessor — As many as four instructions in execution per clock (one to each of the four execution units) — Single clock cycle execution for most instructions —...
  • Page 311 Freescale Semiconductor, Inc. Table A-2 . DC Electrical Characteristics Characteristic Notes Symbol Unit Supply voltage Input high voltage .75 * V + 0.3 EXTAL TTL-compatible inputs – 0.3 0.3 * V Input low voltage Output high voltage =-100 µA * –...
  • Page 312 Freescale Semiconductor, Inc. Table A-2 . DC Electrical Characteristics (Continued) Characteristic Notes Symbol Unit µA @ 125°C -2.5 Hi-Z (off-state) leakage current Capacitance (see Note)* — = 0 V, f = 1 MHz supply current — RUN @ 24 MHz —...
  • Page 313 Freescale Semiconductor, Inc. A.3.2.1 Input AC Characteristics Table A-3 provides the clock AC timing specifications for the MPC509L3C25 as defined in Figure A-1. Table A-3 . Clock AC Timing Specifications MAX = 125° C, θ = 3.3 Vdc ± 0.3, GND = 0 Vdc, T = 37°...
  • Page 314 Freescale Semiconductor, Inc. Figure A-1 Clock Input Timing Diagram Table A-4 : MPC509L3C25 Input AC Timing Specifications (V CC = 3.3 ± 0.3 V dc , GND = 0 V dc ). See Figure A-2. 25 Mhz Characteristic Symbol Unit...
  • Page 315 Freescale Semiconductor, Inc. Table A-4 : MPC509L3C25 Input AC Timing Specifications (Continued) (V CC = 3.3 ± 0.3 V dc , GND = 0 V dc ). See Figure A-2. 25 Mhz Characteristic Symbol Unit Input hold — DSCK & DSDI Ports —...
  • Page 316 Freescale Semiconductor, Inc. Table A-5 : MPC509L3C25 Output AC Timing Specifications (Continued) (V CC = 3.3 ± 0.3 V dc , GND = 0 V dc ) See Figure A-2. 25 Mhz Characteristic Symbol Unit CLK to CS_BOOT, A1:A5 output hold (configured as a chip —...
  • Page 317 Freescale Semiconductor, Inc. 6-10 11-15 INPUT INPUTS 16-25 OUTPUTS OUTPUT 26-35 Figure A-2 Input Timing Diagram Table A-6 JTAG AC Timing Characteristics (Independent of CLK) Characteristic Unit TCK frequency of operation (0 MHz not tested) TCK cycle time — TCK clock pulse width measured at 2.0 V 62.5...
  • Page 318 Freescale Semiconductor, Inc. Figure A-3 JTAG Clock Input Timing Diagram TRST Figure A-4 TRST Timing Diagram DATA INPUTS DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS Figure A-5 Boundary Scan Timing Diagram MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999...
  • Page 319 Freescale Semiconductor, Inc. Figure A-6 Test Access Port Timing Diagram MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 320 Freescale Semiconductor, Inc. A.4 Timing Examples A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-7 Fastest Single Beat Read MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-12 For More Information On This Product,...
  • Page 321 Freescale Semiconductor, Inc. A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-8 Fastest Single Beat Writes MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 322 Freescale Semiconductor, Inc. A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-9 Single-Beat Reads Showing Data-Delay Controls MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-14 For More Information On This Product, Go to: www.freescale.com...
  • Page 323 Freescale Semiconductor, Inc. A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-10 Single-Beat Writes Showing Data Delay Controls MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-15 For More Information On This Product,...
  • Page 324 Freescale Semiconductor, Inc. 9 10 11 12 13 14 15 16 17 A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 In 0 In 1 In 2 In 3 In 0 In 1 In 2 In 0 In 1...
  • Page 325 Freescale Semiconductor, Inc. A.5 MPC509L3C25 Pinout VSSE9 VSSE0 DATA15 ADDR5/CS5 DATA14 ADDR4/CS4 DATA13 ADDR3/CS3 DATA12 ADDR2/CS2 DATA11 ADDR1/CS1 DATA10 ADDR0/CS0 DATA9 CSBOOT DATA8 DATA7 DATA6 DATA5 DATA4 VSSE1 VSSE8 VDDE1 VDDE8 DATA3 DATA2 DATA1 DATA0 VSSIL VSSIR VDDIL MPC509L3C25 VDDIR...
  • Page 326 Freescale Semiconductor, Inc. MPC509L3 MPC509L3C25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-18 For More Information On This Product, Go to: www.freescale.com...
  • Page 327 Freescale Semiconductor, Inc. APPENDIX A MPC509L3M25 ELECTRICAL CHARACTERISTICS The MPC509L3M25 is the first implementation of the PowerPC™ family of reduced instruction set computer (RISC) microprocessors designed for embedded control. This document contains pertinent physical characteristics of the MPC509L3M25. For func-...
  • Page 328 Freescale Semiconductor, Inc. A.2 MPC509L3M25 Features Major features of the MPC509L3M25 are as follows: • High-performance, embedded control microprocessor — As many as four instructions in execution per clock (one to each of the four execution units) — Single clock cycle execution for most instructions —...
  • Page 329 Freescale Semiconductor, Inc. Table A-2 . DC Electrical Characteristics Characteristic Notes Symbol Unit Supply voltage Input high voltage .75 * V + 0.3 EXTAL TTL-compatible inputs – 0.3 0.3 * V Input low voltage Output high voltage =-100 µA * –...
  • Page 330 Freescale Semiconductor, Inc. Table A-2 . DC Electrical Characteristics (Continued) Characteristic Notes Symbol Unit µA @ 125°C -2.5 Hi-Z (off-state) leakage current Capacitance (see Note)* — = 0 V, f = 1 MHz supply current — RUN @ 24 MHz —...
  • Page 331 Freescale Semiconductor, Inc. A.3.2.1 Input AC Characteristics Table A-3 provides the clock AC timing specifications for the MPC509L3M25 as defined in Figure A-1. Table A-3 . Clock AC Timing Specifications MAX = 125° C, θ = 3.3 Vdc ± 0.3, GND = 0 Vdc, T = 37°...
  • Page 332 Freescale Semiconductor, Inc. Figure A-1 Clock Input Timing Diagram Table A-4 : MPC509L3M25 Input AC Timing Specifications (V CC = 3.3 ± 0.3 V dc , GND = 0 V dc ). See Figure A-2. 25 Mhz Characteristic Symbol Unit...
  • Page 333 Freescale Semiconductor, Inc. Table A-4 : MPC509L3M25 Input AC Timing Specifications (Continued) (V CC = 3.3 ± 0.3 V dc , GND = 0 V dc ). See Figure A-2. 25 Mhz Characteristic Symbol Unit Input hold — DSCK & DSDI Ports —...
  • Page 334 Freescale Semiconductor, Inc. Table A-5 : MPC509L3M25 Output AC Timing Specifications (Continued) (V CC = 3.3 ± 0.3 V dc , GND = 0 V dc ) See Figure A-2. 25 Mhz Characteristic Symbol Unit CLK to CS_BOOT, A1:A5 output hold (configured as a chip —...
  • Page 335 Freescale Semiconductor, Inc. 6-10 11-15 INPUT INPUTS 16-25 OUTPUTS OUTPUT 26-35 Figure A-2 Input Timing Diagram Table A-6 JTAG AC Timing Characteristics (Independent of CLK) Characteristic Unit TCK frequency of operation (0 MHz not tested) TCK cycle time — TCK clock pulse width measured at 2.0 V 62.5...
  • Page 336 Freescale Semiconductor, Inc. Figure A-3 JTAG Clock Input Timing Diagram TRST Figure A-4 TRST Timing Diagram DATA INPUTS DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS Figure A-5 Boundary Scan Timing Diagram MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999...
  • Page 337 Freescale Semiconductor, Inc. Figure A-6 Test Access Port Timing Diagram MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-11 For More Information On This Product, Go to: www.freescale.com...
  • Page 338 Freescale Semiconductor, Inc. A.4 Timing Examples A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-7 Fastest Single Beat Read MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-12 For More Information On This Product,...
  • Page 339 Freescale Semiconductor, Inc. A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-8 Fastest Single Beat Writes MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-13 For More Information On This Product, Go to: www.freescale.com...
  • Page 340 Freescale Semiconductor, Inc. A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-9 Single-Beat Reads Showing Data-Delay Controls MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-14 For More Information On This Product, Go to: www.freescale.com...
  • Page 341 Freescale Semiconductor, Inc. A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 Figure A-10 Single-Beat Writes Showing Data Delay Controls MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-15 For More Information On This Product,...
  • Page 342 Freescale Semiconductor, Inc. 9 10 11 12 13 14 15 16 17 A0–A31 CPU A CPU A CPU A Burst AACK ARTRY D0–D31 In 0 In 1 In 2 In 3 In 0 In 1 In 2 In 0 In 1...
  • Page 343 Freescale Semiconductor, Inc. A.5 MPC509L3M25 Pinout VSSE9 VSSE0 DATA15 ADDR5/CS5 DATA14 ADDR4/CS4 DATA13 ADDR3/CS3 DATA12 ADDR2/CS2 DATA11 ADDR1/CS1 DATA10 ADDR0/CS0 DATA9 CSBOOT DATA8 DATA7 DATA6 DATA5 DATA4 VSSE1 VSSE8 VDDE1 VDDE8 DATA3 DATA2 DATA1 DATA0 VSSIL VSSIR VDDIL MPC509L3M25 VDDIR...
  • Page 344 Freescale Semiconductor, Inc. MPC509L3M25 MPC509L3M25 ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL Revised 15 July 1999 A-18 For More Information On This Product, Go to: www.freescale.com...
  • Page 345 Freescale Semiconductor, Inc. INDEX –A– Branch prediction 3-5 AACK 2-12, 5-13, 5-21, 5-51, 5-52 processing unit 3-5 ACKEN 5-45, 5-51 trace enable 3-19 Acknowledge enable 5-45, 5-51 Breakpoint counter A value and control register 8-55 ADDR 2-10, 5-13, 5-20 Breakpoint counter B value and control register 8-55...
  • Page 346 Freescale Semiconductor, Inc. CGBMSK 8-52 CS 2-19, 5-37 Charge pump 5-75 CSBAR 5-41 CHBMSK 8-52 CSBOOT 2-19, 5-37 Checkstop reset 5-29, 5-50, 5-96 base address 5-69 enable 5-5 sub-blocks 5-49 Checkstop state CSBTBAR 5-41 and debug mode 8-37 CSBTOE 5-37 Chip enable.
  • Page 347 Freescale Semiconductor, Inc. and freeze assertion 5-12 Enabling debug mode 8-35 clock enable 5-84, 5-86 Engineering clock reference. See ECROUT register 3-21 Entering debug mode 8-36 DER 8-57 EP bit 3-19 Development Exception cause register 8-56 serial clock. See DSCK Exception prefix 3-19, 5-41, 5-48 serial data in.
  • Page 348 Freescale Semiconductor, Inc. summary 3-12 IEN 5-7 less than or negative 3-12 IEN bit 4-4 overflow exception 3-12 Ignore first match 8-50 enable 3-13 IIFM 8-50 registers 3-10 IMEMBASE 5-7, 5-10 result class descriptor 3-12 IMUL–IDIV 3-5 result flags 3-12...
  • Page 349 Freescale Semiconductor, Inc. IRQENABLE 6-9, 6-10 select bits 5-86 IRQMUX 6-3, 6-8 LPM 5-80, 5-86 IRQPEND 6-9 LPML 5-80, 5-82, 5-88 ISCTL 5-31, 8-1 LPMM 5-81, 5-86 ISE 8-57 LR 3-5, 3-16 ISEE 8-58 LSHOW 5-6 ITYPE 5-46, 5-54, 5-56...
  • Page 350 Freescale Semiconductor, Inc. base address register. See SPECADDR PITIRQL 5-92 mask register. See SPECMASK PITQIL 6-9, 6-10 NRI 3-24 PJ 2-22 Null output encoding 8-34 PJPAR 5-111 PK 2-22 –O– PKPAR 5-111 PL 2-22 OE 5-36, 5-56 PLL 5-74 OE bit 3-13 lock signal.
  • Page 351 Freescale Semiconductor, Inc. back 8-8 –S– in debug mode 8-6 S0 7-4 window 8-8 SAMPLE/PRELOAD 9-6 PRU mode 5-106, 5-113 SBLK 5-45, 5-48 PS 5-46, 5-52, 5-89, 5-92, 5-93 SCCR 5-85 PTE 5-89, 5-92, 5-93 SCLSR 5-87 PVR 3-23 SE bit 3-19 –Q–...
  • Page 352 Freescale Semiconductor, Inc. two-cycle mode 7-4 data input 9-3 SRAMMCR 7-3 data output 9-3 SRR0 3-22 mode select 9-3 SRR1 3-22 reset 9-3 Static RAM. See SRAM Time base 3-17, 5-83 STME 5-88 Time-out period, PIT 5-91 STMS 5-88 Timing, instruction 3-34...
  • Page 353 Freescale Semiconductor, Inc. Watchpoint signals. See WP Watchpoints 8-11 WE 5-36 Window trace 8-8 WP 2-18, 5-45, 5-51 WR 2-10, 5-13, 5-20 Write cycle 5-17 Write enable. See WE Write protection 5-45, 5-51 Write/read signal. See WR WUR 5-82, 5-88 –X–...
  • Page 354 Freescale Semiconductor, Inc. MPC509 INDEX MOTOROLA REFERENCE MANUAL Revised 15 July 1999 Index-10 For More Information On This Product, Go to: www.freescale.com...

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