Freescale Semiconductor MPC5565 Reference Manual

page of 1153

/ 1153
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

Freescale Semiconductor

MPC5565 Microcontroller

Reference Manual

This MPC5565 Reference Manual set consists of the following files:

•

MPC5565 Reference Manual Addendum, Rev 1

•

MPC5565 Microcontroller Reference Manual, Rev 2

MPC5565RM

Rev. 1.1, 05/2012

Table of Contents

Chapters

Table of Contents

Need help?

Do you have a question about the MPC5565 and is the answer not in the manual?

Questions and answers

Summary of Contents for Freescale Semiconductor MPC5565

Page 1 Freescale Semiconductor MPC5565RM Rev. 1.1, 05/2012 MPC5565 Microcontroller Reference Manual This MPC5565 Reference Manual set consists of the following files: • MPC5565 Reference Manual Addendum, Rev 1 • MPC5565 Microcontroller Reference Manual, Rev 2 © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 2 Manual, order number MPC5565RM. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5565 Microcontroller Reference Manual is Revision 1.0. © Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Page 3 Transmit Complete flag is not used. DMA Request Channel Source Description eSCIA_COMBTX ESCIA.SR[TDRE] || eSCIA combined DMA ESCIA.SR[TC] || request of the Transmit ESCIA.SR[TXRDY] Data Register Empty and LIN Transmit Data Ready DMA requests MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 4: Mpc5565 Reference Manual Addendum, Rev
Addresses”/Page A-1 PBRIDGE_A, PBRIDGEB becomes PBRIDGE_B). Only two rows of the table are changed. Module Base Address Page Peripheral Bridge A (PBRIDGE_A) 0xC3F0_0000 Page A-2 Peripheral Bridge B (PBRIDGE_B) 0xFFF0_0000 Page A-31 MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 5 Peripheral bridge A off-platform PBRIDGE_A_OPACR1 32-bit Base + 0x0044 peripheral access control register 1 Peripheral bridge A off-platform PBRIDGE_A_OPACR2 32-bit Base + 0x0048 peripheral access control register 2 Reserved — — Base + (0x004C- 0xC3F7_FFFF) MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 6 Peripheral bridge B off-platform PBRIDGE_B_OPACR2 32-bit Base + 0x0048 peripheral access control register 2 Peripheral bridge B off-platform PBRIDGE_B_OPACR3 32-bit Base + 0x004C peripheral access control register 3 Reserved — — (Base + 0x0050)- 0xFFF0_3FFF) MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 7 Addendum for Revision 1.0 Table 1. MPC5565RM Rev 1.0 addendum (continued) Location Description Figure 16-13,” Unified Reverse the arrow between the "Programmable Filter" and "Edge Detect". Channel Block Diagram”/Page 16-26 MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 8 Addendum for Revision 1.0 Table 1. MPC5565RM Rev 1.0 addendum (continued) Location Description Section13.3/ Page 13-4 Remove cross-reference to Table 13-2. Add the following table and update the cross-reference. MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 9 Interrupt Reserved Section 9.3.1, “eDMA In the Memory controller sub-bullet, delete the line "The hooks to a BIST controller for the local Microarchitecture”/ Page TCD memory are included in this module". 9-29 MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 10 Instruction or Machine check interrupt (IVOR1). data Data Data storage interrupt (IVOR2). External interrupt must be enabled. Machine check can be enabled or disabled. Instruction Instruction storage interrupt (IVOR3). MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 11 01: Replace the term “Invalid value” with “No Trigger” • Bit 30-31–TRIGSELD: Correct the input select description as follows 00: Replace the term “Invalid value” with “No Trigger” 01: Replace the term “Invalid value” with “No Trigger” MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 12 • In software vector mode, the INTC_IACKR must not be read speculatively. • In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before the interrupt acknowledge signal from the processor asserts. MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 13 The example is for software vector mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the processor, hardware vector mode is identical. MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 14 LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop from LIFO is the priority from before peripheral interrupt request 100 interrupted. ISR108 now can access data block coherently after interrupt exception handler executes rfi instruction. MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 15 PLLCFG[2] high. This sets the default predivider (PREDIV) to 0b001. After reset, PREDIV must not be configured to a value less than divide-by-2 (with a 40 MHz crystal/reference).” MPC5565 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 16 • Clarified note in the INTC Interrupt Acknowledge Register . • Added a note in the INTC Memory Map table. • Clarified note at the end of the MPC5565 Interrupt Request Sources table. • Added a paragraph to the Section 10.4.2.1.4, “Priority Comparator Submodule”.
Page 17 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
Page 18 MPC5565 Microcontroller Reference Manual Devices Supported: MPC5565 MPC5565 RM Rev. 1.0 09/2007...
Page 19 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor Hong Kong Ltd.
Page 20: Table Of Contents
Deserial/Serial Peripheral Interface (DSPI) Signals ......2-26 2.3.8 Enhanced Queued A/D Controller (eQADC) Signals ..... . . 2-29 MPC5565 Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 21 Weak Pull Configuration (WKPCFG) ........4-3 MPC5565 Reference Manual, Rev. 1.0...
Page 22 Document Revision History ........... 6-120 MPC5565 Reference Manual, Rev. 1.0...
Page 23 DMA Programming Errors ..........9-37 MPC5565 Reference Manual, Rev. 1.0...
Page 24 11.2 External Signal Description ........... 11-12 MPC5565 Reference Manual, Rev. 1.0...
Page 25 Flash Memory Map ..........13-5 MPC5565 Reference Manual, Rev. 1.0...
Page 26 16.3 Memory Map/Register Definition ..........16-6 MPC5565 Reference Manual, Rev. 1.0...
Page 27 MPC5565 eTPU Implementation ........
Page 28 Memory Map ............19-8 MPC5565 Reference Manual, Rev. 1.0...
Page 29 20.5 Document Revision History ........... 20-41 MPC5565 Reference Manual, Rev. 1.0...
Page 30 22.6 Document Revision History ........... . 22-8 MPC5565 Reference Manual, Rev. 1.0...
Page 31 24.7 NPC Functional Description ..........24-17 MPC5565 Reference Manual, Rev. 1.0...
Page 32 24.15 Document Revision History ........... 24-92 MPC5565 Reference Manual, Rev. 1.0...
Page 33 B.3 Device-Specific Information ........... . 2-4 B.3.1 MPC5565 Calibration Bus Implementation ....... . . 2-4 B.4 Signals and Pads .
Page 34 MPC5565 Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 35: Mpc5565 Reference Manual, Rev
MPC5565 Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 36: Mpc5565 Microcontroller Reference Manual, Rev
(DSP) instructions, beyond the classic PowerPC instruction set. The MPC5565 has two levels of memory hierarchy. The fastest accesses are to the 8 KB unified cache. The next level in the hierarchy contains up to 80 KB of internal SRAM and 2 MB flash memory. Both the internal SRAM and the flash memory can hold instructions and data.
Page 37: Rev.
Introduction Figure 1-1 is a block diagram of the MPC5565. e200z6e core Core registers Master Slave GPRs (64-bits) Internal Slave Integer SRAM SPRs execution 80 KB unit Master Unified Slave 8-KB Flash Multiply cache 2 MB unit Instruction unit Timer unit...
Page 38: Rev.
Introduction Features This section provides a high-level description of the features found in the MPC5565. • Operating parameters — Fully static operation, up to 132 MHz — –40 to 150 °C junction temperature — Low-power design – Less than 1.2 Watts power dissipation –...
Page 39 – Conversion instructions between single precision floating point and fixed point — Long cycle time instructions, except for guarded loads, do not increase interrupt latency in the MPC5565; to reduce latency, long cycle time instructions are aborted upon interrupt requests — Extensive system development support through Nexus debug module •...
Page 40 Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF • Calibration bus interface — Calibration bus interface only accessible through 496-pin VertiCal assembly top connector — 1.8–3.3 V nominal I/O voltage MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 41 — 80 KB general-purpose SRAM of which 32 KB are on standby power — ECC performs single-bit correction, double-bit error detection • Boot assist module (BAM) — Enables and manages the transition of MCU from reset to user code execution in the following configurations: MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 42 — Serial peripheral interface (SPI) – Full duplex communication ports with interrupt and eDMA request support – Supports all functional modes from QSPI submodule of QSMCM (MPC5xx family) – Support for queues in RAM MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 43 — Data trace of eDMA accesses — Read and write access — Configured via the IEEE® 1149.1 (JTAG) port — High-bandwidth mode for fast message transmission — Reduced bandwidth mode for reduced pin usage MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 44: Mpc5500 Family Comparison
Provides initial reset condition up to the voltage at which pins (RESET) can be read safely; it does not guarantee the safe operation of the chip at specified minimum operating voltages MPC5500 Family Comparison The following table compares the product features of the MPC5554 and the MPC5565: Table 1-1. MPC5500 Product Family Comparison MPC5500 Device Feature...
Page 45 32-byte flash page size for programming EBI limited to a 16-bit data bus on the 324 package Select either ADDR[8:31] or ADDR[6:29] to configure a 24-bit address bus Updated FlexCAN module with optional individual receive filters MPC5565 Microcontroller Reference Manual, Rev. 1.0 1-10 Freescale Semiconductor...
Page 46: Detailed Features
Power Architecture technology. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 1-11...
Page 47: System Bus Crossbar Switch (Xbar)
SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is used to minimize the overall module size. MPC5565 Microcontroller Reference Manual, Rev. 1.0 1-12 Freescale Semiconductor...
Page 48: Interrupt Controller (Intc)
EBI but the two buses use separate pads. The calibration bus memory controller supports single data rate (SDR) non-burst mode flash, SRAM, and asynchronous memories. In addition, the bus supports up to MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 49: System Integration Unit (Siu)
1.4.10 Flash Memory The MPC5565 provides 2 MB of programmable, non-volatile, flash memory storage. Non-volatile memory (NVM) can be used for instruction and/or data storage. The flash memory has a flash bus interface unit (FBIU) that connects the system bus to a dedicated flash memory array controller.
Page 50: Static Ram (Sram)
RAM to form a powerful time processing subsystem. The MPC5565 has one eTPU engine. High-level assembler/compiler and documentation can be used to develop customized functions for the eTPU. The eTPU supports several features of older TPU versions, making it easy to port older applications.
Page 51: Enhanced Queued A/D Converter (Eqadc)
The channels and register content are transmitted using a SPI-like protocol. The MPC5565 has three DSPI modules (B, C, and D). The DSPIs have three configurations: • Serial peripheral interface (SPI) configuration where the DSPIs operate as serial ports only with support for queues.
Page 52: Nexus Development Interface (Ndi)
Under software control of the MMU, the logical addresses allocated to modules can be changed on a minimum of a 4 KB boundary. Peripheral modules may be redundantly mapped. The customer must use the MMU to prevent corruption. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 1-17...
Page 53 Introduction Table 1-2 shows an overview of the device memory map. It is intended to illustrate how the crossbar switch integrates into the memory map. Table 1-2. MPC5565 Memory Map (Single-Chip or Single-Master Mode) Base Address XBAR Slave Port ADDR[0:2]...
Page 54 Introduction Table 1-3. MPC5565 Detailed Memory Map (continued) Allocated Size Used Size Address Range (Bytes) (Bytes) 0x4000_8000–0x4001_3FFF 48 KB 48 KB Internal SRAM array 0x4001_4000–0xBFFF_FFFF 2048 MB–80 KB Reserved (total SRAM) Bridge A Peripherals 0xC000_0000–0xC3EF_FFFF 63 MB Reserved 0xC3F0_0000–0xC3F0_3FFF 16 KB —...
Page 55 Introduction Table 1-3. MPC5565 Detailed Memory Map (continued) Allocated Size Used Size Address Range (Bytes) (Bytes) 0xFFF4_C000–0xFFF4_FFFF 16 KB Reserved 0xFFF5_0000–0xFFF7_FFFF 192 KB Reserved 0xFFF8_0000–0xFFF8_3FFF 16 KB Enhanced queued analog-to-digital converter (eQADC) 0xFFF8_4000–0xFFF8_FFFF 48 KB Reserved 0xFFF9_0000–0xFFF9_3FFF 16 KB Reserved 0xFFF9_4000–0xFFF9_7FFF...
Page 56: Multi-Master Operation Memory Map
MCU acting as a slave in a multi-master system from the point of view of the external master. Table 1-5. MPC5565 Family Slave Memory Map as Seen from an External Master External Address Range...
Page 57: Revision History
MPC5554 (Copperhead) for comparison. Removed footnote 4: Select either ADDR[8:31] or ADDR[6:29] to configure a 24-bit address bus from the 32-bit EBI data bus row and added it on the address bus row. Added footnote 5 to the MPC5565 EBI data bus row that reads: The EBI is limited to a 16-bit data bus on the 324 package.
Page 58: Block Diagram
Array (BGA) map are listed in Table 2-2. The 324 package has a limited number of balls which affects the following signals and features: Table 2-1. MPC5565 324 Package Limitations Feature Signals MPC5565 Design 324 Package ADDR[8:11]_GPIO[4:7] no balls available.
Page 59 Table 2-1 for a list of the signals that are not supported CAL_WE/BE[0:1] on the 324 package. CAL_OE The calibration signals only function when using the VertiCal assembly. CAL_TS Figure 2-1. MPC5565 Signals MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 60: External Signal Descriptions
1-bit Primary The main function is used for device Alternate 2-bits compatibility. Main Second alternate 3-bits > 4 All other values reserved for future use. Figure 2-3. Understanding the P/A/G Column Entries MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 61 External address bus Y2, Y1, AD2, – / Up – / Up DDE2 GPIO[23:25] GPIO AD3, AD1 ADDR[30:31]_ External address bus W3, V4 – / Up – / Up AF2, AE3 DDE2 GPIO[26:27] GPIO MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 62 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly AG11, AF12, AG13, AH13, AB4, AA5, AG14, AB5, AB6, AH15, AB7, AA8, AG15, DATA[0:15]_ External data bus AB8, AA9, –...
Page 63 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly WE/BE[0:1]_ External write/byte enable – / Up – / Up N4, N3 U5, T5 DDE2 GPIO[64:65] GPIO...
Page 64 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly AA17, AB16, AA18, 13, 16 CAL_DATA[8:13] Calibration data bus – / Up – / Up — DDE12...
Page 65 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly CNRXB_ FlexCAN B receive PCSC[4]_ DSPI C peripheral chip select – / Up – / Up AB19...
Page 66 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly SCKB_ DSPI B clock PCSC[1]_ DSPI C peripheral chip select – / Up – / Up DDEH10...
Page 67 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly AN[11]_ Single-ended analog input I / – AN[11] / – DDA1 External multiplexed analog input AN[12]_ Single-ended analog input...
Page 68 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly ETPUA[6]_ eTPU A channel – / – / ETPUA[18]_ eTPU A channel (output only) DDEH1 WKPCFG WKPCFG...
Page 69 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly ETPUA[23] eTPU A channel – / – / IRQ[11] External interrupt request DDEH1 WKPCFG WKPCFG GPIO[137] GPIO...
Page 70 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly EMIOS[17]_ eMIOS channel – / – / AF19 DDEH4 GPIO[196] GPIO WKPCFG WKPCFG EMIOS[18]_ eMIOS channel – / –...
Page 71 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly B25, C2, D3, D27, F5, H7, J8, Y21, A2, A20, AA9, B3, C4, AA22, C22, D5, AB8, Internal logic supply input 1.5 V...
Page 72 Signal Description Table 2-2. MPC5565 Signal Properties (continued) Status During After VertiCal Signal Names Signal Functions Type Voltage Type Reset Reset Package assembly K7, N8, R11:13, R17:18, R21, T11:12, T15, T18, U2, U11, U15:16, – External I/O supply input 1.8–3.3 V —...
Page 73 AG17 Because more than one signal is often multiplexed to one pin, each line in the signal name column is a separate function. For all MPC5565 I/O pins the selection of the primary pin function, alternate function, or GPIO is determined in the SIU_PCR registers.
Page 74 EBI_CAL_BR0 through EBI_CAL_BR3 registers for each chip select region. The BR and BG primary signal functions are not implemented on the MPC5565 324 package, however the pin labels remain BR and BG on the BGA map of the 496 assembly.
Page 75: Detailed Signal Description
DSPI module D. 2.3.1.5 Phase Locked-Loop Configuration PLLCFG[2] The MPC5565 does not use PLLCFG[2], therefore it must be tied low. Refer to Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR).” MPC5565 Microcontroller Reference Manual, Rev. 1.0...
Page 76: External Bus Interface (Ebi) Signals
ADDR[8:11]_GPIO[4:7] are the External Bus Interface (EBI) address signals. These signals are not supported in the 324 package. 2.3.2.4 External Address / GPIO ADDR[12:29]_GPIO[8:25] ADDR[12:29]_GPIO[8:25] are the External Bus Interface (EBI) address signals. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-19...
Page 77 DATA[21]_GPIO[49] is an EBI data signal. These signals are not supported in the 324 package. 2.3.2.13 External Data / GPIO DATA[22]_GPIO[50] DATA[22]_GPIO[50] is an EBI data signal. These signals are not supported in the 324 package. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-20 Freescale Semiconductor...
Page 78 DATA[30]_GPIO[58] is an EBI data signal. These signals are not supported in the 324 package. 2.3.2.22 External Data / GPIO DATA[31]_GPIO[59] DATA[31]_GPIO[59] is an EBI data signal. These signals are not supported in the 324 package. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-21...
Page 79 BR__GPIO[72] is the bus request.Because the BR primary signal function is reserved on this device, there is no primary signal function for this ball. GPIO[72] pin has GPIO functionality only. These signals are not supported in the 324 package. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-22 Freescale Semiconductor...
Page 80: Nexus Signals
MDO[11:4]_GPIO[82:75] MDO[11:4]_GPIO[82:75] are the trace message outputs to the development tools for full port mode. These pins function as GPIO when the Nexus port controller (NPC) operates in reduced port mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-23...
Page 81: Jtag Signals
The JCOMP pin is used to enable the JTAG TAP controller. 2.3.4.6 Test Mode Enable Input TEST The TEST pin is used to place the chip in test mode. It must be negated for normal operation. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-24 Freescale Semiconductor...
Page 82: Controller Area Network (Flexcan) Signals
PCSD[4], a peripheral chip select for the DSPI D module. 2.3.6 Serial Communication Interface (eSCI) Signals 2.3.6.1 eSCI A Transmit / GPIO TXDA_GPIO[89] TXDA_GPIO[89] is the transmit pin for the eSCI A module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-25...
Page 83: Deserial/Serial Peripheral Interface (Dspi) Signals
SOUTA_PCSC[5]_GPIO[95] — Because the SOUTA primary function is reserved on this device, there is no primary signal function for this ball. Therefore, the alternate function is the PCSC[5], a peripheral chip select for the DSPI C module and is available on this device. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-26 Freescale Semiconductor...
Page 84 SCKB_PCSC[1]_GPIO[102] — SCKB is the primary function, and is the SPI clock pin for the DSPI B module. The alternate function is PCSC[1], a chip select output for the DSPI C module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 85 PCSB[4]_SCKC_GPIO[109] — PCSB[4] is the primary function and is a peripheral chip select output pin for the DSPI B module. SCKC is the alternate function and is the SPI clock for the DSPI C module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-28...
Page 86: Enhanced Queued A/D Controller (Eqadc) Signals
Analog Input / Differential Analog Input AN[5]_DAN2– AN[5] is a single-ended analog input to the two on-chip ADCs. DAN2– is the negative terminal of the differential analog input DAN2 (DAN2+ to DAN2–). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-29...
Page 87 AN[0:7] and AN[16:39] analog input pins because they are powered by V and can be used as digital DDEH9 pins for the synchronous serial interface (SSI) to external ADCs or used as the multiplexor digital outputs (MA[0]). MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-30 Freescale Semiconductor...
Page 88 This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. This pin is configured by setting the pad configuration register, SIU_PCR218. 2.3.8.17 Analog Input AN[16:39] AN[16:39] are analog input pins. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-31...
Page 89: Enhanced Time Processing Unit (Etpu) Signals
A TCR Clock / External Interrupt Request / GPIO TCRCLKA_IRQ[7]_GPIO[113] TCRCLKA_IRQ[7]_GPIO[113] is the TCR clock input for the eTPU A module. The alternate function is an external interrupt request input for the SIU module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-32 Freescale Semiconductor...
Page 90 ETPUA[5]_ETPUA[17]_GPIO[119] is an input/output channel pin for the eTPU A module. The alternate function, ETPUA[17], is an output channel for the eTPU A module. When configured as ETPUA[17], the pin functions as output only. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-33...
Page 91 A Channel / DSPI B Chip Select / GPIO ETPUA[12]_PCSB[1]_GPIO[126] ETPUA[12]_PCSB[1]_GPIO[126] is an input/output channel pin for the eTPU A module. The alternate function is a peripheral chip select for the DSPI B module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-34 Freescale Semiconductor...
Page 92 A Channel / External Interrupt / GPIO ETPUA[20]_IRQ[8]_GPIO[134] ETPUA[20]_IRQ[8]_GPIO[134] is an input/output channel pin for the eTPU A module. The alternate functions are an external interrupt request inputs for the SIU module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-35...
Page 93 A Channel / DSPI C Chip Select / GPIO ETPUA[31]_PCSC[4]_GPIO[145] ETPUA[31]_PCSC[4]_GPIO[145] is an input/output channel pin for the eTPU A module. The alternate function is a peripheral chip select for the DSPI C module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-36 Freescale Semiconductor...
Page 94: Enhanced Management Input/Output System (Emios) Signals
EMIOS[15]_IRQ[1]_GPIO[194] is an output channel pin for the eMIOS module. The alternate function is an external interrupt request input. 2.3.10.7 eMIOS Channel / GPIO EMIOS[16]_GPIO[195] EMIOS[16]_GPIO[195] is an input/output channel pin for the eMIOS module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-37...
Page 95: General Purpose Input / Output (Gpio) Signals
The GPIO[205] only has GPIO functionality. This pin is reserved for double data rate memory interface support. The pad type for GPIO[205] is MH (3.0–5.5 V). This signal is not supported in the 324 package. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-38...
Page 96: Calibration Bus Signals
CAL_DATA[0:15] is the primary function and is a calibration address. It is only functional on the 496 assembly. 2.3.12.5 Calibration Read/Write CAL_RD_WR CAL_RD_WR is the primary function and is a calibration read/write signal function. It is only functional on the 496 assembly. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-39...
Page 97: Clock Synthesizer Signals
2.3.13.4 Engineering Clock Output ENGCLK ENGCLK is a 50% duty cycle output clock with a maximum frequency of the device system clock divided by two. ENGCLK is not synchronous to CLKOUT. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-40 Freescale Semiconductor...
Page 98: Power / Ground Signals
STBY is the power supply input that is used to maintain a portion of the contents of internal SRAM during STBY power down. If not used, tie V to V STBY MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-41...
Page 99: I/O Power And Ground Segmentation
I/O pins and can be powered by any voltage within the allowed voltage range regardless of the power on the other segments. The power/ground segmentation applies regardless of whether a particular pin is configured for its primary function or GPIO. Table 2-3. MPC5565 Power / Ground Segmentation for 324 Pin Package Power Voltage...
Page 100 Signal Description Table 2-3. MPC5565 Power / Ground Segmentation for 324 Pin Package (continued) Power Voltage I/O Pins Powered by Segment Segment Range EVTI, EVTO, MCKO, MDO[3:0], MDO[11:4]_GPIO[82:75], MSEO[1:0], RDY, TCK, TDI, TDO, TMS, 1.8–3.3 V DDE7 JCOMP, TEST TCRCLKA_IRQ[7]_GPIO[113], ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117],...
Page 101 Signal Description The following table lists the power and ground segmentation for the 496-pin assembly used for calibration. Table 2-4. MPC5565 Device Power/Ground Segmentation for 496 Pin Assembly Power Voltage I/O Pins Powered by Segment Segment Range 5.0 V AN[22:35]...
Page 102: Etpu Pin Connections And Serialization
Signal Description Table 2-4. MPC5565 Device Power/Ground Segmentation for 496 Pin Assembly (continued) Power Voltage I/O Pins Powered by Segment Segment Range 3.3 V RC33 RCCTL 3.0–3.6 V — FLASH 4.5–5.25 V — 0.9–1.1 V — STBY — No connect voltages are ±...
Page 103 • • • IN 4 IN 13 IN 14 IN 3 DSPI C Figure 2-4. ETPUA[0:15]—DSPI C I/O Connections Table 2-5. ETPUA[0:15]—DSPI C I/O Mapping DSPI C Serialized eTPU A Channel Output Input MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-46 Freescale Semiconductor...
Page 104: Etpua[16:31]
DSPI B DSPI D Figure 2-6. ETPUA[24:29]—DSPI B–DSPI D I/O Connections Table 2-6. ETPUA[16:31]—DSPI B I/O Mapping DSPI B Serialized eTPU A Channel Output eTPU A Channel Input Inputs / Outputs MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-47...
Page 105: Emios Pin Connections And Serialization
EMIOS[12:15] connect to pins. The output channels of EMIOS[10:13] can be serialized OUT, and the inputs of EMIOS[12:15] can be serialized IN. The DSPI connections for EMIOS[10:11] are given in Figure 2-7, Figure 2-8 for EMIOS[12:13], and Figure 2-9 for EMIOS[14:15]. MPC5565 Microcontroller Reference Manual, Rev. 1.0 2-48 Freescale Semiconductor...
Page 106 GPIO[203]_ EMIOS[14] eMIOS EMIOS[14]_ CH14 IN IRQ[0]_ CH14 OUT GPIO[193] EMIOS[15]_ CH15 IN IRQ[1]_ CH15 OUT GPIO[194] GPIO[204]_ OUT 15 OUT 14 EMIOS[15] DSPI D Figure 2-9. EMIOS[14:15]—DSPI D I/O Connections MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 2-49...
Page 107: Document Revision History
The calibration signals only function when using the VertiCal assembly. Put footnote 1 in the diagram next to all signals from Table 2-1 MPC5565 324 Package Limitations except for the calibration signals. Put footnote 2 in the diagram next to all the calibration signals.
Page 108: Introduction
GPRs defined for integer instructions. Refer to the e200z6 PowerPC Core Reference Manual for more information on the e200z6 core. 3.1.1 Block Diagram Figure 3-1 shows a block diagram of the e200z6 core complex. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 109: Overview
The e200z6 core complex is built on a single-issue, 32-bit Power Architecture design with 64-bit general-purpose registers (GPRs). Power Architecture floating-point instructions are not supported in hardware, but are trapped and may be emulated by software. A signal processing extension (SPE) auxiliary MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 110: Features
Signal processing extension APU supporting fixed-point and single-precision floating-point operations, using the 64-bit general-purpose register file • Nexus class 3 real-time development unit • Power management — Low-power design — Dynamic power management of execution units, caches, and MMUs MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 111 • Eight-bit process identifier • 32-entry fully associative TLB • Support for nine page sizes (4, 16, 64, and 256 KB; 1, 4, 16, 64, and 256 MB) • Entry flush protection MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 112: Microarchitecture Summary
Branch target addresses are calculated in parallel with branch instruction decode, resulting in execution time of three clocks. Conditional branches which are not taken execute in a single clock. Branches with successful lookahead and target prefetching have an effective execution time of one clock. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 113: Core Registers And Programmer's Model
The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 114 Power Architecture (Read-only) L1CSR0 SPR 1010 processors 2 - Optional registers defined by the Power L1CFG0 SPR 515 L1FINV0 SPR 1016 Architecture embedded category Figure 3-2. Supervisor Mode Programmer’s Model MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 115: Power Architecture Registers
Link register (LR). The LR provides the branch target address for the branch conditional to link register (bclr, bclrl) instructions, and is used to hold the address of the instruction that follows a branch and link instruction, typically used for linking to subroutines. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 116 — Software-use special purpose registers (SPRGs). The SPRG0–SPRG7 registers are provided for operating system use. — Exception syndrome register (ESR). The ESR register provides a syndrome to differentiate between the different kinds of exceptions which can generate the same interrupt. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 117 — Timer status register (TSR). This register contains status on timer events and the most recent watchdog timer-initiated processor reset. For more details about these registers, refer to the Power Architecture embedded category specifications. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-10 Freescale Semiconductor...
Page 118: Core-Specific Registers
L1 cache. — L1 cache control and status register (L1CSR0) controls the operation of the L1 unified cache such as cache enabling, cache invalidation, cache locking, etc. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-11...
Page 119: E200Z6 Core Complex Features Not Supported In The Device
Reservation management logic external to the e200z6 is not implemented. Verification The system version register (SVR) of the e200z6 is 0x 0000_0000. Time base The decrement counters are always enabled in the e200z6. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-12 Freescale Semiconductor...
Page 120: Functional Description
The TLB is accessed indirectly through several MMU assist (MAS) registers. Software can read and write to the MMU assist registers with mtspr (move to SPR) and mfspr (move from SPR) instructions. The MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 121 The instruction fetch, branch, and load/store units generate 32-bit effective addresses. The MMU translates this effective address to a 32-bit real address which is then used for memory accesses. Figure 3-5 shows the effective to real address translation flow. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-14 Freescale Semiconductor...
Page 122 If the translation match was successful, the permission bits are checked as shown in Figure 3-6. If the access is not allowed by the access permission mechanism, the processor generates an instruction or data storage interrupt (ISI or DSI). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-15...
Page 123 Freescale EIS designs, because the tlbsx instruction only searches based on a single SPID value. For more information on the MASn registers is available in the e200z6 PowerPC Core Reference Manual. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-16 Freescale Semiconductor...
Page 124 Entry select for TLB1. ESEL 16–26 Reserved, must be cleared. 27–31 Next replacement victim for TLB1 (software managed). Software updates this field; it is copied to the ESEL field on a TLB error. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-17...
Page 125 0010 16 KB 0111 16 MB 0011 64 KB 1000 64 MB 0100 256 KB 1001 256 MB 0101 1 MB All other values are undefined. 24–31 Reserved, must be cleared. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-18 Freescale Semiconductor...
Page 126 1 All loads and stores to this page are performed without speculation (that is, they are known to be required). Endianness. Determines endianness for the corresponding page. 0 The page is accessed in big-endian byte order. 1 The page is accessed in true little-endian byte order. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-19...
Page 127 Table 3-7. MAS[4]—Hardware Replacement Assist Configuration Register Field Description 0–1 Reserved, must be cleared. 2–3 Default TLB selected TLBSELD 01 TLB1 (ignored by the e200z6, write as 01 for future compatibility) 4–13 Reserved, must be cleared. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-20 Freescale Semiconductor...
Page 128 Table 3-8. MAS[6] — TLB Search Context Register 0 Field Description 0–7 Reserved, must be cleared. 8–15 PID value for searches SPID 16–30 Reserved, must be cleared. AS value for searches MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-21...
Page 129: L1 Cache
Control Logic Control Data Array Address/ Processor Interface Tag Array Data Unit Core Data Data Data Path Address Address Address Path Memory Management Unit Figure 3-13. e200z6 Unified Cache Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-22 Freescale Semiconductor...
Page 130 (and valid). For invalid lines, the V bit is clear, causing the cache line to be ignored during lookups. Valid lines have their V bit set and D bit cleared, MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 131 (one from each way), corresponding to the same index into the cache array. 2. The higher order physical address bits A[0:19] are used as a tag reference or used to update the cache line tag field. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-24 Freescale Semiconductor...
Page 132 Ways disabled for data accesses are not affected by the dcba, dcbf, dcbi, dcblc, dcbst, dcbt, dcbtls, dcbtst, dcbtstls, and dcbz instructions. Cache control operations using L1CSR0[CINV] and L1FINV0 operations are not affected by the WAM setting and proceed normally. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-25...
Page 133 Bit 5 corresponds to way 1. The WID and WDD bits can be used for locking ways of the cache, and also are used in determining the replacement policy of the cache. — Reserved MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-26 Freescale Semiconductor...
Page 134 Indicates a lock overflow (overlocking) condition occurred. This bit is set by hardware on an “overlocking” condition, and will remain set until cleared by software writing 0 to this bit location. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-27...
Page 135 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00000001 (2 way) 00000001000 (8 KB) SPR - 515; Read-only Figure 3-17. L1 Cache Configuration Register 0 (L1CFG0) MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-28 Freescale Semiconductor...
Page 136: Interrupt Types
System reset none, • Reset by assertion of RESET vector to • Watchdog timer reset control 0xFFFF_FFFC • Debug reset control Critical input IVOR0 IVOR0 is not supported in the device MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-29...
Page 137 — SRR[0:1] Data translation lookup did not match a valid entry in the TLB Instruction TLB IVOR 14 — SRR[0:1] Instruction translation lookup did not match a valid TLB entry error MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-30 Freescale Semiconductor...
Page 138: Bus Interface Unit (Biu)
• Timer status register (TSR)—provides status of the timer facilities. • Time base registers (TBU and TBL)—two 32-bit registers (upper and lower) that are concatenated to provide a long-period, 64-bit counter. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-31...
Page 139: Signal Processing Extension Apu (Spe Apu)
SPE instruction in the e200z6 core reference for information on which conditions are recorded and where they are recorded. Most SPE instructions record conditions to the SPEFSCR. Vector compare instructions store the result of the comparison into the condition register (CR). MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-32 Freescale Semiconductor...
Page 140: External References
Not the mask bit 62 of CSRR0, DSRR0, or SRR0 respectively. The destination address is [D,C]SRR0[32:62] || 0b0. bclr, bclrl, bcctr, bcctrl Not the mask bit 62 of the LR or CTR respectively. The destination address is [LR,CTR][32:62] || 0b0. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 3-33...
Page 141: Document Revision History
• From: “Timer External Clock is not supported” • To: The timer external clock is not connected to a clock; Do not select the timer external clock. Corrected order of MAS[3] 26-31 bits. MPC5565 Microcontroller Reference Manual, Rev. 1.0 3-34 Freescale Semiconductor...
Page 142: Introduction
All reset sources initiate execution of the MCU boot assist module (BAM) program with the exception of the software external reset. 1. Unless noted otherwise, the use of ‘clock’ or ‘clocks’ in this section is a reference to the system clock. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 143: External Signal Description
SER bit of the system reset control register (SIU_SRCR). Refer to Section 11.1.4, “FMPLL Modes of Operation” for details of PLL configuration. NOTE During a power on reset, RSTOUT is tri-stated. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 144: Reset Configuration (Rstcfg)
RESET input pin glitch flag. The reset glitch flag bit (RGF) is cleared by writing a 1 to the bit. A write of 0 has no effect on the bit state. The SIU_RSR can be read at all times. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 145 Checkstop reset status 0 No enabled checkstop reset occurred. 1 An enabled checkstop reset occurred. 6–13 Reserved. Software system reset status SSRS 0 No software system reset occurred. 1 A software system reset occurred. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The CRE bit is reset to 1 by POR. Other resets sources do not reset the bit value. Figure 4-2. System Reset Control Register (SIU_SRCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 147: Functional Description
RCHW. Hence, the available reset vector addresses are: 0x0000_0004 0x0000_4004 0x0001_0004 0x0001_C004 0x0002_0004 0x0003_0004 Serial Boot Specified over serial download MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 148: Reset Sources
RSTOUT are kept asserted until the FMPLL is locked. After the FMPLL is locked, the reset controller waits an additional predetermined number of clock cycles before negating the RSTOUT pin. The WKPCFG and BOOTCFG[0:1] pins are sampled 4 clock cycles before the negation of RSTOUT, MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 149 SIU_RSR. The LLRS bit is set, and all other reset status bits in the SIU_RSR are cleared. Refer to Section 4.2.2, “Reset Output (RSTOUT)” Refer to Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL),” for more information on loss-of-lock. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 150 Debug tool sets the software system reset (SSR) bit in the system reset control register (SIU_SRCR) The debug tool writes a one to the software external reset (SER) bit in the system reset control register (SIU_SRCR) to generate an external software reset. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 151 RSTCFG is asserted), and the data is updated in the SIU_RSR. The reset source status bits in the SIU_RSR are unaffected. Refer to Section 4.2.2, “Reset Output (RSTOUT).” Refer to Chapter 23, “IEEE 1149.1 Test Access Port Controller (JTAGC),” for more information. MPC5565 Microcontroller Reference Manual, Rev. 1.0 4-10 Freescale Semiconductor...
Page 152: Reset Configuration And Configuration Pins
This reset configuration is defined by: • Configuration pins • A reset configuration halfword (RCHW), if present • Serial port, if a serial boot is used The following sections describe these configuration pins and the RCHW. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 4-11...
Page 153 MMU is configured, how the external bus is configured, the FlexCAN or eSCI module pin configuration, Nexus enabling, and password selection. Refer to Chapter 2, “Signal Description” for information about the BOOTCFG pins. MPC5565 Microcontroller Reference Manual, Rev. 1.0 4-12 Freescale Semiconductor...
Page 154 0x5A. BOOT_BLOCK_ADDRESS is explained in Section 15.3.2.2.4, “Read the Reset Configuration Halfword.” The fields of the RCHW are shown in Figure 4-3. BOOT_BLOCK_ADDRESS + 0x0000_0000 Boot Identifier = 0x5A Figure 4-3. RCHW Fields MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 4-13...
Page 155 CAN/SCI boot is initiated. For an external boot, only block 0 is checked for a valid boot identifier, and if not found, a CAN/SCI boot is initiated. MPC5565 Microcontroller Reference Manual, Rev. 1.0 4-14 Freescale Semiconductor...
Page 156 RCHW from the first address of each of the six blocks in the low address space (LAS) of internal flash. Table 4-9 shows the LAS addresses. Table 4-9. LAS Block Memory Addresses Block Address 0x0000_0000 0x0000_4000 0x0001_0000 0x0001_C000 0x0002_0000 0x0003_0000 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 4-15...
Page 157: Reset Configuration Timing
4 clock cycles before the negation of RSTOUT and stored in the reset status register (SIU_RSR). BOOTCFG[0:1] are latched only if RSTCFG is asserted. WKPCFG is not dependent on RSTCFG. MPC5565 Microcontroller Reference Manual, Rev. 1.0 4-16 Freescale Semiconductor...
Page 158 This clock count is dependent on the configuration of the FMPLL (Refer to Section 4.2.2, “RSTOUT”). If the FMPLL is configured for 1:1 (dual controller) operation or for bypass mode, this clock count is 16000. Figure 4-4. Reset Configuration Timing MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 4-17...
Page 159: Reset Flow
False RESET asserted True Set latch, wait 8 clock cycles False RESET Set RGF bit asserted True To entry point in internal reset flow Figure 4-5. External Reset Flow Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 4-18 Freescale Semiconductor...
Page 160 The clock count depends on the FMPLL configuration. Refer to Section 4.2.2, “Reset Output (RSTOUT).” If the FMPLL is configure in dual controller (1:1) or bypass mode, the clock count is 16000. Figure 4-6. Internal Reset Flow Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 4-19...
Page 161: Document Revision History
The reset controller then waits 4 clock cycles before the negating RSTOUT, and the associated bits/fields are updated in the SIU_RSR. Refer to the e200z6 Core Guide for more information on the watchdog timer and debug operation. Refer to Section 4.2.2, “Reset Output (RSTOUT).” MPC5565 Microcontroller Reference Manual, Rev. 1.0 4-20 Freescale Semiconductor...
Page 162: Introduction
The PBRIDGE provides programmable access protections for both masters and peripherals. Access protections allow the program to: • Override the privilege level of a master to change it to user mode privilege • Designate masters as trusted or untrusted MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 163 Slave 0 FLASH — Slave 1 — Slave 3 SRAM — Slave 6 PBRIDGE A PBRIDGE A FMPLL EBI control FLASH control eMIOS eTPU reg eTPU PRAM eTPU PRAM mirror eTPU SCM MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 164: Features
Provides configurable per-module write buffering support. • Provides configurable per-module and per-master access protections. 5.1.4 Modes of Operation The PBRIDGE has only one operating mode. External Signal Description The PBRIDGE has no external signals. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 165: Memory Map And Register Definitions
Off-platform peripheral access control register 1 Base + 0x0048 PBRIDGE_B_OPACR2 Off-platform peripheral access control register 2 Base + 0x004C PBRIDGE_B_OPACR3 Off-platform peripheral access control register 3 Base + 0x0050– — Reserved — Base + 0x0053 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 166: Register Descriptions
Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. MTW0 0 Write accesses from the CPU are not trusted 1 Write accesses from the CPU are trusted MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 167 Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. MTW3 0 The EBI is not trusted for write accesses. 1 The EBI is trusted for write accesses. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 168 To ensure code compatibility across all the MPC55XX family of products, writes to those addresses must be qualified with SIU_MIDR[PARTNUM]. NOTE Write PBRIDGE_x_PACR and PBRIDGE_x_OPACR with a read/modify/write for code compatibility. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 169 In the PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0 registers, the BW0 bit is not writeable. The default value is 0b0000 for PACR peripheral access fields that are unused or not connected. Figure 5-3. Peripheral Access Control Registers (PBRIDGE_x_PACRn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 170: Base + 0X0020
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the slave bus. In PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, the BW0 bit is not writeable. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 171: Pbridge_A_Opacr0
SCM 0b0100 — 0b0100 PBRIDGE B PBRIDGE_B_PACR0 PBRIDGE_B_Base + 0x0020 PBRIDGE B 0b0101 XBAR 0b0100 — 0b0000 PBRIDGE_B_PACR2 PBRIDGE_B_Base + 0x0028 ESCM 0b0100 eDMA 0b0100 INTC 0b0100 — 0b0100 — 0b0000 MPC5565 Microcontroller Reference Manual, Rev. 1.0 5-10 Freescale Semiconductor...
Page 172: Pbridge_B_Opacr0
The PBRIDGE provides programmable write buffering capability to buffer write accesses in the PBRIDGE for later completion, while terminating the system bus access early. This provides improved performance in systems where frequent writes to a slow peripheral occur. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 5-11...
Page 173 (if bufferable) or can be initiated. If the buffer has valid entries, a following read cycle stalls until the buffer is emptied and the read cycle can be completed. MPC5565 Microcontroller Reference Manual, Rev. 1.0 5-12 Freescale Semiconductor...
Page 174: General Operation
The PBRIDGE can block user mode accesses to certain slave peripherals or it can allow the individual slave peripherals to determine if user mode accesses are allowed. In addition, peripherals can be designated as write-protected. The PBRIDGE supports the notion of trusted masters for security purposes. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 5-13...
Page 175: Document Revision History
Table 5-8. Changes Between MPC5565RM Revisions 0.1 and 1 Added a NOTE to Section 5.3.1.2, “Peripheral Access Control Registers (PBRIDGE_x_PACR) and Off-Platform Peripheral Access Control Registers (PBRIDGE_x_OPACR)”: NOTE Write PBRIDGE_x_PACR and PBRIDGE_x_OPACR with a read/modify/write for code compatibility. MPC5565 Microcontroller Reference Manual, Rev. 1.0 5-14 Freescale Semiconductor...
Page 176: Introduction
This chapter describes the device system integration unit (SIU) that configures and initializes the following controls: • MCU reset configuration • System reset operation • Pad configuration • External interrupts • General-purpose I/O (GPIO) • Internal peripheral multiplexing MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 177: Block Diagram
IMUX DSPI signals, and I/O channels eQADC triggers Figure 6-1. SIU Block Diagram NOTE The power-on reset detection module, pad interface/pad ring module, and peripheral I/O channels are external to the SIU. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 178: Overview
In normal mode, the SIU provides the register interface and logic that controls the device and system configuration, the reset controller, and GPIO. The SIU continues operation with no changes in stop mode. Debug SIU operation in debug mode is identical to operation in normal mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 179: External Signal Description
RESET has a glitch detector to sense electrical fluctuations that drop below the switch point value of the input buffer logic for the V inputs for more than two clock cycles. DDEH MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 180 2. BAM module boots from internal flash (default = 0b00) 3. Boot value from internal flash is written to BOOTCFG[0:1] field in the reset status register (SIU_RSR) 4. BOOTCFG[0:1] values are latched and driven as output signals from the SIU MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 181 IRQ flag bit is set to 1. For example, the IRQ flag bit is set if a rising-edge event occurs under the following conditions: • Previous filtered IRQ state was a logic 0 • Current latched IRQ state is a logic 1 • Rising-edge event is enabled for the IRQ MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 182 When the ‘DMA done’ signal asserts, the IRQ flag bit is cleared. Refer to the following sections for more information: Section 6.3.1.5, “DMA/Interrupt Request Enable Register (SIU_DIRER)” Section 6.3.1.6, “DMA/Interrupt Request Select Register (SIU_DIRSR)” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 183 IRQ. Refer to the following sections for more information: Section 6.3.1.4, “External Interrupt Status Register (SIU_EISR)” Section 6.3.1.9, “IRQ Rising-Edge Event Enable Register (SIU_IREER)” Section 6.3.1.10, “IRQ Falling-Edge Event Enable Register (SIU_IFEER)” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 184: Memory Map And Register Definition
Base + 0x0984 SIU_ECCR External clock control register Base + 0x0988 SIU_CARH Compare A high register Base + 0x098C SIU_CARL Compare A low register Base + 0x0990 SIU_CBRH Compare B high register MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 185: Register Descriptions
PARTNUM MPC5565 part number R CSP MASKNUM_MAJOR MASKNUM_MINOR Default reset values 324 = 0b101 0b0000 0b0000 Reset values 324 CSP = 0b101 496 pckg Figure 6-2. MPC5565 MCU ID Register (SIU_MIDR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-10 Freescale Semiconductor...
Page 186 PARTNUM MPC5565 reads 0x5565. CSP configuration: 0 Standard package 1 CSP package 17–19 Package settings. PKG selects the pin package for the MPC5565 device. Select for Legacy compatibility 001–01x Reserved Reserved Selects the 324 package Select the 496 calibration assembly Reserved 20–23...
Page 187 The last reset source acknowledged by the reset controller was not a valid assertion of the RESET pin. The last reset source acknowledged by the reset controller was a valid assertion of the RESET pin. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-12...
Page 188 The WKPCFG pin value latched during the last reset was a logical 0 and weak pulldown is the default setting. The WKPCFG pin value latched during the last reset was a logical 1 and weak pullup is the default setting. 17–28 Reserved MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-13...
Page 189 • SERF flag bit set but no previously set bits in the SIU_RSR are cleared Reason The SERF flag bit is cleared by writing a 1 (write 1 to clear) to the bit location or when another reset source is asserted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-14 Freescale Semiconductor...
Page 190 The SSR bit always reads 0. A write of 0 to this bit has no effect. The CRE bit is set to 1 by POR. Other reset sources cannot set the CRE bit. Figure 6-4. System Reset Control Register (SIU_SRCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-15...
Page 191 The IRQ flag bit remains set until cleared by software or through the servicing of a DMA request. The IRQ flag bits are cleared by writing a 1 to the bit. A write of 0 has no effect. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-16...
Page 192 Address: Base + 0x0018 Access: R/W Reset EIRE15 EIRE14 EIRE13 EIRE12 EIRE11 EIRE10 EIRE9 EIRE8 EIRE7 EIRE6 EIRE5 EIRE4 EIRE3 EIRE2 EIRE1 EIRE0 Reset Figure 6-6. DMA/Interrupt Request Enable Register (SIU_DIRER) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-17...
Page 193 DMA/interrupt request select n. Selects between a DMA transfer or external interrupt request when an DIRSn edge-triggered event occurs on the corresponding IRQ[n] pin. Interrupt request is selected. DMA request is selected. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-18 Freescale Semiconductor...
Page 194 Overrun flag n. This bit is set when an overrun occurs on IRQ[n]. Bit 31 (OVF0) is the overrun flag for IRQ[0]; bit 16 OVFn (OVF15) is overrun flag for IRQ[15]. 0 No overrun occurred. An overrun occurred. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-19...
Page 195 Overrun request enable n. Enables the overrun request when an overrun occurs on the IRQ[n] pin. Bit 31 (ORE0) is OREn the enable overrun flag for IRQ[0]; bit 16 (ORE15) is overrun flag for IRQ[15]. Overrun request is disabled. Overrun request is enabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-20 Freescale Semiconductor...
Page 196 Address: Base + 0x002C Access: R/W Reset IFEE9 IFEE8 IFEE7 IFEE6 IFEE5 IFEE4 IFEE3 IFEE2 IFEE1 IFEE0 IFEE15 IFEE14 IFEE13 IFEE12 IFEE11 IFEE10 Reset Figure 6-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-21...
Page 197 For a 100 MHz system clock, this gives a range of 20 ns to 328 µs. The minimum time of three clocks accounts for synchronization of the IRQ input pins with the system clock. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-22...
Page 198 The PA fields in PCR0 through 3 and PCR4 through 7 must not be configured simultaneously to select ADDR[8:11] as an input. Only one pin is to be configured to provide the address input. If external master operation is enabled, clear the HYS bit to 0. Figure 6-13. Sample PCR Register Description MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-23...
Page 199 Open drain output enable. Controls output driver configuration for the pads. Either open drain or push/pull driver configurations can be selected. This feature applies to output pins only. Disable open drain for the pad (push/pull driver enabled). Enable open drain for the pad. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-24 Freescale Semiconductor...
Page 200 When configured as CS[0] or ADDR[8], clear the ODE bit to 0. Refer to the EBI section for weak pullup settings when configured as CS[0] or ADDR[8]. Figure 6-14. CS[0]_ADDR[8]_GPIO[0] Pad Configuration Register (SIU_PCR0) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-25...
Page 201 Table 6-21 lists the PA values for CS[1:3]_ADDR[9:11]_GPIO[1:3]. Table 6-21. PCR1 through PCR3 PA Field Definition PA Field Pin Function 0b00 GPIO[1:3] 0b01 CS[1:3] 0b10 ADDR[9:11] 0b11 CS[1:3] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-26 Freescale Semiconductor...
Page 202 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as ADDR[8:26]. Figure 6-17. ADDR[12:26]_GPIO[8:22] Pad Configuration Registers (SIU_PCR8–SIU_PCR22) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-27...
Page 203 Figure 6-18. ADDR[27:29]_GPIO[23:25] Pad Configuration Registers (SIU_PCR23–SIU_PCR25) Refer to Table 6-19 for bit field definitions. Table 6-24 lists the PA field for ADDR[27:29]_GPIO[23:25]. Table 6-24. PCR23 through PCR25 PA Field Definition PA Field Pin Function GPIO[23:25] ADDR[27:29] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-28 Freescale Semiconductor...
Page 204 Figure 6-19. ADDR[30:31]_GPIO[26:27] Pad Configuration Registers (SIU_PCR26–SIU_PCR27) Refer to Table 6-19 for bit field definitions. Table 6-25 lists the PA field for ADDR[30:31]_GPIO[26:27]. Table 6-25. PCR26–27 PA Field Definition PA Field Pin Function GPIO[26:27] ADDR[30:31] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-29...
Page 205 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[16:20]. Figure 6-21. DATA[16:20]_GPIO[44:48] Pad Configuration Registers (SIU_PCR44–SIU_PCR48) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-30 Freescale Semiconductor...
Page 206 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[22]. Figure 6-23. DATA[22]_GPIO[50] Pad Configuration Registers (SIU_PCR50) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-31...
Page 207 Table 6-28 lists the PA fields for DATA[23]_GPIO[51]. Table 6-28. PCR51 PA Field Definition PA Field Pin Function 0b00 GPIO[51] 0b01 DATA[23] 0b10 Invalid value 0b11 DATA[23] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-32 Freescale Semiconductor...
Page 208 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[25. Figure 6-26. DATA[25]_GPIO[53] Pad Configuration Registers (SIU_PCR53) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-33...
Page 209 Table 6-31 lists the PA fields for DATA[26]_GPIO[54]. Table 6-31. PCR54 PA Field Definition PA Field Pin Function 0b00 GPIO[54] 0b01 DATA[26] 0b10 Invalid value 0b11 DATA[26] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-34 Freescale Semiconductor...
Page 210 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[28]. Figure 6-29. DATA[28]_GPIO[56] Pad Configuration Registers (SIU_PCR56) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-35...
Page 211 Table 6-34 lists the PA fields for DATA[29]_GPIO[57]. Table 6-34. PCR57 PA Field Definition PA Field Pin Function 0b00 GPIO[57] 0b01 DATA[29] 0b10 Invalid value 0b11 DATA[29] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-36 Freescale Semiconductor...
Page 212 If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[31]. Figure 6-32. DATA[31]_GPIO[59] Pad Configuration Registers (SIU_PCR59) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-37...
Page 213 Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. When configured as BDIP, clear the ODE bit to 0. Refer to the EBI section for weak pullup settings when configured as BDIP. Figure 6-34. BDIP_GPIO[63] Pad Configuration Register (SIU_PCR63) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-38 Freescale Semiconductor...
Page 214 Figure 6-36. WE/BE[2:3]_GPIO[66:67] Pad Configuration Registers (SIU_PCR66–SIU_PCR67) Refer to Table 6-19 for bit field definitions. Table 6-39 lists the PA fields for WE/BE[2:3]_GPIO[66:67]. Table 6-37. PCR66–PCR67 PA Field Definition PA Field Pin Function GPIO[66:67] WE/BE[2:3] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-39...
Page 215 When configured as TS, clear the ODE bit to 0. When EBI is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as TS. Figure 6-38. TS_GPIO[69] Pad Configuration Register (SIU_PCR69) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-40 Freescale Semiconductor...
Page 216 Figure 6-40. TEA_GPIO[71] Pad Configuration Register (SIU_PCR71) Refer to Table 6-19 for bit field definitions. Table 6-38 lists the PA fields for TEA_GPIO[71]. Table 6-38. PCR71 PA Field Definition PA Field Pin Function GPIO[71] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-41...
Page 217 Table 6-40 lists the PA field for BG_FEC_MDIO_GPIO[73]. Table 6-40. PCR73 PA Field Definition PA Field Pin Function 0b00 GPIO[73] 0b01 Invalid value 0b10 Invalid value 0b11 Invalid value MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-42 Freescale Semiconductor...
Page 218 Table 6-19 for bit field definitions. Table 6-41 lists the PA fields for CNTXA_TXDA_GPIO[83]. Table 6-41. PCR83 PA Field Definition PA Field Pin Function 0b00 GPIO[83] 0b01 CNTXA 0b10 TXDA 0b11 CNTXA MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-43...
Page 219 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-46. CNTXB_PCSC[3]_GPIO[85] Pad Configuration Register (SIU_PCR85) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-44 Freescale Semiconductor...
Page 220 Table 6-19 for bit field definitions. Table 6-44 lists the PA fields for CNRXB_PCSC[4]_GPIO[86]. Table 6-44. PCR86 PA Field Definition PA Field Pin Function 0b00 GPIO[86] 0b01 CNTXB 0b10 PCSC[4] 0b11 CNTXB MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-45...
Page 221 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-49. CNRXC_PCSD[4]_GPIO[88] Pad Configuration Register (SIU_PCR88) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-46 Freescale Semiconductor...
Page 222 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-51. RXDA_GPIO[90] Pad Configuration Register (SIU_PCR90) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-47...
Page 223 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-53. RXDB_PCSD[5]_GPIO[92] Pad Configuration Register (SIU_PCR92) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-48 Freescale Semiconductor...
Page 224 Table 6-49 lists the PA fields for SCKA_PCSC[1]_GPIO[93]. Table 6-49. PCR93 PA Field Definition PA Field Pin Function 0b00 GPIO[93] 0b01 Invalid value 0b10 PCSC[1] 0b11 Invalid value MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-49...
Page 225 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-56. SOUTA_PCSC[5]_GPIO[95] Pad Configuration Register (SIU_PCR95) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-50 Freescale Semiconductor...
Page 226 Table 6-52 lists the PA fields for PCSA[0]_PCSD[2]_GPIO[96]. Table 6-52. PCR96 PA Field Definition PA Field Pin Function 0b00 GPIO[96] 0b01 Invalid value 0b10 PCSD[2] 0b11 Invalid value MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-51...
Page 227 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-59. PCSA[2]_SCKD_GPIO[98] Pad Configuration Register (SIU_PCR98) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-52 Freescale Semiconductor...
Page 228 Table 6-55 lists the PA fields for PCSA[3]_SIND_GPIO[99]. Table 6-55. PCR99 PA Field Definition PA Field Pin Function 0b00 GPIO[99] 0b01 Invalid value 0b10 SIND 0b11 Invalid value MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-53...
Page 229 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-62. PCSA[5]_PCSB[3]_GPIO[101] Pad Configuration Register (SIU_PCR101) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-54 Freescale Semiconductor...
Page 230 Table 6-19 for bit field definitions. Table 6-58 lists the PA fields for SCKB_PCSC[1]_GPIO[102]. Table 6-58. PCR102 PA Field Definition PA Field Pin Function 0b00 GPIO[102] 0b01 SCKB 0b10 PCSC[1] 0b11 SCKB MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-55...
Page 231 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-65. SOUTB_PCSC[5]_GPIO[104] Pad Configuration Register (SIU_PCR104) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-56 Freescale Semiconductor...
Page 232 Table 6-19 for bit field definitions. Table 6-61 lists the PA fields for PCSB[0]_PCSD[2]_GPIO[105]. Table 6-61. PCR105 PA Field Definition PA Field Pin Function 0b00 GPIO[105] 0b01 PCSB[0] 0b10 PCSD[2] 0b11 PCSB[0] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-57...
Page 233 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-68. PCSB[2]_SOUTC_GPIO[107] Pad Configuration Register (SIU_PCR107) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-58 Freescale Semiconductor...
Page 234 Table 6-19 for bit field definitions. Table 6-64 lists the PA fields for PCSB[3]_SINC_GPIO[108]. Table 6-64. PCR108 PA Field Definition PA Field Pin Function 0b00 GPIO[108] 0b01 PCSB[3] 0b10 SINC 0b11 PCSB[3] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-59...
Page 235 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-71. PCSB[5]_PCSC[0]_GPIO[110] Pad Configuration Register (SIU_PCR110) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-60 Freescale Semiconductor...
Page 236 WPE WPS RESET: The ETRIG[0:1] function is not available on the MPC5565. Do not select 0b1 for the PA field. When configured as GPDO, set the OBE bit to 1. When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Page 237 IBE bit to 1 to show the pin state in the GPDI register. The weak pullup/down selection at reset for the ETPUA[0:3] pin is determined by the WKPCFG pin. Figure 6-74. ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117] Pad Configuration Register (SIU_PCR114–SIU_PCR117) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-62 Freescale Semiconductor...
Page 238 Table 6-19 for bit field definitions. Table 6-70 lists the PA fields for ETPUA[4]_ETPUA[16]_GPIO[118]. Table 6-70. PCR118 PA Field Definition PA Field Pin Function 0b00 GPIO[118] 0b01 ETPUA[4] 0b10 ETPUA[16] 0b11 ETPUA[4] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-63...
Page 239 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. The weak pullup/down selection at reset for the ETPUA[6], ETPUA[18], signals is determined by WKPCFG. Figure 6-77. ETPUA[6]_ETPUA[18]_GPIO[120] Pad Configuration Register (SIU_PCR120) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-64 Freescale Semiconductor...
Page 240 Table 6-19 for bit field definitions. Table 6-73 lists the PA fields for ETPUA[7]_ETPUA[19]_GPIO[121]. Table 6-73. PCR121 PA Field Definition PA Field Pin Function 0b00 GPIO[121] 0b01 ETPUA[7] 0b10 ETPUA[19] 0b11 ETPUA[7] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-65...
Page 241 IBE bit to 1 allows the pin state to be reflected in the corresponding GPDI register. The weak pullup/down selection at reset for the ETPUA[11] pin is determined by the WKPCFG pin. Figure 6-80. ETPUA[11]_ETPUA[23]_GPIO[125] Pad Configuration Register (SIU_PCR125) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-66 Freescale Semiconductor...
Page 242 Table 6-19 for bit field definitions. Table 6-76 lists the PA fields for ETPUA[12]_PCSB[1]_GPIO[126]. Table 6-76. PCR126 PA Field Definition PA Field Pin Function 0b00 GPIO[126] 0b01 ETPUA[12] 0b10 PCSB[1] 0b11 ETPUA[12] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-67...
Page 243 IBE bit to 1 to show the pin state in the GPDI register. The weak pullup/down selection at reset for the ETPUA[16:19] pin is determined by the WKPCFG pin. Figure 6-83. ETPUA[16:19]_PCSD[1:4]_GPIO[130:133] Pad Configuration Register (SIU_PCR130–SIU_PCR133) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-68 Freescale Semiconductor...
Page 244 Table 6-19 for bit field definitions. Table 6-79 lists the PA fields for ETPUA[20]_IRQ[8]_GPIO[134]. Table 6-79. PCR134 PA Field Definition PA Field Pin Function 0b00 GPIO[134] 0b01 ETPUA[20] 0b10 IRQ[8] 0b11 ETPUA[20] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-69...
Page 245 Clear the IBE bit to 0 to reduce power consumption. The IBE bit must be set to 1 for ETPUA[22] or GPIO[136] when configured as input. The weak pullup/down selection at reset for the ETPUA[22] pin is determined by the WKPCFG pin. Figure 6-86. ETPUA[22]_IRQ[10]_GPIO[136] Pad Configuration Register (SIU_PCR136) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-70 Freescale Semiconductor...
Page 246 Table 6-19 for bit field definitions. Table 6-82 lists the PA fields for ETPUA[23]_IRQ[11]_GPIO[137]. Table 6-82. PCR137 PA Field Definition PA Field Pin Function 0b00 GPIO[137] 0b01 ETPUA[23] 0b10 IRQ[11] 0b11 ETPUA[23] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-71...
Page 247 IBE bit to 0 to reduce power consumption. The IBE bit must be set to 1 for GPIO when configured as input. The weak pullup/down value at reset for ETPUA[28:30] is determined by WKPCFG. Figure 6-89. ETPUA[28:30]_PCSC[1:3]_GPIO[142:144] Pad Configuration Register (SIU_PCR142–SIU_PCR144) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-72 Freescale Semiconductor...
Page 248 Table 6-85. PCR145 PA Field Definition (continued) PA Field Pin Function 0b00 GPIO[145] 0b01 ETPUA[31] 0b10 PCSC[4] 0b11 ETPUA[31] 6.3.1.92 Pad Configuration Registers 146–178 (SIU_PCR146–SIU_PCR178) The SIU_PCR146–SIU_PCR178 registers are not implemented in this device. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-73...
Page 249 The IBE bit must be set to 1 for EMIOS[10:11] or GPIO[189:190] when configured as input. The weak pullup/down selection at reset for the EMIOS[10:11] pins is determined by the WKPCFG pin. Figure 6-92. EMIOS[10:11]_PCSD[3:4]_GPIO[189:190] Pad Configuration Register (SIU_PCR189–SIU_PCR190) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-74 Freescale Semiconductor...
Page 250 Table 6-19 for bit field definitions. Table 6-88 lists the PA fields for EMIOS[12]_SOUTC_GPIO[191]. Table 6-88. PCR191 PA Field Definition PA Field Pin Function 0b00 GPIO[191] 0b01 EMIOS[12] 0b10 SOUTC 0b11 EMIOS[12] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-75...
Page 251 When GPIO[193] is configured as input, set the IBE bit 1. The weak pullup/down selection at reset for the EMIOS[14] pin is determined by the WKPCFG pin. Figure 6-95. EMIOS[14]_IRQ[0]_GPIO[193] Pad Configuration Register (SIU_PCR193) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-76 Freescale Semiconductor...
Page 252 Table 6-19 for bit field definitions. Table 6-91 lists the PA fields for EMIOS[15]_IRQ[1]_GPIO[194]. Table 6-91. PCR194 PA Field Definition PA Field Pin Function 0b00 GPIO[194] 0b01 EMIOS[15] 0b10 IRQ[1] 0b11 EMIOS[15] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-77...
Page 253 The IBE bit must be set to 1 for EMIOS[17] or GPIO[196] when configured as input. The weak pullup/down selection at reset for the EMIOS[17] pin is determined by the WKPCFG pin. Figure 6-98. EMIOS[17]_GPIO[196] Pad Configuration Register (SIU_PCR196) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-78 Freescale Semiconductor...
Page 254 Table 6-94 lists the PA fields for EMIOS[18]_GPIO[197]. Table 6-94. PCR197 PA Field Definition PA Field Pin Function 0b00 GPIO[197] 0b01 EMIOS[18] 0b10 Invalid value 0b11 EMIOS[18] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-79...
Page 255 The IBE bit must be set to 1 for EMIOS[20:21] or GPIO[199:200] when configured as input. The weak pullup/down selection at reset for the EMIOS[20:21] pin is determined by the WKPCFG pin. Figure 6-101. EMIOS[20:21]_GPIO[199:200] Pad Configuration Register (SIU_PCR199–SIU_PCR200) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-80 Freescale Semiconductor...
Page 256 Table 6-97 lists the PA fields for EMIOS[22]_GPIO[201]. Table 6-97. PCR201 PA Field Definition PA Field Pin Function 0b00 GPIO[201] 0b01 EMIOS[22] 0b10 Invalid value 0b11 EMIOS[22] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-81...
Page 257 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-104. EMIOS[14:15]_GPIO[203:204] Pad Configuration Registers (SIU_PCR203–SIU_PCR204) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-82 Freescale Semiconductor...
Page 258 SIU_ETISR register. The input source for each SIN, SS, SCK, and trigger signal is individually specified in the DSPI input select register (SIU_DISR). Refer to Section 6.3.1.153, “eQADC Trigger Input Select Register (SIU_ETISR).” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-83...
Page 259 Table 6-19 for bit field definitions. Table 6-100 lists the PA fields for PLLCFG[0]_IRQ[4]_GPIO[208]. Table 6-100. PCR208 PA Field Definition PA Field Pin Function 0b00 GPIO[208] 0b01 PLLCFG[0] 0b10 IRQ[4] 0b11 PLLCFG[0] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-84 Freescale Semiconductor...
Page 260 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. When configured as GPDI, set the IBE bit to 1. Figure 6-109. RSTCFG_GPIO[210] Pad Configuration Register (SIU_PCR210) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-85...
Page 261 When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the corresponding GPDI register. When configured as GPDI, set the IBE bit to 1. Figure 6-111. WKPCFG_GPIO[213] Pad Configuration Register (SIU_PCR213) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-86 Freescale Semiconductor...
Page 262 Table 6-19 for bit field definitions. Table 6-103 lists the PA fields for AN[12]_MA[0]_SDS. Table 6-103. PCR215 PA Field Definition PA Field Pin Function 0b00 0b01 Invalid value 0b10 MA[0] 0b11 AN[12] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-87...
Page 263 Table 6-19 for bit field definitions. Table 6-105 lists the PA fields for AN[14]_MA[2]_SDI. Table 6-105. PCR217 PA Field Definition PA Field Pin Function 0b00 0b01 Invalid value 0b10 MA[2] 0b11 AN[14] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-88 Freescale Semiconductor...
Page 264 6.3.1.120 Pad Configuration Register 223–220 (SIU_PCR223–SIU_PCR220) The SIU_PCR223–SIU_PCR220 registers control the drive strength of MDO[3:0]. Address: Base + 0x01F8 through Base + 0x01FE Access: R/W RESET: Figure 6-118. MDO[3:0 ] Pad Configuration Register (SIU_PCR223–SIU_PCR220) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-89...
Page 265 Figure 6-121. EVTO Pad Configuration Register (SIU_PCR227) 6.3.1.124 Pad Configuration Register 228 (SIU_PCR228) The SIU_PCR228 register controls the drive strength of TDO. Address: Base + 0x0208 Access: R/W RESET: Figure 6-122. TDO Pad Configuration Register (SIU_PCR228) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-90 Freescale Semiconductor...
Page 266 Figure 6-125. CAL_CS[0] Pad Configuration Register (SIU_PCR256) Refer to Table 6-19 for bit field definitions. Table 6-107 lists the PA fields for CAL_CS[0]. Table 6-107. PCR256 PA Field Definition PA Field Pin Function Invalid value CAL_CS[0] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-91...
Page 267 Table 6-109 lists the PA fields for CAL_ADDR[12]. Table 6-109. PCR259 PA Field Definition PA Field Pin Function 0b00 Invalid value 0b01 CAL_ADDR[12] 0b10 Invalid value 0b11 CAL_ADDR[12] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-92 Freescale Semiconductor...
Page 268 Table 6-111 lists the PA fields for CAL_ADDR[14]. Table 6-111. PCR261 PA Field Definition PA Field Pin Function 0b00 Invalid value 0b01 CAL_ADDR[14] 0b10 Invalid value 0b11 CAL_ADDR[14] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-93...
Page 269 6.3.1.135 Pad Configuration Register 264 (SIU_PCR264) The SIU_PCR264 register controls the function, direction, and electrical attributes of CAL_ADDR[17]. Address: Base + 0x0250 Access: R/W WPE WPS RESET: Figure 6-131. CAL_ADDR[17] Pad Configuration Register (SIU_PCR264) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-94 Freescale Semiconductor...
Page 270 6.3.1.137 Pad Configuration Register 266 (SIU_PCR266) The SIU_PCR266 register controls the function, direction, and electrical attributes of CAL_ADDR[19]. Address: Base + 0x0254 Access: R/W WPE WPS RESET: Figure 6-133. CAL_ADDR[19] Pad Configuration Register (SIU_PCR266) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-95...
Page 271 Table 6-118 lists the PA fields for CAL_ADDR[21]. Table 6-118. PCR268 PA Field Definition PA Field Pin Function 0b00 Invalid value 0b01 CAL_ADDR[21] 0b10 Invalid value 0b11 CAL_ADDR[21] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-96 Freescale Semiconductor...
Page 272 Table 6-120 lists the PA fields for CAL_ADDR[23:24]. Table 6-120. PCR270–271 PA Field Definition PA Field Pin Function 0b00 Invalid value 0b01 CAL_ADDR[23:24] 0b10 Invalid value 0b11 CAL_ADDR[23:24] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-97...
Page 273 Table 6-122 lists the PA fields for CAL_ADDR[28]. Table 6-122. PCR275 PA Field Definition PA Field Pin Function 0b00 Invalid value 0b01 CAL_ADDR[28] 0b10 Invalid value 0b11 CAL_ADDR[28] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-98 Freescale Semiconductor...
Page 274 Table 6-124. PCR277 PA Field Definition PA Field Pin Function Invalid value CAL_ADDR[30] 6.3.1.146 Pad Configuration Register 278–293 (SIU_PCR278–SIU_PCR293) The SIU_PCR278–293 registers control the function, direction, and electrical attributes of CAL_DATA[0:15]. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-99...
Page 275 6.3.1.148 Pad Configuration Register 295–296 (SIU_PCR295–SIU_PCR296) The SIU_PCR295–SIU_PCR296 registers control the function, direction, and electrical attributes of CAL_WE/BE[0:1]. Address: Base + 0x028E through base + 0x0290 Access: R/W RESET: Figure 6-144. CAL_WE/BE[0:1] Pad Configuration Registers (SIU_PCR295–296) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-100 Freescale Semiconductor...
Page 276 GPIO[n] pin. The n notation in the 178 SIU_GPDOn register names relate to the [n] in GPIO[n] signal name. For example, SIU_GPDO0 contains the PDO0 bit for CS[0]_GPIO[0]; and MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 277 GPIO pin. If a GPDI register is configured as output, and the input buffer enable bit is set to one in the PCR register, the SIU_GPDIn register reflects the state of the output pin. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-102 Freescale Semiconductor...
Page 278 CFIFO Channel Channel Channel Input GPIO[207] Number) eTPUA[30] eMIOS[10] ETRIG[0] GPIO[206] eTPUA[31] eMIOS[11] ETRIG[1] GPIO[207] eTPUA[29] eMIOS[15] ETRIG[0] GPIO[206] eTPUA[28] eMIOS[14] ETRIG[1] GPIO[207] eTPUA[27] eMIOS[13] ETRIG[0] GPIO[206] eTPUA[26] eMIOS[12] ETRIG[1] GPIO[207] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-103...
Page 279 2. Specifies the input for eQADC trigger 2 [0:1] GPIO[206] ETPUA[29] channel EMIOS[15] channel ETRIG[0] pin 8–9 TSEL1 eQADC trigger input select 1. Specifies the input for eQADC trigger 1 [0:1] GPIO[207] ETPUA[31] channel EMIOS[11] channel ETRIG[1] pin MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-104 Freescale Semiconductor...
Page 280 PCSC[15] serialized input (ETPUA[11]) PCSD[0] serialized input (ETPUA[21]) 4–5 ESEL13 External IRQ input select 13. Specifies the input for IRQ[13]. [0:1] IRQ[13] PCSB[13] serialized input (ETPUA[24]) PCSC[14] serialized input (ETPUA[10]) PCSD[15] serialized input (ETPUA[24]) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-105...
Page 281 PCSC[6] serialized input (ETPUA[2]) PCSD[7] serialized input (EMIOS[10]) 22–23 ESEL4 External IRQ input select 4. Specifies the input for IRQ[4]. [0:1] IRQ[4] PCSB[4] serialized input (ETPUA[19]) PCSC[5] serialized input (ETPUA[1]) PCSD[6] serialized input (EMIOS[11]) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-106 Freescale Semiconductor...
Page 282 DSPI modules. Address: Base + 0x0908 Access: R/W SINSELB SSSELB SCKSELB TRIGSELB Reset SINSELC SSSELC SCKSELC TRIGSELC SINSELD SSSELD SCKSELD TRIGSELD Reset Figure 6-151. DSPI Input Select Register (SIU_DISR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-107...
Page 283 SCKB (Master) SCKD (Master) 22–23 TRIGSELC DSPI C trigger input select. Specifies the source of the PCSC trigger input for [0:1] master or slave mode. Invalid value Invalid value PCSB[4] PCSD[4] MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-108 Freescale Semiconductor...
Page 284 MATCH DISNEX Reset CSRE Reset When system reset negates, the value in this bit depends on the censorship control word and the boot configuration bits. Figure 6-152. Chip Configuration Register (SIU_CCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-109...
Page 285 Furthermore, the suppression of reflections from the non-calibration bus onto the calibration bus is not enabled by CRSE. Those reflections also always are suppressed. Calibration reflection suppression is enabled. Calibration reflection suppression is disabled. Reserved MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-110 Freescale Semiconductor...
Page 286 EBTS bit affects the external bus timing. External bus signals have zero output hold times. External bus signals have non-zero output hold times. Note: Do not change EBTS while an external bus transaction is in process. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-111...
Page 287 The SIU_CARH holds the 32-bit value that is compared against the value in the SIU_CBRH register. The CMPAH field is read/write and is reset by the synchronous reset signal. Address: Base + 0x0988 Access: R/W CMPAH Reset CMPAH Reset Figure 6-154. Compare A Register High (SIU_CARH) MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-112 Freescale Semiconductor...
Page 288 The SIU_CBRH holds the 32-bit value that is compared against the value in the SIU_CARH. The CMPBH field is read/write and is reset by the synchronous reset signal. Address: Base + 0x0990 Access: R/W CMPBH Reset CMPBH Reset Figure 6-156. Compare B Register High (SIU_CBRH) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-113...
Page 289: Functional Description
0b01 FlexCAN/eSCI boot 0b10 Boot from external memory (no arbitration) 0b11 Boot from external memory (external arbitration) Refer to Section 15.3.2.2.4, “Read the Reset Configuration Halfword” for details on the RCHW. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-114 Freescale Semiconductor...
Page 290: Reset Control
IRQ[0:3] inputs can generate either an interrupt request to the interrupt controller or a DMA transfer request to the DMA controller. Figure 6-158 shows the DMA and interrupt request connections to the interrupt and DMA controllers. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-115...
Page 291: Gpio Operation
The internal multiplexing select registers (SIU_ETISR, SIU_EIISR, and SIU_DISR) select the input source for the following components: • eQADC external trigger input signals • SIU external interrupt request signals • DSPI signals used for chaining serial and parallel DSPI modules MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-116 Freescale Semiconductor...
Page 292 An example of the multiplexing of an eQADC external trigger input is given in Figure 6-160. GPIO[206] ETRIG[0]_GPIO[111] ETRIG[0] ETPUA[30] output channel EMIOS[10] output channel SIU_ETISR[TSEL0] Figure 6-160. eQADC External Trigger Input Multiplexing MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-117...
Page 293 MTRIG outputs to trigger inputs through the slaves with the last slave MTRIG output connected to the master trigger input. An example of a serial chain is shown in Figure 6-162. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-118 Freescale Semiconductor...
Page 294 SCK output of any of the other three DSPIs. The input source for the trigger input can be the PCSS output of any of the other three DSPIs. The input source for each DSPI SIN, SS, SCK, and trigger signal is individually specified in the DSPI input select register (SIU_DISR). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 6-119...
Page 295: Document Revision History
• Added overbars on IRQ signals and put [ ] around the IRQ variable n in text. Added BASE + 0x18 and Base + 0x1C in the Memory and Register Map Definition section in Table 6-5. MPC5565 Microcontroller Reference Manual, Rev. 1.0 6-120...
Page 296 Table 6-6 SIU_MIDR Field Descriptions: Changed the descriptions of the CSP and PKG fields in the SIU_MIDR register: CSP — Added a note to the CSP description: “Use CSP with PKG to implement calibration functionality.” PKG — Corrected the conditional text in the PCKCFG notes for the MPC5565. Specified the following PKG bit values per product:...
Page 297 Section 6.3.1.44, “Pad Configuration Register 82–75 (SIU_PCR82–SIU_PCR75) Changed order of MDO[11:4]_GPIO[82:75] to MDO[4:11_GPIO[75:82]. Table 6-41 PCR83 PA Field Definitions: Removed TXDA from MPC5565 in the register description and the table entry. Table 6-42 PCR84 PA Field Definitions: Removed RXDA from MPC5565 in the register description and the table entry.
Page 298: Introduction
Table 7-1. XBAR Switch Ports Port Module Master ID Type Number e200z6 core–CPU instruction / data Master 0 e200z6–Nexus Master 0 eDMA Master 1 External bus interface Master 2 Flash Slave 0 — MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 299: Overview
Memory” for information on accessing flash memory) — EBI — Internal SRAM — Peripheral bridge A — Peripheral bridge B • 32-bit address, 64-bit data paths • Fully concurrent transfers between independent master and slave ports MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 300: Modes Of Operation
Base + 0x060F Base + 0x0610 XBAR_SGPCR6 General-purpose control register for slave port 6 Base + 0x0614– — Reserved — Base + 0x06FF Base + 0x0700 XBAR_MPR7 Master priority register for slave port 7 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 301: Register Descriptions
The XBAR_MPR for a slave port sets the priority of each master port when operating in fixed priority mode. They are ignored in round-robin priority mode unless more than one master has been assigned high priority by a slave. NOTE Masters must be assigned unique priority levels. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 302 Master 2 priority. Set the arbitration priority for master port 2 on the associated slave port. MSTR2 This master has the highest priority when accessing the slave port. 010 This master has the lowest priority when accessing the slave port. 011–111 Invalid values Reserved, must be cleared. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 303 Some of the unused bits in the SGPCRn registers are writeable and readable, but they serve no function. Setting any of these bits has no effect on the operation of this module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 304 10 LPP—Low-power park. When no master is making a request, the arbiter parks the slave port on no master and drives all slave port outputs to a safe state. 11 Invalid value MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 305: Functional Description
Outstanding request to slave port A that has a long response time • Pending access to a different slave port B • Lower priority master also makes a request to the different slave port B. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 306: Master Ports
This occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. A requesting master which does not own the slave port is granted access after a one clock delay. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 307: Priority Assignment
The next master in line is granted access to the slave port when the current transfer is completed, or possibly on the next clock cycle if the current master has no pending access request. MPC5565 Microcontroller Reference Manual, Rev. 1.0 7-10 Freescale Semiconductor...
Page 308 However, when a master does make a request to a slave port parked in low-power-park, a one clock arbitration delay is incurred to get ownership of the slave port. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 309: Document Revision History
Figure 7-2 XBAR_MPRn Register: Made MPR3 (not included) and MPR6 (not included) fields visible and read/write. Table 7-5 XBAR_SCPCRn Field Descriptions: Changed ‘Reserved’ values for the Park field to ‘Invalid value’. MPC5565 Microcontroller Reference Manual, Rev. 1.0 7-12 Freescale Semiconductor...
Page 310: Introduction
— The 64 bits and the new ECC bits are written back. To use ECC with SRAM, the SRAM memory must be written to before ECC is enabled. Refer to Section 8.3, “Initialization and Application Information.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 311: Features
The e200z6 core also provides this functionality and is the preferred method for watchdog implementation. Refer to Section 8.2.1.1, “Software Watchdog Timer Control, Service, and Interrupt Registers (ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR).” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 312: Register Descriptions
In many cases, this error termination is reported directly by the initiating bus master. The ECC reporting logic in the ECSM provides an optional error interrupt mechanism to signal non-correctable memory errors. In addition to the interrupt generation, the ECSM MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 313: Ecc Configuration Register (Ecsm_Ecr)
ECC event occurs, the ECSM hardware automatically handles the ECSM_ESR reporting, clearing the previous data and loading the new state and thus guaranteeing that only a single flag is asserted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 314 ECC events, double-bit noncorrectable errors that are terminated with an error response. If an attempt to force a non-correctable error (by asserting ECSM_EEGR[FRCNCI] or ECSM_EEGR[FRC1NCI]) and ECSM_EEGR[ERRBIT] equals 64, then no data error will be generated. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 315 ERRBIT = 64, then ECC Parity[0] is inverted if ERRBIT = 65, then ECC Parity[1] is inverted if ERRBIT = 71, then ECC Parity[7] is inverted For ERRBIT values greater than 71, no bit position is inverted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 316: Flash Ecc Address Register (Ecsm_Fear)
ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and the appropriate flag (FNCE) in the ECSM_ESR to be asserted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 317: Flash Ecc Master Number Register (Ecsm_Femr)
Size. The reset value of this field is undefined. SIZE 000 8-bit System bus access [0:2] 001 16-bit System bus access 010 32-bit System bus access 011 64-bit System bus access 1xx Reserved MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 318 The data captured on a multi-bit non-correctable ECC error is undefined. Base + 0x0058 Access: Read FEDH Reset FEDH Reset “U” signifies a bit that is uninitialized. Figure 8-7. Flash ECC Data High Register (ECSM_FEDRH) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 319 Flash ECC data. Contains the data associated with the faulting access of the last, properly-enabled Flash ECC FEDL event. The register contains the data value taken directly from the data bus. The reset value of this field is undefined. [0:31] MPC5565 Microcontroller Reference Manual, Rev. 1.0 8-10 Freescale Semiconductor...
Page 320: Ram Ecc Address Register (Ecsm_Rear)
ECSM_REMR, ECSM_REAT and ECSM_REDRs, and the appropriate flag (RNCE) in the ECSM_ESR to be asserted. Base + 0x0066 Access: Read REMR Reset “U” signifies a bit that is uninitialized. Figure 8-10. RAM ECC Master Number Register (ECSM_REMR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 8-11...
Page 321: Ram Ecc Attributes Register (Ecsm_Reat)
1xx Reserved Protection: cache. The reset value of this field is undefined. PROT0 0 Non-cacheable 1 Cacheable Protection: buffer. The reset value of this field is undefined. PROT1 0 Non-bufferable 1 Bufferable MPC5565 Microcontroller Reference Manual, Rev. 1.0 8-12 Freescale Semiconductor...
Page 322 RAM ECC data. Contains the data associated with the faulting access of the last, properly-enabled RAM ECC event. REDH The register contains the data value taken directly from the data bus. The reset value of this field is undefined. [0:31] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 8-13...
Page 323: Initialization And Application Information
ECSM registers and an interrupt request is generated on vector 9 of the INTC. If properly enabled, this INTC vector 9 can cause an external interrupt (IVOR4) along with the data storage interrupt (IVOR2). MPC5565 Microcontroller Reference Manual, Rev. 1.0 8-14 Freescale Semiconductor...
Page 324: Document Revision History
(IVOR2) being taken. Document Revision History Table 8-16. Changes Between MPC5565RM Revisions 0.1 and 1 No changes since the Preliminary Version Rev 0 was released in January, 2006. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 8-15...
Page 325 Error Correction Status Module (ECSM) MPC5565 Microcontroller Reference Manual, Rev. 1.0 8-16 Freescale Semiconductor...
Page 326: Introduction
SRAM-based local memory containing the transfer control descriptors (TCD) for the channels. Figure 9-1 is a block diagram of the eDMA module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 327: Features
32-channel implementation performs complex data transfers with minimal intervention from a host processor — 32 bytes of data registers, used as temporary storage to support burst transfers (refer to SSIZE bit) — Connections to the crossbar switch for bus mastering the data movement MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 328: Modes Of Operation
If the signal asserts during a data block transfer as described by a minor loop in the current active channel’s TCD, the eDMA continues the operation until the minor loop completes. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 329: Memory Map And Register Definition
2 priority register Base + 0x0103 EDMA_CPR3 eDMA channel 3 priority register Base + 0x0104 EDMA_CPR4 eDMA channel 4 priority register Base + 0x0105 EDMA_CPR5 eDMA channel 5 priority register MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 330 01 Base + 0x1040 TCD02 eDMA transfer control descriptor 02 Base + 0x1060 TCD03 eDMA transfer control descriptor 03 Base + 0x1080 TCD04 eDMA transfer control descriptor 04 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 331: Register Descriptions
Read operations on reserved bits in a register return undefined data. Do not write operations to reserved bits. Writing to reserved bits in a register can generate errors. The maximum register bit-width for this device is 32-bits wide. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 332 Channel group 1 priority. Group 1 priority level when fixed-priority group arbitration is enabled. GRP1PRI Reserved. Channel group 0 priority. Group 0 priority level when fixed-priority group arbitration is enabled. GRP0PRI 24–27 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 333 If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 334 Note: Do not rely on the number in the ERRCHN field for group and channel priority errors. Group and channel priority errors need to be resolved by inspection. The application code must interrogate the priority registers to find groups or channels with duplicate priority level. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 335 EDMA_SERQR and EDMA_CERQR. The EDMA_CERQR and EDMA_SERQR are provided so that the request enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EDMA_ERQRL. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-10 Freescale Semiconductor...
Page 336 EDMA_EEIRL. Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-11...
Page 337 EDMA_ERQRL to be asserted. Reads of this register return all zeroes. Address: Base + 0x0018 Access: User write-only SERQ[0:6] Reset Figure 9-6. eDMA Set Enable Request Register (EDMA_SERQR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-12 Freescale Semiconductor...
Page 338 EDMA_EEIRL to be set. Setting bit 1 (SEEIn) provides a global set function, forcing the entire contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 339 Description Reserved. 1–7 Clear enable error interrupt. CEEI[0:6] 0–31 Clear corresponding bit in EDMA_EEIRL 32–63 Reserved 64–127 Clear all bits in EDMA_EEIRH or EDMA_EEIRL Note: Bit 2 (CEEI1) is not used. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-14 Freescale Semiconductor...
Page 340 EDMA_ERL to be zeroed, clearing all channel error indicators. Reads of this register return all zeroes. Address: Base + 0x001D Access:User W/O CERR[0:6] Reset Figure 9-11. eDMA Clear Error Register (EDMA_CER) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-15...
Page 341 1–7 Set START bit (channel service request). SSB[0:6] 0–31 Set the corresponding channel’s TCD START bit 32–63 Reserved 64–127 Set all TCD START bits Note: Bit 2 (SSB1) is not used. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-16 Freescale Semiconductor...
Page 342 The EDMA_CIRQR is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the EDMA_IRQRL. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-17...
Page 343 EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CER is provided so the error indicator for a single channel can easily be cleared. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-18 Freescale Semiconductor...
Page 344 A hardware service request for channel n is present. Note: The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore, this status is affected by the EDMA_ERQRL[ERQn] bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-19...
Page 345 The reset value for the group and channel priority fields, GRPPRI[0–1] and CHPRI[0–3] is the channel number for the priority register; EDMA_CPR31[GRPPRI] = 0b01 and EDMA_CPR31[CHPRI] = 0b1111. Figure 9-17. eDMA Channel n Priority Register (EDMA_CPRn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-20 Freescale Semiconductor...
Page 346 CITER or Link Channel Number CITER.LINKCH Word 5 0x1000 + (32 x n) + 167 Current Major Iteration Count CITER 0x1000 + (32 x n) + 176 Destination Address Offset (Signed) DOFF MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-21...
Page 347 Iteration Count is Half Complete 0x1000 + (32 x n) + 254 Channel Interrupt Enable When Current Major INT_MAJ Iteration Count Complete 0x1000 + (32 x n) + 255 Channel Start START MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-22 Freescale Semiconductor...
Page 348 The TCD structures for the eDMA channels shown in Figure 9-18 implemented in internal SRAM. These structures are not initialized at reset. Therefore, all channel TCD parameters must be initialized by the application code before activating that channel. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-23...
Page 349 This value can be applied to “restore” the source address to the initial value, or adjust the address to reference the next data structure. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-24 Freescale Semiconductor...
Page 350 This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32 byte, otherwise a configuration error is reported. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-25...
Page 351 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for four cycles after each r/w 11 eDMA engine stalls for eight cycles after each r/w MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-26 Freescale Semiconductor...
Page 352 EDMA_ERQL bit when the current major iteration count reaches zero. 0 The channel’s EDMA_ERQL bit is not affected. 1 The channel’s EDMA_ERQL bit is cleared when the outer major loop is complete. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-27...
Page 353: Functional Description
After the inner minor loop completes execution, the address path hardware writes the new values for the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-28 Freescale Semiconductor...
Page 354 The hooks to a BIST controller for the local TCD memory are included in this module. — Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM memory array. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-29...
Page 355: Edma Basic Data Flow
The source reads are initiated and the fetched data is temporarily stored in the data path module until it is gated onto the system bus during the destination write. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-30...
Page 356 TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 9-21. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-31...
Page 357: Edma Performance
Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase. • All slave reads require two wait-states, and slave writes three wait-states, again viewed from the system bus data phase. • All slave accesses are 32-bits in size. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-32 Freescale Semiconductor...
Page 358 The first two parts of the activated channel’s TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-33...
Page 359 A general formula to compute the peak request rate (with overlapping requests) is: PEAKreq = freq / [entry + (1 + read_ws) + (1 + write_ws) + exit] where: PEAKreq - peak request rate freq - system frequency MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-34 Freescale Semiconductor...
Page 360: Initialization / Application Information
1. Write the EDMA_CR if a configuration other than the default is desired. 2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers (optional). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-35...
Page 361 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-36 Freescale Semiconductor...
Page 362: Dma Programming Errors
For all error types other than group or channel priority errors, the channel number causing the error is recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-37...
Page 363: Dma Request Assignments
EQADC.FISR2[RFDF2] eQADC Receive FIFO 2 Drain Flag eQADC_FISR3_CFFF3 EQADC.FISR3[CFFF3] eQADC Command FIFO 3 Fill Flag eQADC_FISR3_RFDF3 EQADC.FISR3[RFDF3] eQADC Receive FIFO 3 Drain Flag eQADC_FISR4_CFFF4 EQADC.FISR4[CFFF4] eQADC Command FIFO 4 Fill Flag MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-38 Freescale Semiconductor...
Page 364: Escia_Combtx
‘fixed’ priority of all groups, it is possible for that group to take all the bandwidth of the eDMA controller; that is, no other groups is serviced if there is always at least one MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 365 Within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-40 Freescale Semiconductor...
Page 366: Dma Transfer
4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a) read_byte (0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word (0x2000) -> first iteration of the minor loop MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-41...
Page 367 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-42 Freescale Semiconductor...
Page 368 TCD.CITER = 2 (TCD.BITER). 15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 16. The channel retires -> major loop complete. The eDMA goes idle or services the next channel. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-43...
Page 369: Tcd Status
The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD.CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-44 Freescale Semiconductor...
Page 370: Channel Linking
The TCD.CITER.E_LINK field are used to determine whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the minor loop except for the last. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 371: Dynamic Programming
Enable channel-to-channel linking on major loop Major Loop completion major.linkch Link channel number when linking at end of major loop 9.4.8 Dynamic Programming This section provides recommended methods to change the programming model during channel execution. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-46 Freescale Semiconductor...
Page 372 TCD after that channel’s TCD.DONE bit is set indicating the major loop is complete. NOTE The user must clear the TCD.DONE bit before writing the TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared automatically by the eDMA engine after a channel begins execution. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 9-47...
Page 373: Document Revision History
Added the following phrase to the BWC bit: “To minimize start-up latency, bandwidth control stalls are suppressed for the first two system bus cycles and after the last write of each minor loop.” Corrected address of footnote 2 in Figure 9-18. MPC5565 Microcontroller Reference Manual, Rev. 1.0 9-48 Freescale Semiconductor...
Page 374: Introduction
Although N (maximum number of addressable IRQ vectors) = 231, the total number of interrupts must be a multiple of four. Therefore, the total number of interrupts is 232: 208 peripheral IRQs, 8 software-configurable IRQs, and 16 reserved. Figure 10-1. INTC Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-1...
Page 375: Overview
Memory eDMA FMPLL External IRQ input pins eMIOS eTPU engine A eQADC DSPI eSCI FlexCAN External interrupt e200z6 Interrupt IRQs exception request core controller (INTC) Figure 10-2. INTC Software Vector Mode MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-2 Freescale Semiconductor...
Page 376 232 interrupt vectors. However, the 232 interrupt vector is reserved and is not available. Figure 10-4. Program Flow–Hardware Vector Mode MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-3...
Page 377: Features
1. Although N (maximum number of addressable IRQ vectors) = 231, the total number of interrupts must be a multiple of four. Therefore, the total number of interrupts is 232: 208 peripheral IRQs, 8 software-configurable IRQs, and 16 reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-4...
Page 378 INTC_EOIR contents nor affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR. The timing relationship between popping the LIFO and disabling recognition of external input has no restriction. The writes can happen in either order. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-5...
Page 379: External Signal Description
SIU as external interrupt request input pins. When configured in this function, an interrupt on the pin sets an external interrupt flag. These flags can cause one of five peripheral interrupt requests to the interrupt controller. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-6 Freescale Semiconductor...
Page 380 A channel IRQ[10] External interrupt request — / WKPCFG — / WKPCFG GPIO[136] GPIO ETPUA[23]_ eTPU A channel IRQ[11] External interrupt request — / WKPCFG — / WKPCFG GPIO[137] GPIO MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-7...
Page 381: Memory Map And Register Definition
INTC software set/clear interrupt register 4 Base + 0x0025 INTC_SSCIR5 INTC software set/clear interrupt register 5 Base + 0x0026 INTC_SSCIR6 INTC software set/clear interrupt register 6 Base + 0x0027 INTC_SSCIR7 INTC software set/clear interrupt register 7 MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-8 Freescale Semiconductor...
Page 382: Register Descriptions
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 VTES HVEN Reset 0 Figure 10-7. INTC Module Configuration Register (INTC_MCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-9...
Page 383 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset 0 Figure 10-8. INTC Current Priority Register (INTC_CPR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-10 Freescale Semiconductor...
Page 384 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INTVEC VTBA Reset 0 Figure 10-9. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 0 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-11...
Page 385 Writing a 1 to CLRn clears it. Writing a 0 to CLRn has no effect. If a 1 is written to a pair SETn and CLRn bits at the same time, CLRn is asserted, regardless of whether CLRn was asserted before the write. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-12...
Page 386 Address: Base + 0x0040 + n (INTC_PSRn); n = 0–231 Access: R/W PRIn Reset Figure 10-13. INTC Priority Select Registers (INTC_PSRn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-13...
Page 387: Functional Description
C language syntax. The syntax is ‘module_register[bit].’ Interrupt requests from the same module location or ORed together. The individual interrupt priorities are selected in INTC_PSRn, where the specific select register is assigned according to the vector. Table 10-9. MPC5565 Interrupt Request Sources Hardware Vector...
Page 388 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x00B0 EDMA_IRQRL[INT00] eDMA channel interrupt 0 0x00C0 EDMA_IRQRL[INT01] eDMA channel interrupt 1 0x00D0 EDMA_IRQRL[INT02] eDMA channel interrupt 2 0x00E0 EDMA_IRQRL[INT03] eDMA channel interrupt 3...
Page 389 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x02A0 EDMA_IRQRL[INT31] eDMA channel interrupt 31 0x02B0 FMPLL_SYNSR[LOCF] FMPLL loss-of-clock flag 0x02C0 FMPLL_SYNSR[LOLF] FMPLL loss-of-lock flag 0x02D0 SIU_OSR[OVF15:OVF0] SIU combined overrun interrupt requests of the external interrupt overrun flags 15–0...
Page 390 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0430 ETPU_MCR[MGEA] eTPU global exception ETPU_MCR[MGEB] ETPU_MCR[ILFA] ETPU_MCR[ILFB] ETPU_MCR[SCMMISF] 0x0440 ETPU_CISR_A[CIS0] eTPU engine A channel 0 interrupt status 0x0450 ETPU_CISR_A[CIS1] eTPU engine A channel 1 interrupt status...
Page 391 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0600 ETPU_CISR_A[CIS28] eTPU engine A channel 28 interrupt status 0x0610 ETPU_CISR_A[CIS29] eTPU engine A channel 29 interrupt status 0x0620 ETPU_CISR_A[CIS30] eTPU engine A channel 30 interrupt status...
Page 392 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x07A0 EQADC_FISR4[PF] eQADC command FIFO 4 pause flag 0x07B0 EQADC_FISR4[EOQF] eQADC command FIFO 4 command queue end-of-queue flag 0x07C0 EQADC_FISR4[CFFF] eQADC command FIFO 4 fill flag...
Page 393 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset eSCI 0x0920 Combined interrupt requests of eSCI module A: • LIN status register 1 • LIN status register 2 • SCI status register 2 ESCIA_SR[TDRE] •...
Page 394 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset FlexCAN A, FlexCAN B, and FlexCAN C 0x0980 CANA_ESR[BOFF_INT] FlexCAN A bus off interrupt CANA_ESR[TWRN_INT] FlexCAN A transmit warning interrupt CANA_ESR[RWRN_INT] FlexCAN A receive warning interrupt...
Page 395 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0B40 CANC_IFRL[BUF4] FlexCAN C buffer 4 interrupt 0x0B50 CANC_IFRL[BUF5] FlexCAN C buffer 5 interrupt 0x0B60 CANC_IFRL[BUF6] FlexCAN C buffer 6 interrupt 0x0B70...
Page 396 Interrupt Controller (INTC) Table 10-9. MPC5565 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x11C0 CANB_IFRL[BUF1] FlexCAN B buffer 1 interrupt 0x11D0 CANB_IFRL[BUF2] FlexCAN B buffer 2 interrupt 0x11E0 CANB_IFRL[BUF3] FlexCAN B buffer 3 interrupt 0x11F0...
Page 397: Priority Management
The asserted interrupt requests are compared to each other based on their PRIn values in INTC priority select registers (INTC_PSR0–INTC_PSR231). The result of that comparison also is compared to PRI in MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-24 Freescale Semiconductor...
Page 398 INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 399: Details On Handshaking With Processor
ISR was preempted. Depending on how much the ISR progressed, that interrupt request can no longer be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-26...
Page 400 The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-27...
Page 401: Initialization/Application Information
PRI in INTC_CPR to zero enable processor recognition of interrupts 10.5.2 Interrupt Exception Handler These example interrupt exception handlers use Power Architecture assembly code. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-28 Freescale Semiconductor...
Page 402 ISR for interrupt with vector 510 address of ISR for interrupt with vector 511 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC # return to epilog MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-29...
Page 403: Isr, Rtos, And Task Hierarchy
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-30...
Page 404: Order Of Execution
INTC_EOIR. Interrupt taken. ISR208 starts to execute, even though peripheral interrupt request 300 asserted first. ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-31...
Page 405: Priority Ceiling Protocol
INTC, and as it is aborting transactions and flushing its pipeline, it is possible that both of these stores are executed. ISR2 thereby thinks that it can access the data block coherently, but the data block has been corrupted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-32 Freescale Semiconductor...
Page 406: And Deadlines
Therefore, executing this later portion which does not need to be executed at this higher priority can prevent the execution of ISRs which do not have a higher priority MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 407: Lowering Priority Within An Isr
LIFO can support. Therefore, through its use of the LIFO the INTC does not support lowering the current priority within an ISR as a way to avoid preemptive scheduling inefficiencies. MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-34 Freescale Semiconductor...
Page 408: Negating An Interrupt Request Outside Of Its Isr
LIFO contents provides a coherent view of the preempted priorities. The code sequence is: pop_lifo: store to INTC_EOIR load INTC_CPR, examine PRI, and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-35...
Page 409: Document Revision History
When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo MPC5565 Microcontroller Reference Manual, Rev. 1.0 10-36 Freescale Semiconductor...
Page 410 • From: "This software settable interrupt request, which usually will have a lower PRIn value in the INTC_PSRn, therefore will not cause priority inversion." • To: "This software settable interrupt request, which usually will have a lower PRIn value in the INTC_PSRn, therefore will not cause preemptive scheduling inefficiencies." MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 10-37...
Page 411 IRQs, 8 software-configurable IRQs, and 16 reserved. Table 10-9 MPC5565 Interrupt Sources: Added to column two heading ‘Number’’ after ‘vector’ and table footnote 1 that reads: The vector number is used to identify the interrupt and does not indicate the maximum number of usable interrupt sources.
Page 412: Introduction
Figure 11-3, “FMPLL External Reference Mode” • Figure 11-4, “FMPLL Crystal Reference Mode Without FM” • Figure 11-5, “FMPLL Crystal Reference Mode With FM” • Figure 11-6, “FMPLL Dual-Controller (1:1) Mode” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-1...
Page 413 MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-1. FMPLL Block and Clock Architecture MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-2 Freescale Semiconductor...
Page 414 MDIS eTPU engines MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-2. FMPLL Bypass Mode MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-3...
Page 415 MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-3. FMPLL External Reference Mode MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-4 Freescale Semiconductor...
Page 416 MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-4. FMPLL Crystal Reference Mode without FM MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-5...
Page 417 MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-5. FMPLL Crystal Reference Mode with FM MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-6 Freescale Semiconductor...
Page 418 MDIS CAN Interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-6. FMPLL Dual Controller (1:1) Mode MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-7...
Page 419: Overview
(INTC),” for details. — User-selectable ability to generate a system reset upon loss of clock Refer to Chapter 4, “Reset,” for details. • Self-clocked mode (SCM) operation in event of input clock failure MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-8 Freescale Semiconductor...
Page 420: Fmpll Modes Of Operation
11-7. Example component values are shown as well. Note that the actual circuit should be reviewed with the crystal manufacturer. A block diagram illustrating crystal reference mode is shown in Figure 11-4. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-9...
Page 421 To enter external reference mode, the default FMPLL configuration must be overridden by following the procedure outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block diagram illustrating external reference mode is shown in Figure 11-3. MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-10 Freescale Semiconductor...
Page 422 When configured for dual-controller mode, the CLKOUT clock divider on the slave device must not be changed from its reset state of divide-by-two. Increasing or decreasing this divide ratio produces unpredictable results from the FMPLL. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-11...
Page 423: External Signal Description
Analog power supply (3.3 V 10%) — DDSYN Ground Analog ground — SSSYN In the MPC5565, tie PLLCFG[2] to ground. 11.3 Memory Map/Register Definition Table 11-3 shows the FMPLL memory map locations. Table 11-3. FMPLL Module Memory Map Address Register Name...
Page 424 4–20 MHz. Refer to the device Data Sheet for F prediv values. Note: To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation by tying PLLCFG2 low (set PREDIV to 0b000). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-13...
Page 425 Selection” for more information. In bypass mode, this bit has no effect. LOCEN does not affect the loss of lock circuitry. 0 Loss of clock disabled. 1 Loss of clock enabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-14 Freescale Semiconductor...
Page 426 / (PREDIV +1) 40 ref_ext Note: To avoid unintentional interrupt requests, clear LOLIRQ before changing RATE. Note: F must be between 100–250 MHz. Refer to Section 11.4.3.2, “Programming System Clock Frequency with Frequency Modulation.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-15...
Page 427 Section 11.1.4, “FMPLL Modes of Operation,” for more information.) Reset state determined during reset. Note: “w1c” signifies that this bit is cleared by writing a 1 to it. Figure 11-9. Synthesizer Status Register (FMPLL_SYNSR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-16 Freescale Semiconductor...
Page 428 Chapter 4, “Reset,” for details on how to configure the system clock mode during reset. Refer to Table 11-1 for more information. 0 Dual-controller mode. 1 Crystal reference or external reference mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-17...
Page 429 FMPLL. If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the MPC5565 Microcontroller Data Sheet for the lock/unlock range. 0 PLL is unlocked.
Page 430: Functional Description
The MCU has been designed so that the oscillator clock can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance. Figure 11-1 shows a block diagram of the FMPLL and the system clock architecture. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-19...
Page 431 EBDF bit field in the SIU external clock control register (SIU_ECCR). The reset value of the EBDF selects a CLKOUT frequency of one half of the system clock frequency. The EBI MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-20...
Page 432: Clock Operation
CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR register. Figure 11-1 shows the two clock domains in the FlexCAN modules. Refer to Chapter 21, “FlexCAN2 Controller Area Network” for more information on the FlexCAN modules. 11.4.2 Clock Operation MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-21...
Page 433 LOCKS status bits are negated. While the FMPLL is in an unlocked condition, the system clocks continue to be sourced from the FMPLL as the FMPLL attempts to re-lock. Consequently, during the re-locking MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-22...
Page 434 If the FMPLL clocks have failed, the FMPLL transitions the system clock source to the reference clock. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-23...
Page 435: Clock Configuration
(FMPLL_SYNCR).” The frequency multiplier is determined by the RFD, PREDIV, and multiplication frequency divisor (MFD) bits in FMPLL_SYNCR. Table 11-9 shows the clock-out to clock-in frequency relationships for the possible clock modes. MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-24 Freescale Semiconductor...
Page 436 RFD factor to provide the desired frequency. The maximum MFD value that can be used is determined by the ICO range. Refer to the Data Sheet for the maximum frequency of the ICO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-25...
Page 437 All MCU peripherals, including the external bus are subjected to this frequency sweep. Operation of timers and serial communications during this search sequence produces unpredictable results. MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-26 Freescale Semiconductor...
Page 438 — Write FMPLL_SYNCR[PREDIV] to the desired final value. — Write FMPLL_SYNCR[MFD] to the desired final value. — Write FMPLL_SYNCR[EXP] to the desired final value. — Write FMPLL_SYNCR[RATE] to the desired final value. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-27...
Page 439 8 MHz, the resulting modulation frequency is proportionally skewed. Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than 20%. MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-28 Freescale Semiconductor...
Page 440 (M) based on MFD setting. To obtain a percent modulation (P) of 1%, × × ÷ the EXP field would have to be set at: MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-29...
Page 441 After the last decision is made, the CALDONE bit of the SYNSR is written to a one. If an error occurs during the calibration routine, then CALPASS is immediately written to a zero. If the routine completed successfully then CALPASS remains a one. MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-30 Freescale Semiconductor...
Page 442 Expected Error Count 0 (EXP) (ERR) Reference counter Control counter A–B = Delta count C–D = Error count Figure 11-11. FM Auto-Calibration Data Flow MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 11-31...
Page 443 For MFD = 21 to 31: M = 160 DIFF > 0 PCALPASS = 0 Let ERR = DIFF - EXP ERR > 0 CAL[N] = 0 Figure 11-12. FM Auto-Calibration Flow Chart MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-32 Freescale Semiconductor...
Page 444: Document Revision History
Modified the crystal oscillator network figure to show resistor on the XTAL signal. Section Table 11-5., “FMPLL_SYNSR Field Descriptions: for the LOCK bit description, added: If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the MPC5565 Microcontroller Data Sheet for the lock/unlock range.
Page 445 Frequency Modulated Phase Locked Loop and System Clocks (FMPLL) MPC5565 Microcontroller Reference Manual, Rev. 1.0 11-34 Freescale Semiconductor...
Page 446: Introduction
For an overview of how the EBI used in the MPC5500 differs from the EBI used in MPC500 devices, refer to Section 12.5.6, “Summary of Differences from MPC5xx.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-1...
Page 447: Block Diagram
324 package and the VertiCal assembly. The VertiCal assembly has ball connections for all the available signals on the device. The 324 package has a limited number of balls which affects the following EBI and calibration signals: Table 12-1. MPC5565 324 Package Limitations Features MPC5565 Design 324 Package ADDR[8:11]_GPIO[4:7] no balls available.
Page 448: Overview
Available on the VertiCAL assembly only. Although the MPC5565 is designed to support a 32-bit EBI, not all pins are available on the 324 package. Refer to Table 12-1 for a description of the differences between the device design and package pinouts.
Page 449: Features
Address bus is 32-bit with transfer size indication • 32-bit internal address bus with transfer size indication Table 12-2 shows the address bus packages supported: Table 12-2. Address Bus Sizes in MPC5565 324 BGA 24 bits 20 bits EBI Address Bus Size...
Page 450: Modes Of Operation
EXTM = 1 and MDIS = 0 in the EBI_MCR register. Because the MPC5565 does not have arbitration, the dual-master operation (multiple masters initiating external bus cycles) is not supported. A multi-MCU system with one master and one slave is supported.
Page 451 The internal bus grant input of the EBI is tied to a negated state. Because the MPC5565 does not have transfer size pins (TSIZ[0:1]), the SIZEN and SIZE fields in the EBI_MCR must be used for MCU-to-MCU transfers to indicate transfer size.
Page 452: External Signal Description
Table 12-1 for a description of the differences between the device design and the 324 package limitations. All EBI and calibration signals designed for this device are available on the VertiCal assembly. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-7...
Page 453: Detailed Signal Descriptions
During a calibration bus access, the DATA bus is not driven by the EBI. 12.2.1.3 Burst Data in Progress (BDIP) BDIP is asserted by a master requesting the next data beat to follow the current data beat. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-8 Freescale Semiconductor...
Page 454 If the transaction is a burst read, TA is asserted for each one of the transaction beats. For write transactions, TA is only asserted once at access completion, even if more than one write data beat is transferred. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-9...
Page 455 Section 12.4.1.13, “Four Write/Byte Enable (WE/BE) Signals — VertiCal Assembly” for more details on the WE/BE functionality. 12.2.1.12 Bus Busy (BB), Bus Grant (BG) and Bus Request (BR) The MPC5565 does not implement the BB, BG, or BR signals. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-10 Freescale Semiconductor...
Page 456: Signal Function And Direction By Mode
12.2.1.13 Transfer Size 0 through 1 (TSIZ[0:1]) TSIZ[0:1] indicates the size of the requested data transfer. Because the MPC5565 does not have transfer size pins (TSIZ[0:1]), use the SIZEN and SIZE fields in the EBI_MCR to indicate the transfer size for MCU-to-MCU transfers.
Page 457 Although the device design supports the TEA signal, it is not available on the 324 package. The TEA signal is available for this device on the VertiCal assembly only. The calibration signals for this device are available on the VertiCal assembly only. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-12 Freescale Semiconductor...
Page 458: Memory Map And Register Definition
EBI Calibration Base Register Bank 2 Base + 0x0054 EBI_CAL_OR2 EBI Calibration Option Register Bank 2 Base + 0x0058 EBI_CAL_BR3 EBI Calibration Base Register Bank 3 Base + 0x005C EBI_CAL_OR3 EBI Calibration Option Register Bank 3 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-13...
Page 459: Register Descriptions
The EBI_MCR contains bits that configure various attributes associated with EBI operation. Base (0xC3F8_4000) Access: R/W SIZE SIZEN Reset ACGE EXTM EARB MDIS Reset Figure 12-2. EBI Module Configuration Register (EBI_MCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-14 Freescale Semiconductor...
Page 460 Single master mode (EXTM = 0) only allows internal masters can access internal memory. 0 Single master mode (external master mode disabled) 1 External master mode Note: In the MPC5565, only master/slave systems support the EXTM functionality. Refer to Section 12.5.5, “Dual-MCU Operation with Reduced Pinout MCUs.“...
Page 461 Bus monitor timeout flag. Set if the cycle was terminated by a bus monitor timeout. BMTF 0 No error 1 Bus monitor timeout occurred This bit can be cleared by writing a 1 to it. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-16 Freescale Semiconductor...
Page 462 BME value, the bus monitor is always disabled for chip select accesses, since these always use internal TA and thus have no danger of hanging the system. 0 Disable bus monitor 1 Enable bus monitor (for non-chip select accesses only) 25–31 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-17...
Page 463 EBI to be 4, 8, or 16 according to the port size so that the burst fetches the number of words chosen by BL. 0 8-word burst length 1 4-word burst length MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-18 Freescale Semiconductor...
Page 464 1 This bank is valid. In the case where EBI_MCR[DBM] is set for 16-bit data bus mode, the PS bit value is ignored and is always treated as a 1 (16-bit port). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-19...
Page 465 Values range from 0 to 15. This is the main parameter for determining the length of the cycle. • The total cycle length for the first beat (including the TS cycle): (2 + SCY) external clock cycles Refer to Section 12.5.3.1, “Example Wait State Calculation”. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-20 Freescale Semiconductor...
Page 466: Functional Description
The EBI allows an external master to access internal address space when the EBI is configured for external master mode in the EBI_MCR. External master operations are described in detail in Section 12.4.2.10, “Bus Operation in External Master Mode.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-21...
Page 467 (EBI_CAL_ORn),” for a full description of all chip select attributes. When no match is found on any of the chip select banks, the default transfer attributes shown in Table 12-12 are used. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-22 Freescale Semiconductor...
Page 468 Port Size Configuration per Chip Select (16 or 32 Bits) The EBI supports memories with data widths of 16 or 32 bits. The port size (PS) for a chip select is configured using the PS bit in the base register. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-23...
Page 469 WE[0:1]. WE[0:1] signals are asserted only during write accesses, while BE[0:1] signals are asserted for both read and write accesses. The timing of the WE/BE[0:1] signals remains the same in both cases. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-24 Freescale Semiconductor...
Page 470 16-bit 32-bit Burst TSIZ is not available on the MPC5565. Also applies when DBM = 1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, but for both transactions the WE/BE[0:1] signals are the only WE/BE signals affected.
Page 471: External Bus Operations
The arbitration phase is where bus ownership is requested and granted. This phase is not needed in single master mode because the EBI is the permanent bus owner in this mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-26 Freescale Semiconductor...
Page 472 Mode,” to read how the flow and timing diagrams change for external master mode. 12.4.2.4.1 Single-Beat Read Flow The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-27...
Page 473 Receives data Figure 12-9. Basic Flow Diagram of a Single-Beat Read Cycle CLKOUT ADDR[8:31] RD_WR BDIP DATA[0:31] DATA is valid CS[n] Figure 12-10. Single-Beat 32-bit Read Cycle, CS Access, Zero Wait States MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-28 Freescale Semiconductor...
Page 474 The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. Figure 12-12. Single-Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-29...
Page 475 Receives address Drives data Receives data CS access Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Waits 1 clock stops driving data Figure 12-13. Basic Flow Diagram of a Single-Beat Write Cycle MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-30 Freescale Semiconductor...
Page 476 Figure 12-14. Single-Beat 32-bit Write Cycle, CS Access, Zero Wait States CLKOUT ADDR[8:31] RD_WR BDIP DATA is valid DATA[0:31] Wait state CS[n] WE[0:3] Figure 12-15. Single-Beat 32-bit Write Cycle, CS Access, One Wait State MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-31...
Page 477 TS assertion of the second access. Refer to Section 12.4.2.9, “Termination Signals Protocol,” for more details. Figure 12-17, Figure 12-18, and Figure 12-19 show a few examples of back-to-back accesses on the external bus. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-32 Freescale Semiconductor...
Page 478 Figure 12-17. Back-to-Back 32-bit Reads to the Same CS Bank CLKOUT ADDR[8:31] RD_WR BDIP DATA[0:31] DATA is valid DATA is valid CS[n] CS[y] Figure 12-18. Back-to-Back 32-bit Reads to Different CS Banks MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-33...
Page 479 External Bus Interface (EBI) CLKOUT ADDR[8:31] RD_WR BDIP DATA is valid DATA[0:31] DATA is valid CS[n] Figure 12-19. Write-After-Read to the Same CS Bank MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-34 Freescale Semiconductor...
Page 480 External Bus Interface (EBI) CLKOUT ADDR[8:31] RD_WR BDIP DATA is valid DATA is valid DATA[0:31] CS[n] Figure 12-20. Back-to-Back 32-bit Writes to the Same CS Bank MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-35...
Page 481 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. Refer to Section 12.4.2.11. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-36...
Page 482 Since burst writes are not supported by the EBI , the EBI negates BDIP during write cycles. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. Refer to Section 12.4.2.11. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-37...
Page 483 Asserts transfer acknowledge (TA) Receives data Next -to- last data beat Negate BDIP Drives last data Asserts transfer acknowledge (TA) Receives last data Figure 12-22. Basic Flow Diagram of a Burst Read Cycle MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-38 Freescale Semiconductor...
Page 484 Figure 12-23. Burst 32-bit Read Cycle, Zero Wait States CLKOUT ADDR[8:31] ADDR[29:31] = ‘000’ RD_WR Expects more data BDIP DATA[0:31] DATA is valid Wait state CS[n] Figure 12-24. Burst 32-bit Read Cycle, One Initial Wait State MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-39...
Page 485 Expects more data BDIP DATA[0:31] DATA is valid Wait state Wait state Wait state Wait state CS[n] Figure 12-25. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 0 MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-40 Freescale Semiconductor...
Page 486 In external master mode, this means that the EBI keeps BB asserted and does not grant the bus to another master until the atomic transaction is complete. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-41...
Page 487 The following sections show a few examples of small accesses. The timing for the remaining cases in Table 12-15 can be extrapolated from these and the other timing diagrams in this document. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-42 Freescale Semiconductor...
Page 488 32-bit write to a 16-bit port, requiring two 16-bit external transactions. CLKOUT ADDR[8:31] RD_WR BDIP DATA is valid DATA is valid DATA[0:31] ABCDXXXX EFGHXXXX CS[n] Figure 12-27. Single Beat 32-bit Write Cycle, 16-bit Port Size, Basic Timing MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-43...
Page 489 Four more external accesses (not shown) are required to complete the internal 32-byte request. The timing of these is the same as accesses 1-4 shown in this diagram. Figure 12-28. 32-Byte Write Cycle with External TA, Basic Timing MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-44 Freescale Semiconductor...
Page 490 ADDR[29:31] = ‘000’ ADDR[28:31] = ‘0000’ RD_WR Expects more data BDIP DATA[0:31] DATA is valid DATA is valid CS[n] Figure 12-29. 32-Byte Read with Back-to-Back 16-Byte Bursts to 32-bit Port, Zero Wait States MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-45...
Page 491 The two bytes of a 16-bit operand are OP0 (most significant) and OP1, or OP2 (most significant) and OP3, depending on the address of the access. • The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-46 Freescale Semiconductor...
Page 492 Figure 12-31 shows the device connections on the DATA[0:31] bus. Interface output register DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31] 32-bit port size 16-bit port size Figure 12-31. Interface to Different Port Size Devices MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-47...
Page 493 32-bit OP0/OP2 OP1/OP3 TSIZ is not enabled on the MPC5565. Also applies when DBM = 1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and OP3.
Page 494 External Bus Interface (EBI) 12.4.2.8 Arbitration The MPC5565 does not have arbitration pins, so multi-master operation with arbitration is not supported. However, limited dual-MCU functionality is supported for the case of a Master/Slave system. Refer to Section 12.5.5, “Dual-MCU Operation with Reduced Pinout MCUs.”...
Page 495 Table 12-20. Termination Signals Protocol Action Negated Negated No termination Asserted – Transfer error termination Negated Asserted Normal transfer termination Latched version (1 cycle delayed) used for externally driven TEA and TA. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-50 Freescale Semiconductor...
Page 496 This is the earliest that the EBI can start another transfer, in the case of continuing a set of small accesses. For all other cases, an extra cycle is needed before the EBI can start another TS. Figure 12-32. Termination Signals Protocol Timing Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-51...
Page 497 MCU to an external master (a second MCU) and a shared SDR memory to operate in external master mode. Limited support for external master accesses (master/slave systems only) is available in the MPC5565, refer to Section 12.5.5, “Dual-MCU Operation with Reduced Pinout MCUs.”...
Page 498 EBI responds with a bus error. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. Refer to Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode”. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-53...
Page 499 MCU asserts TA, and the external master can proceed with another external master access, or relinquish the bus. If an address or data error was detected internally, the MCU asserts TEA for one clock. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-54 Freescale Semiconductor...
Page 500 Address in internal memory Other shared device asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Receives data Figure 12-35. Basic Flow Diagram of an External Master Write Cycle (EARB = 1) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-55...
Page 501 If the external master is another MCU with this EBI, then DATA remains valid as shown due to use of latched TA internally. These extra data valid cycles (past TA) are not required by the slave EBI. Figure 12-37. External Master Write to MCU MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-56 Freescale Semiconductor...
Page 502 Drives data CS access Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Receives data Figure 12-38. Basic Flow Diagram of an EBI Read Access in External Master Mode (EARB = 0) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-57...
Page 503 Figure 12-40 shows a 32-bit read from an external master in 16-bit data bus mode. Figure 12-41 shows a 32-bit write from an external master in 16-bit data bus mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-58 Freescale Semiconductor...
Page 504 CLKOUT ADDR[8:31] RD_WR BDIP TS (Input) DATA is valid DATA is valid DATA[0:15] TA (Output) Minimum 3 wait states Figure 12-41. External Master 32-bit Write to MCU with DBM = 1 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-59...
Page 505 Timing for other cases on the calibration bus can similarly be derived from other figures in this document (by replacing CS with CAL_CS). CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid CS[n] CAL_CS[y] Figure 12-42. Back-to-Back 32-bit Reads to CS, CAL_CS Banks MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-60 Freescale Semiconductor...
Page 506: Initialization And Application Information
SDR burst memory. Refer to Figure 12-14 for an example of the timing of a typical single write operation to SDR memory. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-61...
Page 507: Running With Asynchronous Memories
The connections to an asynchronous memory are the same as for a synchronous memory, except that the CLKOUT, TS, and BDIP signals are not used. Figure 12-44 shows a block diagram of an MCU connected to an asynchronous memory. MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-62 Freescale Semiconductor...
Page 508 16-bit asynchronous memory using three wait states. CLKOUT ADDR[8:31] WE[0:1] DATA[0:31] 3 wait states DATA is valid Figure 12-45. Read Operation to Asynchronous Memory, Three Initial Wait States MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-63...
Page 509 16-bit asynchronous memory using three wait states. CLKOUT ADDR[8:31] WE[0:1] DATA is valid DATA[0:31] 3 wait states Figure 12-46. Write Operation to Asynchronous Memory, Three Initial Wait States MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-64 Freescale Semiconductor...
Page 510: Connecting An Mcu To Multiple Memories
This scenario is straightforward. Simply connect DATA[0:15] between both MCUs, and configure both for 16-bit data bus mode operation (DBM = 1 in EBI_MCR). This configuration does not support 32-bit external memories. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-65...
Page 511 To implement a master/slave system with an MCU that has no arbitration pins (for example, in the MPC5565 that has no BB, BG, BR), the user must configure the master MCU for internal arbitration (EARB = 0 in EBI_MCR) and the slave MCU for external arbitration (EARB = 1). Internally on an MCU with no arbitration pins, the external signals to the EBI will be tied negated.
Page 512: Summary Of Differences From Mpc5Xx
Calibration features implemented by three calibration chip selects • Removed support for 3-master systems • Address decoding for external master accesses uses 4-bit code to determine internal slave instead of straight address decode MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 12-67...
Page 513: Document Revision History
Section 12.4.1.9, “Port Size Configuration per Calibration Chip Select (16 Bits): Conditionalized for 496 assembly only. Section 12.2.1.13, “Transfer Size 0 through 1 (TSIZ[0:1]): Added: Because the MPC5565 does not have transfer size pins (TSIZ[0:1]), the SIZEN and SIZE fields of the EBI_MCR must be used for MCU-to-MCU transfers to indicate transfer size.
Page 514 • Figure 12-1 MPC5565 EBI Connections: Added the following footnotes: Although the MPC5565 is designed to support a 32-bit EBI, not all pins are available on the 324 package. Refer to Table 12-1 for a description of the differences between the device design and package pinouts.
Page 515 External Bus Interface (EBI) MPC5565 Microcontroller Reference Manual, Rev. 1.0 12-70 Freescale Semiconductor...
Page 516: Introduction
Flash BIU contains a two-entry prefetch buffer, each entry containing 256 bits of data, and an associated controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 517 Flash Array Blocks Low address space —256 KB Low address space Mid address space —256 KB Mid address space High address space — 1.5 MB High address space Figure 13-2. Flash Array Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-2 Freescale Semiconductor...
Page 518: Features
Section 13.4.2, “Flash Memory Array: User Mode.” 13.1.4.2 Stop Mode In stop mode (FLASH_MCR[STOP] = 1), all DC current sources in the flash are disabled. Refer to Section 13.4.3, “Flash Memory Array: Stop Mode.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-3...
Page 519: External Signal Description
The access time of the internal flash is lengthened based on the address range being accessed. To access an area with a slower access time, the address is modified per Table 13-2. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-4 Freescale Semiconductor...
Page 520: Flash Memory Map
Array base + 0x0003_FFFF Array base + 0x0004_0000– Mid address space (256 KB) User Array base + 0x0007_FFFF Array base + 0x0008_0000– High address space (1.5 MB) User Array base + 0x001F_FFFF MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-5...
Page 521 128 KB Array base + 0x0016_0000 128 KB Array base + 0x0018_0000 128 KB Array base + 0x001A_0000 128 KB Array base + 0x001C_0000 128 KB Array base + 0x001E_0000 128 KB MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-6 Freescale Semiconductor...
Page 522 FLASH_BIUCR Flash bus interface unit control register Register base + 0x0020 FLASH_BIUAPR Flash bus interface unit access protection register Register base + 0x30 to — Reserved — Register base + 0x7FFF MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-7...
Page 523: Register Descriptions
110 The LAS value of 110 provides two 16-KB blocks, two 48-KB blocks, and two 64-KB blocks. 12–14 Reserved. Mid address space size. Corresponds to the configuration of the mid address space. MAS is read only. 0 Two 128-KB blocks are available MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-8 Freescale Semiconductor...
Page 524 In STOP mode all address spaces, registers, and register bits are deactivated except for the FLASH_MCR[STOP] bit. 0 Flash is not in stop mode; the read state is active. 1 Flash is in stop mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-9...
Page 525 The flash module cannot exit erase suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0 Erase sequence is not suspended. 1 Erase sequence is suspended. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-10 Freescale Semiconductor...
Page 526 (FLASH_MCR).” The write locks detailed in that section do not consider the effects of trying to write two or more bits simultaneously. The effects of writing bits simultaneously which would put the flash module in an illegal state are detailed here. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-11...
Page 527 The reset value of these bits is determined by flash values in the shadow row. Erasing the array sets the reset value to 1. Figure 13-6. Low/Mid Address Space Block Locking Register (FLASH_LMLR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-12...
Page 528 LLOCK bits are used, if a configuration has sixteen 16-KB blocks in the low address space (MCR-LAS = 3’b011), the block residing at address array base + 0, corresponds to LLOCK0. The next 16-KB block corresponds to LLOCK1, and so on up to LLOCK15. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-13...
Page 529 LMLOCK field (FLASH_LMLR), determine if the block is locked from program or erase. An “OR” of FLASH_LMLR and FLASH_SLMLR determine the final lock status. Refer to Section 13.3.2.2, “Low/Mid Address Space Block Locking Register (FLASH_LMLR)” for more information on FLASH_LMLR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-14 Freescale Semiconductor...
Page 530 (FLASH_LMLR). SLLOCK is not writable unless SLE is high. In the event that blocks are not present (due to configuration or total memory size), the SLLOCK bits default to locked, and are not writable. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-15...
Page 531 Three low address space blocks are selected for erase 0b1111 Four low address space blocks are selected for erase 0b0001_1111 Five low address space blocks are selected for erase 0b0011_1111 Six low address space blocks are selected for erase MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-16 Freescale Semiconductor...
Page 532 Access: R/W 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR Reset 0 Figure 13-11. Address Register (FLASH_AR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-17...
Page 533 0 No prefetching can be triggered by this master 1 Prefetching can be triggered by this master These fields are identified as follows: M3PFE= EBI M2PFE= eDMA M1PFE= Nexus M0PFE= MCU core MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-18 Freescale Semiconductor...
Page 534 00 No prefetching is triggered by an instruction read access 01 Prefetching can be triggered only by an instruction burst read access 10 Reserved 11 Prefetching can be triggered by any instruction read access MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-19...
Page 535 For maximum flash performance, set to 0b1. This setting allows for 100 MHz system clock with 2% frequency modulation. This setting allows for 130 MHz system clock with 2% frequency modulation. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-20 Freescale Semiconductor...
Page 536: Functional Description
Several prefetch control algorithms are available for controlling line read buffer fills. Prefetch triggering can be restricted to instruction accesses only, data accesses only, or can be unrestricted. Prefetch triggering can also be controlled on a per-master basis. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-21...
Page 537 When an error response is received, the Flash BIU marks a line read buffer as invalid. An error response can be signaled on read or write operations. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-22 Freescale Semiconductor...
Page 538 Prefetch triggering can be enabled for data reads. Triggering can be enabled for all data reads or only for data burst reads. Prefetches are not triggered by write cycles. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 539: Flash Memory Array: User Mode
The read state is active when FLASH_MCR[PGM] = 1 and/or FLASH_MCR[ERS] = 1 and high voltage operation is ongoing (read while write). NOTE Reads done to the partitions being operated on (either erased or programmed) result in an errors and the FLASH_MCR[RWE] bit is set. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-24 Freescale Semiconductor...
Page 540 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user can program the values in any or all of eight words within a page in a single program sequence. Word addresses are selected using bits 4:2 of the page-bound word. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-25...
Page 541 An interlock write must be performed before setting FLASH_MCR[EHV]. The user can terminate a program sequence by clearing FLASH_MCR[PGM] prior to setting FLASH_MCR[EHV]. If multiple writes are done to the same location the data for the last write is used in programming. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-26 Freescale Semiconductor...
Page 542 The user cannot abort a program sequence while in program suspend. WARNING Aborting a program operation leaves the flash core addresses being programmed in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-27...
Page 543 Note: PEG remains valid under this condition until EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 ESUS User mode read state Erase suspend Figure 13-14. Program Sequence MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-28 Freescale Semiconductor...
Page 544 FLASH_LMSR or FLASH_HSR. If the shadow row is to be erased, this step can be skipped, and FLASH_LMSR and FLASH_HSR are ignored. For shadow row erase, refer to section Section 13.4.2.5, “Flash Shadow Block” for more information. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-29...
Page 545 During suspend, all reads to flash core locations targeted for program and blocks targeted for erase return indeterminate data. Programming locations in blocks targeted for erase during erase-suspended program can result in corrupted data. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-30 Freescale Semiconductor...
Page 546 This can extend the time required for the erase operation. WARNING In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase can corrupt flash core data. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-31...
Page 547 Note: PEG remains valid under this condition until EHV is set high or ERS is cleared. Step 9 Write MCR ERS = 0 User mode read state Figure 13-15. Erase Sequence MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-32 Freescale Semiconductor...
Page 548 The flash module latches the value of the control word prior to the negation of system reset. Censorship logic uses the value latched in the flash module to disable access to internal flash, disable the NDI, prevent modification of the FLASH_BIUAPR bitfields, and/or set the boot default value. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-33...
Page 549 The Nexus port controller is held in reset when in censored mode. The FBIU returns a bus error if an access is attempted while flash access is disabled. Flash access is any read, write or execute access. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-34 Freescale Semiconductor...
Page 550: Flash Memory Array: Stop Mode
FLASH_MCR[PGM] = 1 or FLASH_MCR[ERS] = 1. In stop mode all DC current sources in the flash module are disabled. Stop mode is exited by clearing the FLASH_MCR[STOP] bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-35...
Page 551: Flash Memory Array: Reset
After reset is negated, register accesses can be performed, although registers that require updating from shadow information, or other inputs, cannot read updated values until flash exits reset. FLASH_MCR[DONE] can be polled to determine if reset has been exited. MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-36 Freescale Semiconductor...
Page 552: Revision History
FBIU and are forwarded to the system bus on the following cycle,...” Section 13.1.3, “Features”: Changed 2nd bulletted list, fourth bullet to “Page program size of 256 bits allows programming from one to four consecutive 64-bit doublewords within a page.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 13-37...
Page 553 Flash Memory MPC5565 Microcontroller Reference Manual, Rev. 1.0 13-38 Freescale Semiconductor...
Page 554: Introduction
External Signal Description The external signal for SRAM is the V RAM power supply. If the standby feature of the SRAM is STBY not used, tie the V pin to V STBY MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 14-1...
Page 555: Register Memory Map
1. The ECC mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or flagging errors. 2. The write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data bus. MPC5565 Microcontroller Reference Manual, Rev. 1.0 14-2 Freescale Semiconductor...
Page 556: Access Timing
Pipelined read Read Idle Pipelined read 1,0,0,0 Burst read 64-bit write 2,0,0,0 Burst read 0,0,0,0 (read from the same address) 8-, 16-, or 32-bit write 1,0,0,0 (read from a different address) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 14-3...
Page 557: Reset Effects On Sram Accesses
If the write is not the entire 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is generated that checks the ECC value upon the read. Refer to Section 14.6, “SRAM ECC Mechanism.” NOTE You must initialize SRAM, even if the application does not use ECC reporting. MPC5565 Microcontroller Reference Manual, Rev. 1.0 14-4 Freescale Semiconductor...
Page 558: Example Code
# inc the ram ptr; 32 GPRs * 4 bytes = 128 bdnz init_ram_loop # loop for 80k of SRAM # done 14.8 Document Revision History Table 14-4. Changes Between MPC5565RM Revisions 0.1 and 1 No changes since the last release. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 14-5...
Page 559 SRAM MPC5565 Microcontroller Reference Manual, Rev. 1.0 14-6 Freescale Semiconductor...
Page 560: Introduction
MCU resources to start application code execution. Figure 15-1 is a block diagram of the BAM. Peripheral bridge B control block Figure 15-1. BAM Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-1...
Page 561: Features
This mode of operation can load a user program into internal SRAM using either the eSCI or FlexCAN serial interface, then to execute the downloaded program. The program can then control the downloading of data, as well as erasing and programming the internal or external flash memory. MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-2 Freescale Semiconductor...
Page 562: Memory Map
MMU allows core access to MCU internal resources and the EBI • EBI registers and external bus pads, when using external boot modes • FlexCAN A, eSCI A and their pads, when using serial boot mode MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-3...
Page 563: Bam Program Operation
Enables or disables internal flash memory • Enables or disables the Nexus port • Compares the password received in serial boot mode to a preset public password or a programmable password located in internal flash MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-4 Freescale Semiconductor...
Page 564 Censorship control field–default value configures the device as uncensored. Address: 0x00FF_FDE2 Value: 0x55AA Binary value Hex value Serial boot control field–default value reads a password from internal flash. Figure 15-2. Censorship Word MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-5...
Page 565 16-bit reset configuration halfword (RCHW). If a valid RCHW is read, the BAM program sets the e200z6 watchdog timer enable bit RCHW[WTE]. If a valid RCHW is not read, the BAM program proceeds to serial boot mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-6 Freescale Semiconductor...
Page 566 15-5, the BAM program sets up two MMU regions differently than in internal flash boot mode (refer to Table 15-2). The internal flash logical addresses are mapped to the physical addresses of the EBI. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-7...
Page 567 EBI for no external master (clears EXTM bit) • Enables the EBI for normal operation • Configures the following EBI signals: — ADDR[8:31] — DATA[0:15] — WE[0] — OE — TS — CS[0] MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-8 Freescale Semiconductor...
Page 568 If serial boot mode is entered indirectly from external boot/single-master because no valid RCHW was found, then the MMU and EBI are configured the for an external boot mode with a 16-bit data bus. Refer to Table 15-3 Table 15-5 for more information. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-9...
Page 569 All data received, regardless of errors, is echoed out on the CNTXA signal. NOTE The host computer must compare the ‘echoed data’ to the sent data and restart the process if an error is detected. MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-10 Freescale Semiconductor...
Page 570 Upon receiving a valid FlexCAN message with an ID equal to 0x011 that contains 8 data bytes, or a valid eSCI message, the BAM uses a serial boot submode: FlexCAN serial boot mode, or eSCI serial boot mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 571 The 64-bit password is validated to ensure that none of the four 16-bit halfwords have a value of 0x0000 or 0xFFFF, which are invalid passwords. A valid password must have at least one 0 and one 1 in each halfword lane. MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-12 Freescale Semiconductor...
Page 572 The host computer must not send another FlexCAN message until it receives the echo from the previous message. A FlexCAN message sent before the echo is received is ignored. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-13...
Page 573 The eSCI serial boot mode download process contains the following steps: 1. Download the 64-bit password. 2. Download the start address, VLE flag, and the number of data bytes to download. 3. Download the data. MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-14 Freescale Semiconductor...
Page 574 For each valid eSCI message received, the BAM transmits the same data on the TXDA signal. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-15...
Page 575: Interrupts
ESCI_A_CR2[MDIS] instead of negates. Then the BAM branches to the starting address of the stored data specified in step 2. 15.3.3 Interrupts No interrupts are generated or enabled by the BAM. MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-16 Freescale Semiconductor...
Page 576: Revision History
Added: Set the VLE bit in the serial download data (most significant bit in the LENGTH word) if the code to download uses VLE instructions. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 15-17...
Page 577 Boot Assist Module (BAM) MPC5565 Microcontroller Reference Manual, Rev. 1.0 15-18 Freescale Semiconductor...
Page 578: Introduction
Chapter 16 Enhanced Modular Input/Output Subsystem (eMIOS) 16.1 Introduction This chapter describes the enhanced modular input/output subsystem (eMIOS) which can generate or measure timed events. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-1...
Page 579 Note 1: Connection between UC[n-1] and UCn necessary to implement QDEC mode. Note 2: On channels 12–15, there is no input from EMIOS[12:15], only from the DSPI module. Figure 16-1. eMIOS Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-2 Freescale Semiconductor...
Page 580: Overview
Synchronization among internal and external time bases • Shadow FLAG register • State of module can be frozen for debug purposes • DMA request capability for some channels • Motor control capability MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-3...
Page 581: Emios Operating Modes
• Center-aligned output pulse-width modulation with dead time insertion, buffered • Output pulse-width modulation, normal • Output pulse-width modulation, buffered These modes are described in Section 16.4.4.4, “Unified Channels Operating Modes.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-4 Freescale Semiconductor...
Page 582: External Signal Description
A value of 0 refers to the reset value of the signal. Hi-Z refers to the state of the external pin if a tri-state output buffer is controlled by the corresponding eMIOS signal. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 583: Memory Map/Register Definition
Output update disable register Base + 0x000C–Base + 0x001F — Reserved — Base + 0x0020 Unified channel 0 registers Base + 0x0040 Unified channel 1 registers Base + 0x0060 Unified channel 2 registers MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-6 Freescale Semiconductor...
Page 584 EMIOS_CCRn Channel control register UCn Base + 0x0010 EMIOS_CSRn Channel status register UCn Base + 0x0014 EMIOS_ALTAn Channel alternate address register UCn Base + 0x18–UCn Base + 0x1F — Reserved — MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-7...
Page 585: Register Description
1 Global time base enable out signal asserted Note: The global time base enable input signal controls the internal counters. When asserted, internal counters are enabled. When negated, internal counters disabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-8 Freescale Semiconductor...
Page 586 These bits are mirrors of the FLAG bits of each channel register (EMIOS_CSR) and flag bits in those channel registers cannot be cleared by accessing this ‘mirror’ register. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-9...
Page 587 B2. OUn bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel. 0 Transfer enabled. Depending on the operating mode, transfer occurs immediately or in the next period. Unless stated otherwise, transfer occurs immediately. 1 Transfers disabled MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-10 Freescale Semiconductor...
Page 588 The EMIOS_CBDRn must not be read speculatively. For future compatibility, the TLB entry covering the EMIOS_CBDRn must be configured to be guarded. Address: UCn Base + 0x0004 Access: R/W Reset Reset Figure 16-6. eMIOS Channel B Data Register (EMIOS_CBDRn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-11...
Page 589 — OPWMC – normal — OPWMC – buffered — OPWM – normal — OPWM – buffered — In these modes, the register EMIOS_CBDRn is not used, but B2 can be accessed. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-12 Freescale Semiconductor...
Page 590 DMA request enabling, and output mode control. Address: UCn Base + 0x000C Access: R/W FREN ODIS ODISSL UCPRE Reset EDSEL EDPOL MODE FORCMA FORCMB Reset Figure 16-8. eMIOS Channel Control Register (EMIOS_CCRn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-13...
Page 591 Prescaler. Selects the clock divider value for the unified channel internal prescaler, as shown in the following UCPRE[0:1] table: UCPRE[0:1] Divide Ratio Prescaler enable. Enables the prescaler counter. UCPREN 0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value 1 Prescaler enabled MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-14 Freescale Semiconductor...
Page 592 DMA request Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt DMA request Interrupt DMA request Interrupt DMA request Interrupt DMA request Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt Reserved Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-15...
Page 593 B, otherwise it has no effect. 0 Has no effect 1 Force a match at comparator B For input modes, the FORCMB bit is not used and writing to it has no effect. Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-16 Freescale Semiconductor...
Page 594 For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 0 The EDPOL value is transferred to the output flip-flop 1 The output flip-flop is toggled MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-17...
Page 595 0000101 Input period measurement 0000110 Double-action output compare (with FLAG set on the second match) 0000111 Double-action output compare (with FLAG set on both match) 0001000 Pulse and edge accumulation (continuous) MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-18 Freescale Semiconductor...
Page 596 Output pulse-width modulation. FLAG set at match of internal counter and comparator B, next period update. 0100010 Output pulse-width modulation. FLAG set at match of internal counter and comparator A or comparator B, immediate update. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-19...
Page 597 Center-aligned output pulse-width modulation, buffered. FLAG set on both edges, leading edge dead-time. 1100000 Output pulse-width modulation, buffered. FLAG set on second match. 1100001 Reserved 1100010 Output pulse-width modulation, buffered. FLAG set on both matches. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-20 Freescale Semiconductor...
Page 598 FLAG. Set when an input capture or a match event in the comparators occurs. Write a 1 to clear this bit to 0. FLAG 0 FLAG cleared 1 FLAG set event has occurred Note: When EMIOS_CCR[DMA] bit is set, the FLAG bit is cleared by the eDMA controller. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-21...
Page 599: Functional Description
0 to 7 can share counter bus A and B, UCs 8 to 15 can share counter bus A and C, and UCs 16 to 23 can share counter buses A and D. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-22...
Page 600: Bus Interface Unit (Biu)
The time slot sequence is 0-1-2-3, such that they alternate between engines one and two. Table 16-13. STAC Client Submodule Server Slot Assignment Engine Time Base Server ID TCR1 TCR2 TCR1 TCR2 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-23...
Page 601: Global Clock Prescaler Submodule (Gcp)
Counting is enabled by setting EMIOS_MCR[GPREN]. The counter can be stopped at any time by clearing this bit, thereby stopping the internal counter in all the unified channels. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-24 Freescale Semiconductor...
Page 602: Unified Channel (Uc)
• Control state machine (FSM) The major components and functions of the unified channels are discussed in Section 16.4.4.1, “Programmable Input Filter (PIF)” through Section 16.4.4.4, “Unified Channels Operating Modes.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-25...
Page 603 D for channels 16-23. Refer to Figure 1-1 and EMIOS_CCRn[BS]. 2. Goes to the finite state machine of the UC[n-1]. These signals are used for QDEC mode. Figure 16-13. Unified Channel Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-26 Freescale Semiconductor...
Page 604 A timing diagram of the input filter is shown in Figure 16-15. Selected clock EMIOSn 5-bit counter IF = 0b0011 Time Filter out Figure 16-15. Programmable Input Filter Example MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-27...
Page 605 Section 16.4.4.4.1, “General Purpose Input/Output Mode (GPIO)” through Section 16.4.4.4.14, “Output Pulse-Width Modulation Mode (OPWM) Section 16.4.4.4.18, “Output Pulse-Width Modulation, Buffered Mode (OPWMB)” explain in detail the unified channels’ modes of operation. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-28 Freescale Semiconductor...
Page 606 Register EMIOS_CADRn returns the value of register A2. The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL and EDSEL bits in EMIOS_CCR MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-29...
Page 607 EMIOS_CADRn returns the value of register A1. An output compare match can be simulated in software by setting the FORCMA bit in EMIOS_CCRn. In this case, the FLAG bit is not set. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-30 Freescale Semiconductor...
Page 608 B1 and the trailing edge on register A2. Successive captures are done on consecutive edges of opposite polarity. The leading edge sensitivity (pulse polarity) is selected by EDPOL bit in the MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 609 After input filter. Reading EMIOS_CADRn returns the value of A2, writing EMIOS_CADRn writes to A2. Reading EMIOS_CBDRn returns the value of B1, writing EMIOS_CBDRn writes to B1. Figure 16-19. Input pulse-width Measurement Example MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-32 Freescale Semiconductor...
Page 610 The IPM mode allows the measurement of the period of an input signal by capturing two consecutive rising edges or two consecutive falling edges. Successive input captures are done on consecutive edges of the same polarity. The edge polarity is defined by the EDPOL bit in the EMIOS_CCRn. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-33...
Page 611 A1 value 0xxxxxxx 0xxxxxxx 0x001000 0x001250 Notes: After input filter. Reading EMIOS_CADRn returns the value of A2. Reading EMIOS_CBDRn returns the value of B1. Figure 16-21. Input Period Measurement Example MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-34 Freescale Semiconductor...
Page 612 B2 must occur and the EMIOS_CCRn[ODIS] bit must be cleared. The output flip-flop is set to the value of EMIOS_CCRn[EDPOL] when a match occurs on comparator A and to the complement of EDPOL when a match occurs on comparator B. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-35...
Page 613 A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 16-23. Double Action Output Compare with FLAG Set on the Second Match MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-36 Freescale Semiconductor...
Page 614 EMIOS_CADRn and EMIOS_CBDRn reads do not return coherent data until a new bus capture is triggered to registers A2 and B2. The capture event is indicated when the channel FLAG asserts. If enabled, the FLAG also generates an inter- rupt. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-37...
Page 615 Cleared on the first input event after writing to register A1. After input filter. Writing EMIOS_CADRn writes to A1. Reading EMIOS_CADRn returns the value of A2. Reading EMIOS_CBDRn returns the value of B1. Figure 16-25. Pulse/Edge Accumulation Continuous Mode Example MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-38 Freescale Semiconductor...
Page 616 A1, when a match occur between comparator A and the selected timebase, the internal counter is cleared and it is ready to start counting input events. When the time base matches comparator B1, the MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 617 0x000303 0x000303 EMIOS_CCNTRn EMIOS_CCNTRn A2 value Notes: Writing EMIOS_CADRn writes to A1. Writing EMIOS_CBDRn writes to B1. Reading EMIOS_ALTAn returns the value of A2. Figure 16-27. Pulse/Edge Counting Continuous Mode Example MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-40 Freescale Semiconductor...
Page 618 UCn EDPOL bit selects count direction according to direction signal and UC[n-1] EDPOL bit selects if the internal counter is clocked by the rising or falling edge of the count signal. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 619 A1 match A1 match EMIOS_CCNTRn Value 2 Value 1 0x000000 Time FLAG set event Note: Writing EMIOS_CADRn writes to A1. Figure 16-30. Quadrature Decode Mode Example with Phase_A and Phase_B Encoder MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-42 Freescale Semiconductor...
Page 620 In WPTA mode this register is accessible through the alternate register address EMIOS_ALTAn. NOTE The FORCMA and FORCMB bits have no effect when the unified channel is configured for WPTA mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-43...
Page 621 B1, internal clock source. 0b0010101 Modulus counter. Up/down counter, no change in counter direction upon match of input counter and register B1, external clock source. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-44 Freescale Semiconductor...
Page 622 MC mode. NOTE Any update to the A register takes place immediately, regardless of the current state of the counter and whether the counter is in up mode, or up/down mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-45...
Page 623 A1 value 0xxxxxxx 0x000303 0x000303 0x000200 0x000200 0x000200 Notes: Writing EMIOS_An writes to A2. A2 value transferred to A1 according to OUn bit. Figure 16-33. Modulus Counter Up/Down Mode Example MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-46 Freescale Semiconductor...
Page 624 1. If not currently stored, store value of register A. 2. Set A=B. 3. If immediate 0% duty cycle is desired, set FORCA=1. 4. To return to the previous duty cycle, restore register A with its former value. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-47...
Page 625 Writing EMIOS_An writes to A2. Writing EMIOS_Bn writes to B2. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 16-34. OPWFM with Immediate Update MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-48 Freescale Semiconductor...
Page 626 Writing EMIOS_An writes to A2. Writing EMIOS_Bn writes to B2. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 16-35. OPWFM with Next Period Update MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-49...
Page 627 Table 16-25. Examples of Output Waveforms EDPOL Duty Cycle Waveform (decimal) (decimal) 1000 1000 1000 1000 Active high output 1000 100% 1000 1000 1000 1000 1000 Active low output 1000 100% 1000 MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-50 Freescale Semiconductor...
Page 628 EDPOL bit and the time base is switched to the selected counter bus. This sequence repeats continuously. FLAG can be generated in the trailing edge of the output PWM signal when MODE[5] is cleared, or in both edges, when MODE[5] is set. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-51...
Page 629 MODE[5] bit. NOTE If A1 and B1 are set to the 0x000000, a 0% duty cycle waveform is produced. NOTE Any updates to the A or B register takes place immediately. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-52 Freescale Semiconductor...
Page 630 Writing EMIOS_Bn writes to B1. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 16-36. Output PWMC with Leading Dead-time Insertion MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-53...
Page 631 Output pulse-width modulation. FLAG set at match of internal counter and comparator A or comparator B, immediate update. 0b0100011 Output pulse-width modulation. FLAG set at match of internal counter and comparator A or comparator B, next period update. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-54 Freescale Semiconductor...
Page 632 NOTE Updates to the A register always occur immediately. If next period update is selected via the mode[6] bit, only the B register update is delayed until the next period. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-55...
Page 633 Writing EMIOS_Bn writes to B2. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 16-39. Output PWM with Next Period Update MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-56 Freescale Semiconductor...
Page 634 The MCB mode counts between one and the A1 register value. The counter cycle period in up count mode is equal to the A1 value. In up/down counter mode the period is defined by the formula: (2 × A1) – 2. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 635 FLAG set event 0x000005 0x000007 A2 value A1 value 0x000006 0x000005 0x000007 Note: A2 value transferred to A1 according to OUn bit. Figure 16-41. eMIOS MCB Mode Example — Up/Down Operation MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-58 Freescale Semiconductor...
Page 636 Note: A2 value transferred to A1 according to OUn bit (the transfer is triggered by the A1 load signal). Figure 16-43. eMIOS MCB Mode Example — Up/Down Operation A1 Register Update MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-59...
Page 637 For example, if register A1 is set to 0x000004, the output flip-flop transitions 4 counter periods after the cycle starts, plus one system clock cycle. In the example shown in Figure 16-44 the prescaler ratio is set to two (refer to Section 16.5.3, “Time Base Generation). MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-60 Freescale Semiconductor...
Page 638 Edge detection B1 match B1 match negative edge detect B1 match negative Edge detection Output flip-flop EDPOL = 0 Figure 16-44. eMIOS OPWFMB Mode Example — A1/B1 Match to Output Register Delay MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-61...
Page 639 B1 match negative B1 Match negative edge detect edge Detection Output flip-flop No transition at this point EDPOL = 0 Figure 16-45. eMIOS OPWFMB Mode Example — A1 = 0 (0% Duty Cycle) MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-62 Freescale Semiconductor...
Page 640 A1/B1 load signal 0x000004 0x000006 A1 value 0x000002 0x000002 0x000004 0x000006 A2 value B1 value 0x000008 0x000006 B2 value 0x000008 0x000006 Figure 16-46. eMIOS OPWFMB Mode Example — A1/B1 Updates and Flags MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-63...
Page 641 A or B respectively. Similar to a B1 match, FORCMB clears the internal counter. The FLAG bit is not set when the FORCMA or FORCMB bits are set. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-64...
Page 642 Register A1 contains the ideal duty cycle for the PWM signal and is compared with the selected time base. Register B1 contains the dead time value and is compared against the internal counter. For a leading edge MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 643 B1 and the internal time base, the output flip-flop is set to the value of the EDPOL bit. In the following match between A1 and the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-66 Freescale Semiconductor...
Page 644 Internal counter is set to 1 on A1 match 0x000004 0x000002 0x000001 Time Dead-time Dead-time Output flip-flop FLAG set event Figure 16-50. eMIOS PWMCB Mode Example — Lead Dead Time Insertion MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-67...
Page 645 FORCMA sets the output flip-flop to the compliment of EDPOL. In trailing dead time insertion mode, the output flip-flop is forced to the value of EDPOL. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-68 Freescale Semiconductor...
Page 646 (n+1). In this case the B1 match is masked out and does not cause the output flip-flop to transition. Therefore matches in cycle (n+1) are not affected by the late B1 matches from cycle (n). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 647 A1 or B1. Refer to Figure 16-44, which illustrates the delay from matches to output flip-flop transition in OPWFMB mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-70 Freescale Semiconductor...
Page 648 Values written to A2 or B2 on cycle (n) are loaded to A1 or B1 at the following cycle boundary (assuming EMIOS_OUDR[n] is not asserted). Thus the new values are used for A1 and B1 matches in cycle (n+1). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-71...
Page 649 A1 being set to zero in cycle (n+1). In this case the match positive edge is used instead of the negative edge to transition the output flip-flop. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-72 Freescale Semiconductor...
Page 650 B1 match B1 match negative B1 match negative edge detect edge detection Output flip-flop EDPOL = 0 FLAG bit set Figure 16-54. eMIOS OPWMB Mode Example — 0% Duty Cycle MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-73...
Page 651 EDPOL at B1 matches. In this example, if B1 = 0x000009, a B1 match does not occur, and thus a 0% duty cycle signal is generated. MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-74 Freescale Semiconductor...
Page 652: Initialization/Application Information
Figure 16-58, Figure 16-59, and Figure 16-57 illustrate the time base generation mechanism. Figure 16-60 shows the time base generation when using the internal clock set and clear on match start. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-75...
Page 653 Initial time base period The next clock cycle clears includes the match value. Match occurs the internal counter, starting another period. Figure 16-58. eMIOS Time Base Example — Fastest Prescaler Ratio = 1 MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-76 Freescale Semiconductor...
Page 654 Note 1: When a match occurs, the first clock cycle is used to clear the internal counter. The internal counter starts counting after the second edge of the prescaled clock. Figure 16-60. Time Base Generation Using the Internal Clock with Clear on Match Start MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 16-77...
Page 655: Document Revision History
• From: ‘Note that for the same programmed match value, the period is shorter when using a prescaler ratio greater than one.’ • To: ‘For a programmed match value, the time base-period becomes smaller as the prescaler ratio increases.’ MPC5565 Microcontroller Reference Manual, Rev. 1.0 16-78...
Page 656: Introduction
Chapter 17 Enhanced Time Processing Unit (eTPU) 17.1 Introduction The enhanced time processing unit (eTPU) operates in parallel with the MPC5565 core (CPU) to: • Execute programs independently from the host core • Detect and precisely record the timing of input events •...
Page 657: Block Diagram
Enhanced Time Processing Unit (eTPU) Because of the differences between the MPC5565 implementation of the eTPU and the full eTPU, full register bit descriptions are included within this chapter as well as in the Enhanced Time Processing (eTPU) Reference Manual.
Page 658: Etpu Operation Overview
Function routines, which reside in the SCM, are also used to configure the channel. A function can be assigned to several channels, but a channel can only process MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 659: Etpu Engine
The TCRs can also drive an eMIOS time base through the shared time and counter (STAC) bus, or they can be written by eTPU function software. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-4 Freescale Semiconductor...
Page 660 NOTE The host transfers the code image for the eTPU microcode to the SCM, then the host enables eTPU access to the SCM (which also disables host access). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-5...
Page 661 Reads return the lower 3-bytes of a word sign-extended to 32 bits; the most significant bit of the word’s second most significant byte (byte addresses) is copied in all 8 bits of the most significant read byte. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-6...
Page 662 The scheduler determines the order in which channels are serviced based on channel number and assigned priority. The priority mechanism, implemented in hardware, ensures that all requesting channels are serviced. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-7...
Page 663: Features
— Each channel has an event mechanism that supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal or equal-only comparator. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-8 Freescale Semiconductor...
Page 664 — 24-bit registers and ALU, plus one 32-bit register for full-width SDM access. — Additional 24-bit multiply/MAC/divide unit which supports all signed/unsigned/ multiply/MAC combinations, and unsigned 24-bit divide. The MAC/divide unit works in parallel with the regular microcode commands. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-9...
Page 665: Modes Of Operation
By having access to the shared code memory (SCM), the core has the ability to program the eTPU cores with time functions. 17.2.2 User Mode In user mode the core does not access the eTPU shared code memory, and pre-defined eTPU functions are used. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-10 Freescale Semiconductor...
Page 666: Debug Mode
Each eTPU channel has an input and output associated with it, and these can be connected to external pins or wired internally to other peripheral devices. As shown in Chapter 19, “Deserial Serial Peripheral MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-11...
Page 667 GPIO[138:141] General-purpose I/O 28–29 ETPUA[28:29] DSPI B[9:8] DSPI B[9:8] ETPUA[28:29]_ Primary Input/Output DSPI D[11:10] PCSC[1:2]_ Alternate GPIO[142:143] General-purpose I/O 30–31 ETPUA[30:31] None None ETPUA[30:31]_ Primary Input/Output PCSC[3:4]_ Alternate GPIO[144:145] General-purpose I/O MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-12 Freescale Semiconductor...
Page 668 The output disable channel groups are defined in Table 17-3. Table 17-3. Output Disable Channel Groups eMIOS Channel Engine eTPU Channels Disabled 0–7 8–15 16–23 24–31 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-13...
Page 669: Memory Map And Register Definition
Shared code memory (12 KB) Base + 0x0001_2FFF Base + 0x0001_3000– Not writable Base + 0x0001_FFFF Reads the return value of ETPU_SCMOFFDATAR register. Parameter Sign Extension access area. Refer to the eTPU Reference Manual. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-14 Freescale Semiconductor...
Page 670: Etpu Register Addresses
Base + 0x0000_0238 — Reserved — Base + 0x0000_023C — Reserved — Base + 0x0000_0240 ETPU_CIER_A eTPU A channel interrupt enable register Base + 0x0000_0248 — Reserved — MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-15...
Page 671 2.5 KB Base + 0x0000_8A00– — Reserved — Base + 0x0000_BFFF Base + 0x0000_C000– Base + 0x0000_CBFF — SDM PSE mirror 2.5 KB Base + 0x0000_CC00– — Reserved — Base + 0x0000_FFFF MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-16 Freescale Semiconductor...
Page 672: System Configuration Registers
0 Keep global exception request and status bits ILFA, ILFB, MGEA, MGEB, and SCMMISF as is. 1 Negate global exception, clear status bits ILFA, ILFB, MGEA, MGEB, and SCMMISF. GEC works the same way with either one or both engines in stop mode. 1–3 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-17...
Page 673 This bit is write protected when any of the engines are not in halt or stop states. When VIS=1, the ETPU_ECR MDIS bits are write protected, and only 32-bit aligned SCM writes are supported. The value written to SCM is unpredictable if other transfer sizes are used. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-18 Freescale Semiconductor...
Page 674 SDM base) of the parameters to be transferred: CTBASE Parameter 0 address = {CTBASE, PARM0} × 4 + SDM base [0:4] Parameter 1 address = {CTBASE, PARM1} × 4 + SDM base MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-19...
Page 675 For more details, refer to the eTPU Reference Manual. Address: Base + 0x0000_000C Access: R/W EMISCCMP Reset EMISCCMP Reset Figure 17-7. eTPU MISC Compare Register (ETPU_MISCCMPR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-20 Freescale Semiconductor...
Page 676 SCM Off-range read data value. ETPU SCMOFF DATAR 17.4.3.5 eTPU Engine Configuration Register (ETPU_ECR) Each engine has its own ETPU_ECR. The ETPU_ECR holds configuration and status fields that are programmed independently in each engine. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-21...
Page 677: Time Base Registers
Summarizing engine stop conditions, which STF reflects: STF_A:= (after stop completed) MDIS_A STF_B:= (after stop completed) MDIS_B STF_A and STF_B mean STF bit from engine A and STF bit from engine B respectively. 4–7 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-22 Freescale Semiconductor...
Page 678 For more information on filtering, refer to the eTPU Reference Manual. Changing CDFC during eTPU normal input channel operation is not recommended since it changes the behavior of the transition detection logic while executing its operation. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-23...
Page 679: Global Channel Registers
TCR2. There is one of each of these registers for each eTPU engine. NOTE Writes to this register generate a bus error and are ineffective when MDIS = 1. Reads are always permitted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-24 Freescale Semiconductor...
Page 680 Time Base Configuration Register (ETPU_TBCR) This register configures several time base options. Address: Base + 0x0000_0020 (eTPU A) Access: R/W TCR2CTL TCRCF TCR2P Reset TCR1CTL TCR1P Reset Figure 17-10. eTPU Time Base Configuration Register (ETPU_TBCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-25...
Page 681 TCRCF Filter clock of the channels two sample System clock divided by 2 integration Filter clock of the channels integration For more information, refer to the eTPU Reference Manual. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-26 Freescale Semiconductor...
Page 682 2 or the output of TCRCLK filter, or Peripheral Timebase input. TCR1P The prescaler divides this input by (TCR1P+1) allowing frequency divisions from 1 up to 256. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-27...
Page 683 Figure 17-11. eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R) Table 17-12. ETPU_TB1R Field Descriptions Field Description 0–7 Reserved. 8–31 TCR1 value. Used on matches and captures. For more information, refer to the eTPU Reference Manual. TCR1 [0:23] MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-28 Freescale Semiconductor...
Page 684 Figure 17-12. eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R) Table 17-13. ETPU_TB2R Bit Field Descriptions Field Description 0–7 Reserved. 8–31 TCR2 value. Used on matches and captures. For information on TCR2, refer to the eTPU Reference Manual. TCR2 [0:23] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-29...
Page 685 Enables or disables client/server operation for eTPU slave resources. REN2 enables TCR2 slave bus operations. REN2 1 Server/client operation for resource 2 is enabled. 0 Server/client operation for resource 2 is disabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-30 Freescale Semiconductor...
Page 686 For more information, refer to Section 17.4.6.3, “eTPU Channel n Status Control Register (ETPU_CnSCR),” and the eTPU Reference Manual. NOTE The host core must write 1 to clear (w1c) an interrupt status bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-31...
Page 687 Reference Manual. In the MPC5566, eTPU A channels [0:2,12:15,28:29] are connected to the DMA; in the MPC5565, eTPU channels [0:2, 14:15] are DMA connected. The data transfer request lines that are not connected to the DMA controller...
Page 688 Section 17.4.6.3, “eTPU Channel n Status Control Register (ETPU_CnSCR),” and the eTPU Reference Manual. NOTE The host must write 1 to clear an interrupt overflow status bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-33...
Page 689 Section 17.4.6.3, “eTPU Channel n Status Control Register (ETPU_CnSCR),” and the eTPU Reference Manual. NOTE The host must write 1 to clear a data transfer request overflow status bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-34 Freescale Semiconductor...
Page 690 Section 17.4.6.2, “eTPU Channel n Configuration Register (ETPU_CnCR),” and the eTPU Reference Manual. Address: Base + 0x0000_0240 (eTPU A) Access: R/W R CIE Reset R CIE Reset Figure 17-18. eTPU Channel Interrupt Enable Register (ETPU_CIER) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-35...
Page 691 Enhanced Time Processing Unit (eTPU) Table 17-19. ETPU_CIER Field Descriptions Field Description Channel n interrupt enable. Enable the eTPU channels to interrupt the MPC5565 core. 0–31 0 Interrupt disabled for channel n. CIEn 1 Interrupt enabled for channel n For details about interrupts refer to the eTPU Reference Manual.
Page 692 NOTE Channel service status does not always reflect decoding of the CHAN register, since the CHAN register can be changed by the service thread microcode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-37...
Page 693: Channel Configuration And Control Registers
0x000C Reserved In the MPC5565, eTPU A channels [0:2, 14:15] are connected. The data transfer request lines that are not connected to the DMA controller are left disconnected and do not generate interrupt requests, even if their request status bits assert in registers ETPU_CDTRSR and ETPU_CnSCR.
Page 694 The ETPU_CnCR is a collection of the configuration bits related to an individual channel. Some of these bits are mirrored from the global channel registers. Address: Channel_Register_Base + 0x0000 Access: R/W DTRE ETPD ETCS Reset ODIS OPOL CPBA Reset Figure 17-22. ETPU Channel n Configuration Register (ETPU_CnCR MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-39...
Page 695 This bit selects which channel signal, input or output, is used in the entry point selection. The ETPD value has to be compatible with the function chosen for the channel, selected in the field CFS. For details about entry table and condition encoding schemes, refer to the eTPU Reference Manual. The ETPD bit is only present in the MPC5565 ETPD and MPC5567.
Page 696 The device core must write 1 to clear a status bit. NOTE In the MPC5565, eTPU A channels [0:2, 14:15] are DMA connected. The data transfer request lines that are not connected to the DMA controller are left disconnected and do not generate transfer requests, even if their request...
Page 697 Channel function mode. Each function can use this field for specific configuration. These bits can be tested by microengine code. [0:1] These bits are equivalent to the TPU/TPU2/TPU3 host sequence (HSQ) bits. MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-42 Freescale Semiconductor...
Page 698: Functional Description
After initial power-on reset, the eTPU remains in an idle state (except when debug is asserted on power-on reset—in this case, the microengine awakens in the halt state). In addition, initialize the SCM with the eTPU application prior to configuring the eTPU. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 17-43...
Page 699: Document Revision History
• removed the words “or after the STAC but stop has been asserted” from the STF bit description. In Table 17-11, “ETPU_TBR Field Descriptions, in the TCR2CTL field, removed the phrase • “TCR2 can also be clocked by an internal peripheral timebase signal” and changed TCR2CTL=101 to “Reserved.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 17-44 Freescale Semiconductor...
Page 700: Introduction
The eQADC provides a parallel interface to two on-chip analog-to-digital converters (ADCs), and a single master to single slave serial interface to an off-chip external device. The two on-chip ADCs are architected to allow access to all the analog channels. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-1...
Page 701: Block Diagram
TRIGGERED state and it becomes empty. An RFIFO overflow occurs when an RFIFO is full and more data is ready to be moved to the RFIFO by the host CPU or by eDMA. Accordingly, the eQADC generates MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-2...
Page 702 For users familiar with the QADC, the eQADC system upgrades the functionality provided by that module. Refer to Section 18.5.7, “eQADC versus QADC,” for a comparison between the eQADC and QADC. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-3...
Page 703: Features
— Supports configurable digital filter • Supports four external 8-to-1 muxes that can expand the input channel number from 40 to 68 • Upgrades the functionality provided by the QADC 1. VREF=VRH-VRL. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-4 Freescale Semiconductor...
Page 704: Modes Of Operation
• Command transfer is in progress. eQADC completes the transfer and updates CFIFO status before halting future command transfers from any CFIFO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-5...
Page 705 If valid data (conversion result or data read from an ADC register) is received at the end of the transmission, it is not sent to an RFIFO until stop mode exits. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-6...
Page 706: External Signal Description
Single-ended analog input 2 I / — AN[2] / — Analog DAN1+ Positive terminal differential input AN[3]_ Single-ended analog input 3 I / — AN[3] / — Analog DAN1- Negative terminal differential input MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-7...
Page 707 Single-ended analog input 16 I / — AN[16] / — Analog AN[17:18] Single-ended analog input 17-18 I / — AN[17:19]/ Analog — AN[19:20] Single-ended analog input 19-20 I / — AN[19:20]/ Analog — MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-8 Freescale Semiconductor...
Page 708 I / — AN[37:39] / Analog — Power Supplies Voltage reference high — / — Power Voltage reference low — / — Power REFBYPC Reference bypass capacitor input — / — REFBYPC Power MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-9...
Page 709: Memory Map And Register Definition
Base + 0x024 EQADC_CFPR5 eQADC command FIFO push register 5 Base + 0x028 — Reserved — Base + 0x02C — Reserved — Base + 0x030 EQADC_RFPR0 eQADC result FIFO pop register 0 MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-10 Freescale Semiconductor...
Page 710 Base + 0x092 EQADC_CFTCR1 eQADC command FIFO transfer counter register 1 Base + 0x094 EQADC_CFTCR2 eQADC command FIFO transfer counter register 2 Base + 0x096 EQADC_CFTCR3 eQADC command FIFO transfer counter register 3 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-11...
Page 711 Base + 0x240– EQADC_CF5Rn eQADC CFIFO5 registers 0–3 Base + 0x24C Base + 0x250– — Reserved — Base + 0x2FC Base + 0x300– EQADC_RF0Rn eQADC RFIFO0 registers 0–3 Base + 0x30C MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-12 Freescale Semiconductor...
Page 712: Eqadc Register Descriptions
Base + 0x410– — Reserved — Base + 0x43C Base + 0x440– EQADC_RF5Rn eQADC RFIFO5 registers 0–3 Base + 0x44C Base + 0x450– — Reserved — Base + 0x7FC 18.3.2 eQADC Register Descriptions MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-13...
Page 713 When disabling the eQADC SSI, the FCK does not stop until it reaches its low phase. 18.3.2.2 eQADC Null Message Send Format Register (EQADC_NMSFR) The EQADC_NMSFR defines the format of the null message sent to the external device. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-14 Freescale Semiconductor...
Page 714 The EQADC_ETDFR is used to set the minimum time a signal must be held in a logic state on the CFIFO triggers inputs to be recognized as an edge or level gated trigger. The digital filter length field specifies the MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 715 DFL[0:3] Minimum Clock Count (System Clock = 120MHz) 0b0000 16.67 0b0001 25.00 0b0010 41.67 0b0011 75.00 0b0100 141.67 0b0101 275.00 0b0110 541.67 0b0111 1075.00 0b1000 2141.67 0b1001 4275.00 0b1010 1025 8541.67 MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-16 Freescale Semiconductor...
Page 716 Note: Only whole words must be written to EQADC_CFPR. Writing halfwords or bytes to EQADC_CFPR pushes the entire 32-bit CF_PUSH field into the CFIFO, but undefined data fills the areas of CF_PUSH that were not specifically designated as target locations for the write. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-17...
Page 717 RFCTRn value. Writing to EQADC_RFPRn has no effect. 18.3.2.6 eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) The eQADC_CFCRs contain bits that affect CFIFOs. These bits specify the CFIFO operation mode and can invalidate all of the CFIFO contents. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-18 Freescale Semiconductor...
Page 718 Table 18-10. CFIFO Operation Mode Table MODEn[0:3] CFIFO Operation Mode 0b0000 Disabled 0b0001 Software trigger, single scan 0b0010 Low level gated external trigger, single scan 0b0011 High level gated external trigger, single scan MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-19...
Page 719 EQADC_BASE + 0x064 (EQADC_IDCR2) EQADC_BASE + 0x066 (EQADC_IDCR3) EQADC_BASE + 0x068 (EQADC_IDCR4) EQADC_BASE + 0x06A (EQADC_IDCR5) R NCI TORI EOQI CFUI RFOI PIEn Reset Figure 18-8. eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-20 Freescale Semiconductor...
Page 720 0 Generate interrupt request to move data from the system memory to CFIFOn. 1 Generate eDMA request to move data from the system memory to CFIFOn. Note: CFFSn must not be negated while an eDMA transaction is in progress. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-21...
Page 721 The EQADC_FISRs contain flag and status bits for each CFIFO and RFIFO pair. Writing 1 to a flag bit clears it. Writing 0 has no effect. Status bits are read only. These bits indicate the status of the FIFO itself. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-22...
Page 722 Write 1 to clear the TORFn bit. Writing 0 has no effect. 0 No trigger overrun occurred 1 Trigger overrun occurred Note: The trigger overrun flag is not set for CFIFOs configured for software trigger mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-23...
Page 723 Note: An asserted EOQFn only implies that the eQADC has finished transferring a command with an asserted EOQ bit from CFIFOn. It does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate RFIFO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-24 Freescale Semiconductor...
Page 724 Note: When generation of interrupt requests is selected (CFFSn=0), CFFFn must only be cleared in the ISR after the CFIFOn push register is accessed. Note: CFFFn should not be cleared when CFFSn is asserted (eDMA requests selected). 7–11 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-25...
Page 725 EQADC_RFPRn is read. If the maximum index number (RFIFO depth minus 1) is reached, [0:3] POPNXTPTRn is wrapped to 0, else, it is incremented by 1. For details refer to Section 18.4.4.1, “RFIFO Basic Functionality.” Writing any value to POPNXTPTRn has no effect. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-26 Freescale Semiconductor...
Page 726 CFIFO. The EQADC_CFSSRs are read only. Writing to the EQADC_CFSSRs has no effect. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-27...
Page 727 TC_LCFT0 is a copy of the corresponding TC_CFn in EQADC_CFTCRn (see Section 18.3.2.9) captured at the time a command transfer from CFIFOn to ADCn command buffer is initiated. This field has no meaning when LCFT0 is 0b1111. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-28 Freescale Semiconductor...
Page 728 (EQADC_CFTCRn)”) captured at the time a command transfer from CFIFOn to ADCn command buffer is initiated. This field has no meaning when LCFT1 is 0b1111. The third eQADC CFIFO status snapshot register is displayed in Figure 18-13. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-29...
Page 729 External command buffer number Indicator. Indicates to which external command buffer the last command was transmitted. 0 Last command was transferred to command buffer 2. 1 Last command was transferred to command buffer 3. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-30 Freescale Semiconductor...
Page 730 The EQADC_CFSR contains the current CFIFO status. The EQADC_CFSRs are read only. Writing to the EQADC_CFSR has no effect. Address: Base + 0x0AC Access: Read CFS0 CFS1 CFS2 CFS3 CFS4 CFS5 Reset Reset Figure 18-14. eQADC CFIFO Status Register (EQADC_CFSR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-31...
Page 731 0b11 CFIFO is triggered 18.3.2.12 eQADC SSI Control Register (EQADC_SSICR) The EQADC_SSICR configures the SSI submodule. Address: Base + 0x0B4 Access: Read/Write Reset Reset Figure 18-15. eQADC SSI Control Register (EQADC_SSICR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-32 Freescale Semiconductor...
Page 732 0b001 0b010 0b011 0b100 0b101 0b110 0b111 Table 18-21. System Clock Divide Factor for Baud Clock BR[0:3] System Clock Divide Factor 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-33...
Page 733 DATA. Contains the last result message that was shifted in. Writes to the R_DATA have no effect. R_DATA Messages that were not completely received due to a transmission abort is not copied into EQADC_SSIRDR. [0:25] MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-34 Freescale Semiconductor...
Page 734 CFIFO[0–5]_datan. Returns the value stored within the entry of CFIFO[0–5]. Each CFIFO is composed of four CFIFO[0–5] 32-bit entries, with register 0 being mapped to the entry with the smallest memory mapped address. _DATAn [0:31] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-35...
Page 735 RFIFO[0–5] data n. Returns the value stored within the entry of RFIFO[0–5]. Each RFIFO is composed of four _DATAn 16-bit entries, with register 0 being mapped to the entry with the smallest memory mapped address. [0:15] MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-36 Freescale Semiconductor...
Page 736: On-Chip Adc Registers
ADC0 Gain Calibration Constant Register (ADC0_GCCR) Write/Read 0x05 ADC0 Offset Calibration Constant Register (ADC0_OCCR) Write/Read 0x06–0xFF Reserved — This register is also accessible by configuration commands sent to the ADC1 command buffer. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-37...
Page 737 The ADCn control registers (ADCn_CR) are used to configure the on-chip ADCs. Address: 0x01 Access: Read/Write R ADC0 ADC0_CLK_PS Reset R ADC1 ADC1_CLK_PS Reset Figure 18-19. ADCn Control Registers (ADC0_CR and ADC1_CR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-38 Freescale Semiconductor...
Page 738 ADCn_EN. Table 18-28. System Clock Divide Factor for ADC Clock System Clock ADCn_CLK_PS[0:4] Divide Factor 0b00000 0b00001 0b00010 0b00011 0b00100 0b00101 0b00110 0b00111 0b01000 0b01001 0b01010 0b01011 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-39...
Page 739 ADC0 writes to the same memory location as a write using a configuration command sent to ADC1. NOTE Simultaneous write accesses from ADC0 and ADC1 to ADC_TSCR are not allowed. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-40 Freescale Semiconductor...
Page 740 Counter for a 120 MHz Factor System Clock (MHz) 0b0000 Disabled Disabled 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 3.75 0b1010 1.88 0b1011 0.94 0b1100 0.47 0b1101 0.23 0b1110 - 0b1111 Reserved — MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-41...
Page 741 The ADCn_GCCR contains the gain calibration constant used to fine-tune the ADCn conversion results. Refer to Section 18.4.5.4, “ADC Calibration Feature,” for details about the calibration scheme used in the eQADC. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-42 Freescale Semiconductor...
Page 742 Section 18.4.5.4, “ADC Calibration Feature,” for details about the calibration scheme used in the eQADC. Address: 0x05 Access: Read/Write OCC0 Reset OCC1 Reset Figure 18-23. ADCn Offset Calibration Constant Registers (ADCn_OCCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-43...
Page 743: Functional Description
ADCs, command transfers for on-chip ADCs occur concurrently with the transfers through the serial interface. Commands sent to the ADCs are executed in a first-in-first-out (FIFO) basis MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-44 Freescale Semiconductor...
Page 744 While conversion results are returned, the eQADC is checking the number of entries in the RFIFO and generating requests to empty it. The process of pushing and popping ADC results to and from an RFIFO can occur simultaneously. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-45...
Page 745 SSI NOTES: External Device eQADC SSI n = 0, 1, 2, 3, 4, 5 RFIFO Header Logic ADC Result & Result Buffers Message Figure 18-25. Result Flow During eQADC Operation MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-46 Freescale Semiconductor...
Page 746 2 is empty before the end of the current serial transmission and if at the end of this transmission the external device receives a command to command buffer 2, then the BUSY0 field, that MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 747 ADCs. A conversion result is always returned for conversion commands and time stamp information can be optionally requested. The lower byte of conversion commands is always set to 0 to distinguish it from configuration commands. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-48 Freescale Semiconductor...
Page 748 0 Message sent to ADC 0. 1 Message sent to ADC 1. Calibration. Indicates if the returning conversion result must be calibrated. 0 Do not calibrate conversion result. 1 Calibrate conversion result. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-49...
Page 749 ADCs into the 16-bit format which is sent to the RFIFOs. Refer to Section , “ADC Result Format for On-Chip ADC Operation,” for details. 0 Right justified unsigned. 1 Right justified signed. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-50 Freescale Semiconductor...
Page 750 Note: If both the pause and EOQ bits are asserted in the same command message, the respective flags are set, but the CFIFO status changes as if only the EOQ bit were asserted. 2–4 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-51...
Page 751 R/W bit. EOQ PAUSE Reserved MESSAGE_TAG Reserved (0b0) (0b1) CFIFO Header ADC Command Reserved ADC_REG_ADDRESS ADC Command Figure 18-28. Read Configuration Command Message Format for On-Chip ADC Operation MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-52 Freescale Semiconductor...
Page 752 EB bit setting. 0 Message stored in buffer 0. 1 Message stored in buffer 1. Read/write. An asserted R/W bit indicates a read configuration command. 0 Write 1 Read MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-53...
Page 753 When the CAL bit is negated, this 14-bit data is obtained by executing a 2-bit left-shift on the 12-bit data received from the ADC. When the CAL bit is asserted, MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-54...
Page 754 0b11 when CONVERSION_RESULT is negative. EXT[0:1] 2–15 Conversion result. A digital value corresponding to the analog input voltage in a channel when the conversion CONVERSION command was initiated. _RESULT [0:13] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-55...
Page 755 FIFO control unit/external device to which external command buffer the corresponding command should be sent. The remaining 25 bits can be anything decodable by the external device. Only the ADC command portion of a command message is transferred to the external device. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-56 Freescale Semiconductor...
Page 756 It is 25 bits long and it is transferred together with the BN bit to the external device when the CFIFO is COMMAND triggered. Refer to Section , “Conversion Command Message Format for On-Chip ADC Operation,” for a [0:24] description of the command message used when interfacing with the on-chip ADCs. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-57...
Page 757 ADC_RESULT of any incoming message with a null message tag is ignored. When the MESSAGE_TAG is for an [0:15] RFIFO, the eQADC extracts the 16-bit ADC_RESULT from the raw message and stores it into the appropriate RFIFO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-58 Freescale Semiconductor...
Page 758 (0b1000). The eQADC does not store into an RFIFO any incoming message with a null message tag. CONTENTS OF EQADC_NMSFR REGISTER CONTENTS OF EQADC_NMSFR REGISTER Figure 18-33. Null Message Send Format for External Device Operation MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-59...
Page 759: Command/Result Queues
When a CFIFO is not full, the eQADC sets the corresponding CFFF bit in Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).” If MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-60 Freescale Semiconductor...
Page 760 (EQADC_FISRn),” is decremented by 1, and transfer next data pointer n is incremented by 1 (or wrapped around) to point to the next entry in the CFIFO. The transfer of entries bound for the on-chip MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 761 CFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, CFIFOn with 16 entries is shown in sequence after pushing and transferring entries. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-62 Freescale Semiconductor...
Page 762 • Its commands are bound for an internal command buffer that is not full, and it is the highest priority triggered CFIFO sending commands to that buffer. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-63...
Page 763 BUSY fields of the incoming result messages from the external device (see Section , “Result Message Format for External Device Operation,” for details). MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-64 Freescale Semiconductor...
Page 764 This occurs when the eQADC acknowledges that the status of a higher-priority CFIFO has changed to the TRIGGERED state and attempts to schedule that CFIFO MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 765 CFIFO4 Command for EQADC SSI Usage Command CFIFO5 eQADC SSI Serial Link External Device External SSI Interface Device Command Buffer2 Command ADC2 Command Buffer3 Command ADC3 Figure 18-37. CFIFO Prioritization Logic MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-66 Freescale Semiconductor...
Page 766 CFIFO trigger mode. Only then, after a valid trigger event is detected, the eQADC accordingly changes the CFIFO status. Refer to Figure 18-38 for an example. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-67...
Page 767 CFIFOs can be changed from any other mode to disabled at any time. No trigger event can initiate command transfers from a CFIFO which has its MODE field programmed to disabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-68...
Page 768 In single-scan mode, a single pass through a sequence of command messages in the user-defined command queue is performed. In single-scan software trigger mode, the CFIFO is triggered by an asserted single-scan status bit, EQADC_FISRn[SSS] (see Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-69...
Page 769 The eQADC clears the SSS bit and stops transferring commands from a triggered CFIFO when an asserted EOQ bit is encountered or when CFIFO status changes from triggered due to the detection of a closed gate. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-70...
Page 770 CFIFO to detect such event. A trigger overrun happens when the CFIFO is already in a TRIGGERED state and a new edge trigger event is detected. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-71...
Page 771 SSS bit is asserted. from the CFIFO when CFIFO status changes from triggered due to the detection of a closed gate. Continuous CFIFO starts None. Scan Software automatically after being configured into this mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-72 Freescale Semiconductor...
Page 772 (EQADC_CFSSRn).” The last CFIFO to transfer a command to a specific external command buffer can be identified by reading the EQADC_CFSSRn[LCFTSSI] and EQADC_CFSSRn[ENI] fields (see Section 18.3.2.10, “eQADC CFIFO Status Snapshot Registers 0–2 (EQADC_CFSSRn).” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-73...
Page 773 • No trigger occurred. TRIGGER (0b10) TRIGGERED • Appropriate edge or level trigger occurred, OR (0b11) • CFIFO mode is programmed to single-scan software trigger mode and SSS bit is asserted. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-74 Freescale Semiconductor...
Page 774 The command with a EOQ bit asserted is valid and is transferred. When EQADC_CFCRn[EOQIE] (refer Section 18.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn)”) and EQADC_FISRn[EOQF] are asserted, the eQADC generates an end of queue interrupt request. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-75...
Page 775 In software or level trigger mode, when the eQADC completes the transfer of an entry from CFIFOn with an asserted pause bit, PFn is not set and the command transfers continues without pausing. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-76 Freescale Semiconductor...
Page 776 ADC command buffer, the buffer is only fed with commands from that sequence without ever becoming empty. A command sequence starts when: • A CFIFO in TRIGGERED state transfers its first command to an on-chip ADC. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-77...
Page 777 CFn_ADCa_CMDn – Command n in CFIFOn bound for ADCa CF5_ADC2_CM5 (ADC3 and ADC4 are external devices associated with external CF5_ADC1_CM6(EOQ=1) command buffers 2 and 3). Example 3 Figure 18-41. Command Sequence Examples MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-78 Freescale Semiconductor...
Page 778 2) Execution of a command on the external device takes longer than the time to complete three serial transmissions. Figure 18-42. External Command Buffer Status Detection at Command Sequence Transfer Start MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-79...
Page 779 When the eQADC enters debug or stop mode while a command sequence is executing, the NCF asserts if an empty external command buffer is detected after debug or stop mode exits. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-80 Freescale Semiconductor...
Page 780 CFIFO5 becomes non-coherent. CF5_ADC1_CM3 TNXTPTR – Transfer Next Data Pointer. CFx_ADCa_CMn – Command n in CFIFOx bound for ADCa. Figure 18-43. Non-Coherency Event When Different CFIFOs Use the Same Buffer MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-81...
Page 781 TNXTPTR – Transfer Next Data Pointer. CFx_ADCa_CMn – Command n in CFIFOx bound for external command buffer a. Figure 18-44. Non-Coherency Event When Different CFIFOs Are Using Different External Command Buffers MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-82 Freescale Semiconductor...
Page 782: Result Fifos
RFIFO message to be retrieved from the RFIFO when reading eQADC_RFPR. The receive next data pointer points to the next available RFIFO location for storing the next incoming MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 783 When the eQADC RFIFO pop register n is read and RFIFOn is empty, eQADC does not decrement the counter value and the pop next data pointer n is not updated. The read value is undefined. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-84...
Page 784 RFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, RFIFOn with 16 entries is shown in sequence after popping or receiving entries. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-85...
Page 785 Stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO number or • Ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-86 Freescale Semiconductor...
Page 786: On-Chip Adc Configuration And Control
ADC timebases. is this the case? (Mike Garrard, can you check this one out) can they be read, or even polled to see if 120 ADC clocks is finished?] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-87...
Page 787 ADC clock frequency higher than the maximum one supported by the ADC. ADC clock frequency must not exceed 12 Mhz. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-88 Freescale Semiconductor...
Page 788 0b01100 4.62 0b01101 4.29 0b01110 0b01111 3.75 0b10000 3.53 0b10001 3.33 0b10010 3.16 0b10011 0b10100 2.86 0b10101 2.73 0b10110 2.61 0b10111 0b11000 0b11001 2.31 0b11010 2.22 0b11011 2.14 0b11100 2.07 0b11101 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-89...
Page 789 CAL_RES is the calibrated result corresponding the input voltage V • GCC is the gain calibration constant. • RAW_RES is the raw, uncalibrated result corresponding to an specific input voltage V • OCC is the offset calibration constant. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-90 Freescale Semiconductor...
Page 790 CAL_RES output is the calibrated result, and it is a 14-bit unsigned value. CAL_RES is truncated to 0x3FFF, in case of a overflow, and to 0x0000, in case of an underflow. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-91...
Page 791 The EB and BN bits in the command message uniquely identify the ADC to which a command should be sent. The FIFO control unit decodes these bits and sends the ADC command to the proper ADC. Other MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-92...
Page 792 The second advantage of pipelining conversion commands is to provide equal conversion intervals even though the sample time increases on second and subsequent conversions. Refer to Figure 18-52. This is important for any digital signal process application. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-93...
Page 793 Result Format ADC0_Result0 Stamp Logic ADC1_Result1 Time Stamp0 Calibration Time Stamp1 Submodule TBC_CLK_PS Configuration Register Fields NOTE: n = 0, 1, 2, 3, 4, 5 Figure 18-51. On-Chip ADC Control Scheme MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-94 Freescale Semiconductor...
Page 794: Internal/External Multiplexing
ADC. The differential conversions can only be initiated on four channels: DAN0, DAN1, DAN2, and DAN3. Refer to Table 18-51 Figure 18-52 for the channel numbers used to select differential conversions. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-95...
Page 795 Section 18.5.6.1, “MAC Configuration Procedure” Table 18-52 shows the channel number assignments for multiplexed mode. The ADC with the ADCn_EMUX bit asserted can access 4 differential pairs, 39 single-ended, and, at most, 32 externally MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-96 Freescale Semiconductor...
Page 796 Figure 18-53 shows the maximum configuration of four external multiplexer chips connected to the eQADC. The external multiplexer chip selects one of eight analog inputs and connects it to a single analog MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-97...
Page 797 (ANW, ANX, ANY, and ANZ) by interpreting the CHANNEL_NUMBER field. As a result, up to 32 externally multiplexed channels appear to the conversion queues as directly connected signals. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-98 Freescale Semiconductor...
Page 798: Eqadc Edma/Interrupt Request
(EQADC_IDCRn),” and the interrupt flag bits are described in Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).” Table 18-54 depicts all interrupts and eDMA requests generated by the eQADC. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-99...
Page 799 Writing 1 to the CFFFn bit is not allowed while CFDS = 1. CFFFn = 1 For details refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn),” and Section 18.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn).” MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-100 Freescale Semiconductor...
Page 800 End of Queue Interrupt Request EOQFn TORIEn Trigger Overrun Interrupt Request TORFn CFUIEn CFIFO Underflow Interrupt Request CFUFn RFOIEn RFIFO Overflow Interrupt Request RFOFn Combined Interrupt Request Figure 18-54. eQADC eDMA and Interrupt Requests MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-101...
Page 801: Eqadc Synchronous Serial Interface (Ssi) Submodule
26-bit receive shift register in the slave are linked by the SDO pin. In a similar way, the 26-bit transmit shift register in the slave and 26-bit receive shift register in the master are linked by the SDI pin. Refer to MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-102...
Page 802 SDS was detected by the slave on the preceding FCK negative edge. This is an important requisite since the SDS and the FCK are not MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 803 (EQADC_SSICR)”) selects the system clock divide factor as in Table 18-21. SystemClockFrequency MHz BaudClockFrequency --------------------------------------------------------------------------------------- - SystemClockDivideFactor Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-104 Freescale Semiconductor...
Page 804 23 24 25 26 23 24 25 Slave Sample Input NOTE: = Minimum t is programmable and defined in Section 18.3.2.12, ‘eQADC SSI Control Register (EQADC_SSICR).’ Figure 18-57. Synchronous Serial Interface Protocol Timing MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-105...
Page 805 Slave drives msb bit again due to detection of a negated SDS on the negative edge of FCK. Figure 18-58. Slave Driving the msb and Consecutive Bits in a Data Transmission MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-106 Freescale Semiconductor...
Page 806: Analog Submodule
The digital module also saves each successive sample and adds them according to the RSD algorithm at the end of the entire conversion cycle. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-107...
Page 807 For the 12-bit ADC, the input signal is sampled during the input phase, and after each of the 12 passes through the RSD stage. Thus, 13 total a and b values are collected. Upon collecting all these MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-108...
Page 808: Initialization/Application Information
900 μs Fast Current sensing of PWM hardware-triggered controlled actuators queue Fast repetitive every 2 ms Throttle position time-based queue Software-triggered every 3.9 ms Command triggered by queue software strategy MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-109...
Page 809 8. Because CFIFO0 is in single-scan software mode and it is also the highest priority CFIFO, the eQADC starts to transfer configuration commands to the on-chip ADCs and to the external device. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-110 Freescale Semiconductor...
Page 810 At the end of the command queue, the “EOQ” bit is asserted as shown in Table 18-57. c) Results are returned to RFIFO3 as specified in the MESSAGE_TAG field of commands. 2. Reserve memory space for storing results. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-111...
Page 811 2. For receiving, set the source address of the eDMA TCDn to point to EQADC_RFPR3. Refer to Section 18.3.2.5, “eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn).” Set the destination address of the eDMA to point to the starting address of result queue 1. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-112 Freescale Semiconductor...
Page 812: Eqadc/Edma Controller Interface
CFIFO Push Register One command transfer Command 3 per DMA request • • eDMA_TCDn • • • • Source Address Command n-1 Command n Destination Address Figure 18-65. Command Queue/CFIFO Interface MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-113...
Page 813 Result 2 RFIFO Pop Register One result transfer Result 3 per DMA request • • • • • Source Address • Result n-1 Destination Address Result n Figure 18-66. Receive Queue/RFIFO Interface MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-114 Freescale Semiconductor...
Page 814: Sending Immediate Command Setup Example
Section 18.4.3.5.1, “Disabled Mode,” for a description of what happens when MODEn is changed to disabled. b) Poll EQADC_CFSR[CFSn] until it becomes IDLE (see Section 18.3.2.11, “eQADC CFIFO Status Register (EQADC_CFSR)”). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-115...
Page 815: Command Queue And Result Queue Usage
0 command was sent to result queue 1. This happens because the system can be configured so that several command queues can have results sent to a single result queue. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-116 Freescale Semiconductor...
Page 816: Adc Result Calibration
This allows for calculations of more representative calibration constants. The eQADC provides these voltages via channel numbers 43 and 44. VREF=V MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-117...
Page 817 4. Reformat GCC and OCC to the proper data formats as specified in Section 18.4.5.4.2, “MAC Unit and Operand Data Format.” GCC is an unsigned 15-bit fixed point value and OCC is a signed 14-bit value. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-118 Freescale Semiconductor...
Page 818 - see MAC output equation in Section 18.4.5.4, “ADC Calibration Feature.” The maximum absolute quantization error is reduced by half leading to an increase in accuracy. 1. This calculation is rounded down due to binary approximation. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-119...
Page 819: Eqadc Versus Qadc
QADC. Digital control logic for analog Analog-to-digital converter device Trigger & External queue control Command queues Result queues triggers logic Interrupt request Figure 18-69. QADC Overview MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-120 Freescale Semiconductor...
Page 820 FIFO instead of queue. These register names, register contents, and signals are functionally equivalent to the queue counterparts in the QADC. Table 18-59 lists how the eQADC register, register contents, and signals are related to QADC. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-121...
Page 821 Write to the eQADC SSI registers. Queue Execution Require software or external trigger Require software or external trigger events to start queue execution. events to start command transfers from a CFIFO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-122 Freescale Semiconductor...
Page 822: Document Revision History
Removed section 9.2 “Detailed Signals” from this chapter because this information is contained in the Signals chapter of the Reference Manual. Added this cross reference to the EQADC_NMSFR[NMF] bit: “Refer to the section “Null Message Format for External Device Operation” for more information.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 18-123...
Page 823 Enhanced Queued Analog-to-Digital Converter (eQADC) MPC5565 Microcontroller Reference Manual, Rev. 1.0 18-124 Freescale Semiconductor...
Page 824: Introduction
A, B, C, and D, and others implement only B, C, and D, for example. The “x” appended to signal names signifies the module to which the signal applies. Thus PCSx[0] specifies that the PCS signal applies to module A, B, etc. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-1...
Page 825: Block Diagram
DSPI deserialized output connections to the SIU. The channels and register content are transmitted using an SPI protocol. There are three identical DSPI modules (DSPI B, DSPI C, and DSPI D) on the device. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-2 Freescale Semiconductor...
Page 826: Features
Buffered transmit and receive operation using the TX and RX FIFOs, with depths of four entries • Visibility into TX and RX FIFOs for ease of debugging • FIFO bypass mode for low-latency updates to SPI queues MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-3...
Page 827 — eTPUA, and eMIOS output channels — Memory-mapped register in the DSPI • Deserialized data destinations — eTPUA and eMIOS input channels — SIU external interrupt request inputs — Memory-mapped register in the DSPI MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-4 Freescale Semiconductor...
Page 828: Modes Of Operation
DSPI is stopped while in module disable mode. The DSPI enters the module disable mode when the MDIS bit in DSPIx_MCR is set. For more information, refer to Section 19.4.1.3, “Module Disable Mode.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-5...
Page 829: External Signal Description
When the pin is used for DSPI master mode as a chip select output, set the OBE bit. When the pin is used in DSPI slave mode as a slave select input, set the IBE bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-6...
Page 830 19.2.2.7 Serial Clock (SCKx) SCKx is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode, SCKx is an input from an external bus master. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-7...
Page 831: Memory Map And Register Definition
DSPI receive FIFO register 1 Base + 0x0084 DSPIx_RXFR2 DSPI receive FIFO register 2 Base + 0x0088 DSPIx_RXFR3 DSPI receive FIFO register 3 Base + 0x008C– — Reserved — Base + 0x00B8 MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-8 Freescale Semiconductor...
Page 832: Register Descriptions
Continuous SCK enable. Enables the serial communication clock (SCK) to run continuously. Refer to CONT_SCKE Section 19.4.8, “Continuous Serial Communications Clock,” for details. 0 Continuous SCK disabled 1 Continuous SCK enabled MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-9...
Page 833 Peripheral chip select inactive state. Determines the inactive state of the PCSxn signal. PCSx[0] / SS must PCSISn be configured as inactive high for slave mode operation. 0 The inactive state of PCSxn is low 1 The inactive state of PCSxn is high Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-10 Freescale Semiconductor...
Page 834 Halt. Provides a mechanism for software to start and stop DSPI transfers. Refer to Section 19.4.2, “Start and HALT Stop of DSPI Transfers,” for details on the operation of this bit. 0 Start transfers 1 Stop transfers MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-11...
Page 835 DSPI,” for a discussion on DSPI/QSPI compatibility. At the initiation of an SPI or DSI transfer, control logic selects the DSPIx_CTAR that contains the transfer’s attributes.Do not write to the DSPIx_CTARs while the DSPI is running. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-12 Freescale Semiconductor...
Page 836 Base + 0x001C (DSPIx_CTAR4) Base + 0x0020 (DSPIx_CTAR5) Base + 0x0024 (DSPIx_CTAR6) Base + 0x0028 (DSPIx_CTAR7) FMSZ CPOL CPHA PCSSCK PASC Reset CSSCK Reset Figure 19-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-13...
Page 837 The following table lists the frame sizes. [0:3] FMSZ Frame Size FMSZ Frame Size 0000 Invalid value 1000 0001 Invalid value 1001 0010 Invalid value 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-14 Freescale Semiconductor...
Page 838 PCSx. Use in master mode only. The following table lists the prescaler values. The description for bitfield ASC in [0:1] Table 19-5 details how to compute the after SCKx delay. After SCKx Delay PASC Prescaler Value MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-15...
Page 839 The baud rate prescaler values are listed in the following table. The description for PBR in Section 19.4.6.1, “Baud Rate Generator” details how to compute the baud rate. Baud Rate Prescaler Value MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-16 Freescale Semiconductor...
Page 840 The after SCKx delay is a multiple of the system clock period, and it is computed using the following equation: × × ---------- - PASC Prescaler value ASC Scaler value Note: Refer to Section 19.4.6.3, “After SCK Delay (tASC),” for more details. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-17...
Page 841 The delay after transfer is a multiple of the system clock period. It is computed using the following equation: × × ---------- - PDT Prescaler value DT Scaler value Note: Refer to Section 19.4.6.4, “Delay after Transfer (tDT),” for more details MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-18 Freescale Semiconductor...
Page 842 DSPIx_SR by writing a 1 to clear it (w1c). Writing a 0 to a flag bit has no effect. Address: Base + 0x002C Access: R/W R TCF TXRXS EOQF TFUF TFFF RFOF RFDF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Figure 19-6. DSPI Status Register (DSPIx_SR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-19...
Page 843 RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-20 Freescale Semiconductor...
Page 844 Do not write to the DSPIx_RSER while the DSPI is running. Address: Base + 0x0030 Access: R/W TCF_ EOQF TFUF_ TFFF_ TFFF_ RFOF RFDF RFDF_ DIRS DIRS Reset Reset Figure 19-7. DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-21...
Page 845 RFDF_RE RFDF_DIRS bit selects between generating an interrupt request or a DMA request. 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enabled MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-22 Freescale Semiconductor...
Page 846 TXDATA is used in master and slave modes. Address: Base + 0x0034 Access: R/W CONT CTAS PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 Reset TXDATA Reset Figure 19-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-23...
Page 847 0 Do not clear SPI_TCNT field in the DSPIx_TCR 1 Clear SPI_TCNT field in the DSPIx_TCR Note: Use in SPI master mode only. 6–7 Reserved. 8–9 Reserved, but implemented. These bits are writable, but have no effect. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-24 Freescale Semiconductor...
Page 848 FIFO. Therefore, read DSPIx_POPR only when you need the data. For compatibility, configure the TLB (MMU table) entry for DSPIx_POPR as guarded. Address: Base + 0x0038 Access: R/O Reset RXDATA Reset Figure 19-9. DSPI POP RX FIFO Register (DSPIx_POPR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-25...
Page 849 Transmit command. Contains the command that sets the transfer attributes for the SPI data. Refer to TXCMD Section 19.3.2.6, “DSPI PUSH TX FIFO Register (DSPIx_PUSHR),” for details on the command field. [0:15] 16–31 Transmit data. Contains the SPI data to be shifted out. TXDATA [0:15] MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-26 Freescale Semiconductor...
Page 850 The following table describes the field in the DSPI receive FIFO register: Table 19-11. DSPIx_RXFRn Field Description Field Description 0–15 Reserved, must be cleared. 16–31 Receive data. Contains the received SPI data. RXDATA [15:0] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-27...
Page 851 Trigger polarity. Selects the active edge of the internal hardware trigger input signal (ht). The bit selects which TPOL edge initiates a transfer in the DSI configuration. Refer to Section 19.4.4.5, “DSI Transfer Initiation Control,” for more information. 0 Falling-edge initiates a transfer 1 Rising-edge initiates a transfer MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-28 Freescale Semiconductor...
Page 852 DSI peripheral chip select n. The DPCS bits select which of the PCSx signals to assert during a DSI transfer. DPCSx The DPCS bits assert and negate the PCSx signals in DSI master mode only. 0 Negate PCSx 1 Assert PCSx MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-29...
Page 853 The DSPIx_ASDR allows the host software to write data to be serialized. When the TXSS bit in the DSPIx_DSICR is set, the data in the DSPIx_ASDR is the source of the serialized data. Writes to the DSPIx_ASDR take effect on the next frame boundary. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-30 Freescale Semiconductor...
Page 854 Address: Base + 0x00C8 Access: R/O Reset COMP_DATA Reset Figure 19-15. DSPI DSI Transmit Comparison Register (DSPIx_COMPR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-31...
Page 855: Functional Description
The DSPI can also be used to reduce the number of pins required for I/O by serializing and deserializing up to 16 parallel input/output signals from the eTPU and eMIOS. All communications are through an SPI-like protocol. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-32 Freescale Semiconductor...
Page 856 Section 19.4.6, “DSPI Baud Rate and Clock Delay Generation.” Refer to Section 19.4.10, “Power Saving Features” for information on the power-saving features of the DSPI. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-33...
Page 857: Modes Of Operation
SS asserted. In slave mode the SCK is provided by the bus master. All transfer attributes are controlled by the bus master, except the clock polarity, clock phase and the number of bits to transfer which must be configured in the DSPI slave to communicate correctly. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-34 Freescale Semiconductor...
Page 858: Start And Stop Of Dspi Transfers
The TXRXS bit in the DSPIx_SR is set in the RUNNING state. Figure 19-18 shows a state diagram of the start and stop mechanism. RESET RUNNING TXRXS = 1 Power-on-Reset STOPPED TXRXS = 0 Figure 19-18. DSPI Start and Stop State Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-35...
Page 859: Serial Peripheral Interface (Spi) Configuration
(SCKx) and the peripheral chip select (PCSx) signals. The SPI command field in the executing TX FIFO entry determines which CTARs are used to set the transfer attributes and which PCSx signal to assert. The MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-36...
Page 860 TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is transferred into the shift register from the TX FIFO. Refer to Section 19.3.2.4, “DSPI Status Register (DSPIx_SR)” for more information on DSPIx_SR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-37...
Page 861 The POPNXTPTR field in the DSPIx_SR points to the RX FIFO entry that is returned when the DSPIx_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPIx_RXFR0. For example, POPNXTPTR equal to two means that the DSPIx_RXFR2 contains the received SPI data MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-38 Freescale Semiconductor...
Page 862: Deserial Serial Interface (Dsi) Configuration
(SCK) and peripheral chip select (PCS) signals. Refer to Section 19.4.4.7, “Multiple Transfer Operation (MTO),” for details on the serial and parallel chaining support. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-39...
Page 863 A copy of the last DSI frame shifted out of the shift register is stored in the DSPIx_COMPR. This register provides added visibility for debugging and it serves as a reference for transfer initiation control. Section 19.3.2.13, “DSPI DSI Transmit Comparison Register (DSPIx_COMPR),” contains details on the DSPIx_COMPR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-40 Freescale Semiconductor...
Page 864 Data transfers for a master DSPI in DSI configuration are initiated by a condition. When chaining DSPIs, the master and all slaves must be configured for the transfer initiation. The transfer initiation conditions are selected by the TRRE and CID bits in the DSPIx_DSICR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-41...
Page 865 Detection,” for details on how the DSPI deserialized outputs can be used to trigger external interrupt requests and Section 17.3.2, “Output and Input Channel Signals” for a discussion on eTPU connections. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-42 Freescale Semiconductor...
Page 866 1 on IMUX for external IRQ[10] eTPUA output channel 26 eTPUA input channel 26, input 1 on IMUX for external IRQ[11] eTPUA output channel 25 eTPUA input channel 25, input 1 on IMUX for external IRQ[12] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-43...
Page 867 6 Input 2 on IMUX for external IRQ[9] eTPUA output channel 7 Input 2 on IMUX for external IRQ[10] eTPUA output channel 8 Input 2 on IMUX for external IRQ[11] MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-44 Freescale Semiconductor...
Page 868 10 Input 3 on IMUX for external IRQ[5] eMIOS output channel 13 Input 3 on IMUX for external IRQ[6] eMIOS output channel 12 Input 3 on IMUX for external IRQ[7] MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-45...
Page 869 SCKx and PCSx0 outputs from the other two DSPIs connect to the multiplexers on the DSPI B inputs. DSPI B, DSPI C and DSPI D have similar multiplexers on their inputs. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-46 Freescale Semiconductor...
Page 870 (ht) input can be the MTRIG signal from any of the other DSPIs. The DSPI input select register (SIU_DSR) selects the source for each DSPI SINx, SSx, SCKx, and ht signal individually. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 871 The MTOCNT field in the DSPIx_DSICR must be written with the number of bits to be transferred. In parallel chaining the number written to MTOCNT must match the FMSZ field in the selected DSPIx_CTAR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-48 Freescale Semiconductor...
Page 872 DSI frames, as long as each DSPI transfers a minimum of 4 bits and a maximum of 16 bits and the total size of the concatenated frame is less than or equal to 48 bits long. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 873: Combined Serial Interface (Csi) Configuration
SPI frames are determined by the DSPIx_CTAR selected by the CTAS field in the SPI command halfword. The transfer attributes for the DSI frames are determined by the DSPIx_CTAR selected by the DSICTAS field in the DSPIx_DSICR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-50 Freescale Semiconductor...
Page 874 When DSI frames are transferred the returned frames are deserialized and latched into the DSPIx_DDR. When SPI frames are transferred the returned frames are deserialized and written to the RX FIFO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-51...
Page 875: Dspi Baud Rate And Clock Delay Generation
Table 19-22. Baud Rate Computation Example Prescaler Scaler Baud Rate Value Value Value 100 MHz 0b00 0b0000 25 Mb/sec 20 MHz 0b00 0b0000 10 Mb/sec MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-52 Freescale Semiconductor...
Page 876 PCSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers select the delay after transfer. Refer to Figure 19-32 for an illustration of the delay after transfer. The following formula expresses the PDT/DT/delay after transfer relationship: × × MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-53...
Page 877 PASC Table 19-26 shows an example of the computed t delay. PCSSCK Table 19-26. Peripheral Chip Select Strobe Assert Computation Example PCSSCK Prescaler Delay before Transfer 0b11 100 MHz 70.0 ns MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-54 Freescale Semiconductor...
Page 878: Transfer Formats
Section 19.4.7.4, “Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1).” In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted between frames. Refer to Section 19.4.7.5, “Continuous Selection Format” for details. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-55...
Page 879 For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 19-32. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-56 Freescale Semiconductor...
Page 880 For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of Figure 19-33. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-57...
Page 881 Table 19-28. Delayed Master Sample Point Number of System Clock Cycles between SMPL_PT Odd-numbered Edge of SCK and Sampling of SIN Invalid value MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-58 Freescale Semiconductor...
Page 882 SCK to PCS delay must be greater or equal to half of the SCK period. NOTE For the modified transfer format to operate correctly, you must thoroughly analyze the SPI link timing budget. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-59...
Page 883 When the CONT bit = 0, the DSPI drives the asserted chip select signals to their idle states in between frames. The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-60...
Page 884 When the CONT bit = 1 and the PCS signals for the next transfer are different from the present transfer, the PCS signals behave as if the CONT bit was not set. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 885: Continuous Serial Communications Clock
At the start of a DSI frame transfer, the CTAR specified by the DSICTAS field is used. • In all configurations, the currently selected CTAR remains in use until the start of a frame with a different CTAR specified, or the continuous SCK mode is terminated. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-62 Freescale Semiconductor...
Page 886 SCK format with continuous selection enabled. (CPOL = 0) (CPOL = 1) Master SOUT Master SIN Transfer 1 Transfer 2 Figure 19-40. Continuous SCK Timing Diagram (CONT=1) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-63...
Page 887: Interrupts/Dma Requests
TCF_RE bit is set in the DSPIx_RSER. Refer to the TCF bit description in Section 19.3.2.4, “DSPI Status Register (DSPIx_SR).” Refer to Figure 19-32 Figure 19-33 that illustrate when TCF is set. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-64 Freescale Semiconductor...
Page 888: Power Saving Features
Changes to the DIS_TXF and DIS_RXF fields of the DSPIx_MCR does not have any affect in the module disable mode. In the module disable mode, all status bits and register flags MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 889: Initialization And Application Information
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit. 11. Enable serial transmission and serial reception of data by clearing the EOQF bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-66 Freescale Semiconductor...
Page 890: Baud Rate Settings
4.88 kHz 3.49 kHz 4096 6.10 kHz 4.07 kHz 2.44 kHz 1.74 kHz 8192 3.05 kHz 2.04 kHz 1.22 kHz 872 Hz 16384 1.53 kHz 1.02 kHz 610 Hz 436 Hz 32768 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-67...
Page 891: Delay Settings
DSPIx_CTARs to match the default cases for the possible combinations of the MPC5xx family control bits in its command RAM. The defaults for the MPC5xx family are based on a system clock of 40 MHz. MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-68 Freescale Semiconductor...
Page 892: Calculation Of Fifo Pointer Addresses
Section 19.4.3.5, “Receive First In First Out (RX FIFO) Buffering Mechanism,” for details on the FIFO operation. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-69...
Page 893 [(RXCTR + POPNXTPTR - 1) modulo RXFIFO depth] where: RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter POPNXTPTR = pop next pointer RX FIFO depth = receive FIFO depth, implementation specific MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-70 Freescale Semiconductor...
Page 894: Document Revision History
Section 19.5.5.2, “Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO,” changed • From: “First-in entry address = TX FIFO base + 4 (POPNXTPTR)” • To: “First-in entry address = RX FIFO base + 4 (POPNXTPTR)” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 19-71...
Page 895 Deserial Serial Peripheral Interface (DSPI) MPC5565 Microcontroller Reference Manual, Rev. 1.0 19-72 Freescale Semiconductor...
Page 896: Introduction
BAUD ÷16 Data format control bus clock generator Transmit control TDRE generation Transmit shift register TC IRQ Finite state eSCI data register machine TX data out Figure 20-1. eSCI Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-1...
Page 897: Overview
• 1/16 bit-time noise detection • Two-channel DMA interface 20.1.4 Modes of Operation The eSCI functions the same in normal, special, and emulation modes. It has a low-power module disable mode. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-2 Freescale Semiconductor...
Page 898: External Signal Description
The total address for each register is the sum of the base address for the eSCI module (ESCIx_base) and the address offset for each register. There are two eSCI modules on this device: • eSCI A base address is 0xFFFB_0000 • eSCI B base address is 0xFFFB_4000 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-3...
Page 899: Register Descriptions
20.3.3.1 eSCI Control Register 1 (ESCIx_CR1) Address: Base + 0x0000 Access: R/W Reset LOOPS RSRC WAKE TCIE ILIE Reset Figure 20-2. eSCI Control Register 1 (ESCIx_CR1) MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-4 Freescale Semiconductor...
Page 900 During reception, the received parity bit is verified in the most significant bit position. The received parity bit is not masked out. 0 Parity function disabled 1 Parity function enabled MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-5...
Page 901 Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters. 0 No break characters 1 Transmit break characters MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-6 Freescale Semiconductor...
Page 902 Activate RX DMA channel. If this bit is enabled and the eSCI has received data, it raises a DMA RX request. RXDMA Activate TX DMA channel. Whenever the eSCI is able to transmit data, it raises a DMA TX request. TXDMA MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-7...
Page 903 Parity flag interrupt enable. Generates an interrupt, when parity flag is set. For a list of interrupt enables and flags, PFIE Refer to Table 20-21. 20.3.3.3 eSCI Data Register (ESCIx_DR) Address: Base + 0x0006 Access: R/W Reset Figure 20-4. eSCI Data Register (ESCIx_DR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-8 Freescale Semiconductor...
Page 904 All bits in ESCIx_SR except for RAF are cleared by writing 1 to them. Address: Base + 0x0008 Access: R/W1c R TDRE RDRF IDLE BERR W w1c Reset LWAKE STO CERR OVFL W w1c Reset Figure 20-5. eSCI Status Register (ESCIx_SR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-9...
Page 905 Parity error flag. PF is set when the parity enable bit, PE, is set and the parity of the received data does not match its parity bit. Clear PE by writing 1 to it. 0 No parity error 1 Parity error 8–10 Reserved, Must be 0. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-10 Freescale Semiconductor...
Page 906 ESCIx_LRR overflow. The LIN receive register has not been read before a new data byte, CRC, or checksum byte OVFL has been received from the LIN bus. Set when the condition is detected, and cleared by writing 1 to it. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-11...
Page 907 Double stop flags. When a bit error is detected, an additional stop flag is added to the byte in which the error occurred. Activating parity generation. Generate the two parity bits in the LIN header. PRTY MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-12 Freescale Semiconductor...
Page 908 Additionally it is possible to flush the ESCIx_LTR by setting the ESCIx_LCR[LRES] bit. NOTE Not all values written to the ESCIx_LTR generate valid LIN frames. The values are determined according to the LIN specification. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-13...
Page 909 3rd Write (Table 20-10) W HDCHK CSUM TX (RX) T[11:8] 4th Write (Table 20-11) W T[7:0] 5th Write (Table 20-12) W D[7:0] Reset Figure 20-8. LIN Transmit Register (ESCIx_LTR) Alternate Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-14 Freescale Semiconductor...
Page 910 Transmit direction. Indicates that the eSCI transmits a frame to a slave. Otherwise, an RX frame is assumed, and the eSCI only transmits the header. The data bytes are received from the slave. 0 RX frame 1 TX frame MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-15...
Page 911 The timeout period starts with the transmission of the LIN break character. 8–31 Reserved. Table 20-12. ESCIx_LTR Tx Frame Fourth+ Byte/ Rx Frame Fifth+ Byte Field Description Field Description 0–7 Data bits for transmission. 8–31 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-16 Freescale Semiconductor...
Page 912 LIN bus otherwise the data byte is lost and OVFL is set. Note: The data must be collected and the LIN frame finished (including CRC and checksum if applicable) before a wake-up character can be sent. 8–31 Reserved. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-17...
Page 913: Functional Description
CPU and remote devices, including other CPUs. The eSCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the eSCI, writes the data to be transmitted, and processes received data. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-18 Freescale Semiconductor...
Page 914: Data Format
Bit M in ESCIx_CR1 Set Data Bit START START Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 STOP Figure 20-12. eSCI Data Formats MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-19...
Page 915: Baud Rate Generation
SBR[0:12] Clock (Hz) Clock (Hz) Rate 0x0023 3,657,143 228,571 230,400 –0.79 0x0045 1,855,072 115,942 115,200 +0.64 0x008B 920,863 57,554 57,600 –0.01 0x00D0 615,385 38,462 38,400 +0.16 0x01A1 306,954 19,185 19,200 –0.08 MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-20 Freescale Semiconductor...
Page 916: Transmitter
LOOP Control Load from Shift Preamble Break ESCIx_DR enable (All 1s) (All 0s) LOOPS Parity generation RSRC Transmitter control TDRE TDRE interrupt request interrupt TCIE request Figure 20-13. eSCI Transmitter Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-21...
Page 917 ESCIx_DR, where the ninth bit is written to the T8 bit in ESCIx_DR if the eSCI is in 9-bit data format. 3. Repeat step 2 for each subsequent transmission. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-22 Freescale Semiconductor...
Page 918 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 919 Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the eSCI data register. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-24 Freescale Semiconductor...
Page 920 Section 20.4.5.3, “Data Sampling.”). TX Output Shift Reg Compare Sample RX Input Points Shift Reg BESM13 = 0 BESM13 = 1 Clock RT Clock Count Figure 20-15. Fast Bit Error Detection Timing Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-25...
Page 921: Receiver
If the receive interrupt enable bit, RIE, in eSCI control register 1 (ESCIx_CR1) is also set, the RDRF flag generates an RDRF interrupt request. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-26...
Page 922 RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-27...
Page 923 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 20-20 summarizes the results of the stop bit samples. Table 20-20. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-28 Freescale Semiconductor...
Page 924 The receiver samples an incoming frame and re-synchronizes the RT clock on any valid falling edge within the frame. Re-synchronization within frames corrects a misalignment between transmitter bit times and receiver bit times. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-29...
Page 925 The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 4.19%, as is shown below: 167 – 160 × ------------------------- - 4.19% MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-30 Freescale Semiconductor...
Page 926 The receiver can be put into a standby state, which disregards all input requests targeted for other receivers in multiple-receiver systems. Setting the receiver wake-up bit (RWU) in eSCI control register 1 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor...
Page 927 Address mark wake-up allows messages to contain idle characters but requires that the msb be reserved for use in address frames. NOTE With the WAKE bit clear, setting the RWU bit after the RXD signal has been idle can cause the receiver to wake-up immediately. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-32 Freescale Semiconductor...
Page 928: Single-Wire Operation
(ESCIx_CR1). Setting the LOOPS bit disables the path from the RXD signal to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-33...
Page 929: Modes Of Operation
When TC is set, the TXD pin becomes idle (logic 1). The TC bit is cleared by writing a one to the TC bit location in the ESCIx_SR. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-34 Freescale Semiconductor...
Page 930 ESCIx_SR[17] TXIE mode, the transmitter ready (TXRDY) flag is set when the eSCI can accept a control or data byte. Clear the TXRDY flag by writing a 1 to the bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-35...
Page 931 CPU load. The OVFL flag is cleared by writing a 1 to the bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-36 Freescale Semiconductor...
Page 932: Using The Lin Hardware
The eSCI and FlexCAN modules use the same CRC polynomial, the LIN protocol processes CAN bytes as data bytes. Break Sync Data • • • Data CRC1 CRC2 CSum Figure 20-24. LIN Frame with CRC bytes MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-37...
Page 933 In contrast to the standard software implementation where each byte transmission requires several interrupts, the DMA controller and eSCI handle communication, bit error and physical bus error checking, checksum, and CRC generation (checking on the RX side). MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-38 Freescale Semiconductor...
Page 934 CPU. NOTE It is also possible to setup a whole sequence of RX and TX frames, and generate a single event at the end of that sequence. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-39...
Page 935 (FE) flag in the eSCI status register. If the RXD input remains at the same value for 15 cycles after a transmission starts, the LIN hardware sets the PBERR flag in the LIN status register. A bit error can also occur. MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-40 Freescale Semiconductor...
Page 936: Document Revision History
• A single 32-bit write to ESCI_CR1 can be used in place of steps b–d above.” Table 20-21: Incorporated the interrupt flag descriptions into this table. Rewrote section of chapter to remove vague verbose passive voice to active concise text. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 20-41...
Page 937 Enhanced Serial Communication Interface (eSCI) MPC5565 Microcontroller Reference Manual, Rev. 1.0 20-42 Freescale Semiconductor...
Page 938: Introduction
This FlexCAN2 version implements individual mask registers and a reception queue thereby allowing queuing of received frames before requiring interrupt processing. Also included is a feature for disabling self-reception of TX frames. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-1...
Page 939: Block Diagram
CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. Sixty-four message buffers (MBs) are stored in an embedded 1024-byte RAM dedicated to the FlexCAN2 module. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-2 Freescale Semiconductor...
Page 940: Features
Independent of the transmission medium (an external transceiver is assumed) • Multi master concept • High immunity to EMI • Short latency time due to an arbitration scheme for high-priority messages MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-3...
Page 941: Modes Of Operation
21.2.1 Overview The FlexCAN2 module has two I/O signals connected to the external MCU pins. These signals are summarized in Table 21-1 and described in more detail in the next sub-sections. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-4 Freescale Semiconductor...
Page 942: Detailed Signal Description
Free running timer Base + 0x000C — Reserved — Base + 0x0010 CANx_RXGMASK RX global mask Base + 0x0014 CANx_RX14MASK RX buffer 14 mask Base + 0x0018 CANx_RX15MASK RX buffer 15 mask MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-5...
Page 943: Message Buffer Structure
The message buffer structure used by the FlexCAN2 module is represented in Figure 21-2. Both extended and standard frames (29-bit identifier and 11-bit identifier, respectively) used in the CAN specification (version 2.0 Part B) are represented. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-6 Freescale Semiconductor...
Page 944 Data field. Up to eight bytes can be used for a data frame. For RX frames, the data is stored as it is received from the CAN bus. For TX frames, the CPU prepares the data field to be transmitted within the frame. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-7...
Page 945 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. 1100 0100 Transmit remote frame unconditionally once. After transmission, the MB automatically becomes and RX MB with the same ID. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-8 Freescale Semiconductor...
Page 946: Register Descriptions
MAXMB field, which should only be changed while the module is in freeze mode. Address: Base + 0x0000 Access: User read/write NOTRDY 0 FRZACK MDISACK MDIS FRZ HALT SOFTRST MBFEN Reset MAXMB Reset Figure 21-3. Module Configuration Register (CANx_MCR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-9...
Page 947 The SOFTRST bit remains asserted while reset is pending, and is automatically negated when reset completes. Therefore, software can poll this bit to know when the soft reset has completed. 0 No reset request 1 Resets values in registers indicated above. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-10 Freescale Semiconductor...
Page 948 0 Individual RX masking and reception queue features are disabled (thus the device is compatible with previous FlexCAN versions, i.e. one global mask register is used). 1 Individual RX masking and reception queue features are enabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-11...
Page 949 Resync jump width. Defines the maximum number of time quanta that a bit time can be changed by one RJW[0:1] re-synchronization. The valid programmable values are 0–3. Resync Jump Width RJW + 1 MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-12 Freescale Semiconductor...
Page 950 0 Just one sample is used to determine the RX bit value 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-13...
Page 951 The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. This captured value is written into the TIME STAMP entry in a message buffer after a successful reception or transmission of a message. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-14 Freescale Semiconductor...
Page 952 RX 14 Mask 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-15...
Page 953 Standard ID mask bits. These bits are the same mask bits for the standard and extended formats. 14–31 Extended ID mask bits. These bits are used to mask comparison only in extended format. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-16 Freescale Semiconductor...
Page 954 Access: User R/W MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 Reset MI15 MI14 MI13 MI12 MI11 MI10 Reset Figure 21-7. RX Individual Mask Registers (CANx_RXIMR0 – CANx_RXIMR63) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-17...
Page 955 (indicated by the ACKERR bit in CANx_ESR). After the transition to the ‘error passive’ state, the TXECTR does not increment anymore by acknowledge errors. Therefore the device never goes to the bus off state. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-18 Freescale Semiconductor...
Page 956 TLB entry covering the CANx_ESR must be configured to be guarded. Address: Base + 0x0020 Access: User R/W TWRN RWRN Reset R BIT1 BIT0 BOFF IDLE TXRX FLTCONF Reset Figure 21-9. Error and Status Register (CANx_ESR) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-19...
Page 957 0 No such occurrence 1 TXECTR ≥ 96 RX error counter. This status bit indicates when repetitive errors are occurring during messages reception. RXWRN 0 No such occurrence 1 RXECTR ≥ 96 MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-20 Freescale Semiconductor...
Page 958 (that is, when the corresponding IFRH bit is set). Address: Base + 0x0024 Access: User R/W R BUF Reset R BUF Reset Figure 21-10. Interrupt Masks High Register (CANx_IMRH) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-21...
Page 959 Each successful transmission or reception sets the corresponding IFRH bit. If the corresponding IMRH bit is set, an interrupt will be generated. The interrupt flag may be cleared by writing it to 1. Writing 0 has no effect. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-22 Freescale Semiconductor...
Page 960 The interrupt flag may be cleared by writing it to 1. Writing 0 has no effect. Address: Base + 0x0030 Access: User R/W R BUF W w1c Reset R BUF W w1c Reset Figure 21-13. Interrupt Flags Low Register (CANx_IFRL) MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-23...
Page 961: Functional Description
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-24...
Page 962: Receive Process
DATA field (8 bytes at most), and the LENGTH field are stored, the CODE field is updated, and a status flag is set in CANx_IFRL or CANx_IFRH, and an interrupt is generated if the corresponding interrupt mask is enabled in CANx_IMRL/H. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-25...
Page 963 1. If, however, the CPU has read the MB2 data and released it before the next matching process at the CRC frame, then, even if the MB2 RX code is FULL, the MB2 is free to receive and the message will be stored in MB2 rather than in MB5. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-26...
Page 964: Message Buffer Handling
If a TX MB containing the lowest ID (or lowest buffer if LBUF is set) is deactivated after FlexCAN2 has scanned it while in arbitration process, then FlexCAN2 can transmit a MB with ID that may not be the lowest at the time. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-27...
Page 965 CANx_ESR. • If a locked MB is released, and there exists a matching frame within the SMB, this frame is then transferred to the matching MB. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-28 Freescale Semiconductor...
Page 966: Can Protocol Related Features
The FlexCAN2 module supports a variety of means to setup bit timing parameters that are required by the CAN protocol. The CANx_CR has various fields used to control bit timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW. Refer to Section 21.3.3.2, “Control Register (CANx_CR).” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-29...
Page 967 Figure 21-14. Segments within the Bit Time 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-30 Freescale Semiconductor...
Page 968 The system clock frequency cannot be smaller than the oscillator clock frequency, i.e. the PLL cannot be programmed to divide down the oscillator clock. • There must be a minimum ratio of 16 between the system clock frequency and the CAN bit rate. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-31...
Page 969: Modes Of Operation Details
This low power mode is entered when the CANx_MCR[MDIS] bit is asserted. If the module is disabled during freeze mode, it shuts down the clocks to the CPI and MBM sub-modules, sets the CANx_MCR[MDISACK] bit and negates the CANx_MCR[FRZACK] bit. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-32 Freescale Semiconductor...
Page 970: Interrupts
Byte, word and long word accesses are allowed to the unused MB space. NOTE Unused MB space must not be used as general purpose RAM while FlexCAN is transmitting and receiving CAN frames. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-33...
Page 971: Initialization And Application Information
Set required mask bits in CANx_IMRH and CANx_IMRL registers (for all MBs interrupts), and in CANx_CR (for bus off and error interrupts). • Negate the CANx_MCR[HALT] bit. Starting with this last event, FlexCAN2 attempts to synchronize with the CAN bus. MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-34 Freescale Semiconductor...
Page 972: Flexcan2 Addressing And Ram Size
• Most of the fields in this register should only be changed while the module is disabled or in freeze mode. • Table 21-8: CANx_CR Field Descriptions: Deleted from field description for CLK_SRC: To guarantee reliable operation, this bit should only be changed while the module is disabled. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 21-35...
Page 973 Preface MPC5565 Microcontroller Reference Manual, Rev. 1.0 21-36 Freescale Semiconductor...
Page 974: Introduction
Introduction The voltage regulator controller (VRC) and power-on reset (POR) module contains circuitry to control regulation of the external 1.5 V supply used by the MPC5565. It also contains POR circuits for the 1.5 V supply, V and the V supply that powers the RESET pad.
Page 975: External Signal Description
The voltage regulator RCCTL controller slowly turns on the pass transistor while the 3.3 V POR is asserted. The pass transistor is completely turned on by the time the 3.3 V POR negates. MPC5565 Microcontroller Reference Manual, Rev. 1.0 22-2 Freescale Semiconductor...
Page 976: Por Circuits
The PORs for each supply are not intended to indicate that the voltage has dropped below the specified voltage range. You must monitor the supplies externally and assert RESET to achieve precise monitoring. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 22-3...
Page 977 The RESET power POR circuit monitors the supply that powers the RESET pin, and ensures that the voltage supply to the RESET pin is high enough to reliably propagate the state of the input. The supply monitored by this POR cannot exceed 5.5 V. MPC5565 Microcontroller Reference Manual, Rev. 1.0 22-4 Freescale Semiconductor...
Page 978: Initialization And Application Information
ON Semiconductor NJD2873 • Phillips Semiconductor BCP68 Refer to the MPC5565 Microcontroller Data Sheet for information on the operating characteristics. 22.5.3 Power Sequencing Requirements This section describes the following power sequencing requirements for the device: • If an external 1.5 V power supply is used and V...
Page 979 This ensures that the digital 1.5 V logic, which is reset by the ORed POR only that can cause the 1.5 V supply to decrease below its specification, is reset correctly. MPC5565 Microcontroller Reference Manual, Rev. 1.0 22-6 Freescale Semiconductor...
Page 980 Refer to the following sections or documents for more information: Section 22.5.3.4, “Pin Values after POR Negates” MPC5565 Microcontroller Data Sheet for the VDD33_LAG specification. 22.5.3.4 Pin Values after POR Negates Depending on the final PLL mode required, the PLLCFG[0:1] and RSTCFG pins must have the values...
Page 981: Document Revision History
The behavior for each POR during power sequencing is shown in Figure 22-2. “ Section 22.2, “External Signal Description,” incorporated the detailed signal descriptions in Table 22-1 “Voltage Regulator Control and POR Block External Signals.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 22-8 Freescale Semiconductor...
Page 982: Introduction
Power-on Test access port (TAP) reset controller 1-bit bypass register 32-bit device identification register Boundary scan register 5-bit TAP instruction decoder 5-bit TAP instruction register Figure 23-1. JTAG Controller Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 23-1...
Page 983: Overview
The instruction register is loaded with the IDCODE instruction. In addition, execution of certain instructions can result in assertion of the internal system reset. These instructions include EXTEST, CLAMP, and HIGHZ. MPC5565 Microcontroller Reference Manual, Rev. 1.0 23-2 Freescale Semiconductor...
Page 984 JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive. For more information on the TAP controllers refer to Chapter 24, “Nexus Development Interface.” MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 23-3...
Page 985: External Signal Description
During the capture-IR TAP controller state, the instruction shift register is loaded with the value 0b10101, making this value the register’s read value when the TAP controller is sequenced into the Shift-IR state. Instruction Code Reset Figure 23-2. 5-Bit Instruction Register MPC5565 Microcontroller Reference Manual, Rev. 1.0 23-4 Freescale Semiconductor...
Page 986: Bypass Register
Design center. Indicates the Freescale design center. For the MPC5565 this value is 0x20. 10–19 Part identification number. Contains the part number of the device. For the MPC5565, this value is 0x165. 20–30 Manufacturer identity code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for Freescale, 0xE.
Page 987: Functional Description
TMS signal sampled on the rising edge of the TCK signal. Figure 23-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the test-logic-reset state. MPC5565 Microcontroller Reference Manual, Rev. 1.0 23-6 Freescale Semiconductor...
Page 988 NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 23-5. IEEE 1149.1-2001 TAP Controller Finite State Machine MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 23-7...
Page 989: Jtagc Instructions
Grants the Nexus dual-eTPU development interface (NDEDI) ownership of the TAP ACCESS_AUX_TAP_DMA 10011 Grants the Nexus crossbar DMA interface (NXDM) ownership of the TAP BYPASS 11111 Selects bypass register for data operations MPC5565 Microcontroller Reference Manual, Rev. 1.0 23-8 Freescale Semiconductor...
Page 990 SAMPLE/PRELOAD instruction before the selection of EXTEST. EXTEST asserts the internal system reset for the MCU to force a predictable internal state while performing external boundary scan operations. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 23-9...
Page 991: Boundary Scan
The boundary scan register consists of this shift-register chain, and is connected between TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register chain contains a serial input and serial output, as well as clock and control signals. MPC5565 Microcontroller Reference Manual, Rev. 1.0 23-10 Freescale Semiconductor...
Page 992: Initialization/Application Information
2. Load the appropriate instruction for the test or action to be performed. 23.6 Document Revision History Table 23-4. Changes Between MPC5565RM Revisions 0.1 and 1 No changes since the last release. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 23-11...
Page 993 IEEE 1149.1 Test Access Port Controller (JTAGC) MPC5565 Microcontroller Reference Manual, Rev. 1.0 23-12 Freescale Semiconductor...
Page 994: Introduction
TAP is achieved by loading the appropriate enable instruction for the desired Nexus client in the JTAG controller (JTAGC) when JCOMP is asserted. Refer to Table 24-4 for the JTAGC opcodes to access the different Nexus clients. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 24-1...
Page 995: Block Diagram
JTAG port controller Auxiliary port • • • JCOMP EVTI MSEO[0:1] MCKO MDO(4 or 12) EVTO Some MPC5500 devices have one eTPU engine, others have two engines. Figure 24-1. NDI General Block Diagram MPC5565 Microcontroller Reference Manual, Rev. 1.0 24-2 Freescale Semiconductor...
Page 996: Features
DMA generated reads and/or writes to selected address ranges in the device’s memory map. — Watchpoint messaging (WPM) via the auxiliary port. — Watchpoint trigger enable/disable of data trace messaging. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 24-3...
Page 997: Modes Of Operation
Following negation of power-on reset, the NPC remains in reset until the system clock achieves lock. In PLL bypass mode, the NDI can transition out of the reset state immediately following negation of power-on reset. Refer to Section 24.4.5, “System Clock Locked Indication” for more details. MPC5565 Microcontroller Reference Manual, Rev. 1.0 24-4 Freescale Semiconductor...
Page 998 Nexus modules in reset as well. This prevents Nexus read/write to memory mapped resources and the transmission of Nexus trace messages. Refer to Table 13-16 information on Nexus port enabling and disabling regarding censorship. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 24-5...
Page 999: External Signal Description
EVTO signals from all Nexus modules that implement the signal. 24.2.1.2 Event In (EVTI) EVTI is used to initiate program and data trace synchronization messages or to generate a breakpoint. EVTI is edge-sensitive for synchronization and breakpoint generation. MPC5565 Microcontroller Reference Manual, Rev. 1.0 24-6 Freescale Semiconductor...
Page 1000 The TDI pin receives serial test instruction and data. TDI is sampled on the rising edge of TCK. 24.2.1.10 Test Mode Select (TMS) The TMS pin is used to sequence the IEEE® 1149.1-2001 TAP controller state machine. TMS is sampled on the rising edge of TCK. MPC5565 Microcontroller Reference Manual, Rev. 1.0 Freescale Semiconductor 24-7...

Freescale Semiconductor MPC5565 Reference Manual

Introduction

Chapter 1

Chapter 10 Interrupt Controller (INTC)

Chapter 5 System Integration Unit (SIU)

Chapter 2

Chapter 3 Microarchitecture Summary

Chapter 4

5.3 Memory Map and Register Definitions

Chapter 7

8.2.1 Register Descriptions

Chapter 11

Chapter 12

Chapter 13

Chapter 14

Chapter 15 BAM Program Operation

Chapter 16

Chapter 20

Chapter 17

Chapter 18

Chapter 23 Modes of Operation

Chapter 19

Chapter 24 Modes of Operation

Chapter 21

Chapter 22 POR Circuits

Chapter 8

Chapter 9

Appendix A B.4.2 Pad Ring

Quick Links

Chapters

Need help?

Questions and answers

Related Manuals for Freescale Semiconductor MPC5565

Summary of Contents for Freescale Semiconductor MPC5565