Freescale Semiconductor MPC5634M Manual

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MPC563XM Microcontroller

Reference Manual

Devices Supported:

MPC5634M

MPC5633M

MPC5632M

MPC563XRM

Rev. 1

25 Jul 2008

MPC563XM Reference Manual, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

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Page 1 MPC563XM Microcontroller Reference Manual Devices Supported: MPC5634M MPC5633M MPC5632M MPC563XRM Rev. 1 25 Jul 2008 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 2 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 3: Table Of Contents
3.1.1 144 LQFP ..........................63 3.1.2 Ballmap: 208 MAPBGA ....................65 External Signal Summary ........................66 Detailed Signal Descriptions ......................76 3.3.1 Reset / Configuration ......................76 3.3.2 Calibration External Bus Interface (EBI) .................76 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 4 Overview ............................105 Modes of Operation ........................105 5.2.1 Normal Mode ........................105 5.2.2 Debug Mode ........................105 5.2.3 Low Power Modes ......................105 Modes and Clock Architecture ......................106 5.3.1 Block Diagrams ......................106 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 5 8.1.2 Device-Specific Features ....................169 8.1.3 Device-Specific Register Information ................170 Introduction ...........................171 8.2.1 Overview .........................171 8.2.2 Features ...........................173 8.2.3 Limitations ........................173 8.2.4 General Operation ......................173 XBAR Registers ..........................174 8.3.1 Register Summary ......................174 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 6 10.3.2 C90FL Block Features ....................215 10.3.3 C90FL Modes of Operation ....................216 10.3.4 C90FL Block Diagram ....................216 10.3.5 C90FL Flash EEPROM Functional Description ............217 10.3.6 C90FL Memory Map and Register Definition ...............219 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 7 12.6 Functional Description ........................300 12.6.1 Access Timing .........................300 12.7 Module Memory Map ........................301 12.8 Register Descriptions ........................301 Chapter 13 External Bus Interface (EBI) 13.1 Information Specific to This Device .....................303 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 8 14.3.1 Normal Mode ........................414 14.3.2 Debug Mode ........................415 14.3.3 Stop Mode ........................415 14.3.4 Factory Test Mode ......................415 14.4 External Signal Description ......................416 14.5 Memory Map/Register Definition ....................416 14.5.1 Memory Map ........................416 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 9 System Integration Unit (SIU) 16.1 Overview ............................465 16.2 Features ............................465 16.3 Modes of Operation ........................466 16.3.1 Normal Mode ........................466 16.3.2 Debug Mode ........................466 16.4 Block Diagram ..........................466 16.5 Signal Description .........................467 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 10 16.9.23Compare A High Register ....................548 16.9.24Compare A Low Register ....................548 16.9.25Compare B High Register ....................549 16.9.26Compare B Low Register ....................549 16.9.27System Clock Register (SIU_SYSDIV) .................550 16.9.28Halt Register (SIU_HLT) ....................551 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 11 19.2.3 Modes of Operation ......................591 19.3 External Signal Description ......................591 19.4 Memory Map and Register Definition ..................592 19.4.1 Memory Map ........................592 19.4.2 Register Descriptions ......................592 19.5 Functional Description ........................596 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 12 22.1.1 Device-Specific Features ....................623 22.1.2 Device-Specific Channel Information ................623 22.1.3 Device-Specific Register Information ................625 22.2 Introduction ...........................626 22.2.1 Overview .........................627 22.2.2 Features ...........................627 22.2.3 Modes of Operation ......................627 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 13 23.4.5 Enhanced Channels ......................798 23.4.6 Time Bases ........................842 23.4.7 EAC - eTPU Angle Counter ...................849 23.4.8 Microengine ........................868 23.4.9 Microinstruction Set .......................885 23.4.10Test and Development Support ..................917 23.5 Initialization/Application Information ..................924 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 14 24.6.6 On-Chip ADC Configuration and Control ..............1065 24.6.7 Internal/External Multiplexing ..................1074 24.6.8 EQADC DMA/Interrupt Request .................1080 24.6.9 EQADC Synchronous Serial Interface (SSI) Sub-Block ..........1083 24.6.10EQADC Parallel Side Interface (PSI) Sub-Block ............1088 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 15 25.6.1 Initialization Procedure ....................1140 25.7 Application Information ......................1140 25.7.1 EQADC IP as the Master Block ...................1140 25.8 Filter Example Simulation ......................1141 25.8.1 Coefficients Calculation ....................1141 25.8.2 Input Data Calculation ....................1142 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 16 Enhanced Serial Communication Interface (eSCI) 27.1 Introduction ..........................1213 27.1.1 Bibliography .........................1213 27.1.2 Acronyms and Abbreviations ..................1213 27.1.3 Glossary ........................1213 27.1.4 Overview ........................1214 27.1.5 Features .........................1214 27.1.6 Modes of Operation ......................1215 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 17 28.5.6 Data Coherence ......................1302 28.5.7 Rx FIFO ........................1305 28.5.8 CAN Protocol Related Features ..................1305 28.5.9 Modes of Operation Details ..................1310 28.5.10Interrupts ........................1313 28.5.11Bus Interface .........................1313 28.6 Initialization/Application Information ..................1314 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 18 30.4.5 1.2V Voltage Regulator Controller ................1343 30.4.6 1.2V LVI ........................1344 30.4.7 LVI 1.0V ........................1344 30.4.8 Resets and Interrupts .....................1344 30.5 Application Information ......................1347 30.5.1 Regulator Example .......................1347 30.5.2 Recommended Power Transistors .................1347 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 19 32.4 Register Definition ........................1368 32.4.1 Register Descriptions ....................1369 32.5 Functional Description ........................1373 32.5.1 NPC Reset Configuration .....................1373 32.5.2 Auxiliary Output Port ....................1373 32.5.3 IEEE 1149.1-2001 (JTAG) TAP ...................1376 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 20 32.5.5 MCKO and ipg_sync_mcko ..................1380 32.5.6 EVTO Sharing ......................1380 32.5.7 Nexus Reset Control .....................1380 32.5.8 System Clock Locked Indication ..................1380 32.6 Initialization/Application Information ..................1381 32.6.1 Accessing NPC tool-mapped registers .................1381 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 21 IEEE-ISTO 5001-2003 Standard for a Global Embedded Processor Interface (Nexus) • IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture • Power Architecture Book E V1.0 (http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf?fsrch=1) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 22 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 23: The Mpc563Xm Microcontroller Family
Controller Area Network, and an enhanced modular input-output system, that are important for today’s lower-end powertrain applications MPC563XM Device Summary Table 1-1 summarizes the MPC563XM family of microcontrollers. Table 1-1. MPC563XM Device Summary Feature MPC5634M MPC5633M MPC5632M Flash memory size (KB) 1536 1024 RAM size (KB)
Page 24: Mpc563Xm Blocks
Table 1-1. MPC563XM Device Summary (continued) Feature MPC5634M MPC5633M MPC5632M JTAG controller Microsecond Bus compatible interface NDI (Nexus development interface) level Class 2+ Class 2+ Class 2+ Non-maskable interrupt and critical interrupt PIT (peripheral interrupt timers) Task monitor timer 4 channels...
Page 25: Block Summary
MPC563XM family. Table 1-2. MPC563XM Block Summary Block Function e200z335 core Executes programs and interrupt handlers Flash memory Provides storage for program code, constants, and variables MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 26: Mpc563Xm Features
— Low power design – Less than 400 mW power dissipation (nominal) – Designed for dynamic power management of core and peripherals – Software controlled clock gating of peripherals MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 27 – Branch acceleration using Branch Lookahead Instruction Buffer — Load/store unit – One-cycle load latency – Fully pipelined – Big and Little Endian support – Misaligned access support – Zero load-to-use pipeline bubbles MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 28 — Supports variable sized queues and circular queues — Source and destination address registers are independently configured to post-increment or remain constant — Each transfer is initiated by a peripheral, CPU, or eDMA channel request MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 29 — Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output clocks – User-selectable ability to generate an interrupt request upon loss of clock MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 30 – Quadruple 128-bit wide prefetch/burst buffers – Prefetch buffers can be configured to prefetch code or data or both — Censorship protection scheme to prevent flash content visibility MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 31 — Memory block: – For MPC5634M: 18 blocks (4 x 16 KB, 2 x 32 KB, 2 x 64 KB, 10x 128 KB) – For MPC5633M: 14 blocks (4 x 16 KB, 2 x 32 KB, 2 x 64 KB, 6x 128 KB) –...
Page 32 – Supports both right-justified unsigned and signed formats for conversion results – Temperature sensor to enable measurement of die temperature – Ability to measure all power supply pins directly MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 33 – Compatible with Microsecond Bus Version 1.0 downlink • 2 enhanced serial communication interface (eSCI) modules — UART mode provides NRZ format and half or full duplex interface MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 34 — A 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions — A 5-bit instruction register that supports additional public instructions — 3 test data registers: a bypass register, a boundary scan register, and a device identification register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 35: E200Z335 Core
All other taken branches have an execution time of two clocks. Memory load and store operations are provided for MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 36 Interrupt is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed to be recoverable (code execution may be resumed from where it stopped). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 37: Crossbar
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes • Transfer control descriptor organized to support two-deep, nested transfer operations • An inner data transfer loop defined by a “minor” byte transfer count MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 38: Interrupt Controller
• Hardware connection to processor or read from register • Each interrupt source can be programmed to one of 16 priorities • Preemptive prioritized interrupt requests to processor MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 39: Fmpll
— detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system clock to the crystal clock and causes an interrupt request MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 40: Calibration Ebi
Optional automatic CLKOUT gating to save power and reduce EMI • Compatible with MPC5xx external bus (with some limitations) • Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 41: Ecsm
— Allows selection of interrupt requests between external pins and DSPI 1.4.9 ECSM The error correction status module provides status information regarding platform memory errors reported by error-correcting codes. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 42: Flash
Embedded hardware program and erase algorithm • Erase suspend, program suspend and erase-suspended program • Shadow information stored in non-volatile shadow block • Independent program/erase of the shadow block MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 43: Sram
The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual output compare as well as PWM output. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 44: Etpu
Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 45 — 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 46: Eqadc
The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 47 Decimation Filter — Programmable decimation factor (2 to 16) — Selectable IIR or FIR filter — Up to 4th order IIR or 8th order FIR — Programmable coefficients MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 48: Dspi
— programmable inter-frame gap in continuous mode — bit source selection allows microsecond bus downlink with command or data frames up to 32 bits — Microsecond bus dual receiver mode MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 49 — FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty) — FIFO Overrun (serial frame received while RX FIFO is full) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 50: Esci
— Autonomous transmission of entire frames — Configurable to support all revisions of the LIN standard — Automatic parity bit generation — Double stop bit after bit error MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 51: Flexcan
32 partial (8 bits) IDs, with individual masking capability • Selectable backwards compatibility with previous FlexCAN versions • Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 52: System Timers
The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR . It consists of a single 32-bit counter, clocked by the system clock, and four independent MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 53: Software Watchdog Timer (Swt)
5 V I/O signals to increase usable I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using VertiCal calibration. In the VertiCal calibration package, the full 12-bit Auxiliary port is available. See http://www.autosar.org/ MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 54 (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. — Watchpoint trigger enable of program trace messaging MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 55: Jtag
— Boundary scan register — Device identification register • A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry • Censorship Inhibit Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 56 — If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 57: Introduction
Under software control of the Memory Management Unit (MMU), the logical addresses allocated to IP blocks may be changed on a minimum of a 4 KB boundary. Memory Map Table 2-1 shows the MPC5634M memory map. Table 2-1. MPC5634M Memory Map Flash Memory (1.5 MB) 0x0000_0000...
Page 58 Table 2-1. MPC5634M Memory Map (continued) 0xC3F9_0000 eSCI_B 0xFFFB_4000 0xC3F9_3FFF 0xFFFB_7FFF Reserved 0xC3F9_4000 Reserved 0xFFFB_8000 0xC3F9_FFFF 0xFFFB_FFFF eMIOS 0xC3FA_0000 FlexCAN_A 0xFFFC_0000 0xC3FA_3FFF 0xFFFC_3FFF 0xC3FA_4000 Reserved 0xFFFC_4000 0xC3FB_FFFF 0xFFFC_7FFF eTPU Registers 0xC3FC_0000 FlexCAN_C 0xFFFC_8000 0xC3FC_3FFF 0xFFFC_9FFF Reserved 0xC3FC_4000 Reserved for FlexCAN_C...
Page 59 Table 2-2. Detailed MPC5634M Memory Map (continued) Allocated Used Size Address Range Size (bytes) (bytes) 0xC3F9_8000 - 0xC3F9_BFFF 16 K Reserved 0xC3F9_C000 - 0xC3F9_FFFF 16 K Not allocated 0xC3FA_0000 - 0xC3FA_3FFF 16 K Modular Timer System (eMIOS_A) 0xC3FA_4000 - 0xC3FA_7FFF...
Page 60 Table 2-2. Detailed MPC5634M Memory Map (continued) Allocated Used Size Address Range Size (bytes) (bytes) 0xFFF3_0000 - 0xFFF3_3FFF 16 K Not Allocated 0xFFF3_4000 - 0xFFF3_7FFF 16 K Reserved 0xFFF3_8000 - 0xFFF3_BFFF 16 K 0xFFF3_C000 - 0xFFF3_FFFF 16 K 0xFFF4_0000 - 0xFFF4_3FFF...
Page 61 Table 2-2. Detailed MPC5634M Memory Map (continued) Allocated Used Size Address Range Size (bytes) (bytes) 0xFFFC_A000 - 0xFFFC_FFFF Reserved for FlexCAN_C (higher MSBs) 0xFFFD_0000 - 0xFFFD_3FFF 16 K Reserved 0xFFFD_4000 - 0xFFFD_7FFF 16 K Reserved 0xFFFD_8000 - 0xFFFD_BFFF 16 K...
Page 62 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 63: Device Pin Assignments
This chapter describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. Device Pin Assignments 3.1.1 144 LQFP Figure 3-1 shows the pinout of the 144-pin LQFP. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 64 PCSB5 ETPUA23 VDDEH1A RSTOUT ETPUA22 CNTXC TXDA ETPUA21 RXDA ETPUA20 CNRXC ETPUA19 RESET ETPUA18 ETPUA17 VDDEH6A ETPUA16 VSSPLL ETPUA15 XTAL VDDEH1B EXTAL ETPUA14 VDDPLL Figure 3-1. 144-Pin LQFP MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 65: Ballmap: 208 Mapbga
3.1.2 Ballmap: 208 MAPBGA Figure 3-2 shows the ballmap for the 208 MAPBGA package. AN11 VDDA1 VSSA1 AN27 VSSA0 AN12-SD MDO2 MDO0 VRC33 AN38 AN21 REFBYPC AN22 AN25 AN28 VDDA0 AN13-SD MDO3 MDO1 VSTBY AN17 AN34 AN16 AN23 AN32 AN33 AN14-SDI AN15-FC MSEO0...
Page 66: External Signal Summary
Nexus Event In VDDE7 CAL_ADDR CAL_EVTO Nexus Event Out VDDE12 O / Low EVTO / High VDDE7 CAL_MCKO Nexus Message Clock Out VDDE12 O / Low MCKO / VDDE7 Enabled MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 67 - / - - / - eTPU_A[27]_ eTPU A Channel GPIO[224] GPIO MSEO[1]_ Nexus Message Start/End Out VDDEH7 - / - - / - eTPU_A[29]_ eTPU A Channel GPIO[225] GPIO MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 68 Receive VDDEH6a - / Up - / Up GPIO[92] GPIO DSPI(9) SCK_B_ DSPI_B Clock VDDEH6b - / Up - / Up PCS_C[1]_ DSPI_C Peripheral Chip Select GPIO[102] GPIO MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 69 I / - AN[5] / - DAN2- Negative Terminal Differential Input AN[6] Single Ended Analog Input VDDA I / - AN[6] / - DAN3+ Positive Terminal Differential Input MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 70 Single Ended Analog Input VDDA I / - AN[39] / - Multiplexed Analog Input Voltage Reference High VDDA - / - Voltage Reference Low VSSA0 - / - MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 71 - / WKPCFG PCS_B[4]_ DSPI_B Periph Chip Select WKPCFG eTPU_A[9]_ eTPU_A Channel GPIO[128] GPIO eTPU_A[15]_ eTPU_A Channel VDDEH1b - / WKPCFG PCS_B[5]_ DSPI_B Periph Chip Select WKPCFG GPIO[129] GPIO MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 72 - / WKPCFG PCS_C[1]_ DSPI_C Peripheral Chip Select WKPCFG GPIO[142] GPIO eTPU_A[29]_ eTPU_A Channel (Output Only) VDDEH1a - / WKPCFG PCS_C[2]_ DSPI_C Peripheral Chip Select WKPCFG GPIO[143] GPIO MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 73 O / - XTAL EXTAL_ Crystal Oscillator Input VDDEH6a I / - EXTAL EXTCLK External Clock Input Power / Ground () VDDPLL PLL Supply Voltage VDDPLL I / - (1.2V) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 74 I/O Supply Input VDDEH6 I / - VDDEH6b (3.3V - 5.0V) VSSE6a I/O Ground Input VSSEH6 VSSE6b VDDEH7 (x2) I/O Supply Input VDDEH7 I / - (3.3V - 5.0V) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 75 If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived from the 5 volt power supply. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 76: Detailed Signal Descriptions
CAL_ADDR[12:18] are the calibration address signals. 3.3.2.2 CAL_ADDR[16:27]_MDO[0:11] — Calibration Addr / Nexus Message Data Out CAL_ADDR[16:27]_MDO[0:11] are the calibration address signals. The alternate function are nexus message data outputs. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 77 CAL_WE[0:1]_BE[0:1] specify which data pins contain valid data for a calibration bus transfer. 3.3.2.12 CAL_EVTO— Nexus Event out CAL_EVTO is an output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 78: Nexus Port Controller (Npc)
MDO[1]_eTPU_A[19]_GPIO[221] — Nexus Message Data Out / eTPU_A Channel / GPIO Is the trace message output to the development tools. The alternate functions are output channel for eTPU_A[19] module and GPIO[221]. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 79: Jtag
TMS — JTAG Test Mode Select Input TMS controls test mode operations for the on-chip test logic. 3.3.4.5 JCOMP — JTAG Compliance Input The JCOMP pin is used to enable the JTAG TAP controller. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 80: Flexcan
TXD_B_GPIO[91] is the transmit pin for the eSCI B module. 3.3.6.4 RXD_B_GPIO[92] — eSCI_B Transmit / - / GPIO RXD_B_GPIO[92] is the transmit pin for the eSCI B module. Its first alternate function is not implemented. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 81: Dspi
PCS_B[5]_PCS_C[0]_GPIO[110] is a peripheral chip select output pin for the DSPI B module. The alternate function is a peripheral chip select output pin for the DSPI C module. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 82: Eqadc
AN[6]_DAN3+ — Analog Input / Differential Analog Input Positive Terminal AN[6] is a single ended analog input pin. DAN3+ is the positive terminal input of the differential analog input DAN3. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 83 AN[13]_MA[1]_eTPU_A[21]_SDO is a single ended analog input pin. The alternate function is a MUX address pin. The second alternate function is eTPU_A[21] channel input/output pin. The third alternate function is the serial data output for the eQADC SSI. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 84 VRL — Voltage Reference Low VRL is the voltage reference low input pin for the eQADC. 3.3.8.23 REFBYPC — Bypass Capacitor REFBYPC is the bypass capacitor input pin for the eQADC. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 85: Etpu
3.3.9.7 eTPU_A[9:11]_eTPU_A[21:23]_GPIO[123:125] — eTPU_A Channel / GPIO eTPU_A[9:11]_eTPU_A[21:23]_GPIO[123:125] are input/output channel pins for the eTPU_A module. The alternate functions are the output channel pins for the eTPU_A. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 86 — eTPU_A Channel / External Interrupt / GPIO eTPU_A[20:21]_IRQ[8:9]_GPIO[134:135] are input/output channel pins for the eTPU_A module. The alternate functions are external interrupt request inputs for the SIU module. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 87 The alternate function is the external interrupt request input for the SIU module, LVDS+ output for DSPI C chip select. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 88: Emios
3.3.10.3 eMIOS[4]_eTPU_A[4]_GPIO[183] — eMIOS Channel / eTPU Channel / GPIO eMIOS[4]_eTPU_A[4]_GPIO[183] is an eMIOS channel input and output pin. Alternate function is an eTPU[4] channel output pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 89: Clock Synthesizer
The function of this pin is determined by the state of the PLLREF pin during reset. 3.3.11.3 CLKOUT — System Clock Output CLKOUT is the MPC563XM clock output for the calibration external bus interface. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 90: Power / Ground
VDD is the 1.2 V logic supply input. 3.3.12.11 VDDEH1a/b — I/O Supply Input VDDEH1a/b are the 3.3 V to 5.0 V +/- 5% supply input pins to the I/O segment 1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 91 VDDE12 is the 1.8V to 3.3 V +/- 5% I/O supply input pin to the I/O segment 12. It is only used on the 496-pin package. 3.3.12.18 VSS — Ground VSS is the ground reference input pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 92 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 93: Reset Sources
RCHW from the specified location, and then uses the RCHW value to determine and execute the specified boot procedure. NOTE The reset controller latches the value on the BOOTCFG input to the SIU 4 clock cycles prior to the negation of RSTOUT. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 94: Reset Vector
2900 External 16500 Crystal 3400 External 17000 Crystal 3900 External 17500 Crystal 4400 External 18000 SWTR Crystal 4900 External 18500 Crystal 5400 External 19000 Crystal 5900 External 19500 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 95: Clock Quality Monitor Gating Signal
Figure 4-1 Figure 4-2. Figure 4-1 shows the reset flow for assertion of the RESET pin. Figure 4-2 shows the internal processing of reset for all reset sources. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 96 Clock Cycles RESET Asserted? Set Latch, Wait 8 Clock Cycles RESET Set RGF Bit Asserted? To entry point in internal reset flow Figure 4-1. External Reset Flow Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 97 Clock Cycles NOTES: 1. The clock count CNT depends on the reset source and type of clock reference. Please refer to Table 4-1. Figure 4-2. Internal Reset Flow Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 98: Power-On Reset
“RSTOUT”). Once the clock count finishes, the WKPCFG and BOOTCFG pins are sampled. The reset controller then waits 4 clock cycles before negating RSTOUT, and the associated bits/fields are updated MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 99: Loss Of Clock
A Software Watchdog Timer Reset occurs when the watchdog timer in the SWT module is enabled and programmed to generate a reset. The effect of a Software Watchdog Timer Reset request is the same for MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 100: Checkstop Reset
RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, the SSRS bit is set, and all other reset status bits in the SIU_RSR are cleared. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 101: Software External Reset
RSTOUT pin, then the BAM program reads the RCHW from the lowest address of the internal flash memory. This address is 0x0000_0000. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 102 E code or as Freescale VLE code. 1 = Boot code executes as Freescale VLE code 0 = Boot code executes as Classic PowerPC Book E code BOOTID — Boot Identifier MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 103: Reset Configuration Timing
‘1’ during POR assertion. NOTE: 1. The clock count CNT depends on the reset source and type of clock reference. Please refer to Table 4-1. Figure 4-4. Reset Configuration Timing MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 104: Reset Weak Pull Up/Down Configuration
4 clock cycles before the negation of RSTOUT. After reset, software may modify the weak pull up/down selection for all I/O pins through the PCR registers in the SIU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 105: Overview
Table 5-1 lists the modules that support Module Disable Mode. The register and bit in each module that must be written to enter or MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 106: Modes And Clock Architecture
Modes and Clock Architecture 5.3.1 Block Diagrams This section contains block diagrams that illustrate the FMPLL, the clock architecture and the various FMPLL and clock configurations that are available. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 107 2 Decimation Filter CLKOUT CLKOUT Divider MDIS ipg_stop_ack ipg_stop INTC eQADC ipg_stop_ack one bit per peripheral SIU_HLT ipg_stop Figure 5-1. FMPLL Bypass Mode with Crystal Reference MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 108 2 Decimation Filter CLKOUT CLKOUT Divider MDIS ipg_stop_ack ipg_stop INTC eQADC ipg_stop_ack one bit per peripheral ipg_stop SIU_HLT Figure 5-2. FMPLL Bypass Mode with External Reference MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 109 2 Decimation Filter CLKOUT CLKOUT Divider MDIS ipg_stop_ack ipg_stop INTC eQADC ipg_stop_ack one bit per peripheral SIU_HLT ipg_stop Figure 5-3. FMPLL Normal Mode with Crystal Reference MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 110: Clock Architecture
SIU_HLT ipg_stop Figure 5-4. FMPLL Normal Mode with External Reference 5.3.2 Clock Architecture This section describes the clocks and clock architecture on this MCU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 111 Figure 5-5 illustrates how the MDIS and halt bits affect the clocks to the modules. For compatibility with eSYS family, the default value of MDIS bit is ZERO. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 112 Table 5-1. MDIS Support Block Name Register Name Bit Name DSPI_B DSPI_B_MCR MDIS DSPI_C DSPI_C_MCR MDIS EBI_MCR MDIS eTPU ETPUECR_1 MDIS FlexCAN A FLEXCAN_A_MCR MDIS FlexCAN C FLEXCAN_C_MCR MDIS MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 113 CPU so that it can exit the stopped state. Typically, the wake-up interrupt request will come from one of three sources: periodic interval timer (PIT) interrupt, external pin interrupt or CAN wake-up interrupt. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 114 Selecting the oscillator as the clock source ensures very low jitter on the CAN bus. Software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR register or by writing to the SIU_HLT register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 115: Introduction
Load/store unit — 1 cycle load latency — Fully pipelined — Big and Little endian support — Misaligned access support — Zero load-to-use pipeline bubbles • Power management MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 116: Location Of Detailed Documentation
Detailed documentation of the Z335 core is available as a separate document titled “e200z3 Power Architecture Core Reference Manual”. This document is located on the Freescale Web site at http://www.freescale.com/files/32bit/doc/ref_manual/e200z3RM.pdf?fsrch=1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 117: Information Specific To This Device
DSPI_B Receive FIFO Drain Flag DSPI_C_SR_TFFF DSPI_C.DSPI_SR[TFFF] DSPI_C Transmit FIFO Fill Flag DSPI_C_SR_RFDF DSPI_C.DSPI_SR[RFDF] DSPI_C Receive FIFO Drain Flag DECFIL_FILL_BUF DECFIL_FILL_BUF Decimation Filter Fill Buffer DECFIL_DRAIN_BUF DECFIL_DRAIN_BUF Decimation Filter Drain Buffer MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 118: Introduction
(TCD) for the channels. This SRAM-based implementation is utilized to minimize the overall module size. Figure 7-1 is a block diagram of the DMA module. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 119: Overview
— Parameterized support for 32- and 64-bit AMBA-AHB datapath widths • 32-byte transfer control descriptor per channel stored in local memory • 32 bytes of data registers, used as temporary storage to support burst transfers MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 120: Features
} t_minor_link_citer; typedef union { struct { /* biter.e_link = 1 */ unsigned short biter.linkch:6; /* link channel number, */ unsigned short biter:9; /* beginning (“major”) iteration count */ MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 121 (nbytes), the source size (ssize) and the destination size (dsize). The completion of the minor loop is equal to one iteration of the major loop. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 122 /* convert the destination transfer size into a byte count */ switch (dma_engine.dsize) { case 0: /* 8-bit transfer */ dest_xfr_size = 1; break; case 1: /* 16-bit transfer */ dest_xfr_size = 2; break; MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 123 /* if the dsize < ssize, do multiple writes to equal the ssize */ /* if the dsize => ssize, do a single write of dest data */ number_of_dest_writes = xfer_size / dest_xfer_size; for (number_of_dest_writes) { write_to_amba-ahb (dma_engine.daddr, dest_xfr_size) = dma_engine.data; MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 124 /* since the major loop is complete, perform the final address adjustments */ /* sum the current {src,dst} addresses with “last” adjustment */ write_to_local_memory [channel].saddr = dma_engine.saddr + dma_engine.slast; write_to_local_memory [channel].daddr = dma_engine.daddr + dma_engine.dlast; MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 125: Memory Map/Register Definition
The descriptions in this section define the 64-channel implementation. For 16- or 32-channel designs, the unused bits are not implemented: reads return zeroes, and writes are ignored. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 126 Priority (DCHPRI40) Priority (DCHPRI41) Priority (DCHPRI42) Priority (DCHPRI43) 0x012c DMA Channel 44 DMA Channel 45 DMA Channel 46 DMA Channel 47 Priority (DCHPRI44) Priority (DCHPRI45) Priority (DCHPRI46) Priority (DCHPRI47) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 127: Register Descriptions
Unused group priority registers, per configuration, are unimplemented in the DMACR. In group round robin mode, the group priorities are ignored and the groups are cycled through without regard to priority. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 128 The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes. The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the last write sequence. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 129 See Figure 7-3 Table 7-4 for the DMAES definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 130 TCD.daddr is inconsistent with TCD.dsize. Destination Offset Error No destination offset configuration error. The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is inconsistent with TCD.dsize. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 131 The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. See Figure 7-4 Table 7-5 for the DMAERQ definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 132 DMAEEI{H,L} registers. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 133 DMAERQ{H,L} register to be set. A data value of 64 to 127 (regardless of the number of implemented channels) provides a global set function, forcing the entire MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 134 DMAEEI{H,L} register to be set. A data value of 64 to 127 (regardless of the number of implemented channels) provides a global set function, forcing the entire MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 135 DMAINT{H,L} register to be cleared. A data value of 64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the entire MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 136 The data value on a register write causes the START bit in the corresponding Transfer Control Descriptor to be set. A data value of 64 to 127 (regardless of the number of implemented channels) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 137 The outputs of this register are directly routed to the platform’s interrupt controller. During the execution of the interrupt service routine associated with any given channel, it is software’s MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 138 31-00. The dma_engine signals the occurrence of a error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the DMAEEI register, then MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 139 Figure 7-15 Table 7-16 for the DMAERR definition. Figure 7-15. DMA Error (DMAERRH, DMAERRL) Registers Register address: DMA_Offset + 0x0028 (DMAERRH), +0x002c (DMAERRL) RESET: RESET: RESET: RESET: = Unimplemented MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 140 Enable Channel Preemption Channel n cannot be suspended by a higher priority channel’s service request. Channel n can be temporarily suspended by the service request of a higher priority channel. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 141 0 of the TCDn structure, the saddr field. Figure 7-17. TCDn Word 0 (TCDn.saddr) Field Register address: DMA_Offset + 0x1000 + (32 x n) + 0x00 saddr[31:16] RESET: saddr[15:0] RESET: = Unimplemented MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 142 For this application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0-modulo-size range. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 143 2 of the TCDn structure, the nbytes field. Figure 7-19. TCDn Word 2 (TCDn.nbytes) Field Register address: DMA_Offset + 0x1000 + (32 x n) + 0x08 nbytes[31:16] RESET: nbytes[15:0] RESET: = Unimplemented MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 144 This value can be applied to “restore” the source address to the initial value, or adjust the address to reference the next data structure. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 145 Figure 7-22. TCDn Word 5 (TCDn.{citer,doff}) Fields Register address: DMA_Offset + 0x1000 + (32 x n) + 0x14 citer. citer[14:9] or citer[8:0] e_link citer.linkch[5:0] RESET: doff[15:0] RESET: = Unimplemented MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 146 0x0001. doff[15:0] Destination address signed offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 147 Figure 7-24. TCDn Word 7 (TCDn.{biter,control/status}) Fields Register address: DMA_Offset + 0x1000 + (32 x n) + 0x1c biter[15:0] RESET: major.linkch[5:0] done active major. e_sg d_req int_ha int_m start e_link RESET: = Unimplemented MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 148 If the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 149 This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared by the dma_engine as the inner minor loop completes or if any error condition is detected. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 150 The halfway complete interrupt is disabled when biter values are less than two. The half-point interrupt is disabled. The half-point interrupt is enabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 151: Functional Description
(matching the maximum transfer size) and the necessary mux logic to support any required data alignment. The AMBA-AHB read data bus is the primary input, and the AHB write data bus is the primary output. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 152: Dma Basic Data Flow
The TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the dma_engine.addr_path.channel_{x,y} registers. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 153 The source reads are initiated and the fetched data is temporarily stored in the data_path module until it is gated onto the AMBA-AHB bus during the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 154 These include the final address adjustments and reloading of the biter field into the citer. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 155: Dma Performance
DMA also factors significantly into the resulting metric. The peak transfer rates for several different source and destination transfers are shown in Table 7-27. The following assumptions apply to Table 7-27 Table 7-28: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 156 Cycle 8 - ?: The last part of the TCD is read in. This cycle represents the 1st data phase for the read, and the address phase for the destination write. The exact timing from this point is a function of the response times for the channel’s read and write MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 157 - wait states seen during the system bus read data phase write_ws - wait states seen during the system bus write data phase exit - channel shutdown (3 cycles) For example: consider a platform with the following characteristics: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 158: Initialization/Application Information
3. Enable error interrupts in the DMAEEI registers if so desired. 4. Write the 32 byte TCD for each channel that may request service. 5. Enable any hardware service requests via the DMAERQ register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 159: Dma Programming Errors
In general, if priority levels are not unique, the highest (channel/group) priority that has an active request will be selected, but the lowest numbered (channel/group) with that priority will be selected by arbitration MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 160: Dma Arbitration Mode Considerations
Within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to channel priority levels. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 161: Dma Transfer
The final source and destination addresses are adjusted to return to their beginning values. TCD.citer = TCD.biter = 1 TCD.nbytes = 16 TCD.saddr = 0x1000 TCD.soff TCD.ssize MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 162 DMAis programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s hardware requests is enabled in the DMAERQ register, channel service requests are initiated by the slave device. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 163 -> second iteration of the minor loop read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b) write_word(0x2018) -> third iteration of the minor loop read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 164: Tcd Status
The 'true' values of the saddr, daddr, and nbytes are the values the dma_engine is currently using in its internal register file and not the values in the TCD local memory for that channel. The MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 165: Channel Linking
TCD.major.e_link = 1 TCD.major.linkch = 0x7 will execute as: 1. minor loop done -> set channel 12 TCD.start bit 2. minor loop done -> set channel 12 TCD.start bit MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 166: Dynamic Programming
The following coherency model is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. Set the TCD.major.e_link bit. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 167: Hardware Request Release Timing
Figure 7-28. ipd_req hardware handshake hclk htrans AHB_AP AHB_DP hwrite ipd_req ipd_ack ipd_done done_lw ipd_complete Note: ipd_req must de-assert in this cycle unless another service request is intended MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 168 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 169: Information Specific To This Device
Also, dynamic priority elevation and alternate context switching are not supported on this device. • Table 8-1 shows the master-slave connections for this device. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 170: Device-Specific Register Information
Slave 7 0xFFF0_4700 0xFFF0_4710 (peripheral bridge B) 8.1.3.2 Master Priority Register (MPR) Information • Reset value: 0x0003_0210 • Implemented fields: — MSTR0 — MSTR1 — MSTR2 — MSTR4 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 171: Introduction
The 8 x 8 configuration is the generic configuration. Please reference your project specific specification for the configuration used in your project. 1.An alternate abbreviation for this module is MAX. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 172 IP wdata(s) Slv hresp IP rdata IP rdata(s) halt request IP term IP term(s) halt grant Max_halted halt grant(s) Slave 7 read data Figure 8-2. XBAR Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 173: Features
(hready held negated) until the targeted slave port can service the master’s request. The latency in servicing the request will depend on each master’s priority level and the responding peripheral’s access time. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 174: Xbar Registers
IP bus clock cycles. The registers can only be read from and written to in supervisor mode. Additionally, these registers can only be read from or written to by 32-bit accesses. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 175 General Purpose Control Register for Slave port 7 0x714 ASGPCR7 Alternate General Purpose Control Register for Slave port 7 0x800 MGPCR0 General Purpose Control Register for Master port 0 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 176 HPE7HPE6HPE5HPE4HPE3HPE2HPE1HPE0 + n*0x100) PCTL PARK ASGPCRn ($BASE + 0x014 HPE7HPE6HPE5HPE4HPE3HPE2HPE1HPE0 + n*0x100) PCTL PARK MGPCRn ($BASE + 0x800 + n*0x100 AULB Note: for n = 0 to 7 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 177: Xbar Register Descriptions
8.3.2.1 Master Priority Register The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and resides in each slave port. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 178 These bits are initialized by hardware reset. 111This master has the lowest priority The reset value is 101 when accessing the slave port. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 179 No two available master ports may be programmed with the same priority level. Attempts to program two or more available masters with the same priority level will result in an error response and the MPR will not be updated. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 180 AMPR will not be updated. 8.3.2.3 Slave General Purpose Control Register The Slave General Purpose Control Register (SGPCR) controls several features of each slave port. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 181 Once the RO bit is written to a 1, only hardware reset will return it to a 0. BIT 0 PCTL PARK TYPE: RESET: Note: Note: for n = 0 to 7 Figure 8-5. Slave General Purpose Control Register n MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 182 Slave General Purpose Control Register Reserved - This bit is reserved for future expansion. It is read as zero and should be written with zero for upward compatibility. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 183 $BASE + 0x014 + n*100 ASGPCRn Alternate Slave General Purpose Control Register n Wait State: 0 Access: S BIT1 TYPE: RESET: Note: BIT 0 PCTL PARK TYPE: RESET: Note: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 184 Wait State: 0 Access: S BIT1 TYPE: RESET: Note: BIT 0 AULB TYPE: RESET: Note: Note: for n = 0 to 7 Figure 8-7. Master General Purpose Control Register n MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 185: Coherency
Arbitration The XBAR supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a simple round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave port. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 186 If the new requesting master’s priority level is lower than that of the master that currently has control of the slave port the new requesting master will be forced to wait until the master that currently has control MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 187: Priority Assignment
MPR and SGPCR will be selected, when sX_ampr_sel is 1 the AMPR and the ASGPCR will be selected. This hardware input is useful for context switching so the user does not have to rewrite the MPR or SGPCR MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 188: Master Port Functionality
MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 189 Async/Flopped_sel Illegal_access Request_enable Hready_in Slv_hready[7:0] Hready_out Slv_hresp[7:0] Hresp Slv_is_mine[7:0] Control_bits Rdata_sel Registers Read_sel Write_sel Wdata Control_bits Xfr_wait Xfr_error Rdata Hrdata Slv_hrdata[7:0] Figure 8-8. XBAR Master Port Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 190 The idle state is used when the master runs a valid IDLE cycle to the master port. The master port makes no requests to the slave ports (disables the slave port decoder) and terminates the IDLE cycle. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 191: Slave Port Functionality
The register slice contains the registers associated with the specific slave port. The registers have a quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 192 8 to 1 muxes, one for each master-to-slave signal in fact. All the muxes are designed in an AND - OR fashion, so that if no master is selected the output of the muxes will be zero. (This is an important feature for low power park mode.) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 193 4 bit field with mX_high_priority being the MSB. The XBAR uses these bits in determining priority levels when programmed for fixed priority mode of operation or when one of the enabled mX_high_priority inputs is asserted. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 194 Master 5 Master 5 Master 2 Master 3 Master 4 XBAR owner IDLE NSEQ NSEQ NSEQ NSEQ NSEQ IDLE htrans hready Figure 8-10. Low to high priority mastership change MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 195 Figure 8-12 shows an example of round-robin mode of operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 196 When that master access the slave port again it will not pay any arbitration penalty; however, if any other master wishes to access the slave port a one clock arbitration penalty will be imposed. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 197 4’s access will be taken first. The slave port parks on master 2 once it has given control to master 2. This same situation can occur when parking on a specific master as well. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 198: Initialization/Application Information
No initialization is required by or for the XBAR. Hardware reset ensures all the register bits used by the XBAR are properly intialized. Interface This section provides information on the XBAR interface. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 199: Overview
MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 200: Slave Ports
When a master runs a locked cycle through the XBAR, the master will be guaranteed ownership of all slave ports it accesses while running locked cycles for one cycle beyond when the master finishes running locked cycles. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 201: Pbridge Features
The PBRIDGE is the interface between the system bus interface and on-chip peripherals as shown in Figure 9-1. Crossbar Switch Peripheral Bridge B (PBRIDGE0) Figure 9-1. PBRIDGE Interface PBRIDGE Signal Description The PBRIDGE has no external signals. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 202: Pbridge Functional Description
32-bit boundary. Misaligned writes that do not cross a 32-bit boundary are supported. 64-bit data writes (not instruction) are not supported. PBRIDGE Registers The PBRIDGE does not contain any user-programmable registers. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 203: Introduction
Provides hardware and software configurable read and write access protections on a per-master basis. 1.This chapter is only valid for the primary version of the MPC5633M, in the future it may use the LC Flash. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 204: Modes Of Operation
AHB. Up to four lines of data (128-bit width) are buffered by the PFLASH_C90FL. Lines may be prefetched in advance of being requested by the AHB interface, allowing single-cycle (zero AHB wait-states) read data responses on buffer hits. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 205 PFlash Memory Controller. Request pipelining allows for improved performance by reducing the access latency seen by the system bus master. Access pipelining can be applied to both read and write cycles by the Flash array. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 206 This policy maximizes performance based on reference patterns of flash accesses and allows for prefetched data to remain valid when non-prefetch enabled bus masters are granted flash access. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 207 The censorship control word is a 32-bit value located at the base address of the shadow row plus 0x1E0. The flash module latches the value of the control word prior to the negation of system reset. Censorship MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 208: Memory Map And Register Definition
Table 10-2 shows the Flash array memory map, and shows the configuration registers for the flash Controller. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 209: C90Fl Register Descriptions
Operation of the C90FL block is controlled by three registers – PFCR1, PFAPR, and PFCR2. These registers should only be referenced with 32-bit accesses. 10.2.8.1 PFlash Configuration Register 1 (PFCR1) The PFCR1 specifies the operation of the C90FL block. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 210 This field must be set to a value corresponding to the operating frequency of the PFLASH_C90FL. The required settings are documented in Table 10-5. This field is set to “11” by hardware reset. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 211 Table 10-5. APC, RWSC, WWSC Settings vs. Frequency of Operation Target Max Frequency RWSC WWSC (MHz) Illegal combinations exist, all entries must be taken from the same row To be changed after analysis and characterization MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 212 Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 213 RESET: = Unimplemented or Reserved Table 10-10. PFlash Configuration Register 2 (PFCR2) The reset value is read from address 0x7E00 of the Shadow Block of the Flash array. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 214: Flash Memory Block (C90Fl)
Section 10.2, “Platform Flash (PFlash) Memory Controller”. The base address for the flash bus and flash registers is 0x03F8_8000. There are three address spaces: • Low Address Space (256 Kbytes) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 215: C90Fl Block Features
Software programmable block program/erase restriction control for low, mid and high address spaces • Erase of selected block(s) • Read page and program page size of 128 bits (4 words) • ECC with single-bit correction, double-bit detection MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 216: C90Fl Modes Of Operation
C90FL flash memory block. C90FL Memory Block C90FL Memory Interface (MI) MPC563XM e200z335 Platform Peripheral System (PFLASH_C90FL) C90FL Flash Core (FC) Figure 10-4. C90FL Flash System Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 217: C90Fl Flash Eeprom Functional Description
The FC is also divided into blocks to implement independent erase or program protection. The shadow block exists outside the normal address space and is programmed, erased and read independently of the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 218 The erase operation is resumed by clearing the ESUS bit. The C90FL continues the erase sequence from one of a set of predefined points. This can extend the time required for the erase operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 219: C90Fl Memory Map And Register Definition
FLASH_BASE + 0x3_0000 FLASH_BASE + 0x4_0000 Mid Address Space FLASH_BASE + 0x6_0000 FLASH_BASE + 0x8_0000 High Address Space FLASH_BASE + 0xC_0000 FLASH_BASE + 0x10_0000 - Reserved FLASH_BASE + 0xFF_7FFF MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 220 FLASH_REGS_BASE + 0x48 FLASH_REGS_BASE + 0x4C FLASH_REGS_BASE + 0x50 FLASH_REGS_BASE + 0x54 FLASH_REGS_BASE + 0x58 10.3.6.1 Module Configuration Register (MCR) The MCR register is defined Table 10-14 Table 10-15. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 221 100 Eight 16 Kbyte, two 64 Kbyte Blocks 101 Reserved 110 Two 16 Kbyte, two 48 Kbyte, two 64 Kbyte Blocks 111 Reserved 13-14 Reserved, reset to 0. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 222 DONE is set to a 1 within Tdones (Appendix A) of a 1 to 0 transition of EHV which aborts a high voltage operation. 0 Flash is executing a high voltage operation 1 Flash is not executing a high voltage operation MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 223 (PGM is low and UTE is low). ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0 Flash is not executing an erase sequence 1 Flash is executing an erase sequence MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 224 This is implemented through a priority mechanism among the bits. The bit changing priorities are detailed in Table 10-16. Table 10-16. MCR Bit Set/Clear Priority Levels Priority Level MCR Bit(s) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 225 Flash values in the shadow block. An erased shadow block causes the reset value to be 1. 10.3.6.2.1 LML Register The following field and bit descriptions fully define the LML register (Table 10-17). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 226 Reset causes the bits to go back to their shadow block value. The default value of the SLOCK bits (assuming erased shadow location) is locked. SLOCK is not writable unless LME is high. 12-13 Reserved, reset to 0 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 227 Flash values in the shadow block. An erased shadow block causes the reset value to be 1. 10.3.6.3.1 HBL Register The following field and bit descriptions fully define the HBL register (Table 10-19). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 228 These bits, along with bits in the LLOCK (LML), determine if the block is locked from program or erase. An “OR” of LML and SLL determine the final lock status. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 229 Secondary Mid Address Block Lock. This bit is an alternative method that may be used to lock the SMLOCK[1:0] Mid Address Space blocks from programs and erases. SMLOCK has the same description as MLOCK. SMLOCK is not writable unless SLE is high. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 230 The following field and bit descriptions fully define the LMS register (Table 10-23). Offset 0x0010 Access: User read/write MSEL RESET: LSEL RESET: = Unimplemented or Reserved Table 10-23. LMS Register LMS register functions are shown in Table 10-24. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 231 The High Address Space Block Select Register (HBS) provides a means to select blocks to be operated on during erase. 10.3.6.6.1 HBS Register The following field and bit descriptions fully define the HBS register (Table 10-25). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 232 The Address register (ADR) provides the first failing address in the event module failures (ECC or PGM/Erase state machine) 10.3.6.7.1 ADR Register The following field and bit descriptions fully define the ADR register (Table 10-27). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 233 In addition to these features, the ADR register also has some features available in Test Mode. For details on these features, refer to c90fl Test Guide. 29-31 Reserved, reset to 0. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 234 101 - Access request require five additional hold cycles. (Not needed for spec frequency range of c90fl) 110 - Access request require six additional hold cycles. (Not needed for spec frequency range of c90fl) 111 - No address pipelining. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 235 The Bus Interface Unit 1 Register (BIU1) provides a means for BIU specific information, or BIU configuration information to be stored. 10.3.6.9.1 BIU1 Register The following field and bit descriptions fully define the BIU1 register (Table 10-31). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 236 10-34. Table 10-34. BIU2 Field Descriptions Field Description 0-31 BIU2 Generic Registers. The BIU generic registers are reset based on the information stored in the BIU2[31:0] shadow block. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 237 1* indicates that the reset value of these registers is determined by Flash values in the shadow block. An erased shadow block causes the reset value to be 1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 238 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MISR Reset Table 10-39. UM0 Register MISR register functions are shown in Table 10-40. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 239 0-31 See the description of the MISR field in Table 10-40. MISR[63:32] 10.3.6.13.3 UM2 Register The following field and bit descriptions fully define the UM2 register (Table 10-43). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 240 Description 0-31 See the description of the MISR in Table 10-40. MISR[127:96] 10.3.6.13.5 UM4 Register The following field and bit descriptions fully define the UM4 register (Table 10-47). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 241 MISR register functions are shown in Table 10-48. Table 10-48. UM4 Field Descriptions Field Description 0-14 Reserved, reset to 0. 15-31 See the description of the MISR in Table 10-40. MISR[144:12 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 242 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 243: Introduction
BIU contains a four-entry prefetch buffer, each entry containing 128 bits of data, and an associated controller that prefetches sequential lines of data from the Flash array into the buffer. Prefetch buffer hits MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 244: Features
Erase of selected blocks • ECC with single-bit correction, double-bit detection • Embedded hardware program and erase algorithm • Read-while-write with multiple partitions • Stop mode for low power stand-by MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 245: Modes Of Operation
Array Base + 0x0008_0000 – High address space (512 KB) Array Base + 0x000F_FFFF Array Base + 0x0008_0000 – High address space (256 KB) Array Base + 0x000B_FFFF MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 246 TestFlash base + 0x0000_0000 – Test block space (16 KB) Test TestFlash base + 0x0000_3FFF MPC5634M only MPC5633M only MPC5632M only The Flash module is composed of three partitions. The Read-While-Write functionality is supported between partitions 0 and 1 and 0 and 2.
Page 247 Shadow base + 0x0000_3E18 (NVUSRO) Non-Volatile User Options register 8 byte Shadow base + 0x0000_3E20 Reserved 480 byte MPC5634M and MPC5633M only MPC5634M only Table 11-3 shows the register set for the Flash module. Table 11-3. Module Register Memory Map Size...
Page 248: Register Descriptions
Access: User read/write R EDC SIZE W rc/0 Reset R EER PEAS DONE PEG PRD STOP PGM PSUS ERS ESUS EHV W w1c Reset Figure 11-2. Module Configuration Register (CFLASH_MCR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 249 RWE) were correct. Since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. A write of 0 has no effect. 0 Reads are occurring normally. 1 A read-while-write error occurred during a previous read. 18–19 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 250 1 Flash is executing a program sequence. Program SUSpend (Read/Write) PSUS Program suspend is not supported; Writting to this bit has no effect, but the written data can be read back MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 251 Flash core data. This should be avoided due to reliability implications. Aborting a high voltage operation leaves Flash core addresses in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 252 These bits along with bits in the secondary LMLOCK field (CFLASH_SLMLR), determine if the block is locked from program or erase. An “OR”’ of CFLASH_LMLR and CFLASH_SLMLR determine the final MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 253 0 Shadow row is available to receive program and erase pulses; Test is available to receive program pulses 1 Shadow and Test sectors are locked for program (and shadow erase). 12–13 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 254 Figure 11-5. Secondary Low/Mid Address Space Block Locking Register (CFLASH_SLMLR) The reset value of these bits is determined by Flash values in the shadow row. An erased array sets the reset value to 1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 255 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11-6. Low/Mid Address Space Block Select Register (CFLASH_LMSR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 256 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11-7. Address Register (CFLASH_AR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 257 “code Flash”. It includes fields that provide specific information for up to two separate AHB ports (p0 and the optional p1). The register is described below in Figure 11-8 Table 11-12. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 258 This field is set to 0b00010 by hardware reset. 00000 No additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added 111111 31 additional wait-states are added MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 259 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. This field is set to 2b11 by hardware reset. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 260 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 261 No additional wait-states are added 00001 One additional wait-state is added 00010 Two additional wait-states are added 111111 31 additional wait-states are added This field is ignored in single bank Flash configurations. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 262 This bit is set by hardware reset, enabling the use of the holding register. 0 The holding register is disabled from satisfying read requests. 1 The holding register is enabled to satisfy read requests on hits. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 263 M3AP M2AP M1AP M0AP Reset Figure 11-10. PFLASH Access Protection Register (CFLASH_BIU2) Table 11-14. PFLASH Access Protection Register Field Descriptions Field Description Reserved, should be cleared. Reserved ARBM MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 264 Figure 11-11 Table 11-15. Offset 0x01c Access: Read/write BK0_XRWS BK0_XAPC BK0_XWWSC Reset B0_P B0_P B0_P BK0_WWS B0_P0_PFL BK0_APC BK0_RWSC 0_IP 0_BF Reset Figure 11-11. PFLASH Configuration Register 1 (PFCR1) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 265 This field is set to 0b00001 by hardware reset. 00000 No additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added 111111 31 additional wait-states are added MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 266 0 No prefetching is triggered by an instruction fetch read access 1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch read access Reserved, should be cleared. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 267 Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 268 2 and 3 for data accesses. The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. Reserved, should be cleared MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 269 No prefetching is triggered by a data read access If page buffers are enabled (B0_P1_BFE = 1), prefetching is triggered by any data read access This field is ignored in the <<BLOCK NAME>> implementation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 270 0x203E08 of the shadow block in the Flash array must be programmed using the normal sequence of operations. The reset value shown in Figure 11-14 reflects an erased or unprogrammed value from the shadow region. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 271 No additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added 111111 31 additional wait-states are added This field is ignored in single bank Flash configurations. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 272 User Test 0 register (CFLASH_UT0) Address Offset: 0x0003C Reset value: 0x00000001 DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 273 If this bit is high together with bit EIE, the Read Reset Operation is selected. 0: Margin reads are not enabled, all reads are User mode reads. 1: Margin reads are enabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 274 DAI2 DAI2 DAI2 DAI2 DAI2 DAI2 DAI2 DAI2 DAI1 DAI1 DAI1 DAI1 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 275 32 array bits representing Word 1 within the double word. 0: The array bit is forced at 0. 1: The array bit is forced at 1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 276 The Multiple Input Signature Register provides a means to evaluate the Array Integrity. The User Multiple Input Signature Register 1 represents the bits 63-32 of the whole 144-bit word (two Double Words MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 277 These bits represents the MISR value obtained accumulating the bits 95-64 of all the pages read from the Flash Memory. The MS can be seeded to any value by writing the UMISR2 register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 278 The Multiple Input Signature Register provides a means to evaluate the Array Integrity. The User Multiple Input Signature Register 4 represents the ECC bits of the whole 144-bit word (two Double Words MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 279: Functional Description
The Flash BIU also has the capability of extending the normal AHB access time by inserting additional wait states for reads and writes. This capability is provided to allow emulation of other memories which MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 280: Access Protections
The second case that can cause an error response to the AHB is when an access is performed to the Flash array and is terminated with a Flash error response. This may occur for either a read or a write operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 281: Access Pipelining
1. Invalid - the buffer contains no valid data 2. Used - the buffer contains valid data which has been provided to satisfy an AHB burst type read MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 282 The buffers can be organized as a “pool” of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 283: Read-While-Write Functionality
AHB bus and hready_out negated to terminate the system bus transfer. • BKn_RWWC = 0b110 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 284: Wait-State Emulation
These wait-states are applied to the initial access of a burst fetch or to single-beat read accesses on the AHB system bus. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 285: Flash Memory Array: User Mode
The read state is active when CFLASH_MCR[STOP] = 0 (user mode read). • The read state is active when CFLASH_MCR[PGM] = 1 and/or CFLASH_MCR[ERS] = 1 and high voltage operation is ongoing (read-while-write). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 286 (in that segment) because the ECC calculation has already completed for that 64-bit segment. Attempts to program the adjoining word results in an operation failure. All programming operations must be from 64 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 287 8 of the program sequence. An aborted program results in CFLASH_MCR[PEG] being set low, indicating a failed operation. The data space being operated on before the abort contains indeterminate data. The user cannot abort a program sequence while in program suspend. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 288 Aborting a program operation leaves the Flash core addresses being programmed in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 289 EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 ESUS User Mode Read State Erase Suspend Figure 11-15. Program Sequence MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 290 7. Write a logic 0 to the CFLASH_MCR[EHV] bit. 8. If more blocks are to be erased, return to step 2. 9. Write a logic 0 to the CFLASH_MCR[ERS] bit to terminate the erase. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 291 CFLASH_MCR[PGM] is low. A 0 to 1 transition of CFLASH_MCR[ESUS] causes the Flash module to start the sequence which places it in erase suspend. The user must wait until CFLASH_MCR[DONE] = 1 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 292 /* Reset ESUS in MCR: Erase Resume */ WARNING In an erase-suspended program, programming Flash locations in blocks which were being operated on in the erase can corrupt Flash core data. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 293 Figure 11-16. Erase Sequence 11.7.12.5 User Test Mode User Test Mode is used to test the integrity of the Flash Module. Three kinds of test can be performed: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 294 6. Compare UMISR0-4 content with the expected result. 7. Write a logic 0 to the UT0.AIE bit. 8. If more blocks are to be checked, return to step 2. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 295 Example 11-5. Margin Read Setup versus 1’s = 0xF9F99999; /* Set UTE in UT0: Enable User Test */ = 0x80000020; /* Set MRE in UT0: Select Operation */ MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 296 The ECC Logic Check operation consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Write in UT1.DAI31-0 and UT2.DAI63-32 the Double Word Input value. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 297 CFLASH_MCR.PEAS is high. The Shadow block may be locked/unlocked against program or erase by using the CFLASH_LMLR.SLOCK and CFLASH_SLLLR.SSLOCK registers. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 298 Don’t care 0x55AA Enabled Disabled Private mode Uncensored Don’t care 0x55AA Disabled Enabled Public External boot Censored 0x55AA Don’t care Disabled Enabled mode Uncensored 0x55AA Don’t care Enabled Enabled MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 299: Overview
VSTBY. Updates to the standby portion of the SRAM are inhibited during system reset or during Standby Mode. 12.4 Block Diagram The SRAM block diagram is shown in Figure 12-1. Standby Switch SRAM 32 KB 62 KB STBY Figure 12-1. SRAM Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 300: Functional Description
RAM access during the previous clock. Table 12-1. Wait States During RAM Access Current Previous Wait States Read Idle Read 32/64-bit Write 8/16-bit Write MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 301: Module Memory Map
Table 2-2 Table 2-3. Table 12-2 shows the SRAM memory map. Table 12-2. SRAM Memory Map Address MPC5634M MPC5633M MPC5632M L2SRAM_BASE 32 KB RAM, Powered by V 32 KB RAM, Powered by V 32 KB RAM, Powered by V stby...
Page 302 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 303: Information Specific To This Device
EBI_BR0–EBI_BR3 BA[0:2] 0b001 EBI_CAL_BR0–3 EBI_OR0–EBI_OR3 AM[0:2] 0b111 EBI_CAL_OR0–3 13.2 Introduction Figure 13-1 is a block diagram of the EBI. The signals shown are external pins to the MCU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 304: Overview
The EBI also enables an external master to access internal address space. The EBI includes a memory controller that generates interface signals to support a MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 305: Features
The BR, BG and BB signals are not used by the EBI in this mode, and are MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 306 Mode. In this mode, only 16 data signals are used by the EBI. The user can select which 16 data signals are used (DATA[0:15] or DATA[16:31]) by writing the D16_31 bit in the EBI_MCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 307 Section 13.5.2.14, “Address Data Multiplexing. 13.2.3.8 Debug Mode When the MCU is in Debug Mode, the EBI behavior is unaffected and remains dictated by the mode of the EBI. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 308: External Signal Description
Address bits 0-7 are internally driven by the EBI for external master accesses depending on which internal slave is to be accessed. See Section 13.5.2.10.1, “Address Decoding for External Accesses more details. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 309 BR is asserted to request ownership of the external bus. The BR signal is only used by the EBI when the EBI is in External Master Mode. In Single Master Mode, the BR signal is never asserted or sampled by the EBI. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 310 DATA[0:31] is driven by the EBI in the address phase with the ADDR value if the Address on Data multiplexing mode is enabled. See Section 13.2.3.7, “Multiplexed Address on Data Bus Mode,” details. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 311 Section 13.5.2.9, “Termination Signals Protocol for more details. 13.3.2.14 TS — Transfer Start TS is asserted by the current bus owner to indicate the start of a transaction on the external bus. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 312 For chip-select accesses to a 16-bit port, only WE[0:1]/BE[0:1] are used by the EBI, regardless of which half of the DATA bus is selected via the D16_31 bit in the EBI_MCR. Section 13.5.1.13, “Four Write/Byte Enable (WE/BE) Signals for more details on WE[0:3]/BE[0:3] functionality. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 313: Signal Function/Direction By Mode
EBI signal must have its pad configured prior to operating in each of the EBI modes. See Section 13.4.1.1, “EBI Module Configuration Register (EBI_MCR) for details on the EXTM and MDIS bits. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 314: Signal Output Buffer Enable Logic By Mode
SoC logic outside EBI block. The logic in Table 13-6 can be overwritten by SoC logic, so see the device-specific SoC Guide for any exceptions to the logic below. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 315: Memory Map/Register Definition
EBI Base Register Bank 2 (EBI_BR2) EBI_BASE+0x24 EBI Option Register Bank 2 (EBI_OR2) EBI_BASE+0x28 EBI Base Register Bank 3 (EBI_BR3) EBI_BASE+0x2c EBI Option Register Bank 3 (EBI_OR3) EBI_BASE+0x30 - Reserved EBI_BASE+0x3c MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 316: Register Descriptions
= Unimplemented or Reserved Reset value is device-specific. Refer to the device-specific SoC Guide for the reset value for a particular MCU. Figure 13-2. EBI Module Configuration Register (EBI_MCR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 317 The ACGE bit enables the EBI feature of turning off CLKOUT (holding it high) during idle periods in-between external bus accesses. 1 = Automatic CLKOUT Gating is enabled 0 = Automatic CLKOUT Gating is disabled EXTM - External Master Mode MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 318 1 = Module Disable Mode is active (negate "enable clk" signal) 0 = Module Disable Mode is inactive (assert "enable clk" signal) D16_31 — Data Bus 16_31 Select MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 319 This bit is set if the cycle was terminated by an externally generated TEA signal. 1 = External TEA occurred 0 = No error BMTF — Bus Monitor Timeout Flag MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 320 This bit controls whether the bus monitor is enabled for internal to external bus cycles. The BME bit is ignored (treated as 0) for chip-select accesses with internal TA (SETA=0). 1 = Enable bus monitor (for external TA accesses only) 0 = Disable bus monitor MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 321 Mode, the PS bit value is ignored and is always treated as a ’1’ (16-bit port). 1 = 16-bit port 0 = 32-bit port AD_MUX — Address on Data Bus Multiplexing MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 322 1 = Only assert BDIP (BSCY+1) external cycles before expecting subsequent burst data beats 0 = Assert BDIP throughout the burst cycle, regardless of wait state configuration SETA — Select Transfer Acknowledge SETA — Select External Transfer Acknowledge MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 323 Any clear bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be used in MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 324: Functional Description
Valid transaction sizes are 8, 16 and 32 bits. Only 24-29 address lines are pinned out #beats is the number of beats (4,8,16) determined by BL and PS bits in Base Register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 325 A match on a valid calibration chip-select register overrides a match on any non-calibration chip-select register, with CAL_CS0 having the highest priority. Thus the full priority of the chip-selects is: CAL_CS0,...,CAL_CS3,CS0,...,CS3 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 326 TA is used BSCY don’t care since external TA is used AD_MUX Address on Data multiplexing SETA Select external TA to terminate access MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 327 Each chip select can be configured (via the SETA bit) to have TA driven internally (by the EBI), or externally (by an external device). See Section 13.4.1.4, “EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3) for more details on SETA bit usage. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 328 The Write/Byte Enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS=1) are shown in Table 13-13. Only Big Endian byte ordering is supported by the EBI. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 329 This feature must be disabled for multi-master systems. In those cases, one master is getting its clock source from the other master and needs it to stay valid continuously. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 330: External Bus Operations
The basic transfer protocol defines the sequence of actions that must occur on the external bus to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is shown in Figure 13-8. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 331 External Master Mode. 13.5.2.4.1 Single Beat Read Flow The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 332 CS access & !SETA? asserts transfer acknowledge (TA) asserts transfer acknowledge (TA) receives data Figure 13-9. Basic Flow Diagram of a Single Beat Read Cycle MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 333 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA[0:31] DATA is valid Figure 13-10. Single Beat 32-bit Read Cycle, CS Access, Zero Wait States MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 334 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA[0:31] Wait State DATA is valid Figure 13-11. Single Beat 32-bit Read Cycle, CS Access, One Wait State MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 335 Figure 13-12. Single Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States 13.5.2.4.2 Single Beat Write Flow The handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 336 CS access & ! SETA? asserts transfer acknowledge (TA) asserts transfer acknowledge (TA) waits 1 clock stops driving data Figure 13-13. Basic Flow Diagram of a Single Beat Write Cycle MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 337 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA is valid DATA[0:31] WE[0:3] Figure 13-14. Single Beat 32-bit Write Cycle, CS Access, Zero Wait States MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 338 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA is valid DATA[0:31] Wait State WE[0:3] Figure 13-15. Single Beat 32-bit Write Cycle, CS Access, One Wait State MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 339 Section 13.5.2.6, “Small Accesses (Small Port Size and Short Burst Length) for small access timing). A dead cycle refers to a cycle between the TA of a previous transfer and the TS of the next transfer. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 340 TS assertion of the second access. See Section 13.5.2.9, “Termination Signals Protocol for more details. The following diagrams show a few examples of back-to-back accesses on the external bus. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 341 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA[0:31] DATA is valid DATA is valid Figure 13-17. Back-to-Back 32-bit Reads to the Same CS Bank MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 342 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA[0:31] DATA is valid DATA is valid Figure 13-18. Back-to-Back 32-bit Reads to Different CS Banks MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 343 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA is valid DATA[0:31] DATA is valid Figure 13-19. Write After Read to the Same CS Bank MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 344 CLKOUT ADDR[3:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA is valid DATA is valid DATA[0:31] Figure 13-20. Back-to-Back 32-bit Writes to the Same CS Bank MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 345 Burst Transfer The EBI supports wrapping 32-byte critical-doubleword-first burst transfers. Bursting is supported only for internally-requested cache-line size (32-byte) read accesses to external devices that use the chip selects MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 346 Section 13.5.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode. This case (of 2 external burst transfers being required) applies only to AMBA data bus width of 64 bits. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 347 , the EBI negates BDIP during write cycles. Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See Section 13.5.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 348 BDIP next to last data beat? negate BDIP drives last data asserts transfer acknowledge (TA) receive last data Figure 13-22. Basic Flow Diagram of a Burst Read Cycle MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 349 CLKOUT ADDR[3:31] ADDR[29:31] = ‘000’ RD_WR TSIZ[0:1] ‘00’ Expects another data BDIP DATA[0:31] DATA is valid Figure 13-23. Burst 32-bit Read Cycle, Zero Wait States MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 350 (BSCY). Figure 13-25 shows an example of the TBDIP=0 timing for a 4-beat burst with BSCY=1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 351 When using TBDIP=1, the BDIP behavior changes to toggle between every beat when BSCY is a non-zero value. Figure 13-26 shows an example of the TBDIP=1 timing for the same 4-beat burst shown in Figure 13-25. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 352 If this is the case, the EBI initiates multiple transactions until all the requested data is transferred. It should be noted that all the transactions initiated to complete the data transfer are considered MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 353 13.5.2.6.1 Small Access Example #1: 32-bit Write to 16-bit Port Figure 13-27 shows an example of a 32-bit write to a 16-bit port, requiring two 16-bit external transactions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 354 TA and the next TS in order to get the next 64-bits of write data internally and RD_WR negates during this extra cycle. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 355 0x10 to the lower 5 bits of the 1st address (no carry), and then masking out the lower 4 bits to fix them at zero. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 356 Masking Lower 4 Bits) 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 357 13.5.2.6.4 Small Access Example #4: 64-bit Read to 16-bit Port Figure 13-30 shows an example of a 64-bit read to a 16-bit port, requiring four 16-bit external transactions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 358 EBI. The behavior of the EBI for request sizes not shown below is undefined. No error signal is asserted for these erroneous cases. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 359 • The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. This can be seen in Figure 13-31. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 360 MCU. The bytes indicated as ‘-’ are not driven during that write cycle. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 361 Bus Busy to assume ownership of the bus. The new master must sample Bus Busy negated for two cycles before asserting Bus Busy, to avoid any potential conflicts. Any time the arbiter has MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 362 MCU must rearbitrate for the bus before the next transaction. The determination of priority between masters is determined entirely by the external arbiter in this mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 363 The priority between internal and external masters over the external bus is determined by the EARP field of the EBI_MCR. See Table 13-9 for the EARP field description. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 364 (Master 0), while another master is configured for external arbitration (Master 1). In this case, the BR signals of each master MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 365 Ext. master owns bus for next transaction, waiting for MCU to negate BG=0, BB=0/1 BB from current transaction in progress Table 13-21 shows the truth table for the internal arbiter protocol. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 366 Once a transaction for a pending request has been started on the external bus, this internal signal is cleared. The state machine uses the previous clock value to avoid potential speed paths with trying to calculate bus grant based on a late-arriving internal request signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 367 (depending on BR, BB, etc., according to normal transition logic). Figure 13-37 shows the internal finite state machine that implements the arbiter protocol. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 368 BB=hiZ BB=0 or RBG=1 ETP=External Transaction in Progress IRP=Internal Request Pending EHP=External has Higher Priority BR=Bus Request BG=Bus Grant BB=Bus Busy Figure 13-37. Internal Bus Arbitration State Machine MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 369 This means that for any accesses where the EBI drives TA (chip-select accesses with SETA=0 and external master accesses to EBI), a TEA assertion that occurs 1 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 370 "take turns" driving the termination signals. This assumes a system using slave devices that drive termination signals. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 371 External Master Mode enables an external master to access the internal address space of the MCU. Figure 13-39 shows how to connect an MCU to an external master (second MCU) and a shared SDR memory to operate in External Master Mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 372 When the external master requires external bus accesses, it takes ownership on the external bus, and the direction of most of the bus signals is inverted, relative to its direction when the MCU owns the bus. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 373 Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See Section 13.5.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 374 If an address or data error was detected internally, the MCU asserts TEA for one clock. Figure 13-40 Figure 13-41 illustrate the basic flow of read and write external master accesses. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 375 ** External arbiter is the EBI unless a central arbiter device is used. *** Determined by the internal arbiter of the external master device. Figure 13-40. Basic Flow Diagram of an External Master Read Access MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 376 ** External arbiter is the EBI unless a central arbiter device is used. *** Determined by the internal arbiter of the external master device. Figure 13-41. Basic Flow Diagram of an External Master Write Cycle MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 377 * If the external master is another MCU with this EBI, then BB and other control pins are turned off as shown due to use of latched TA internally. This extra cycle is not required by the slave EBI. Figure 13-42. External Master Read from MCU MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 378 ** If the external master is another MCU with this EBI, then DATA remains valid as shown due to use of latched TA internally. These extra data valid cycles are not required by the slave EBI. Figure 13-43. External Master Write to MCU MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 379 Single Master Mode in earlier sections. See Section 13.5.2.4, “Single Beat Transfer Section 13.5.2.5, “Burst Transfer. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 380 CS access & ! SETA ? asserts transfer acknowledge (TA) asserts transfer acknowledge (TA) receives data Figure 13-44. Basic Flow Diagram of an EBI Read Access in External Master Mode MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 381 EBI is assumed to be configured for internal arbitration while the external master is configured for external arbitration. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 382 This case assumes the MCU has no higher priority internal request pending and is able to park the external master on the bus. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 383 ADDR[3:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid Figure 13-46. External Master Read followed by MCU Read to Same CS Bank MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 384 ADDR[3:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid Figure 13-47. MCU Read followed by External Master Read to Different CS Bank MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 385 Both masters off ADDR[3:31] RD_WR TSIZ[0:1] BDIP DATA is valid DATA[0:31] DATA is valid Figure 13-48. External Master Read followed by External Master Write to Different CS Bank MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 386 32-bit read from an external master in 16-bit data bus mode. Figure 13-50 shows a 32-bit write from an external master in 16-bit data bus mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 387 DATA is valid Minimum 2 Wait States DATA is valid * Or DATA[16:31], based on D16_31 bit in EBI_MCR. Figure 13-49. External Master 32-bit Read from MCU with DBM=1 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 388 DATA is valid *DATA[0:15] TA (output) Minimum 3 Wait States * Or DATA[16:31], based on D16_31 bit in EBI_MCR. Figure 13-50. External Master 32-bit Write to MCU with DBM=1 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 389 13-18, except the CSy is replaced by CAL_CSy. Timing for other cases on calibration bus can similarly be derived from other figures in this document (by replacing CS with CAL_CS). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 390 AMBA AHB V6 specification. The EBI works under the assumption that all internal masters on the SoC do not produce any misaligned access cases (to the EBI) other than the ones below. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 391 For this case, the EBI internally treats HSIZE as 10 (4-byte access). Table 13-24 shows which external transfers are generated by the EBI for the misaligned access cases in Table 13-23, for each port size. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 392 1000 0111 1011 0011 0111 Word @0x2,0xA 1100 0011 0011 0011 Word @0x3,0xB 1110 0001 1011 0011 0111 Word @0x5,0xD 1000 (2 AHB 0111 transfers) 1011 0011 0111 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 393 AMBA bus. All other misaligned cases are not supported. If an unsupported misaligned access to the EBI is attempted (such as non-chip-select or burst misaligned MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 394 TSIZ[0:1] signals are not intended to be used for misaligned accesses, so they are not specified in Table 13-26. Table 13-26. Misalignment Cases Supported by a 32 bit AMBA EBI (external bus) Program Size ADDR[30:31] WE_BE[0:3] and byte offset Half @0x1 1001 1011 0111 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 395 This clock gap already exists (for other reasons) for non-small-access transfers, so no additional clock gap is inserted for those cases. See Figure 13-52 for an example of a small access read with A/D multiplexing enabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 396 DATA[16:31] (or DATA[0:15]) would be used for address and data on an external muxed device. ** Or DATA[0:15], based on D16_31 bit in EBI_MCR. Figure 13-52. Small access (32-bit read to 16-bit port) on Address/Data multiplexed bus MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 397: Initialization/Application Information
Burst Read operation to an SDR burst memory. Refer to Figure 13-14 for an example of the timing of a typical Single Write operation to SDR memory. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 398: Running With Asynchronous Memories
* Flash memories typically use one WE signal as shown, RAMs use 2 or 4 (16-bit or 32-bit) Figure 13-54. MCU Connected to Asynchronous Memory Figure 13-55 shows a timing diagram of a read operation to a 16-bit asynchronous memory using 3 wait states. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 399 16-bit asynchronous memory using 3 wait states. CLKOUT ADDR[3:31] WE[0:1] DATA[0:31] DATA is valid 3 Wait States Figure 13-55. Read Operation to Asynchronous Memory, Three Initial Wait States MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 400: Connecting An Mcu To Multiple Memories
The MCU can be connected to more than one memory at a time. Figure 13-57 shows an example of how two memories could be connected to one MCU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 401: Address Decoding Example For External Master Accesses
The EBI allows external masters to access internal address space when the EBI is configured for External Master Mode. Since <32 bits are available on the external bus, special decoding logic is required to allow MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 402: Ebi Operation With Reduced Pinout Mcus
This scenario is straightforward. Simply connect DATA[0:15] between both MCUs, and configure both for 16-bit Data Bus Mode operation (DBM=1 in EBI_MCR). Note that 32-bit external memories are not supported in this scenario. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 403 BDIP to burst. Many external memories use a self-timed configurable burst mechanism that does not require a dynamic burst indicator. Check the applicable external memory specification to see if BDIP is required in your system. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 404: Address/Data Multiplexing Connection Examples
32-bit A/D muxed devices at the same time. Neither of these cases are possible if a value of 0 for EBI_MCR[D16_31] bit is used (because ADDR[0:15] will be muxed onto DATA[16:31] for 32-bit mode, DATA[0:15] for 16-bit mode). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 405 ** These refer to the DATA pins of the MCU, which are used for both address and data functions in this system. Note that a few of the upper DATA pins are data-only. Figure 13-58. Address/Data Multiplexing with a 32-bit bus MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 406 ** These refer to the DATA pins of the MCU, which are used for both address and data functions in this system. Figure 13-59. Address/Data Multiplexing with a 16-bit bus MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 407 ** These refer to the DATA pins of the MCU, which are used for both address and data functions in this system. Figure 13-60. Address/Data Multiplexing with both 16-bit and 32-bit memories MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 408: Summary Of Differences From Mpc5Xx
EBI frequency • Modified TSIZ[0:1] functionality to only indicate size of current transfer, not give information on ensuing transfers that may be part of the same atomic sequence MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 409 — rationale: new feature to reduce minimum pin count • Added support for using either half of data bus for 16-bit port transfers — rationale: helps A/D muxed usability, while maintaining backwards compatibility MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 410 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 411: Information Specific To This Device
The high priority portion is initiated by a peripheral interrupt request, but then the ISR can assert a software setable interrupt request to finish MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 412: Block Diagram
INTC. In this document, any features described for Processor 0 are intended to be backward compatible with the single core interrupt controller used on the eSYS family of devices. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 413: Features
Features • Parameterizable up to 504 peripheral interrupt request sources. • Each interrupt source is software steerable to Processor 0, Processor 1 or both processors interrupt request outputs. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 414: Modes Of Operation
(INTC_CPR_PRC1)” onto the associated LIFO and updates PRI in the associated INTC_CPR_PRCx with the new priority. Furthermore, the interrupt vector to the processor is driven as all ‘0’s. The interrupt acknowledge signal from the associated processor is ignored. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 415: Debug Mode
14.3.4 Factory Test Mode All INTC registers are accessible in factory test mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 416: External Signal Description
32 bits. In software vector mode, the side effects of a read of Section 14.5.6, “INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0)” and Section 14.5.7, “INTC Interrupt Acknowledge MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 417: Intc Block Configuration Register (Intc_Bcr)
‘0’s will determine the size of each vector table entry. Refer to Section 14.7.3, “Code Compression’s Impact on Vector Table,” for a use of the VTES_PRC0 or VTES_PRC1 bit. 1 = 8 bytes 0 = 4 bytes MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 418: Intc Current Priority Register For Processor 0 (Intc_Cpr_Prc0)
Section 14.7.6.2, “Ensuring Coherency,” example code to ensure coherency. PRI[0:3] — Priority. PRI is the priority of the currently executing ISR according to the field values defined in Table 14-3. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 419: Intc Current Priority Register For Processor 1 (Intc_Cpr_Prc1)
Figure 14-4. INTC Current Priority Register (INTC_CPR_PRC1) The functionality of this register is the same as described for Processor 0 in Section 14.5.4, “INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0)”. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 420: Intc Interrupt Acknowledge Register For Processor 0 (Intc_Iackr_Prc0)
INTVEC_PRC0 is the vector of the peripheral or software setable interrupt request that caused the interrupt request to the processor. When the interrupt request to the processor asserts, the INTVEC_PRC0 is updated, whether the INTC is in software or hardware vector mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 421: Intc Interrupt Acknowledge Register For Processor 1 (Intc_Iackr_Prc1)
INTC_EOIR_PRC0 are ignored. Those values and sizes written to this register neither update the INTC_EOIR_PRC0 contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all ‘0’s to the INTC_EOIR_PRC0. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 422: Intc End Of Interrupt Register For Processor 1 (Intc_Eoir_Prc1)
14.5.10 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3 - INTC_SSCIR4_7) INTC_BASE+0x20 CLR0 CLR1 SET0 SET1 RESET: CLR2 CLR3 SET2 SET3 RESET: = Unimplemented or Reserved Figure 14-9. INTC Software Set/Clear Interrupt Register 0 - 3 (INTC_SSCIR0_3) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 423 SETx bit. Writing a ‘0’ to CLRx will have no effect. 1 = Interrupt request pending within INTC. 0 = Interrupt request not pending within INTC. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 424 The PRC_SELx or PRIx field of an INTC_PSRx_x must not be modified while its corresponding peripheral or software setable interrupt request is asserted. PRC_SEL0[0:1] - PRC_SEL511[0:1] - Processor Select MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 425: Functional Description
Setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC as an interrupt event setting the flag bit. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 426: Priority Management
(INTC_CPR_PRC1)”. The results of those comparisons are used to manage the priority of the ISR being executed by the associated processor. The associated LIFO also assists in managing that priority. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 427 Interrupt requests whose PRIx in INTC_PSRx_x are zero will not cause a preemption because their PRIx will not be higher than PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 428: Handshaking With Processor
Section 14.5.6, “INTC Interrupt Acknowledge Register for Processor (INTC_IACKR_PRC0)” or Section 14.5.7, “INTC Interrupt Acknowledge Register for processor 1 (INTC_IACKR_PRC1)” is updated with the preempting interrupt request’s vector when the interrupt MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 429 This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 430 The handshaking near the end of the interrupt exception handler, that is the writing to the associated INTC_EOIR_PRC0 or INTC_EOIR_PRC1, is the same as in software vector mode. Refer to Section 14.6.3.1.2, “End of Interrupt Exception Handler”. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 431: Reserved Spaces In Memory Map
14.6.4 Reserved Spaces in Memory Map The memory map has spaces reserved for alternate implementations of the INTC. These features are not in this implementation of the INTC. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 432: Initialization/Application Information
# branch to ISR; link register updated with epilog # address epilog: r3,hi(INTC_EOIR_PRCx) # form INTC_EOIR_PRC0 address r3,r3,lo(INTC_EOIR_PRCx) r4,0x0 # form 0 to write to INTC_EOIR_PRCx r4,0x0(r3) # store to INTC_EOIR_PRCx, informing INTC to lower priority MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 433 SRR0 and SRR1 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC # branch to epilog MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 434: Code Compression's Impact On Vector Table
ISRs execute in the time order that their peripheral or software setable interrupt requests asserted. The example in Table 14-6 shows the order of execution of both ISRs with different priorities and the same priority. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 435: Priority Ceiling Protocol
OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol therefore allows coherent accesses of the ISRs to that shared resource. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 436: Selecting Priorities According To Request Rates And Deadlines
ISRs with request rates around 1 ms would share a priority, ISRs with request rates around 500 μs would share a priority, ISRs with request rates around 250 μs would share MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 437: Software Setable Interrupt Requests
The accesses to the block of data must be done coherently. The procedure is that the first processor writes a ‘1’ MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 438: Lowering Priority Within An Isr
Their PRIx values in Section 14.5.11, “INTC Priority Select MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 439: Examining Lifo Contents
When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR_PRCx load INTC_IACKR_PRCx if stacked PRI values are not depleted, branch to push_lifo MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 440 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 441: Introduction
In software vector mode, IVOR4 is used for the external input, that is, the interrupt request to the e200z335 from the INTC. Figure 15-1 shows the software vector mode interrupt exception handler address calculation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 442 IVPR. The vectors for each source are shown in Table 15-1. The amount of the offset is the vector times 16 bytes. Figure 15-2 shows the hardware vector mode interrupt exception handler address calculation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 443: Critical Input
Table 15-1. The Source column is written in C language syntax. The syntax is block_instance.register[bit]. The syntax ‘||’ represents the ORing of individual interrupt requests from the block. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 444 0x00f0 eDMA.DMAINTL[INT4] eDMA channel Interrupt 4 eDMA_INTL_INT5 0x010 eDMA.DMAINTL[INT5] eDMA channel Interrupt 5 eDMA_INTL_INT6 0x011 eDMA.DMAINTL[INT6] eDMA channel Interrupt 6 eDMA_INTL_INT7 0x012 eDMA.DMAINTL[INT7] eDMA channel Interrupt 7 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 445 0x023 eDMA.DMAINTL[INT24] eDMA channel Interrupt 24 eDMA_INTL_INT25 0x024 eDMA.DMAINTL[INT25] eDMA channel Interrupt 25 eDMA_INTL_INT26 0x025 eDMA.DMAINTL[INT26] eDMA channel Interrupt 26 eDMA_INTL_INT27 0x026 eDMA.DMAINTL[INT27] eDMA channel Interrupt 27 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 446 0x036 eMIOS.eMIOSFLAG[F3] eMIOS channel 3 Flag eMIOS_FLAG_F4 0x037 eMIOS.eMIOSFLAG[F4] eMIOS channel 4 Flag eMIOS_FLAG_F5 0x038 eMIOS.eMIOSFLAG[F5] eMIOS channel 5 Flag eMIOS_FLAG_F6 0x039 eMIOS.eMIOSFLAG[F6] eMIOS channel 6 Flag MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 447 Channel 5 Interrupt Status eTPU_CISR_1_CIS6 0x04a eTPU.eTPUCISR_1[CIS6] eTPU_1 Channel 6 Interrupt Status eTPU_CISR_1_CIS7 0x04b eTPU.eTPUCISR_1[CIS7] eTPU_1 Channel 7 Interrupt Status eTPU_CISR_1_CIS8 0x04c eTPU.eTPUCISR_1[CIS8] eTPU_1 Channel 8 Interrupt Status MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 448 Channel 25 Interrupt Status eTPU_CISR_1_CIS26 0x05e eTPU.eTPUCISR_1[CIS26] eTPU_1 Channel 26 Interrupt Status eTPU_CISR_1_CIS27 0x05f0 eTPU.eTPUCISR_1[CIS27] eTPU_1 Channel 27 Interrupt Status eTPU_CISR_1_CIS28 0x060 eTPU.eTPUCISR_1[CIS28] eTPU_1 Channel 28 Interrupt Status MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 449 FIFO 2 Non-Coherency Flag eQADC_FISR2_PF2 0x070 eQADC.eQADC_FISR2[PF2] eQADC command FIFO 2 Pause Flag eQADC_FISR2_EOQF2 0x071 eQADC.eQADC_FISR2[EOQF2] eQADC command FIFO 2 command queue End Of Queue Flag MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 450 FIFO 5 command queue End Of Queue Flag eQADC_FISR5_CFFF5 0x081 eQADC.eQADC_FISR5[CFFF5] eQADC Command FIFO 5 Fill Flag eQADC_FISR5_RFDF5 0x082 eQADC.eQADC_FISR5[RFDF5] eQADC Receive FIFO 5 Drain Flag MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 451 DSPI_C_ISR_RFDF 0x08c DSPI_C.DSPI_ISR[RFDF] DSPI_C Receive FIFO Drain Flag Reserved 0x08d Reserved Reserved Reserved 0x08e Reserved Reserved Reserved 0x08f0 Reserved Reserved Reserved 0x090 Reserved Reserved Reserved 0x091 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 452 CRC Error, eSCI_A.LINSTAT1[CKERR] || Checksum Error, eSCI_A.LINSTAT1[FRC] || Frame Complete interrupts requests, eSCI_A.LINSTAT2[OVFL] and LIN Status Register 2 Receive Register Overflow Reserved 0x093 Reserved Reserved Reserved 0x094 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 453 FLEXCAN_A Buffer 0 Interrupt BUF0I FLEXCAN_A_IFLAG1_ 0x09c FLEXCAN_A.IFLAG1[BUF1I] FLEXCAN_A Buffer 1 Interrupt BUF1I FLEXCAN_A_IFLAG1_ 0x09d FLEXCAN_A.IFLAG1[BUF2I] FLEXCAN_A Buffer 2 Interrupt BUF2I FLEXCAN_A_IFLAG1_ 0x09e FLEXCAN_A.IFLAG1[BUF3I] FLEXCAN_A Buffer 3 Interrupt BUF3I MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 454 FLEXCAN_C_ESR_ERR_ 0x0ae FLEXCAN_C.ESR[ERR_INT] FLEXCAN_C Error Interrupt FLEXCAN_C_WAKEUP_ 0x0af0 FLEXCAN_C.IPI_INT_WAKEIN FLEXCAN_C Wakeup Interrupt FLEXCAN_C_IFLAG1_ 0x0b0 FLEXCAN_C.IFLAG1[BUF0I] FLEXCAN_C Buffer 0 Interrupt BUF0I FLEXCAN_C_IFLAG1_ 0x0b1 FLEXCAN_C.IFLAG1[BUF1I] FLEXCAN_C Buffer 1 Interrupt BUF1I MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 455 FLEXCAN_C.IFLAG1[BUF31I:BUF16 FLEXCAN_C Buffers 31 - 16 BUF31_16I Interrupts Reserved 0x0c1 Reserved Reserved Reserved 0x0c2 Reserved Reserved Reserved 0x0c3 Reserved Reserved Reserved 0x0c4 Reserved Reserved Reserved 0x0c5 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 456 Reserved 0x0d3 Reserved Reserved Reserved 0x0d4 Reserved Reserved Reserved 0x0d5 Reserved Reserved Reserved 0x0d6 Reserved Reserved Reserved 0x0d7 Reserved Reserved Reserved 0x0d8 Reserved Reserved Reserved 0x0d9 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 457 Reserved 0x0e7 Reserved Reserved Reserved 0x0e8 Reserved Reserved Reserved 0x0e9 Reserved Reserved Reserved 0x0ea Reserved Reserved Reserved 0x0eb Reserved Reserved Reserved 0x0ec Reserved Reserved Reserved 0x0ed Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 458 Reserved 0x101 Reserved Reserved Reserved 0x102 Reserved Reserved Reserved 0x103 Reserved Reserved Reserved 0x104 Reserved Reserved Reserved 0x105 Reserved Reserved Reserved 0x106 Reserved Reserved Reserved 0x107 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 459 Reserved 0x115 Reserved Reserved Reserved 0x116 Reserved Reserved Reserved 0x117 Reserved Reserved Reserved 0x118 Reserved Reserved Reserved 0x119 Reserved Reserved Reserved 0x11a Reserved Reserved Reserved 0x11b Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 460 Reserved 0x129 Reserved Reserved Reserved 0x12a Reserved Reserved Reserved 0x12b Reserved Reserved Reserved 0x12c Reserved Reserved PIT0 0x12d ipi_int_pit[0] PIT[0] PIT1 0x12e ipi_int_pit[1] PIT[1] PIT2 0x12f0 ipi_int_pit[2] PIT[2] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 461 Reserved 0x13d Reserved Reserved Reserved 0x13e Reserved Reserved Reserved 0x13f0 Reserved Reserved Reserved 0x140 Reserved Reserved Reserved 0x141 Reserved Reserved Reserved 0x142 Reserved Reserved Reserved 0x143 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 462 Reserved 0x151 Reserved Reserved Reserved 0x152 Reserved Reserved Reserved 0x153 Reserved Reserved Reserved 0x154 Reserved Reserved Reserved 0x155 Reserved Reserved Reserved 0x156 Reserved Reserved Reserved 0x157 Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 463 0x169 Reserved Reserved Reserved 0x16A Reserved Reserved Reserved 0x16B Reserved Reserved The priorities are selected in INTC_PSRx_x, where the specific select register is assigned according to the vector. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 464 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 465: Overview
Internal Multiplexing — Allows serial and parallel chaining of DSPIs — Allows flexible selection of eQADC trigger inputs — Allows selection of interrupt requests between external pins and DSPI MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 466: Modes Of Operation
SIU. The signals shown are external pins to the device. The SIU registers are accessed through the crossbar switch. Note that the Power-on Reset Detection block, Pad Interface/Pad Ring block, and Peripheral I/O Channels are external to the SIU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 467: Signal Description
IRQ Inputs, IMUX Peripheral I/O Channels DSPI Signals, & eQADC Triggers Figure 16-1. SIU Block Diagram 16.5 Signal Description Table 16-1 lists the external pins used by the SIU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 468: Detailed Signal Descriptions
The GPIO states from general purpose input and output. The GPIO pins are generally multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an 8-bit input (GPDI) or MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 469: Wkpcfg (Wkpcfg_Nmi_Gpio[213]) — I/O Pin Weak Pull Up Reset Configuration Pin
Operation,” defines the boot modes specified by the BOOTCFG1 pin. During the assertion of RSTOUT, the BOOTCFG1 pin is used to update the RSR and the BAM boot mode MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 470: Reset Control
NMI input or Critical Interrupt input, are drive by this logic. For this device the SIU outputs to eDMA are not connected. If SIU_DIRSR register selects the eDMA output, the effect will be to disable the interrupts. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 471: Gpio Operation
The six eQADC external trigger inputs can be connected to either an external pin, an eTPU channel, or an eMIOS channel. The input source for each eQADC external trigger is individually specified in the eQADC MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 472 DSPI block is connected to the same external device type, a separate interrupt can be generated for each device. This also applies to DSPI blocks connected to external devices of different type that have status bits in the same bit location of the deserialized information. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 473: Memory Map
DMA/Interrupt Request Enable Register (SIU_DIRER) SIU_BASE + 0x1C DMA/Interrupt Request Select Register (SIU_DIRSR) SIU_BASE + 0x20 Overrun Status Register (SIU_OSR) SIU_BASE + 0x24 Overrun Request Enable Register (SIU_ORER) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 474 Compare B High Register (SIU_CMPBH) SIU_BASE + 0x994 Compare B Low Register (SIU_CMPBL) SIU_BASE + 0x998 Reserved SIU_BASE + 0x9A0 System Clock Register (SIU_SYSDIV) SIU_BASE + 0x9A4 Halt Register (SIU_HLT) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 475: Siu_Base
Define Flash memory size, small granularity (see Table 16-5 for details) 19-10 Temp Range Define maximum operating range Rsvd Reserved for future enhancements 12-13 Max Freq Define maximum device speed MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 476 1024 Kbyte 2048 Kbyte Kbyte Table 16-5. Flash Memory Size Detailed Flash Size 2 field Size 0x(Flash size 1)/8 1x(Flash size 1)/8 2x(Flash size 1)/8 nx(Flash size 1)/8 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 477: Mcu Id Register (Siu_Midr)
Table 16-7. Memory Size Core Dependency PARTNUM Field z0, z1 z3, z4, z5 Reserved Reserved 128 Kbyte 512 Kbyte 256 Kbyte 768 Kbyte 320 Kbyte/384 Kbyte 1024 Kbyte MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 478: Reset Status Register (Siu_Rsr)
SIU_RSR is implemented, if unidirectional synchronous mode is selected at top level, all registers named Mode 1 are implemented, otherwise bidirectional asynchronous mode is selected and all registers named Mode 2 are implemented. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 479 SWTRS — Software Watchdog Timer Reset Status 1 = An enabled SWT Reset has occurred. 0 = No enabled SWT Reset has occurred. SSRS — Software System Reset Status MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 480: System Reset Control Register (Siu_Srcr)
The CRE bit in the SIU_SRCR allows software to enable a Checkstop Reset. If enabled, a Checkstop Reset will occur if the checkstop reset input to the reset controller is asserted. The Checkstop Reset is enabled by default. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 481: External Interrupt Status Register (Siu_Eisr)
0 = No reset occurs when the e200z335 core enters a checkstop state. 16.9.5 External Interrupt Status Register (SIU_EISR) The External Interrupt Status Register is used to record edge triggered events on the IRQ0 - IRQ15 inputs to the SIU. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 482: Dma/Interrupt Request Enable Register (Siu_Direr)
SIU to the interrupt controller. The EIRE bits allow selection of which External Interrupt Request Flag bits cause assertion of the one interrupt request signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 483: Dma/Interrupt Request Select Register (Siu_Dirsr)
Figure 16-11. DMA/Interrupt Request Select Register (SIU_DIRSR) DIRSx — DMA/Interrupt Request Select x This bit selects between a DMA or interrupt request when an edge triggered event occurs on the corresponding IRQx input. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 484: Overrun Status Register (Siu_Osr)
SIU to the interrupt controller is asserted. SIU_BASE + 0x24 RESET RESET = Unimplemented or Reserved Figure 16-13. Overrun Request Enable Register (SIU_ORER) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 485: Irq Rising-Edge Event Enable Register (Siu_Ireer)
The External IRQ Falling-Edge Event Enable Register allows falling edge triggered events to be enabled on the corresponding IRQx inputs. Rising and falling edge events can be enabled by setting the corresponding bits in both the SIU_IREER and SIU_IFEER. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 486: External Irq Digital Filter Register (Siu_Idfr)
= Unimplemented or Reserved Figure 16-16. IRQ Digital Filter Register (SIU_IDFR) DFL[0-3] — Digital Filter Length This field defines the digital filter period on the IRQx inputs according to Equation 16-1: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 487: Pad Configuration Registers (Siu_Pcr)
All pin names on this device begin with the primary function, followed by the alternate functions, and then GPIO. For example, for SIU_PRC87 and the CNTX_C_GPIO[87] pin, CNTX_C is the primary function. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 488 0100 Second Alternate Function 0101 Reserved 0110 Reserved 0111 Reserved 1000 Third Alternate Function 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 489 Actual slew rate is dependent on the pad type and load. See the electrical specification for this information. 16.9.13.1 Pad Configuration Register 83 (SIU_PCR83) The SIU_PCR83 register controls the pin function, direction, and static electrical attributes of the CNTX_A_TXD_A_GPIO[83] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 490 The SIU_PCR87 register controls the function, direction, and static electrical attributes of the CNTX_C_GPIO[87] pin. The PCS_D[3] function is not available on this device. This register allows selection of the CNTX_C and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 491 Figure 16-20. CNRX_C_GPIO[88] Pad Configuration Register (SIU_PCR88) 16.9.13.5 Pad Configuration Register 89 (SIU_PCR89) The SIU_PCR89 register controls the function, direction, and static electrical attributes of the TXD_A_eMIOS[13]_GPIO[89] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 492 The SIU_PCR91 register controls the function, direction, and static electrical attributes of the TXD_B_GPIO[91] pin. The PCS_D[1] function is not available on this device. This register allows selection of the TXD_B and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 493 16.9.13.9 Pad Configuration Register 102 (SIU_PCR102) The SIU_PCR102 register controls the function, direction, and static electrical attributes of the SCK_B_PCS_C[1]_GPIO[102] pin. This register allows selection of the SCK_B, PCS_C[1] and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 494 16.9.13.11 Pad Configuration Register 104 (SIU_PCR104) The SIU_PCR104 register controls the function, direction, and static electrical attributes of the SOUT_B_PCS_C[5]_GPIO[104] pin. This register allows selection of the SOUT_B, PCS_C[5] and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 495 The SIU_PCR106 register controls the function, direction, and static electrical attributes of the PCS_B[1]_GPIO[106] pin. The PCS_D[0] function is not available on this device. This register allows selection of the PCS_B and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 496 16.9.13.15 Pad Configuration Register 108 (SIU_PCR108) The SIU_PCR108 register controls the function, direction, and static electrical attributes of the PCS_B[3]_SIN_C_GPIO[108] pin. This register allows selection of the PCS_B, SIN_C and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 497 16.9.13.17 Pad Configuration Register 110 (SIU_PCR110) The SIU_PCR110 register controls the function, direction, and static electrical attributes of the PCS_B[5]_PCS_C[0]_GPIO[110] pin. This register allows selection of the PCS_B, PCS_C[0] and GPIO functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 498 The SIU_PCR115 - SIU_PCR118 registers control the functions, directions, and static electrical attributes of the eTPU_A[1:4]_eTPU_A[13:16]_GPIO[115:118] pins. Only the output channels of eTPU_A[13:16] are connected to pins. Both the input and output channels of eTPU_A[1:4] are connected to pins. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 499 It is required to program the PA field of both registers, SIU_PCR119 and SIU_PCR120, to select the SCK_LVDS alternate function, and then use the register SIU_PCR120 to program the SCK_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 500 It is required to program the PA field of both registers, SIU_PCR119 and SIU_PCR120, to select the SCK_LVDS alternate function, and then use the register SIU_PCR120 to program the SCK_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 501 It is required to program the PA field of both registers, SIU_PCR121 and SIU_PCR122, to select the SOUT_LVDS alternate function, and then use the register SIU_PCR122 to program the SOUT_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 502 It is required to program the PA field of both registers, SIU_PCR121 and SIU_PCR122, to select the SOUT_LVDS alternate function, and then use the register SIU_PCR122 to program the SOUT_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 503 GPDI register. The weak pull up/down selection at reset for the eTPU_A[9:11] pin is determined by the WKPCFG pin. Figure 16-40. eTPU_A[9:11]_eTPU_A[21:23]_GPIO[123:125] Pad Configuration Register (SIU_PCR123 - SIU_PCR125) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 504 GPDI register. The weak pull up/down selection at reset for the eTPU_A[13] pin is determined by the WKPCFG pin. Figure 16-42. eTPU_A[13]_PCS_B[3]_GPIO[127] Pad Configuration Register (SIU_PCR127) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 505 GPDI register. The weak pull up/down selection at reset for the eTPU_A[15] pin is determined by the WKPCFG pin. Figure 16-44. eTPU_A[15]_PCS_B[5]_GPIO[129] Pad Configuration Register (SIU_PCR129) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 506 GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. The weak pull up/down selection at reset for the eTPU_A[17] pin is determined by the WKPCFG pin. Figure 16-46. eTPU_A[17]_GPIO[131] Pad Configuration Register (SIU_PCR131) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 507 GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. The weak pull up/down selection at reset for the eTPU_A[19] pin is determined by the WKPCFG pin. Figure 16-48. eTPU_A[19]_GPIO[133] Pad Configuration Register (SIU_PCR133) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 508 GPIO[136] when configured as inputs. The weak pull up/down selection at reset for the eTPU_A[22] pin is determined by the WKPCFG pin. Figure 16-50. eTPU_A[22]_IRQ[10]_eTPU_A[17]_GPIO[136] Pad Configuration Register (SIU_PCR136) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 509 It is required to program the PA field of both registers, SIU_PCR138 and SIU_PCR139, to select the SCK_LVDS alternate function, and then use the register SIU_PCR139 to program the SCK_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 510 It is required to program the PA field of both registers, SIU_PCR138 and SIU_PCR139, to select the SCK_LVDS alternate function, and then use the register SIU_PCR139 to program the SCK_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 511 It is required to program the PA field of both registers, SIU_PCR140 and SIU_PCR141, to select the SOUT_LVDS alternate function, and then use the register SIU_PCR141 to program the SOUT_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 512 It is required to program the PA field of both registers, SIU_PCR140 and SIU_PCR141, to select the SOUT_LVDS alternate function, and then use the register SIU_PCR141 to program the SOUT_LVDS characteristics (drive strength using the slew rate field). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 513 The IBE bit must be set to one for GPIO when configured as input. The weak pull up/down selection at reset for the eTPU_A[28:29] pin is determined by the WKPCFG pin. Figure 16-56. eTPU_A[28:29]_PCS_C[1:2]_GPIO[142:143] Pad Configuration Register (SIU_PCR142 - SIU_PCR143) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 514 GPIO when configured as input. The weak pull up/down selection at reset for the eTPU_A[31] pin is determined by the WKPCFG pin. Figure 16-58. eTPU_A[31]_PCS_C[4]_eTPU_A[13]_GPIO[145] Pad Configuration Register (SIU_PCR145) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 515 GPIO when configured as input. The weak pull up/down selection at reset for the eMIOS[2] pins are determined by the WKPCFG pin. Figure 16-60. eMIOS[2]_eTPU_A[2]_GPIO[181] Pad Configuration Register (SIU_PCR181) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 516 GPIO[187:188] when configured as inputs. The weak pull up/down selection at reset for the eMIOS[8:9] pins is determined by the WKPCFG pin. Figure 16-62. eMIOS[8:9]_eTPU_A[8:9]_GPIO[187:188] Pad Configuration Register (SIU_PCR187 - SIU_PCR188) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 517 GPIO[191] when configured as an input. The weak pull up/down selection at reset for the eMIOS[12] pin is determined by the WKPCFG pin. Figure 16-64. eMIOS[12]_SOUT_C_eTPU_A[27]_GPIO[191] Pad Configuration Register (SIU_PCR191) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 518 Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to one for both eMIOS[23] and GPIO[202] when configured as inputs. The weak pull up/down selection at reset for the eMIOS[23] pins is determined by the WKPCFG pin. Figure 16-66. eMIOS[23]_GPIO[202] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 519 Figure 16-67. PLLREF_IRQ[4]_ETRIG[0]_GPIO[208] Pad Configuration Register (SIU_PCR208) 16.9.13.52 Pad Configuration Register 212 (SIU_PCR212) The SIU_PCR212 register control the function, direction, and static electrical attributes of the BOOTCFG1_IRQ[3]_ETRIG[1]_GPIO[212] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 520 The SIU_PCR215 register controls the function, direction, and static electrical attributes of the AN[12]_MA[0]_eTPU_A[19]_SDS pin. The AN[12] function is an analog pin on this device. This register allows selection of the MA[0] and SDS functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 521 Input and output buffers are enabled/disabled based on PA selection. Both input and output buffer disabled for AN[13] function. Output buffer only enabled for MA[1] and SDO functions. Figure 16-71. AN[13]_MA[1]_eTPU_A[21]_SDO Pad Configuration Register (SIU_PCR216) PA — Pin Assignment MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 522 The SIU_PCR218 register controls the function, direction, and static electrical attributes of the AN[15]_FCK_eTPU_A[29] pin. The AN[15] function is an analog pin on this device. This register allows selection of the FCK function. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 523 The WPS bit should be set to one when configured as GPIO. Figure 16-74. MCKO/CLKOUT_GPIO[219] Pad Configuration Register (SIU_PCR219) 16.9.13.59 Pad Configuration Register 220 (SIU_PCR220) The SIU_PCR220 register controls the drive strength of the MDO[0]_eTPU_A[13]_GPIO[220] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 524 When configured as GPI, the IBE bit should be set to one. Figure 16-76. MDO[1]_eTPU_A[19]_GPIO[221] Pad Configuration Register (SIU_PCR221) 16.9.13.61 Pad Configuration Register 222 (SIU_PCR222) The SIU_PCR222 register controls the drive strength of the MDO[2]_eTPU_A[21]_GPIO[222] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 525 When configured as GPI, the IBE bit should be set to one. Figure 16-78. MDO[3]_eTPU_A[25]_GPIO[223] Pad Configuration Register (SIU_PCR223) 16.9.13.63 Pad Configuration Register 224 (SIU_PCR224) The SIU_PCR224 register control the drive strength of the MSEO[0]_eTPU_A[27]_GPIO[224] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 526 When configured as GPI, the IBE bit should be set to one. Figure 16-80. MSEO[1]_eTPU_A[29]_GPIO[225] Pad Configuration Register (SIU_PCR225) 16.9.13.65 Pad Configuration Register 227 (SIU_PCR227) The SIU_PCR227 register controls the drive strength of the EVTO_eTPU_A[4]_GPIO[227] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 527 The SIU_PCR229 register controls the enabling/disabling and drive strength of the CLKOUT pin. The CLKOUT pin is enabled and disabled by setting and clearing the OBE bit. The CLKOUT pin is enabled during reset. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 528 = Unimplemented or Reserved Figure 16-84. RSTOUT Pad Configuration Register (SIU_PCR230) 16.9.13.69 Pad Configuration Register 231 (SIU_PCR231) The SIU_PCR231 register controls the function and drive strength of the EVTI_eTPU_A[2]_GPIO[231] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 529 When configured as GPI, the IBE bit should be set to one. Figure 16-86. TDI_eMIOS[5]_GPIO[232] Pad Configuration Register (SIU_PCR232) 16.9.13.71 Pad Configuration Register 336 (SIU_PCR336) The SIU_PCR336 register controls the drive strength of the CAL_CS[0] pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 530 The SIU_PCR340 register controls the drive strength of the CAL_ADDR[12:30] pins. Multiple pins are controlled by this PCR. SIU_BASE + 0x2E8 DSC[0-1] RESET RESET = Unimplemented or Reserved Figure 16-89. CAL_ADDR[12:15] Pad Configuration Register (SIU_PCR340) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 531 = Unimplemented or Reserved Figure 16-91. CAL_RD_WR, CAL_WE[0:1]/BE[0:1] and CAL_OE Pad Configuration Register (SIU_PCR342) 16.9.13.76 Pad Configuration Register 343 (SIU_PCR343) The SIU_PCR343 register controls the drive strength of the CAL_TS_ALE pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 532 Figure 16-93. CAL_MCKO and CAL_EVTO Pad Configuration Register (SIU_PCR344) 16.9.13.78 Pad Configuration Register 345 (SIU_PCR345) The SIU_PCR345 register controls the drive strength of the CAL_ADDR[16:27]_CAL_MDO[0:11], CAL_ADDR[28:29]_CAL_MSEO[0:1] and CAL_ADDR[30]_CAL_EVTI pins. Multiple pins are controlled by this PCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 533 Writes to the SIU_GPDOx_x registers have no effect on the state of the corresponding pins when the pins are configured for their primary function by the corresponding PCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 534: Gpo Data Output Registers (Siu_Gpdo350 - Siu_Gpdo413)
Writes to the SIU_GPDOx_x registers have no effect on the state of the corresponding pins when the pins are configured for their primary function by the corresponding PCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 535 (IBE) bit is set in the associated Pad Configuration Register, the SIU_GPDIx_x register reflects the actual state of the output pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 536: Eqadc Trigger Input Select Register (Siu_Etisr)
0 = Signal on pin is less than or equal to VIL. 16.9.17 eQADC Trigger Input Select Register (SIU_ETISR) The eQADC Trigger Input Select Register (SIU_ETISR) selects the source for the eQADC trigger inputs. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 537 The input for eQADC trigger 3 is specified by the TSEL3 field according to Table 16-19. Table 16-19. TSEL3 Field Definition TSEL3 Field eQADC Trigger 3 Input eTSEL3 eTPU_A[28] channel eMIOS[14] channel ETRIG[1] pin MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 538: External Irq Input Select Register (Siu_Eiisr)
ESEL13[0-1 ESEL12[0-1 ESEL11[0-1 ESEL10[0-1 ESEL9[0-1] ESEL8[0-1] RESET ESEL7[0-1] ESEL6[0-1] ESEL5[0-1] ESEL4[0-1] ESEL3[0-1] ESEL2[0-1] ESEL1[0-1] ESEL0[0-1] RESET = Unimplemented or Reserved Figure 16-103. External IRQ Input Select Register (SIU_EIISR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 539 The IRQ[12] input is specified by the ESEL12 field according to Table 16-26. Table 16-26. ESEL12 Field Definition ESEL12 Field IRQ[12] Input IRQ[12] pin DSPI_B[12] serialized input DSPI_C[13] serialized input reserved DSPI_D[14] serialized input MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 540 The IRQ[8] input is specified by the ESEL8 field according to Table 16-30. Table 16-30. ESEL8 Field Definition ESEL8 Field IRQ[8] Input IRQ[8] pin DSPI_B[8] serialized input DSPI_C[9] serialized input reserved DSPI_D[10] serialized input MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 541 The IRQ[4] input is specified by the ESEL4 field according to Table 16-34. Table 16-34. ESEL4 Field Definition ESEL4 Field IRQ[4] Input IRQ[4] pin DSPI_B[4] serialized input DSPI_C[5] serialized input reserved DSPI_D[6] serialized input MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 542: Dspi Input Select Register (Siu_Disr)
The DSPI Input Select Register (SIU_DISR) register specifies the source of each DSPI data input, slave select, clock input, and trigger input to allow serial and parallel chaining of the DSPI blocks. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 543 The source of the clock input of DSPI_B when in slave mode is specified by the SCKSELB field according to Table 16-41. Table 16-41. SCKSELB Field Definition SCKSELB Field DSPI_B Clock Input (Slave) SCK_B_PCS_C[1]_GPIO[102] pin Reserved DSPI_C_SCK (Master) reserved DSPI_D_SCK (Master; not available) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 544 The source of the clock input of DSPI_C when in slave mode is specified by the SCKSELC field according to Table 16-45. Table 16-45. SCKSELC Field Definition SCKSELC Field DSPI_C Clock Input (Slave) PCS_B[4]_SCK_C_GPIO[109] pin Reserved DSPI_B_SCK (Master) reserved DSPI_D_SCK (Master; not available) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 545: Mux Select Register 3 (Siu_Isel3)
Enhanced Trigger Input Not connected (default) RTI Trigger PIT0 Trigger PIT1 Trigger PIT2 Trigger PIT3 Trigger eTPU Channel (see Table 16-48., “ADC Queue Trigger x eTPU Channel) Reserved Reserved Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 546: Chip Configuration Register (Siu_Ccr)
When CRSE is asserted, the values driven onto the calibration bus pins will not be reflected onto the non-calibration bus pins. When CRSE is negated, the values driven onto the calibration bus pins will MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 547: External Clock Control Register (Siu_Eccr)
0 = External bus signals have zero output hold times. NOTE: The EBTS bit must not be modified while an external bus transaction is in progress. The field [16-24] is reserved and should not be used. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 548: Compare A High Register
The SIU_CMPAL register holds the 32-bit value that is compared against the value in the SIU_CMPBL register. The CMPAL field is read/write and is reset by the IP Green-Line synchronous reset signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 549: Compare B High Register
The SIU_CMPBL register holds the 32-bit value that is compared against the value in the SIU_CMPAL register. The CMPBL field is read/write and is reset by the IP Green-Line synchronous reset signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 550: System Clock Register (Siu_Sysdiv)
50% duty cycle. 00 = Divide by 2 01 = Divide by 4 10 = Divide by 8 11 = Divide by 16 30-31 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 551: Halt Register (Siu_Hlt)
SIU. These outputs will be connected as shown in Table 16-51. SIU_BASE + 0x9A4 RESET RESET = Unimplemented or Reserved Figure 16-113. Halt Register (SIU_HLT) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 552: Halt Acknowledge Register (Siu_Hltack)
IP Green-Line synchronous reset signal. The ipg_stop_en input signals from each module will be connected as shown in Table 16-52., “HALT Acknowledge Register Field Descriptions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 553 26 rsvd for eSCI_F 27 rsvd for eSCI_E 28 rsvd for eSCI_D 29 rsvd for eSCI_C 30 eSCI_B 31 eSCI_A bits left reserved for forward compatibility, not used on this device MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 554 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 555: Information Specific To This Device
The FMPLL multiplication factor, reference clock pre-divider factor, output clock divider ratio, modulation depth and multiplication rate are all controllable through programmable registers. Figure 17-1 shows the block diagram of the FMPLL. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 556: Features
— User-selectable ability to generate a system reset upon loss of lock • Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output clocks MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 557: Modes Of Operation
In bypass mode the PLL itself may or may not be running, depending on the state of the CLKCFG[1] bit of the ESYNCR1 register, but the PLL output is not connected to the system clock. Consequently, frequency modulation is not available. The pre-divider is also bypassed. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 558: External Signal Description
VDDPLL Analog power supply (1.2V +/- 10%) Power — VSSPLL Analog ground Ground — 17.3.1 Detailed Signal Descriptions Table 17-4 describes the external signals used by the FMPLL. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 559: Memory Map And Register Definition
— 0x018 SYNFMMR — Synthesizer FM Modulation Register 0x00000000 17.4.2.5/17-56 The symbol * means that the reset value is defined at SoC integration or by an external pin. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 560: Register Descriptions
Reset – – – – – – – – – – – Reset 1 Reset value is determined by the SoC integration. Figure 17-2. Synthesizer Control Register (SYNCR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 561 LOLRE bit. See Section 17.5.3, “Lock Detection. 0 Ignore loss-of-lock. Reset not asserted. 1 Assert reset on loss-of-lock when operating in normal mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 562 Access: User read/write Reset LOLF LOC MODE LOCKS LOCK LOCF Reset – Reset value is determined by the state of the PLLREF pin. Figure 17-3. Synthesizer Status Register (SYNSR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 563 PLLREF pin cannot be changed anymore after reset. In enhanced mode, the PLLREF bit reflects the value of the CLKCFG[2] bit of the ESYNCR1 register. 0 External clock reference. 1 Crystal oscillator reference. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 564 1 Reset value is determined by the SoC integration. Reset value determined by an input signal external to the module, typically connected to the PLLREF pin. Figure 17-4. Enhanced Synthesizer Control Register 1 (ESYNCR1) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 565 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Clock inhibit MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 566 In bypass mode, the loss-of-clock function is always enabled, regardless of the state of the LOCEN bit. Furthermore, the LOCEN bit has no effect on the loss-of-lock detection circuitry. 0 Loss of clock disabled. 1 Loss of clock enabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 567 It can only be programmed when the FMPLL is locked. Writing to this register while the FMPLL is unlocked has no effect. Furthermore, when the PLL loses lock, FM modulation is disabled and the SYNFMMR register is reset. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 568 EMFD represents the nominal value of the feedback loop divider. NOTE The product of INCSTEP and MODPERIOD cannot be larger than (2 - 1). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 569: Functional Description
4 MHz. The LOCK flag is immediatly negated after any of the following events: 1. In legacy mode, the PREDIV or MFD fields of the SYNCR1 register are changed MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 570: Lock Detection
1. Note that changing only the CLKCFG[0] bit to move from bypass to normal or vice-versa, and keeping the values of the other ESYNCR1 register fields unchanged, will not cause the PLL to lose lock or the lock flag to be cleared. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 571 — Bypass mode with crystal reference and PLL off — Bypass mode with external reference and PLL running — Bypass mode with crystal reference and PLL running — MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 572 — — Bypass mode with external reference and PLL running — — Bypass mode with crystal reference and PLL running — — Normal mode with external reference — MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 573 SYNCR in legacy mode which modifies the PREDIV or MFD fields, or a write to ESYNCR1 in enhanced mode which modifies the EMODE, EPREDIV, EMFD or CLKCFG[1:0] fields. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 574: Frequency Modulation
The following equations define how to calculate MODPERIOD and INCSTEP based on the frequency of the feedback divider (f ), the modulation frequency (f ) and the modulation depth percentage (MD): MODPERIOD round ------------------ × MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 575 After programming FM parameters, it takes some time until these parameters get propagated to the PLL analog circuitry. During this time, the BSY bit gets asserted. The modulation must only be enabled when MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 576 2. Program the MODSEL, MODPERIOD and INCSTEP fields of the SYNFMMR. 3. Poll the BSY bit of the SYNFMMR until it negates. 4. Assert the MODEN bit of the SYNFMMR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 577: Overview
PRAM ECC Address (PREAR) PRAM ECC Syndrome PRAM ECC Master PRAM ECC Attributes 0x64 Reserved (PRESR) (PREMR) (PREAT) 0x68 PRAM ECC Data High (PREDRH) 0x6c PRAM ECC Data Low (PREDRL) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 578: Register Descriptions
ECSM captures specific information (memory address, attributes and data, bus master number, etc.) which can be useful for subsequent failure analysis. Figure 18-1 Table 18-2 for the ECC Configuration Register definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 579 4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request. Figure 18-2 Table 18-3 for the ECC Status Register definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 580 This register can only be read from the IPS programming model; any attempted write is ignored. See Figure 18-3 Table 18-4 for the Platform Flash ECC Address Register definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 581 Value PFEMR Flash ECC Master This 4-bit register contains the AXBS bus master number of the faulting access Number Register of the last, properly-enabled platform flash ECC event. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 582 This register can only be read from the IPS programming model; any attempted write is ignored. See Figure 18-6 Table 18-7 for the Platform Flash ECC Data Register definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 583 This register can only be read from the IPS programming model; any attempted write is ignored. See Figure 18-7 Table 18-8 for the Platform RAM ECC Address Register definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 584 The PRESR register can only be read from the IPS programming model; any attempted write is ignored. Figure 18-8 Table 18-9 for the Platform RAM ECC Syndrome Register definition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 585 0x0C 0x52 0x0E 0x54 0x12 0x56 0x14 0x58 0x16 0x5A 0x18 0x5C 0x1A 0x5E 0x1C 0x60 0x50 0x62 0x22 0x64 0x24 0x66 0x26 0x68 0x28 0x6A 0x2A 0x6C MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 586 0x2C Even 0x58 0x2E Even 0x30 0x30 Even 0x32 0x32 Even 0x34 0x34 Even 0x64 0x36 Even 0x38 0x38 Even 0x62 0x3A Even 0x70 0x3C Even 0x60 0x3E MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 587 Platform RAM ECC Master Number Register definition. Register address: ECSM Base + 0x66 PREMR RESET: = Unimplemented Figure 18-9. Platform RAM ECC Master Number (PREMR) Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 588 PREAR, PRESR, PREMR, PREAT and PREDR registers, and the appropriate flag ( PRNCE) in the ECC Status Register to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 589 This 64-bit register contains the data associated with the faulting access of the RAM ECC Data PREDR last, properly-enabled platform RAM ECC event. The register contains the data Register value taken directly from the platform data bus. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 590 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 591: Information Specific To This Device
STM_CR register. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues to run. 19.3 External Signal Description The STM does not have any external interface signals. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 592: Memory Map And Register Definition
STM Channel 3 Interrupt Register 0x0048 STM_CMP3 STM Channel 3 Compare Register 0x004C - Reserved 0x3FFF 19.4.2 Register Descriptions The following sections detail the individual registers within the STM programming model. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 593 0 = STM counter continues to run in debug mode. 1 = STM counter is stopped in debug mode. Timer Counter Enabled. 0 = Counter is disabled. 1 = Counter is enabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 594 Figure 19-3. STM Channel Control Register (STM_CCRn) Table 19-4. STM_CCRn Field Descriptions Field Description Channel Enable. 0 = The channel is disabled. 1 = The channel is enabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 595 Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 596: Functional Description
STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the STM_CIRn[CIF] bit has no effect. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 597: Information Specific To This Device
• Stopped in debug mode (FRZ = 1) • Enabled (WEN = 1) • 32.7 ms timeout for 8 MHz crystal • WATCHDOG_PERIOD timeout for 20 MHz crystal MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 598: Introduction
SWT generates a system reset on an invalid access otherwise a bus error is generated. If either the HLK or SLK bits in the SWT_CR are set then the SWT_CR, SWT_TO, SWT_WN, SWT_SK registers are read only. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 599: Memory Map
Some devices can be configured to automatically clear the SWT_CR[WEN] bit during the boot process. This register is read only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 600 1 = SWT_CR, SWT_TO, SWT_WN and SWT_SK are read only registers Clock Selection. Selects the clock that drives the internal timer. 0 = System clock. 1 = Oscillator clock. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 601 The SWT Time-Out (SWT_TO) register contains the 32-bit time-out period. The reset value for this register is device specific. This register is read only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 602 20.4.2.5 SWT Service Register (SWT_SR) The SWT Time-Out (SWT_SR) service register is the target for service operation writes used to reset the watchdog timer. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 603 Therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 604: Functional Description
0xC520 followed by a write of 0xD928 to the SWT_SR[WSC] field. There is no timing requirement between the two writes. The unlock sequence logic ignores service sequence MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 605 The SWT_CO can be used during a software self test of the SWT. For example, the SWT can be enabled and not serviced for a fixed period of time less than the time-out value. Then the SWT can be disabled MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 606 (SWT_CR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter is working properly. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 607: Overview
The BAM program is not executed when the device comes out of reset in OnCE debug mode. The user must provide the required device initialization using the development tool before accessing the device resources. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 608: Internal Boot Mode
BAM program 0xFFFF_FFFC Device reset vector 0xFFFF_FFF8 BAM Last executed instruction 21.5 Functional Description 21.5.1 BAM Program Flow Chart The BAM program flow chart is shown in Figure 21-1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 609: Bam Program Operation
BAM program configures the e200z335 core MMU to allow access to all device internal resources, according to Table 21-2. This MMU setup remains the same for internal Flash boot mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 610 BOOTCFG pin to enable/disable the internal flash memory and the Nexus interface. The address of the Censorship word is 0x00FF_BDE0. The censorship word consists of two fields: censorship control MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 611: Reset Configuration Half Word (Rchw)
RCHW has to be programmed with a starting address of the user application. The BAM program uses this location to fetch the address, where it passes control to. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 612 The watchdog timeout periods, when the watchdogs are controlled by RCHW, are shown in Table 21-5. Table 21-5. WatchDog Timeouts Crystal Frequency (MHz) Core WD Timeout (ms) SWT Timeout (ms) 40.96 32.7 27.3 21.8 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 613: Internal Boot Mode
The BAM searches the internal Flash memory for a valid reset configuration half word (RCHW). Possible RCHW locations are shown in Table 21-6. Table 21-6. Possible RCHW Locations in the Internal Flash Block Address 0x0000_0000 0x0000_4000 0x0001_0000 0x0001_C000 0x0002_0000 0x0003_0000 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 614: Serial Boot Mode
Push/Pull output, CNTX_A Push/Pull output, GPIO with medium slew with medium slew rate rate CNRX_A GPIO CNRX_A Input with pull-up CNRX_A Input with pull-up GPIO and hysteresis and hysteresis MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 615 11-bit identifier format detailed in CAN 2.0A specification. See Table 21-8 for examples of baud rates. Only one message buffer 0 is used for all communications. The bit timing is configured as shown in Figure 21-6. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 616 A message with 0x12 ID and 8-byte length is used to send the start address, length, and the VLE mode bit. The device transmits back the same data, but with ID set to 0x2. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 617 The VLE mode bit instructs the device to program MMU entries 1-3 with VLE attribute. If it is 1, the downloaded code must be compiled to VLE instructions, if it is 0 the code contains classic Power Book E architecture instructions. 3. Download data. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 618 If the CNRX_A pin transitions first, the BAM program starts CAN baud rate detection routine, ignoring RXD_A. After detecting the CAN baud rate, the BAM program transitions to the CAN download protocol routine described above. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 619 21-9. (See FlexCAN chapter for the parameters definition). Table 21-9. Lookup Table for CAN Bit Timing Time segment 1 Time Segment 2 Time quanta per bit PROPSEG PSEG1 PSEG2 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 620: Booting From The Calibration Bus
The RCHW[PS0] bit has to be programmed to ‘1’, since the Calibration Bus does not support a 32-bit port size. If no valid RCHW was read, BAM switches to the serial boot mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 621 Set pads to 20pf drive strength CAL_ADDR[12:15] SIU_PCR345 for CAL_ADDR[16:30] SIU_PCR341 for CAL_DATA[0:15] SIU_PCR336 for CAL_CS[0] SIU_PCR342 for CAL_WE[0], CAL_RD/WR & CAL_OE SIU_PCR343 for Selects TS function CAL_TS 20pf drive strength MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 622 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 623: Information Specific To This Device
Double-action output compare (DAOC) Modulus counter buffered (MCB) Output pulse width and frequency modulation buffered (OPWFMB) 22.1.2.2 Channel Connections Table 22-2 shows the eMIOS channel connections for this device. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 624 The eMIOS channels on this device are grouped in three groups, according to their functionality: Channel Small, Channel Medium and Channel Big. The grouping is shown in Table 22-3. Table 22-3. eMIOS Channel Groups Channel SMALL MEDIUM Number MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 625: Device-Specific Register Information
Table 22-4. Table 22-4. eMIOS Registers per Channel Functionality Category GPIO SAIC SAOC OPWM IPM IPWM DAOC MCB OPWFMB B1 B2 Counter Channel Small Channel Medium Channel Big MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 626: Introduction
Modular Input/Output System Notes: 1. Connection between UC[n-1] and UC[n] Notes: 2: Illustration of a 24 channel eMIOS200 necessary to implement QDEC mode Output Disable Figure 22-1. eMIOS200 Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 627: Overview
The Unified Channels can be configured to operate in the following modes: • General purpose input/output • Single Action Input Capture • Single Action Output Compare • Input Pulse Width Measurement • Input Period Measurement MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 628: External Signal Description
Pull up emiosi[n] input eMIOS200 Channel n input chip dependent emioso[n] output eMIOS200 Channel n output 0/ Hi-Z chip dependent emios_flag_out[n] output eMIOS200 Channel n flag chip dependent MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 629: Memory Map/Register Definition
Global FLAG register (EMIOSGFLAG) $007 Output Update Disable (EMIOSOUDIS) $008 $00B Disable Channel (EMIOSUCDIS) $00C $00F reserved $010 $01F Channel [0] $020 $11F Channel [7] Channel [8] $120 $21F Channel [15] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 630 Table 22-8. Wheel Speed Channel Memory Map WSC[n] Base Address + Description T24CAPA + EVCNT register (EMIOSWSCAEC[n]) T24CAPB register (EMIOSWSCAPB[n]) Control register 1 (EMIOSWSC1[n]) Control register 2 (EMIOSWSC2[n]) Status register (EMIOSWSS[n]) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 631: Register Descriptions
Puts the eMIOS200 in low power mode. The MDIS bit is used to stop the clock of the block, except the access to registers EMIOSMCR, EMIOSOUDIS and EMIOSUCDIS. 1 = Enter low power mode 0 = Clock is running MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 632 Section 22.5.4, “Red Line Client submodule (REDC),” for details). GPRE[0:7] — Global Prescaler bits The GPRE[0:7] bits select the clock divider value for the global prescaler, as shown in Figure 22-9. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 633 Channels that occupy a pair of slots, such as WSC, are referred to by their lower slot number (LSB=0 standard), therefore the bits that correspond to their higher slot number always read 0. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 634 CHDIS[n] — Enable Channel [n] bit The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock. 1 = Channel [n] disabled 0 = Channel [n] enabled MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 635 OPWMC, OPWMCB, MC, MCB, PEA, PEC, WPTA. It means that if no mode requiring EMIOSB register is implemented then the register can be removed during synthesis through proper parameterization. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 636 EMIOSCNT[n] address: UC[n] base address + $08 C[0:7] RESET: C[8:23] RESET: = Unimplemented or reserved In GPIO mode or Freeze action, this register is writable. Figure 22-8. eMIOS200 UC Counter Register (EMIOSCNT[n]) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 637 0 = Normal operation ODIS — Output Disable bit The ODIS bit allows disabling the output pin when running any of the output modes with the exception of GPIO mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 638 Table 22-13. For output modes, these bits have no meaning. Table 22-13. UC Input Filter bits IF[0:3] Minimum input Pulse width [FLT_CLK periods] 0000 bypassed 0001 0010 0100 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 639 Table 22-14. UC BSL bits BSL[0:1] selected bus All channels: counter bus[A] Channels 0 to 7: counter bus[B] Channels 8 to 15: counter bus[C] Channels 16 to 23: counter bus[D] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 640 For output modes, the EDPOL bit is used to select the logic level on the output pin. 1 = A match on comparator A sets the output flip-flop, while a match on comparator B clears it MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 641 Center Aligned Output Pulse Width Modulation Buffered (with trail edge dead-time) 10111b1 Center Aligned Output Pulse Width Modulation Buffered (with lead edge dead-time) 11000b0 Output Pulse Width Modulation Buffered 1100001 through 1111111 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 642 The OVFL bit must be cleared by writing a 1 to the OVFLC. 1 = Clear OVFL bit 0 = Do not change OVFL bit UCIN — Unified Channel Input pin bit MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 643 Section 22.5.1.1.10, “Windowed Programmable Time Accumulation (WPTA) Mode,” Section 22.5.1.1.19, “Output Pulse Width Modulation with Trigger (OPWMT) Mode,” for a more detailed description of the use of EMIOSALTA[n] register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 644 T24CAPA[n] register. T24CAPB[n] and T24CAPA[n] store coherent data if T24CAPA[n] is read before T24CAPB[n] register in Wheel Speed mode out of freeze state. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 645 The IF[ bits control the programmable input filter, selecting the minimum input pulse width that can pass through the filter, as shown in Table 22-13. For output modes, these bits have no meaning. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 646 PWREN states. See Table 22-18. 1 = Either both edges or none triggering 0 = Either falling or rising edge triggering EDPOLCAP — Capture Register Edge Polarity bit MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 647 PWSWR and PWREN, be done only during Disable mode, otherwise the results are unpredictable. WSPRE[0:7] — Prescaler bits MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 648 The FLAGSEL[4:0] bits select the FLAG and FLAG Overrun that is used for interrupt generation according to Table 22-22. Table 22-22. WSC Interrupt Flag Selection FLAGSEL[4:0] selected flag 00000 none MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 649 Writing 1 to OVRCAPC bit clears the OVRCAP status bit. This bit is self negated, thus reading it returns always 0. 1 = Clear OVRCAP bit 0 = No effect MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 650 0 = No effect FLAGCEC — FLAGCE Clear bit Writing 1 to FLAGCEC bit clears the FLAGCE status bit. This bit is self negated, thus reading it returns always 0. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 651 FLAGPWOC bit set. If when attempting to clear the FLAGPWO flag the T16PWCNT counter rolls over again, then the FLAGPWO flag remains set. 1 = T16PWCNT overflow occurred 0 = T16PWCNT overflow did not occur MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 652 0 = No overflow To see in detail the precedence of events that set and clear flags and overruns go to Section 22.5.2.3, “Wheel Speed Channel Flags Operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 653 EMIOSWSCEV[n] address: WSC[n] base address + $18 T24CAPEV[23:16] RESET T24CAPEV[15:0] RESET: = Unimplemented or Reserved Figure 22-18. eMIOS200 WSC Capture Event Register (eMIOSWSCEV[n]) The EMIOSWSCEV[n] register provides read access to the 24-bit T24CAPEV register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 654: Functional Description
MCU. Up to four time bases can be shared by the channels through four counter buses and each channel can generate its own time base. Optionally one of the counter buses can be driven by an external time base imported through the Red-Line interface. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 655 In this case the application software should not access any register located in the channel[2] memory. Any attempt to access those registers will return no meaningful data and a Transfer Error will be generated . MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 656 A. Note that there are unified Channels with no external pin associated to it. Those channels are used to trigger internal SoC signals such as Interrupt requests or DMA transfer requests. Since MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 657: Unified Channel (Uc)
Two comparators (equal only) A and B, which compares the selected counter bus with the value in the data registers • Internal counter, which can be used as a local time base or to count input events MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 658 Multiplexors select the input of comparators and data for the registers inputs, thus configuring the datapath in order to implement the channel modes. The outputs of A and B comparators are connected to the uc_ctrl control block. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 659 As the internal counter EMIOSCNT[n] continues to run in all modes (except for GPIO mode), it is possible to use this as a time base if the resource is not used in the current mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 660 The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL and EDSEL bits in EMIOSC[n] register. Figure 22-25 Figure 22-26 show how the Unified Channel can be used for input capture. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 661 A1 must be written before the mode is entered. A1 register can be updated at any time thus modifying the match value which will reflect in the output signal generated by the channel. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 662 B1 and the trailing edge on register A2. Successive captures are done on consecutive edges of opposite polarity. The leading edge sensitivity (i.e., pulse polarity) is MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 663 EMIOSA[n] read. The B1 register updates remains locked until EMIOSB[n] read occurs. If EMIOSA[n] read is performed B1 is updated with A1 register content even if B1 update is locked by a previous EMIOSA[n] read operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 664 The input pulse period is calculated by subtracting the value in B1 from A2. Figure 22-32 shows how the Unified Channel can be used for input period measurement. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 665 When the DAOC mode is entered, coming out from GPIO mode both comparators are disabled and the output flip-flop is set to the complement of the EDPOL bit in the EMIOSC[n] register. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 666 2. EMIOSB[n] = B1 (when reading) A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 22-34. Double Action Output Compare with FLAG set on the second match MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 667 B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred. The desired time interval can be determined by subtracting register B1 from A2. Registers EMIOSA[n] and EMIOSB[n] return the values in register A2 and B1, respectively. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 668 EMIOSB[n] reads will not return coherent data until a new bus capture is triggered to registers A2 and B2. This capture event is indicated by the channel FLAG being asserted. If enabled, the FLAG also generates an interrupt. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 669 The PEC mode returns the amount of pulses or edges detected on the input for a desired time window. MODE[6] bit selects between continuos or single shot operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 670 $000303 $000303 B1 value EMIOSCNT[n] EMIOSCNT[n] A2 value Notes: 1. EMIOSA[n] = A1 2. EMIOSB[n] = B1 3. EMIOSALTA[n] = A2 Figure 22-39. Pulse/Edge Counting continuous mode example MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 671 EDPOL bit selects the count direction according to the phase difference between phase_A & phase_B signals. Figure 22-41 Figure 22-42 show two Unified Channels configured to quadrature decode mode for count & direction encoder and phase_A & phase_B encoders, respectively. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 672 FLAG bit is set. At the same time the content of EMIOSCNT[n] is transferred to register A2. Reading registers EMIOSCNT[n] or A2 returns the high or low time of the input signal, MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 673 — Internal clock source is selected if MODE[6] is cleared. In this case the counter clears as soon as the match signal occurs. The channel FLAG is set at the same time the match occurs. At the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 674 FLAG pin/register $xxxxxx $000303 $000303 $000200 $000200 A1 value $000303 Notes: 1. EMIOSA[n] = A1 A2 = A1according to OU[n] bit Figure 22-44. Modulus Counter up mode example MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 675 A1 values. Register A1 is loaded with A2 register value at the cycle boundary. Thus any value written to A2 register within cycle n will be updated to A1 at MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 676 (EMIOSCNT[n]) is loaded with $1. The load signal pulse has the duration of one system clock period. If A2 is written within cycle n its value is available at A1 at the first clock of MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 677 B1 plus one. MODE[6] bit controls the transfer from register B2 to B1, which can be done either immediately (MODE[6] cleared, MODE[0:6]=00110b0), providing the fastest change in the duty cycle, or at every match of register A1 (MODE[6] set, MODE[0:6]=00110b1). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 678 B2 value Notes: 1. EMIOSA[n] = A1 2. EMIOSB[n] = B2 A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 22-50. OPWFM with immediate update MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 679 OPWFMB mode regarding output pin transitions and A1/B1 registers match events. Note that the output pin transition occurs when the A1 or B1 match signal is MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 680 This allows to use the A1 posedge match to mask the B1 negedge match when they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 681 B2 data written on cycle n were loaded to A1 or B1, respectively, thus generating matches in cycle n+1. Note that the FLAG has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 682 EDPOL should be set to 0. Note that both the channel and global prescalers are set to $0 (each divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 683 A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater or equal to B1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 684 In the next match between register A1 and the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 685 If A1 and B1 are set to the $0, a 0% duty cycle waveform is produced. Figure 22-57 Figure 22-58 show the Unified Channel running in OPWMC with leading and trailing MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 686 Notes: 1. EMIOSA[n] = A1 2. EMIOSB[n] = B1 A2 = A1according to OU[n] bit MODE[6] = 0 B2 = B1according to OU[n] bit Figure 22-58. OPWMC with trailing dead time insertion MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 687 $2 to $1. This event defines the cycle boundary. Note that values written to A2 or B2 within cycle n are loaded into A1 or B1 registers, respectively, and used to generate matches in cycle n+1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 688 Center Aligned PWM signal. Note that both A1 and B1 register values are changing within the same cycle which allows to vary at the same time the duty cycle and dead time values. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 689 When the match between register B1 and the selected time base occurs the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 690 FORCMA bit set does not set the internal time-base to $1 as a regular A1 match. The FLAG bit is not set either in case of a FORCMA or FORCMB or even if both forces are issued at the same time. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 691 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 692 At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding to a match on A or B respectively. Note that FLAG bit is not set by the FORCMA and FORCMB operations. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 693 $001000 Notes: 1. EMIOSA[n] = A1 2. EMIOSB[n] = B2 A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 22-63. PWM with immediate update MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 694 Any value written to A2 or B2 on cycle n is loaded to A1 and B1 registers at the following cycle boundary (assuming OU[n] bit of EMIOSOUDIS register is not asserted). Thus the new values will be used for A1 and B1 matches in cycle n+1 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 695 B1=$8 negedge signal. In this case A1 match has precedence over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 696 Disable does not modify the Flag bit behavior. Note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to EDPOL. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 697 The mode is intended to be used in conjunction with other channels MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 698 FLAG signal but it has no effect on the PWM output signal generation. The typical setup to obtain a trigger with FLAG is enabling DMA and driving the channel’s ipd_done input high. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 699 When the Output Disable input signal is negated, the output pin will return to operate as normal. Figure 22-69 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and duty cycle update on next period update. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 700 2. EMIOSB[n] = B2 for write, B1 for read Figure 22-70. OPWMT with 0% Duty Cycle Figure 22-71 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and 100% duty cycle. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 701 A timing diagram of the input filter is shown in Figure 22-73. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 702 When exiting debug mode or freeze enable bit is cleared (FRZ in the EMIOSMCR or FREN in the EMIOSC[n] register) the channel actions resume, but may be inconsistent until channel enters GPIO mode again. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 703: Wheel Speed Channel (Wsc)
4. 24-bit capture register triggered by the event counter match logic 5. Interrupt generation capability based on the event counter or event detection An event is defined as a positive or negative edge in the sensor signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 704 This interrupt can be based on a match between the EVCNT counter register and the EVENT register or on an event detection. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 705 Thus it is important to determine the pulse width, high time or low time, of the sensor signal which is implemented by the T16PWCNT counter and T16PWCAP register in the pulse width measurement logic. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 706 WSC does not have an internal time base. An event is defined as a falling or rising edge on the sensor output signal MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 707 In general set events have precedence over clear events for flags, which means that if a certain event that sets the flag occurs, then the flag will be set regardless of events that cleared the flag. Additionally, the flag MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 708 In this case the flag overrun bit is not shown since this bit remains cleared. flag_set_event flag_reg flag_clr_event Figure 22-78. FLAG Set and Clear MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 709 The Local Clock Prescaler divides the Global Clock Prescaler output signal to generate a clock enable for the T16PWCNT counter of the Wheel Speed Channel, thus the channel is a synchronous implementation MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 710: Ip Bus Interface Unit (Biu)
IP interface. The BIU allows 8, 16 and 32 bits access. They are performed over a 32-bit data bus in a single cycle clock. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 711: Red Line Client Submodule (Redc)
In order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. Write 0 at GPREN bit in EMIOSMCR register, thus disabling global prescaler; MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 712: Initialization/Application Information
For MC and OPWFM with internal clock source operation modes, the internal counter rate can be modified by configuring the clock prescaler ratio. Figure 22-83 shows an example of a time base with prescaler ratio equal to one. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 713 NOTE MCB and OPWFMB modes have a different behavior. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 714 Note 1: The match occurs only when the input event/prescaler clock enable is active. Then, the internal counter is immediately cleared. Figure 22-86. Time base generation with clear on match end MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 715 The timebase channel and the output channel may be the same for some applications such as in OPWFM(B) mode or whenever the output channel is intended to run the timebase itself. At any time the flags can be configured. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 716 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 717: Introduction
CPU. Instructions execute faster, service time is reduced and program memory compacted. Instructions executed by the eTPU are connected directly to the eTPU timing hardware and allow parallelism of hardware related actions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 718: Overview
Both eTPU Engine CPUs, hereafter called microengines, fetch microinstructions from a Shared Code Memory - SCM. Shared Parameter RAM - SPRAM - holds eTPU application parameters and work data. It is accessed by Host and both microengines. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 719 32-bit Shared Parameter RAM (SPRAM) is used for two eTPU Engines data storage and for passing information between the eTPU Engines and the Host CPU. Figure 23-2 shows the block diagram for the eTPU Engine. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 720 TCRCLK clock pin. In addition, the TCR2 timebase can be derived from special angle-clock hardware which enables implementing angle-based functions. This feature is added to support advanced angle based engine control applications. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 721 Host interface registers to assign a Function and priority to each channel. In addition, the Host writes to the Host Service Request and channel configuration MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 722 Each Function may require a different number of parameters. During the eTPU initialization the Host has to program channel base addresses, allocating proper parameters for each channel according to its selected Function. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 723: Features
— enhanced input digital filters on the input pins for improved noise immunity. The eTPU digital filter can use 2 samples, 3 samples or work in continuous mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 724 (1024 bytes) — support for indirect and stacked data access schemes. — parallel execution of: data access, ALU, Channel control and flow control subinstructions in selected combinations. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 725 Input and Output features separated in channel logic and microinstructions, allowing input and output signals to be processed separately or combined. • Increased time resolution and execution unit to 24 bits. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 726 CHAN. They can also be requested simultaneously at the same instruction. • Channel Flags 0 and 1 can now be tested for branching, besides selecting the entry point. • Channel digital filters can be bypassed. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 727: Modes Of Operation
User debugs eTPU code, accessing special Trace/Debug features via Nexus interface: — hardware breakpoint/watchpoint setting — access to internal registers — single-step execution — forced instruction execution — software breakpoint insertion and removal. • Module Disable Mode MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 728 Stop Mode when SoC stop request is negated, but only if VIS=0. If SoC stop request is negated and VIS=1, eTPU will leave Stop Mode as soon as VIS=0. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 729: External Signal Description
Value 0 refers to the reset value of the signal. Hi-Z refers to the state of the pads, if controlled by the eTPU output buffer Enable signals, i.e., eTPU output buffer Enable resets in negated state. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 730: Detailed Signal Descriptions
MCU technology. Sampled on the T4 microcycle phase, see Section 23.6.1, “Microcycle and I/O Timing. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 731: Memory Map/Register Definition
23-3. Each of the register areas shown may have their own reserved address areas. Table 23-4 shows a detailed memory map. Offsets are relative to the eTPU Base address, which is MCU-dependent. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 732 ETPUMCR - eTPU Module Configuration Register 0x04 ETPUCDCR - eTPU Coherent Dual-Parameter Controller Register 0x08 RESERVED 0x0C ETPUMISCCMPR - eTPU MISC Compare Register 0x10 ETPUSCMOFFDATAR - eTPU SCM Off-range Data Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 733 ETPUCIOSR_1 - eTPU 1 Channel Interrupt Overflow Status Register 0x224 ETPUCIOSR_2 - eTPU 2 Channel Interrupt Overflow Status Register 0x228 RESERVED 0x22C RESERVED 0x230 ETPUCDTROSR_1 - eTPU 1 Channel Data Transfer Request Overflow Status Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 734 ETPUC0CR_2 - eTPU 2 Channel 0 Configuration Register 0x804 ETPUC0SCR_2 - eTPU 2 Channel 0 Status and Control Register 0x808 ETPUC0HSRR_2 - eTPU 2 Channel 0 Host Service Request Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 735: System Configuration Registers
This register is global to both eTPU Engines, and resides in the Shared BIU. ETPUMCR gathers global configuration and status in the eTPU system, including Global Exception. It is also used for configuring the SCM (Shared Code Memory) operation and test. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 736 SPRAM status parameter, for instance. This bit is cleared by writing 1 to GEC. 1 = Global Exception requested by microcode is pending 0 = No microcode-requested Global Exception pending. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 737 0 to 1, disabling the MISC operation. VIS — SCM Visibility Bit VIS bit turns SCM visible to the IP-Bus and resets MISC state (but SCMMISEN keeps its value). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 738 Figure 23-4. ETPUCDCR Register STS — Start Bit Engine is stopped in Module Disable or Stop Modes, but accesses to registers in Stop Mode is defined in the MCU level. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 739 ETPUMISCCMPR holds the 32-bit signature expected from the whole SCM array. This register must be written by the host with the 32-bit word to be compared against the calculated signature at the end of the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 740 Section 23.4.2.6.3, “SCM Off-range Data. NOTE This register is not implemented in some of the first eTPU implementations. Please consult the particular MCU’s SoC Guide or Reference Manual. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 741 The MDIS reset value is MCU-dependent. Please consult the SoC Guide of the specific MCU. Engine may go to Debug state (halted) soon after reset, depending on the NDEDI configuration (see NDEDI Block Guide). Figure 23-7. ETPUECR Register FEND — Force End MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 742 The Timebase registers can still be read with MDIS=1, but writes are ineffective and a Bus Error is issued. Global Channel Registers and SPRAM can be accessed normally. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 743 “Enhanced Digital Filter - EDF”). Changing CDFC during eTPU normal input channel operation is not recommended since it changes the behavior of the transition detection logic while executing its operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 744 Entry Table Base Address for Entry Table Base Address for Host Address Microcode Address 00000 0x000 0x000 00001 0x800 0x200 00010 0x1000 0x400 11110 0xF000 0x3C00 11111 0xF800 0x3E00 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 745: Time Base Registers
Rise or Fall transition on TCRCLK signal increments the TCR2 prescaler. both edges DIV8 clock (system clock / 8) do not use with AM=1 Peripheral Timebase clock source MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 746 Table 23-10. AM - Angle Mode Selection Valu Tooth processing TCR2 Value Tooth signal channel Timebase (EAC operation disabled) not applicable TCRCLK input Angle Ticks channel 1 input channel 2 input MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 747 TCR1 prescaler TCR1 frozen, except as a Red Line client; All other combinations of TCR1CTL and TCR1CS are reserved. This selection must not be used in Angle Mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 748 Bases). This register is read-only. The value of the TCR2 time base shown can be driven by the TCR2 counter, the Angle Mode logic, or imported from Red Line, depending on Angle Mode and Red Line configurations set in registers ETPUTBCR and ETPUREDCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 749 / imported from other device. In eTPU context, a resource can be TCR1 or TCR2 (either Time or Angle values). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 750: Engine Related Registers
This section gathers registers that are engine-related, other than ETPUECR (see Section 23.3.2.5, “ETPUECR - eTPU Engine Configuration Register). 23.3.4.1 ETPUWDTR - eTPU Watchdog Timer Register This register configures the watchdog timer for the engine. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 751 The TST microcycles are also counted by the watchdog. 23.3.4.2 ETPUIDLER - eTPU Idle Register This register counts the microcycles in which the microengine is idle (see Section 23.4.10.4.1, “Idle Counter). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 752: Channel Registers Layout
Engine. Reserved areas are placed to allow doubling the number of channels to 64 for each eTPU Engine. 0x200 Global Channel Registers 0x26C RESERVED 0x400 Engine 1 Channel Registers 0x600 RESERVED 0x800 Engine 2 Channel Registers 0xA00 RESERVED Figure 23-14. Channel Registers Area MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 753: Global Channel Registers
CICx — Channel x Interrupt Clear 1 = clear interrupt status bit. 0 = keep interrupt status bit unaltered. For details about interrupts see Section 23.4.9.3.10, “Channel Interrupt and Data Transfer Requests. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 754 DTRCx — Channel x Data Transfer Request Clear 1 = clear status bit. 0 = keep status bit unaltered For details about interrupts see Section 23.4.9.3.10, “Channel Interrupt and Data Transfer Requests. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 755 CIOCx — Channel x Interrupt Overflow Clear 1 = clear status bit. 0 = keep status bit unaltered. For details about interrupt overflow, see Section 23.4.2.2.2, “Interrupt and Data Transfer Request Overflow. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 756 DTROCx — Channel x Data Transfer Request Overflow Clear 1 = clear status bit. 0 = keep status bit unaltered. For details about data transfer request overflow, see Section 23.4.2.2.2, “Interrupt and Data Transfer Request Overflow. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 757 DTRE DTRE RESET: DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE DTRE RESET: = Unimplemented or Reserved Figure 23-20. ETPUCDTRER Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 758 WDSCx — Channel x Watchdog Status Clear 1 = clear watchdog status bit. 0 = keep watchdog status bit unaltered. For details about Watchdog mechanism, see Section 23.4.1.4, “Watchdog MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 759 The register can be read during normal eTPU operation for monitoring the scheduler activity. NOTE Channel Service Status does not always reflect decoding of the CHAN register, since the later can be changed by the service thread microcode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 760: Channel Configuration And Control Registers
Register Name Offset 0x00 ETPUCxCR - eTPU Channel Configuration Register 0x04 ETPUCxSCR - eTPU Channel Status/Control Register 0x08 ETPUCxHSRR - eTPU Channel Host Service Request Register 0x0C RESERVED MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 761 The base address for the structure presented can be calculated by using the following equation: Channel_Register_Base = ETPU_Engine_Channel_Base + (channel_number * 0x10) where: ETPU_Engine_Channel_Base = ETPU_Base + 0x400 for Engine 1 ETPU_Engine_Channel_Base = ETPU_Base + 0x800 for Engine 2 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 762 CPR[1:0] — Channel Priority This field defines the priority level for the channel, used by the Hardware Scheduler (See Section 23.4.3, “Scheduler”). Table 23-15. Priority level Bits Priority Disabled Middle MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 763 Organization). As seen by the Host, the channel parameter base (byte) address is: without parameter sign extension: ETPU_Base + 0x8000 + CPBA*8 with parameter sign extension: ETPU_Base + 0xC000 + CPBA*8 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 764 These bits are mirrored in ETPUCIOSR - see Section 23.3.6.3, “ETPUCIOSR - eTPU Channel Interrupt Overflow Status Register). See also Section 23.4.2.2.2, “Interrupt and Data Transfer Request Overflow. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 765 ETPUCxHSRR - eTPU Channel x Host Service Request Register ETPUCxHSRR is used by the Host to issue service requests to the channel. These bits are equivalent to the TPU/TPU2/TPU3 Host Sequence (HSQ) bits. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 766: Functional Description
There is one HSR register field for each Channel • Each signal is associated with only one Channel, which has its own Match registers and independent mode configuration. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 767 Once the Scheduler chooses a channel among pending Service Requests, the Entry Point is taken from an Entry Table, based on the Function assigned for the channel and other conditions. Entry Table layout is shown in Figure 23-27. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 768 ETPUECR register field ETB. Note that the Engines can use different Entry Tables, with or without the same set of Functions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 769 Columns Host Request Bits, Link Request, Match1/Trans2, and Match2/Trans1 determine the type of event. A non-zero value in these columns represents the recognition of the event, while “x” indicates that MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 770 When HSR is 0, i.e., Host did not issue a Service Request to the channel, the other event conditions, the input signal state and channel flags determine the Entry Point. Note that channel flag 1 does not influence the encoding in this scheme. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 771 Channel Condition Request Request Trans.2 Trans.1 Pin State Flag1 Flag0 s [C4-C0] Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 772 The remaining Entry Points use both channel flags for better state decoding, making this scheme better suited for Functions which need more states and/or faster state decoding, without needing many HSRs. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 773 Condition Request Request Trans.2 Trans.1 Pin State Flag1 Flag0 s [C4-C0] Bits 00000 00001 00010 00011 00100 10x/001 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 774 Entry Point information includes a Preload-Parameter selection field, a Match Enable field, and the first microcode address of the thread. The Entry Point format is illustrated in Figure 23-29. MICROCODE ADDRESS Figure 23-29. Entry Point Format MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 775 TDL1/2, MRL1/2, LSR, FM[1], FM[0], and PSS). The branch conditions are coherent with the timebase capture values sampled into ERT1/2 (if MRL1/2, TDL1/2 are set at the same time MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 776 Registers B, C, D and SR are not altered by TST and keep their values from the previous thread. The values of registers A, MACL and MACH are not guaranteed at the thread start. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 777 Y 3rd Inst μINST Y 2nd Inst SPRAM Wait X END TST1 TST2 TST3 Y 1st Inst Y 2nd Inst Y 3rd Inst Figure 23-30. TST Timing - No Wait-states MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 778 Y1st Inst Addr μINST Entry Point Y 1st Inst SPRAM Wait X END TST1 TST3 Y 1st Inst TST1 wait TST2 Figure 23-31. TST Timing - 1 Wait-State MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 779 Section 23.4.9.4.1, “Ending Current Thread - END”). • a forced END by host writing to the ETPUECR bit FEND (see Section 23.3.2.5, “ETPUECR - eTPU Engine Configuration Register”). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 780 Watchdog must not be enabled when the microengine enters halt mode. The counter does not run when the engine is stopped, and resets when the watchdog is disabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 781: Host Interface
An SCM signature mismatch detected by the Multiple Input Signature Calculator - MISC. See Section 23.4.10.3.1, “SCM Test - Multiple Input Signature Calculator. This source is flagged by the bit SCMMISF in register ETPUMCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 782 In 32-bit access, Host can access all 32 bits or only the lower 24 bits with an automatic sign extension (see Section 23.4.2.3.4, “Parameter Sign Extension Area). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 783 Besides channel parameters, global areas may have to be allocated for parameters that are shared by more than one channel, in one or both Engines. Also, temporary parameter areas should be reserved to be used MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 784 Single-engine eTPU or dual eTPU system may require less parameters than the maximum number provided by the SPRAM. Since the SPRAM partition is fully dynamic, there is no limitation of fixed channel addresses, and the reduced array can be fully utilized. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 785 Both Engines must be stopped or halted to set VIS=1. Only 32-bit aligned writes are allowed to SCM from the Host. Write accesses of other sizes store unpredictable values into SCM. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 786 Section 23.4.9.7, “Microinstruction Formats MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 787: Scheduler
1. grant bits are also cleared in the next clock, when the service channel is chosen, or when the microengine is idle, using the same scheme. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 788 If the Scheduler was not reset to time slot one and two channels requested service at the same time, one with high priority and the other with low priority, the channel to be serviced would be the low-priority channel. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 789 Middle High → → High Middle When priority is passed to another level, that level is serviced and the fixed-priority-level sequence is resumed with the next time slot. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 790 “ETPUECR - eTPU Engine Configuration Register”), which disables the priority passing mechanism. When priority passing is disabled, at the end of the thread the slot number is incremented until a time slot MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 791 Unlike what happened with priority passing, the next serviced is the high priority channel, as the time slot increments to 3. The second middle priority channel request in cycle D is finally serviced next, on time slot 5. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 792 3. The Scheduler resumes with the fixed-priority sequence on time slot three; however, no channels are requesting service. The Scheduler returns to time slot one, waiting for requests. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 793 Each time slot may require a different number of microcycles, depending on the thread of a Function to be executed. This variation is shown in Figure 23-37. For more details on latency evaluation, see Section 23.5.5, “Estimating Worst Case Latency.” MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 794: Parameter Sharing And Coherency
Access” and Section 23.4.4.2, “Microengine Side Atomic Accesses.” a microengine access to the SPRAM in the moment CDC is performing the transfer may suffer a maximum of two wait-states. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 795 Engine, since a thread cannot be suspended (preempted). For 1 parameter coherent access, or dual parameter coherency between only one Microengine and Host, the alternatives shown in previous sections apply. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 796 The maximum number of Host wait states on CDC occurs when both microengines overlap their TSTs, delayed 3 system clocks from each other. One microcycle takes two system clocks. Microengines get wait-states in multiples of microcycles, while Host and CDC wait-states are multiples of system clocks. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 797 SPRAM in the following microcycles, the third and fourth consecutive accesses are considered the first and second of a new back-to-back dual access. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 798: Enhanced Channels
The Capture The microengine access slot is between its own T4 and T2 edges (see Section 23.6.1, “Microcycle and I/O Timing)). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 799 Every time the CHAN register is written, even if with the same previous value, a channel is selected and its flags and registers are updated. For further detail, see Section , “Channel Selection Register - CHAN. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 800 Enhanced Digital Filter, which eliminates spurious glitches on input pin signal. Output Buffer Enable is meant to control output MCU pad signal driver. A high level diagram of Channel logic and registers is shown in Figure 23-39. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 801 = Channel 0 only PSTO Synchr. Output Buffer Enable Synchr. Output Signal ipp_obe_etpuch channel output Input Signal Input Signal TCRCLK channel input Figure 23-39. Channel Logic Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 802 Each Event Register set contains: • a 24-bit Match register (Match1 or Match2), which holds a match value. This value is compared against the selected match time base (TCR1 or TCR2). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 803 Entry Point which, in turn, is determined partially by the channel latches. See Section 23.4.1.1.2, “Entry Point Address Generation.” MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 804 TBS1/2 are 3-bit registers which have the following effect on channel configuration: • Selection of the timebase (TCR1 or TCR2) to be compared against the match values in Match1 and/or Match2 registers. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 805 OPAC1, OPAC2 000,000 PSTI flag test on branch PSTO flag test on branch, write immediate BCC (test) PSC, PSCS (set) write only immediate TBS1 values 1000,1001 (negated) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 806 Match1 and/or Match2 events. The PSTO register stores the driven pin state determined by the Pin Control logic. The Output Buffer Enable signal, if used at MCU integration, MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 807 Threads). When the channel logic issues a service request, the filtered input signal PSTI is sampled into an internal channel flag PRSS. There is one such PRSS flag for each The filter can be bypassed. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 808 TBS1[2:0] TBS1[3]=1 enable output buffer disable output buffer do nothing other values reserved Output Buffer Enable: there is one independent OBE signal for each channel. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 809 23.4.5.1.3 General Channel Registers These registers control other aspects of channel logic. Except for CHAN, they are unique per channel. Table 23-27 summarizes the registers and access options. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 810 MRL1/2 and TDL1/2 flags. Table 23-28 shows the commands, flags and registers selected by the CHAN register value Table 23-28. CHAN-selected features Selected by Feature Used CHAN channel-relative SPRAM access MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 811 PDCM is also used to select the User Programmable Channel Mode. If this selection is made, the channel behavior is defined by the settings of the UDCM register (see Section , “UDCM - User Defined Channel Mode). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 812 Link Service Requests or Host Service Requests, neither MRL1/2 or TDL1/2 microcode branch tests nor Entry Table selection . SRI is asserted during reset and is controlled by microcode field MTD. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 813 Section , “IPAC1,IPAC2 and OPAC1,OPAC2 - Input and Output Pin Action Control Registers. In TPU, SRI also blocked TDL and MDL branches and enabled any transition to capture time base. Microcode can also negate MRLE1/2. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 814 (only for IPAC=0xx). Before that, microcode should also negate MRL1 (MRL2), otherwise an old match may be recognized by the scheduler and serviced as a new one MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 815 (reprogrammed) one. In order to prevent this ambiguity to the code that services the match, it is advisable to clear the MRLE (besides MRL) together with the match reprogramming, avoiding the match on the old MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 816 Registers). When using a channel mode where the In TPU3, when TCR1 was counting at maximum rate of system clock divided by 2, the next value was captured. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 817 1.TCCE1 provides compatibility with TPU when service request is inhibited. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 818 Table 23-30. MSR[1:0] signals - Match Service Requests value issue no Service Requests on Matches issue Service Request on Match 2 only issue Service Request on 2nd Match issue Service Request on both Matches MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 819 Match 1 blocks Match 2 M2BM1 Match 1 is initially enabled, (Match 2 Blocks Match 1) and Match 2 blocks Match 1 M2BT Match 2 blocks Transitions (Match 2 Blocks Transition) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 820 Section , “Both Match Request Modes (bm_st, bm_dt) Section , “Single Match Modes (sm_st, sm_dt). sm_st_e is an exception in the capture scheme. See Section , “Single Match Enhanced Mode (sm_st_e). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 821 (channels 1, 2 only) MSR[1] Tooth Detection MSR[1] (see figure 59) MSR[0] Match1 SR Trans1 SR Trans2 SR Match2 SR Figure 23-42. Channel Mode Logic and Event Flags MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 822 If both match recognitions occur at the same time, both MRL1 and MRL2 are set, before the mutual blocking takes effect. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 823 In these modes both match recognitions are independent and each of them generates service request. Each match recognition captures its related time base and does not block the other. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 824 Match1 recognition. Each match recognition captures its own programmed timebase. In case of simultaneous match recognition, both MRL1 and MRL2 are set, and OPAC2 register has priority over OPAC1 for selecting the pin action. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 825 Unlike other double transition modes, bm_dt blocks Match1 with Transition 2 (not with Transition 1), so that the second transition blocks both matches. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 826 These are ordered match modes on which Match1 recognition must precede Match2 recognition (ordered 1->2). Match1 asserts MRL1 and enables Match2 and transitions. Match2 asserts MRL2, generates a match service request, and blocks both transitions. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 827 Figure 23-47. Ordered Modes with Match2 Request (m2_o_st, m2_o_dt) Single Match Modes (sm_st, sm_dt) Single match modes support single or double transition with single match recognition. MRL2 is never set, and MRLE2 has no effect. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 828 In an output channel, it has the same functionality of sm_st (captures both time bases at once due to a match recognition). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 829 Single Transition, Single Match: em_b_st, sm_st, sm_st_e • Single Transition, Double Match: em_nb_st, bm_st, m2_st, m2_o_st • Double Transition, Single Match: em_b_dt, sm_dt • Double Transition, Double Match: em_nb_dt, bm_dt, m2_dt, m2_o_dt MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 830 TDL1 and writing to the CHAN register its own value (in order to update the MRL1 flag in the branch logic). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 831 It is similar to m2_st, but in this case, it is the second transition that blocks match2. MRL2 assertion is a global timeout condition for the two pulses. Like m2_st, MRL2 can conditionally eliminate the window from opening. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 832 TDL1 and TDL2. MRL2 assertion captures its related timebase and disables the assertion of both TDL1 and TDL2. Transitions can be MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 833 In this mode, the first transition detection asserts TDL1, captures a timebase in Capture1 and enables TDL2. The second signal transition asserts TDL2, blocks Match1, captures a timebase in Capture2 and generates a service request. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 834 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 835 Match1 recognition generates service request and sets the pin state according to OPAC1 register. It captures at once the timebase selected by TBS1 in Capture1 and the timebase selected by TBS2 in Capture2. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 836 Match 1 opens a window for transitions and also enables Match 2. A rising edge on input sets output high. On Match 2 the window closes, and input signal is checked: if sampled high, the output resets; otherwise it stays high. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 837 Transition detection. Depending on the Channel Mode, these Match and Transition may have conflicting effects on other Transition/Match blocking or enabling. In these cases, blocking always prevails over enabling, effective on the next microcycle. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 838 IPAC2 := 000; OPAC2 := 001; Match2 := window close time = Match1 + pulse width; PDCM := em_nb_dt; enables Match 1 Match 2 Input signal Output signal Figure 23-50. Input/Output combination MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 839 SPRAM parameters. All links are negated on reset. That can only happen if the link service request came from the other Engine or from the serviced channel itself. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 840 Continuous mode may reject a real signal transition and delay the response to the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 841 Section 23.3.3.1, “ETPUTBCR - eTPU Time Base Configuration Register), the TCRCLK filter will be clocked as if FCSS=0. always dividing system clock /2 using FPSCK, regardless if FCSS is 0 or 1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 842: Time Bases
TCR1CTL bit, as shown in Figure 23-52. For more information on clock source selection, please refer to Section 23.3.3.1, “ETPUTBCR - eTPU Time Base Configuration Register.” MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 843 The TCR2 is a 24-bit counter which can be used in the following modes: • Pin Transition Mode: Count the rise, fall or both transitions of TCRCLK signal. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 844 EAC and Channel 0. The TCRCLK synchronizer is an improved filter that provides best latency while maintaining proper noise filtering (see Section 23.3.3.1, MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 845 When system clock divided by two is selected, the synchronizer and the digital filter are guaranteed to pass pulses that are wider than four system clocks (two filter clocks). Otherwise the TCRCLK is filtered with MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 846 The eTPU Angle Counter (EAC) logic runs continuously and updates the TCR2 Angle counter, eliminating the microcode latency in updating the TCR2 value. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 847 Red Line Controller, and there may be a client linked to that server by the ETPUREDCR bits SRV1/2 on each Engine. When the server address on the Red Line bus matches the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 848 = 0. Microcode can always write to TCR1/2 registers, with either value of etpu_gtbe_in. NOTE The timebase prescalers are reset when the GTBE input is negated. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 849: Eac - Etpu Angle Counter
(depending on the ETPUTBCR field AM) to generate angle information on the TCR2 bus which is passed to all the local engine channels. The EAC helps to implement a digital angle PLL (see Table 23-58), which MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 850 When eTPU is not in angle mode (AM bit is negated in ETPUTBCR register), all angle mode registers can be used as general purpose registers. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 851 Decremented on each estimated tooth, stops at zero. Used for generation of “Dummy Tooth” whenever it holds a non-zero value (see Table 23-40). Table 23-40. MISSCNT Values Value Meaning no Missing Tooth One Missing Tooth Two Missing Teeth Three Missing Teeth MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 852 Section 23.4.7.12, “Special TPR Write Cases”. NOTE Bits LAST, IPH and HOLD must not be asserted all at once. missing a physical tooth naturally causes EAC to get into Halt mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 853 Section 23.4.7.4.1, “Calculating the Angle Tick Period Integer and Fraction for a complete description about the mechanism to calculate the value to be written into this register. INTEGER[14:7] RESET: INTEGER[6:0] FRACTION RESET: Figure 23-57. TRR Register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 854 TCR1<estimated tooth time TCR1>estimated tooth time PHYSICAL TOOTH HIGH RATE MODE HALT MODE N TICKS TCR1>estimated tooth time --> DECELERATION TCR1<estimated tooth time --> ACCELERATION Figure 23-58. EAC “PLL” MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 855 Count Contol & High Rate Logic Dummy Tooth Count TCR2 Reset Last Tooth Angle Mode TCR2 Time Base AM (ETPUTBCR) Angle Counter Logic Figure 23-59. eTPU Angle Counter System MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 856 0 up to TICKS, is controlled by the Angle Tick Generator logic and cannot be accessed by microcode. Refer to Figure 23-60 for a generic presentation of the angle tick count and the measurement of a single tooth period. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 857 The tooth period (TCR1ToothPeriod) is not, in general, the value of estimated tooth time. It is obtained by microcode by subtracting TCR1 values between two teeth detections. Its comparison with the estimated tooth time indicates acceleration (if minor) or deceleration (if greater) to the microcode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 858 High Rate mode angle tick. The fraction accumulator resets when the tick count advances to the next tooth, or when TRR is written by the microcode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 859 EAC switches to the proper mode. See Figure 23-61 for a detailed diagram of Normal Mode behavior. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 860 On low RPM microcode service latency takes little percentage of the tooth period, but there may be cases of extreme acceleration and deceleration. The microcode latency can be calculated MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 861 Rate Mode does not alter the immediate EAC state, but it is still detected by the EAC channel logic and can, therefore, alter future EAC behavior (for instance, closing the tooth detection window - see Section 23.4.7.10, “Angle Logic and Channel Modes). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 862 This delay can be obtained by the effect of microcode writes to fields HOLD and IPH is immediate in High Rate mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 863 “dummy” tooth, the Angle Tick Counter is incremented as if there was a physical tooth. A “dummy” tooth can be inserted only during Normal or High Rate operation modes. The microcode inserts “dummy” teeth by writing to the MISSCNT field in TPR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 864 (either the missing teeth are both last in an engine cycle or both not last, but not last in one engine cycle and first in the next). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 865 EAC sees the remaining portion of the current tooth period as another tooth period. The microcode can detect the situation when the acceleration in not realistic, or MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 866 Angle logic is disabled. The Angle Logic state-machine resets to Normal mode and the tick prescaler to the initial count by AM=00, but not the microengine registers TPR and TRR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 867 Because of different results depending on the EAC mode at the time of TPR write, it is not advisable to write 1 to IPH and change TICKS at the same microinstruction. A consistent behavior is obtained if IPH MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 868: Microengine
Latency is worsened when channels from a same eTPU engine contend for microengine service. Figure 23-65 a block diagram of microengine architecture is shown. Follows a summary of Microengine features: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 869 • MDU (MAC/Divide Unit) performs integer MAC, multiply and divide operations. • Fixed Microinstruction Size of 32bits. • Fixed-length instruction execution (2 system clocks) • Static superscalar operation MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 870 ERT1 to Branch Logic Channels + TCRs ERT2 MRL1, MRL2, TDL1, TDL2, PSTI, PSTO TCR1 to Branch Logic Microengine’s DataPath TCR2 eTPU CHANNELS Figure 23-65. Microengine Block Diagram MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 871 Mode”). DIOB is automatically loaded with one parameter before the thread starts (parameter preload). For more information see Section 23.4.1.1.5, “Entry Point Format Section 23.4.1.2, “Time Slot Transition. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 872 CHAN is a 5-bit register that can be used as source and destination in arithmetic operations. The contents of CHAN register affects the execution of many channel-related microinstructions, because its number MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 873 ALU operations: Overflow is updated only on addition and absolute value operations, Carry flag is updated in most ALU operations, and only Zero and Negative are updated in all ALU operations. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 874 Overflow flag behavior for addition is defined in Table 23-42. Overflow flag for Absolute operation is explained in Section 23.4.8.2.8, “Absolute Value MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 875 AS + BS AS + BS + 1 AS - BS AS - BS - 1 ALU operations only occur on formats where a destination field is found (T2ABD/T2D). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 876 8 bits rotate right adder carry from bit 7 to bit 8 16 bits rotate right adder carry from bit 15 to bit 16 24 bits rotate right alu_adder_output[24] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 877 Table 23-47. Types of Bitwise Operations ALUOP BINV Operation 10000 AS | BS 10000 AS | (~BS) 10001 AS ^ BS 10001 AS ^ (~BS) 10010 AS & BS 10010 AS & (~BS) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 878 = AS[31 - BS[4:0]] if C_flag == 1 result = AS | (1 << (31 - BS[4:0])) else result = AS & ~(1 << (31 - BS[4:0])) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 879 C-flag. Note that if AS is 8-bit or 16-bit, its sign is taken into account and copied to C only if sign-extension is performed. Table 23-50 summarizes flag updating for Absolute Value operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 880 AS mdu_op BS AS mdu_op (-BS) reserved reserved There is no distinct selection of 24-bit fractional multiplication, for it works exactly as a 24-bit ordinary multiplication. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 881 (signed) MACH,MACL = (signed) AS * (signed) BS MC and MV flags are reset. MZ is set if result is 0, resets otherwise. MN is set if result is negative. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 882 Only A-Source is taken as a signed number. The value of B-Source is considered the unsigned numerator of a fraction with denominator 2 or 2 for the 8- and 16-bit operations, respectively. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 883 MN flag is always a copy of MACH bit 23 at the end of the operation, either in signed or unsigned ones. Note that MACH holds the rest of a division operation, which is always unsigned. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 884 Serviced channel does not change during execution of a thread, and it is the channel that requested a service (initial value of CHAN register when a thread starts). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 885: Microinstruction Set
Section 23.4.9.7, “Microinstruction Formats.” Parallelism conflicts may arise when two operations are executed in the same microinstruction. These situations are explained in Section 23.4.9.6, “Microinstruction Parallelism Issues”. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 886 Since the SPRAM word address is shifted two bits up in DIOB, its contents hold the same parameter address value used by Host. The equation is: physical_address = DIOB[13:2], or physical_address = (truncated) DIOB / 4 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 887 When performing a Zero SPRAM write operation (see Section 23.4.9.1.5, “Zero SPRAM Operation”), RSIZ defines the size of operation regardless of the P/D field (Section 23.4.9.1.2, “SPRAM Source/Destination Registers”). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 888 15 downto 2, i.e.: the bits 23 to 16 and 1 to 0 are left untouched by STC pre-decrement and post-increment. Table 23-57. DIOB Post-Increment / Pre-Decrement - STC Meaning Post-Increment of DIOB MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 889 In formats without ABSE/ABDE, the field T4BBS determines the register sets used by T2ABD and T4ABS, as shown in Section , “Microinstructions Without Fields ABSE and ABDE.” MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 890 (e.g., CHAN[4:0] is an 8-bit source). See Section 23.4.9.2.3, “Flags Sampling Control for more information. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 891 AS[23:0] = A[23:0] AS[4:0]=CHAN[4:0] 1010 AS[23:0] = SR[23:0] AS[14:2] = CHAN_BASE 1011 AS[23:0] = DIOB[23:0] AS[13:0] = ENGINE_BASE 1100 AS[23:0] = TCR1[23:0] Reserved 1101 AS[23:0] = TCR2[23:0] Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 892 T2ABD=0011 with first register set also writes to Match2 register of the selected channel if field ERW2=0. if no destination is selected, ALU flags are updated, although the result is lost. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 893 16 bits 16 bits 8 or 16 bits 24 bits 16 bits 8 or 16 bits 16 bits 24 bits 16 bits 24 bits 24 bits 24 bits MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 894 BINV (1 bit, Table 23-67). A zero value for BINV activates B-source inversion. Table 23-67. B-Source Inversion - BINV BINV Meaning invert B-source MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 895 SR can be used as a general purpose register and it can easily shift-right its contents, combined or not to post-ALU shift operations. If field SRC (1 bit) in microcode is 0, SR will shift its contents 1 bit to the right MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 896 Carry flag is only updated when CCS or CCSV[1:0] fields allow it (see Section 23.4.9.2.3, “Flags Sampling Control”). Algorithmic descriptions of post-ALU shift operations are presented in Section 23.4.8.2.2, “ALU ADD Operation with and without shifting”. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 897 Meaning A-source size override to 8 bits A-source size override to 16 bits used for conditional execution (see Section 23.4.9.2.7, “Conditional ALU/MDU Operation Execution) execute unconditionally/no size override MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 898 The ALU operations are defined in Section 23.4.8.2, “ALU and Post-ALU Shifter”. The MDU operations are defined in Section 23.4.8.3, “MAC and Divide Unit (MDU)”. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 899 Addition/Subtraction is selected by field BINV (see Section 23.4.9.2.4, “B-Source Inversion”) In setb and clrb operations, the register that drives A source is not changed, unless selected as destination of the operation. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 900 = AS[23:8] 01011 AD[7:0] = AS[7:0] & #imm8, AD[23:8] bitwise AND with clear = 0x0 01100 AD[15:8] = AS[15:8] | #imm8, bitwise OR AD[23:16] = AS[23:16], AD[7:0] = AS[7:0] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 901 Each channel has two associated hardware flags, called Channel Flag 0 and Channel Flag 1. Microcode field FLC (3 bits) allows them to be set or cleared, as shown in Table 23-78. These flags can be tested by MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 902 Table 23-80. Time Base Selection 2 - TBS2 TBS2 bit Comparator Capture Match TB bitfield selection selection selection TBS2[3] = 0 greater or TCR1 TCR1 equal equal-only TCR2 TCR2 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 903 OPAC1 (see Section 23.4.9.3.3, “Transition Detection and Pin Action Control”) set signal as specified by OPAC2 (see Section 23.4.9.3.3, “Transition Detection and Pin Action Control”) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 904 Table 23-85 defines the two-bit TDL field. Table 23-84. Clear Transition/Match Event Registers - MRL1/2, TDL Field Meaning MRL1 0 = clear MRL1 event register, 1 = don’t change MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 905 Link Service Request and Host Service Request. MTD sets or resets registesr SRI (for more details see Section , “SRI - Match/Transition Service Request Inhibit Latch) and TCCE1 (see Section 23.4.5.3.2, “TCCE1 - Transition Continous Capture Enable). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 906 23.4.9.3.10 Channel Interrupt and Data Transfer Requests Microcode can issue Interrupt Requests, Data Transfer Requests and Global Exception through CIRC field. For more information see Section 23.4.2.2, “Interrupts and Data Transfer Requests. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 907 Section 23.4.8.3, “MAC and Divide Unit (MDU)) that could be still pending when the thread is finished is left incomplete. END also releases any semaphore locked by the Engine. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 908 Z ALU flag 110011 “Lower or Equal” ALU flag combination (unsigned) 100100 MV MDU flag 110100 P[24] 100101 MN MDU flag 110101 P[25] 100110 MC MDU flag 110110 P[26] MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 909 Section 23.4.9.4.5, “Flush Pipeline”) when field R/D is used. Return execution through RTN always flushes the pipeline. Table 23-96. Return from Sub-routine - RTN Meaning return with pipeline flush MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 910 / call / dispatch jump / dispatch call / return is executed do not flush pipeline when jump / call / dispatch jump / dispatch call / return is executed MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 911 HALT case. If the microengine decodes an illegal instruction, the following actions are taken: MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 912 Table 23-98. DIOB load from SPRAM and ALU DIOB selected as DIOB selected as DIOB load value SPRAM read destination? ALU destination? DIOB, --DIOB (pre-decrement), or DIOB++ (post-increment) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 913 If ERT1/2 is the destination of an ALU operation at the same instruction, Match1/2 gets the ALU result (see Section 23.4.9.6.3, “ERT1/2 as ALU destination and ERW1/2), but the ERT1/2 not being written still receives the old Match1/2 values. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 914 CHAN. When a pin action is commanded through PCS/PSCS and a CHAN assignment is done simultaneously, the output signal affected is selected with the old CHAN value. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 915 23.4.9.7 Microinstruction Formats Table 23-99. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 916 Table 23-99. Microinstruction Formats format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 IMM[15:13] IMM[7:2] IMM[23:16] IMM[11:9] T4ABS T2ABD CCSV ALUOP AS/CE ALUOP I[3:2] I[1:0] [1:0]...
Page 917: Test And Development Support
Table 23-99. Microinstruction Formats (continued) format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 1 1 BCC[4:0] BAF[13:0] AID[2:0] rsv SMPR format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ALU Operations Channel Control/Config Operations RAM Operations...
Page 918 If all halt conditions are cleared when VIS=1, microengine(s) keep on halt state until VIS=0, when it automatically exits halt state, except on single-step (see Section 23.4.10.2.6, “Single-step Execution), so that single-step execution is ignored while VIS=1. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 919 There are situations when requests for stopping an engine, breakpoint and service can occur simultaneously. Breakpoint requests always prevails over a stop request (ETPUECR bit MDIS=1 or SoC MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 920 Like any other microinstruction, HALT increments the PC and pre-fetches the next instruction. So, before the halt state is suspended, if the original program flow must be followed, the original instruction at the MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 921 Single-step execution is controlled by the debug interface, and is a feature available from Nexus if eTPU is connected to the NDEDI block (see eTPU Integration Guide and NDEDI Block Guide).The MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 922 If the eTPU runs (not single-stepping) after exiting the halted state, the conditions modified during halt may remain only for the first microcycle after the halted state. After the first microcycle, branch conditions are altered only according to their regular update scheme. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 923 Once started by the Host the MISC runs continuously, restarting after the completion of each cycle, when it sets the ETPUMCR register flag SCMMISC (see Section 23.3.2.1, “ETPUMCR - eTPU Module MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 924: Initialization/Application Information
Configuration procedures are summarized as follows: except when SoC debug request is asserted on power-on reset: in this case, the microengines wake-up in halt state. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 925: Reset Options
System Configuration and Global Channel registers assume their reset values. This operation is done before enabling active channels to avoid time events happening before the channel initialization. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 926: Multiple Parameter Coherency Methods
It does not have to be responsible for the transfer, though: it may access the TPA directly, and a Transfer Service can then be used to copy data from TPA to PPA. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 927: Programming Hints And Caveats
Interrupts and DMA requests can still be checked and cleared through the Global Channel Registers, though. DMA requests can also be cleared by the hardware handshaking with the DMA controller when the engine is stopped. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 928: Estimating Worst Case Latency
The worst case time includes the time the execution unit takes to execute threads for other active channels, and other delays described later in this section. Refer to Figure 23-67. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 929 Scheduler determines the order in which the channels are serviced. Worst-case latency for a channel can be derived from the details of the priority scheme that the scheduler uses (see Section 23.4.3, “Scheduler). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 930 (not counting initialization threads), it is safe to say that the worst-case latency shown in Figure 23-68 represents both the worst-case high time and the worst-case low time. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 931 High-priority channels are allocated four of seven time slots, middle-priority channels are allocated two of seven time slots, and low-priority channels are allocated one of seven time slots. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 932 (has a set SRR) and has not been granted service (has a clear SGR). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 933 RAM with or without using the CDC. This percentage gives a good RCR and CPCR. The eTPU application provides a good estimation of CCR. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 934 SGRs. The worst-case latency is the time from the end of the channel’s service until the end of the channel’s next service. See Figure 23-71. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 935 Table 23-101. Longest Threads and RAM Accesses for old TPU Functions Function Longest Thread RAM Accesses 40 (no linking) 42 (linking) SPWM Mode 0 Mode1 Mode 2 20 (no linking) 22 (linking MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 936 The following shows how to find the WCL for PWM on channel 0. 1. Find the worst-case service time for each active channel. Longest thread of PWM is 24 CPU clocks with four RAM accesses. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 937 Channel 0 worst-case service time 25 clocks Channel 1 worst-case service time 46 clocks Two 6-clock time-slot transitions 12 clocks Total clocks 83 clocks 83 clocks * 25 ns/clock = 2075 ns MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 938 Also the function threads would have more efficient coding. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 939 Following is an example of a second-pass analysis for calculating worst-case latency for a channel. The second-pass analysis is useful for higher-performance systems, since it gives a more realistic worst-case latency result than first-pass analysis. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 940 This example requires three 50% PWM waveforms: one 5 kHz (200 ms/period) and two 50 kHz (20 ms/period), each running DC motors. (Remember that the PWM function requests service from the eTPU MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 941 Longest thread of PPWA in mode 0 is 44 CPU clocks with nine RAM accesses. 44 + ((9 RAM accesses +1)* 0 * 2 CPU clock waits) = 44 CPU clocks MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 942 CPU clock rate = 40 MHz, or 60 ns per clock period To find the WCL for channel 0, assume channel 0 has just finished service. Map the channels in the H-M-H-L-H-M-H sequence. See Figure 23-76. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 943 PWM at 5 kHz (needs a 40-μs WCL) PPWA at 5 kHz (needs a 80-μs WCL) DIO as input at rate of 1 ms 0% RAM collision rate MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 944: Endianness
For timings of eTPU block internal interface signals, consult the eTPU Integration Guide. For timings internal to the eTPU, refer to the eTPU Creation Guide. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 945 Pin Execution Pin Action Updated Pin Value due uInstr Note: TCR clock/prescaler selection = 2 x system clock Figure 23-78. Execution and Channel Timing, TCR1CS=0 MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 946 That is, no operation occurs during these states. Both T2 and T4 states occur in multiples of two system clocks to keep the microengine synchronized with the free running channels. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 947 Figure 23-80 Figure 23-81 shows the timing of T2 and T4 timing states, respectively. WAIT-T2 T CLOCKS SYS.CLOCK μPC μINST (A0) (A1) (A1) Figure 23-80. T2 timing MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 948 The channel output flip-flops drive the eTPU output signals directly, without any synchronous delays. Consult the MCU SoC Guide or Reference Manual for information on additional delays added at the integration. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 949: Initialization Code Example
#define ETPUTBCR_1 (*((volatile unsigned int*)(ETPUTBCR_1_OFFSET + ETPU_BASE))) #define ETPUECR_1 (*((volatile unsigned int*)(ETPUECR_1_OFFSET + ETPU_BASE))) #define ETPUCIER_1 (*((volatile unsigned int*)(ETPUCIER_1_OFFSET + ETPU_BASE))) #define ETPUCDTRER_1 (*((volatile unsigned int*)(ETPUCDTRER_1_OFFSET + ETPU_BASE))) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 950 0x00010000 //System clock/4 //ETPUCxCR fields - Channelx Configuration Register #define CHANNEL_INT_ENABLE 0x80000000 //Channel Interrupt enable #define CHANNEL_DATA_TRANSF_REQ_ENABLE 0x40000000 //Channel data transfer req. enable #define CHANNEL_PRIORITY_DISABLE 0x00000000 //Channel disable MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 951 ETPUC0CR_1 =(ETPUC0CR_1 | CHANNEL_PRIORITY_HIGH); ETPUC1CR_1 =(ETPUC1CR_1 | CHANNEL_PRIORITY_HIGH); //Monitor channel host service request register for completion //of initialization //HSR should be zero in the end of initialization temp = ETPUC0HSRR_1; MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 952: Predefined Channel Mode Summary
TDL1, the matches become enabled again, and from this point on the channel behaves as if the first transition had never occurred. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 953 Table 23-110. Predefined Channel Mode Summary 1st event 2nd event 3rd event 4th event initially Mode [blocks] [blocks] [blocks] [blocks] blocked event type Capt. event type Capt. event type Capt. event type Capt. (enables (enables) (enables) (enables) em_nb_st none match 1/2 none match 2/1 none...
Page 954 Table 23-110. Predefined Channel Mode Summary (continued) 1st event 2nd event 3rd event 4th event initially Mode [blocks] [blocks] [blocks] [blocks] blocked event type Capt. event type Capt. event type Capt. event type Capt. (enables (enables) (enables) (enables) m2_st trans 1 match 1 (trans 1) match 2...
Page 955: Misc Algorithm
The value calculated by this algorithm must be loaded into register ETPUMISCCMPR prior to activating the SCM MISC calculator in eTPU. Once the MISC calculator is activated (bit SCMMISEN in register MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 956 MISC hardware is optimized to read 32-bit words from memory and to calculate this CRC in parallel, rather than shifting one bit at a time. The actual implementation inside eTPU, although bringing to the same results, does not match exactly the algorithm shown here. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 957: Information Specific To This Device
SDO functions are selected will result in an undefined conversion result. As this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the AN[0:11,16:39] analog input pins. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 958: Introduction
CFIFOs and RFIFOs, and accordingly generates DMA or interrupt requests to control data movement between the FIFOs and the system memory, which is external to the EQADC. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 959: Block Diagram
EQADC Parallel Side Interface (EQADC PSI) which allows communication with on-chip eQADC companion modules. There are 6 CFIFOs and 6 RFIFOs, each with 4 entries. Companion modules can be DSP modules or any other processing block. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 960: Features
DMAC. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 961 — Generates interrupt when command coherency is not achieved • External Hardware Triggers — Supports rising edge, falling edge, high level and low level triggers — Supports configurable digital filter MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 962: Modes Of Operation
Streaming mode requires 2 trigger inputs. The standard queue 0 trigger, in this mode referred to as ‘Repeat Trigger’ and a second internal trigger input to the eQADC called ‘Advance’ trigger. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 963: Debug Mode
The CFIFO status bits will still be updated after the completion of the serial transmission, therefore, after debug mode entry request is detected, the EQADC status bits will only stop changing several system clock cycles after the on-going serial transmission completes. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 964: Stop Mode
CFIFO. The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after stop mode is exited. • Command transfer is in progress MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 965: Factory Test Mode
Differential analog input positive terminal AN1/DAN0- Input Single-ended analog input / Analog Differential analog input negative terminal AN2/DAN1+ Input Single-ended analog input / Analog Differential analog input positive terminal MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 966 Single-ended analog input Analog AN21 Input Single-ended analog input Analog AN22 Input Single-ended analog input Analog AN23 Input Single-ended analog input Analog AN24 Input Single-ended analog input Analog MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 967 Input External trigger for CFIFO2 Digital ETRIG3 Input External trigger for CFIFO3 Digital ETRIG4 Input External trigger for CFIFO4 Digital ETRIG5 Input External trigger for CFIFO5 Digital VREF=VRH-VRL MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 968: Detailed Signal Descriptions
AN6/DAN3+ — Single-ended analog input/Differential analog input positive terminal AN6 is a single-ended analog input to the two on-chip ADCs. DAN3+ is the positive terminal of the differential analog input DAN3 (DAN3+ - DAN3-). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 969 24.4.2.14 AN13/T25PVREF — Single-ended analog input/ Test 25% VREF analog output AN13 is a single-ended analog input to the two on-chip ADCs. T25PVREF is used during ADC factory test. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 970 24.4.2.24 VRH, VRL — Voltage reference high and voltage reference low VRH and VRL are voltage references for the ADCs. VRH is the highest voltage reference, while VRL is the lowest voltage reference. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 971: Memory Map/Register Definition
EQADC Result FIFO Pop Register 3 (EQADC_RFPR3) Read only EQADC_BASE+0x040 EQADC Result FIFO Pop Register 4 (EQADC_RFPR4) Read only EQADC_BASE+0x044 EQADC Result FIFO Pop Register 5 (EQADC_RFPR5) Read only MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 972 EQADC_BASE+0x140 - EQADC CFIFO1 Registers (EQADC_CF1Rw) (w=0, .., 3) Read only EQADC_BASE+0x14C EQADC_BASE+0x150 - Reserved EQADC_BASE+0x17C EQADC_BASE+0x180 - EQADC CFIFO2 Registers (EQADC_CF2Rw) (w=0, .., 3) Read only EQADC_BASE+0x18C MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 973: Eqadc Register Descriptions
The EQADC Module Configuration Register (EQADC_MCR) contains bits used to control how the EQADC responds to a debug mode entry request, and to enable the EQADC SSI interface. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 974 Meaning 0b00 Do not enter debug mode. 0b01 Reserved 0b10 Enter debug mode. If the EQADC SSI is enabled, FCK stops while the EQADC is in debug mode. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 975 The EQADC Null Message Send Format Register (EQADC_NMSFR) defines the format of the null message sent to the external device. Register address: EQADC_BASE+0x008 RESET: RESET: = Unimplemented or Reserved Figure 24-4. EQADC Null Message Send Format Register (EQADC_NMSFR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 976 Register address: EQADC_BASE+0x00C RESET: RESET: Figure 24-5. EQADC External Trigger Digital Filter Register (EQADC_ETDFR) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 977 CQueues. Refer to Section 24.6.4, “EQADC Command FIFOs for more information on the CFIFOs and to Section 24.6.2.3, “Message Format in EQADC for a description on command message formats. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 978 24.5.2.6 EQADC Result FIFO Pop Registers (EQADC_RFPR) The EQADC Result FIFO Pop Registers (EQADC_RFPR) provide a mechanism to retrieve data from RFIFOs. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 979 CFIFO operation mode and can invalidate all of the CFIFO contents. Register address: EQADC_BASE+0x050 MODE0 AMODE0 CFIN RESET: MODE1 CFIN RESET: = Unimplemented or Reserved Figure 24-8. EQADC CFIFO Control Register 0 (EQADC_CFCR0) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 980 FIFO. For more details, refer to Section 24.6.4.2, “CFIFO0 Streaming Mode Description. 1 = Enable the streaming mode of CFIFO0. 0 = Streaming mode of CFIFO0 is disabled. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 981 High Level Gated External Trigger, Single Scan 0b0100 Falling Edge External Trigger, Single Scan 0b0101 Rising Edge External Trigger, Single Scan 0b0110 Falling or Rising Edge External Trigger, Single Scan 0b0111 - 0b1000 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 982 The EQADC Interrupt Control Registers (EQADC_IDCR) contain bits to enable the generation of interrupt or DMA requests when the corresponding flag bits are set in Section 24.5.2.9, “EQADC FIFO and Interrupt Status Registers (EQADC_FISR). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 983 NCIEx enables the EQADC to generate an interrupt request when the corresponding NCFx in Section 24.5.2.9, “EQADC FIFO and Interrupt Status Registers (EQADC_FISR) is asserted. 1 = Enable non-coherency interrupt request. 0 = Disable non-coherency interrupt request. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 984 Section 24.5.2.9, “EQADC FIFO and Interrupt Status Registers (EQADC_FISR) is asserted. 1 = Enable CFIFO Fill DMA or Interrupt request. 0 = Disable CFIFO Fill DMA or Interrupt request. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 985 1 = Generate DMA request to move data from RFIFOx to the system memory. 0 = Generate interrupt request to move data from RFIFOx to the system memory. NOTE: RFDSx must not be negated while a DMA transaction is in progress. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 986 18 flags becomes asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See Section 24.6.8, “EQADC DMA/Interrupt Request for details. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 987 When the EQADC completes the transfer of an entry with an asserted EOQ bit from CFIFOx, EOQFx will be set. The transfer of entries bound for the on-chip ADCs is MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 988 Writing to SSSx has no effect. SSSx has no effect in continuous-scan or in disabled mode. 1 = CFIFO in single-scan level- or edge-trigger mode will detect a trigger event, or CFIFO in single-scan software-trigger mode is triggered. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 989 RFDFx by writing a “1” to it. Writing a “0” has no effect. When RFDSx is asserted (DMA requests selected), RFDFx is automatically cleared by the EQADC when the RFIFO becomes empty. 1 = RFIFOx has at least one valid entry. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 990 24.5.2.10 EQADC CFIFO Transfer Counter Registers (EQADC_CFTCR) The EQADC CFIFO Transfer Counter Registers (EQADC_CFTCR) record the number of commands transferred from a CFIFO. The EQADC_CFTCR supports the monitoring of command transfers from a CFIFO. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 991 CBuffer. The transfer of entries bound for an external device is considered completed when the serial transmission of the entry is completed. The EQADC increments the TC_CFx value by MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 992 Writing to the EQADC_CFSSR registers has no effect. Register address: EQADC_BASE+0x0A0 CFS0_TCB CFS1_TCB CFS2_TCB CFS3_TCB CFS4_TCB CFS5_TCB RESET: LCFTCB0 TC_LCFTCB0 RESET: = Unimplemented or Reserved Figure 24-18. EQADC CFIFO Status Snapshot Register 0 (EQADC_CFSSR0) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 993 Last command was transferred from CFIFO2 0b0011 Last command was transferred from CFIFO3 0b0100 Last command was transferred from CFIFO4 0b0101 Last command was transferred from CFIFO5 0b0110 - 0b1110 Reserved MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 994 Section 24.5.2.10, “EQADC CFIFO Transfer Counter Registers (EQADC_CFTCR) captured at the time a current command transfer to an external CBuffer is initiated. This field has no meaning when LCFTSSI is 0b1111. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 995 EQADC transferred the last entry of the queue in continuous-scan edge trigger mode. CFIFO is triggered TRIGGERED 0b11 24.5.2.13 EQADC SSI Control Register (EQADC_SSICR) The EQADC SSI Control Register (EQADC_SSICR) configures the SSI sub-block. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 996 BR field. NOTE: The BR field must only be written when the EQADC SSI is disabled - See ESSIE field Section 24.5.2.1, “EQADC Module Configuration Register (EQADC_MCR). MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 997 The RDV bit indicates if the last received data is valid. This bit is cleared automatically whenever the EQADC_SSIRDR register is read. Writes have no effect. 1 = Receive data is valid. 0 = Receive data is not valid. MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 998 Figure 24-24. EQADC CFIFO0 Registers (EQADC_CF0Rw) (w=0, .., 3) Register address: EQADC_BASE+0x140 Register address: EQADC_BASE+0x144 Register address: EQADC_BASE+0x148 Register address: EQADC_BASE+0x14C CFIFO1_DATAw RESET: CFIFO1_DATAw RESET: Figure 24-25. EQADC CFIFO1 Registers (EQADC_CF1Rw) (w=0, .., 3) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 999 Figure 24-26. EQADC CFIFO2 Registers (EQADC_CF2Rw) (w=0, .., 3) Register address: EQADC_BASE+0x1C0 Register address: EQADC_BASE+0x1C4 Register address: EQADC_BASE+0x1C8 Register address: EQADC_BASE+0x1CC CFIFO3_DATAw RESET: CFIFO3_DATAw RESET: Figure 24-27. EQADC CFIFO3 Registers (EQADC_CF3Rw) (w=0, .., 3) MPC563XM Reference Manual, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice...
Page 1000 CFIFOs. These registers are read only. Data written to these registers is ignored. CFIFOx_DATAw[0:31] — CFIFOx Data w (w = 0, .., 3) MPC563XM Reference Manual, Rev. 1 1000 Freescale Semiconductor Preliminary—Subject to Change Without Notice...

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Freescale Semiconductor MPC5634M Manual

Chapter 1 Block Summary

Chapter 14 Interrupt Controller

Chapter 11

Chapter 20 Software Watchdog Timer (SWT)

Chapter 31 JTAG

Chapter 2 Ballmap: 208 MAPBGA

Chapter 32 Nexus Port Controller (NPC)

Chapter 4

Chapter 5

Chapter 6 Location of Detailed Documentation

Chapter 7

Chapter 9

Chapter 10

Chapter 18

Chapter 15

Chapter 29

Chapter 17

Chapter 8

Chapter 21

Chapter 22

Chapter 27

Chapter 23

Chapter 30 Block Diagram

Chapter 24

Chapter 25

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