Panasonic FP0R User Manual page 264

Name
No.
404/
Interrupt input: X4Interrupt 4
405
404/
Interrupt input: X5Interrupt 5
405
404/
Interrupt input: X6Interrupt 6
405
404/
Interrupt input: X7Interrupt 7
405
 If the same input has been set as high-speed counter input, pulse catch
input or interrupt input, the following order of precedence is effective:
High-speed counter  Pulse catch  Interrupt.
 If reset input settings overlap for channel 0 and channel 1, the channel 1
setting takes precedence. If reset input settings overlap for channel 2
and channel 3, the channel 3 setting takes precedence.
 The input modes two-phase, incremental/decremental, or
incremental/decremental control require a second channel. If channel 0,
2, or channel 4 has been set to one of these modes, the settings for
channel 1, 3, and 5, respectively, will be invalid.
 The settings for pulse catch inputs and interrupt inputs can only be
specified in the system registers.
Transistor types (C16 and higher)
 CPU outputs which have been specified as pulse output or PWM output
cannot be used as normal outputs.
 Input numbers X4 to X7 can be used as home input of pulse output
channels 0 to 3. When using the home return function, always set the
home input. In this case, X4 to X7 cannot be used as high-speed
counter inputs.
 The output numbers for the deviation counter clear signal, which can be
used with the home return function, are fixed for each channel.
For C16: Channel 0 = Y6, channel 1 = Y7
For C32/T32/F32: Channel 0 = Y8, channel 1 = Y9, channel 2 = YA,
channel 3 = YB
If used for the deviation counter clear signal, these outputs are not
available as pulse outputs.
Default Values
Unused Rising edge/Falling edge/Rising and falling edge
Unused Rising edge/Falling edge/Rising and falling edge
Unused Rising edge/Falling edge/Rising and falling edge
Unused Rising edge/Falling edge/Rising and falling edge
Appendix
263