Download Print this page

NXP Semiconductors LPC29 Series User Manual

NXP Semiconductors LPC29 Series User Manual

Arm9 microcontroller with can and lin

Hide thumbs Also See for LPC29 Series:

User manual (566 pages)

Table Of Contents

page of 571

/ 571
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

UM10316

LPC29xx ARM9 microcontroller with CAN and LIN

Rev. 00.06 — 17 December 2008

Document information

Info

Content

Keywords

LPC2917/01; LPC2919/01; LPC2927; LPC2929; LPC2921; LPC2923;

LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN

Abstract

This document extends the LPC29xx data sheets with additional details to

support both hardware and software development. It focuses on functional

description and typical application use.

User manual

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the LPC29 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for NXP Semiconductors LPC29 Series

Page 1 UM10316 LPC29xx ARM9 microcontroller with CAN and LIN Rev. 00.06 — 17 December 2008 User manual Document information Info Content Keywords LPC2917/01; LPC2919/01; LPC2927; LPC2929; LPC2921; LPC2923; LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN Abstract This document extends the LPC29xx data sheets with additional details to support both hardware and software development.
Page 2 UM10316 NXP Semiconductors LPC29xx Revision history Date Description 00.06 <tbd> Modifications: • CGU chapter updated with description of CGU1 and internal base clocks. • SCU chapter: description of SFSP_5_18/18, SEC_DIS, and SEC_STA registers added. • RGU chapter updated. • PMU chapter updated.
Page 3: Chapter 1: Lpc29Xx Introductory Information
UM10316 Chapter 1: LPC29xx Introductory information Rev. 00.06 — 17 December 2008 User manual 1. Introduction The LPC29xx combine an 125 MHz ARM968E-S CPU core, Full Speed USB 2.0 OTG and device, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication.
Page 4 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information – Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO. – Two I C-bus interfaces. • Other peripherals: – Up to three ADCs: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range and one, 8-channel 10-bit ADC with 5.0 V measurement range provide a...
Page 5: Ordering Information
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information – CPU operating voltage: 1.8 V ± 5 %. – I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V. • Available in 100-pin,144-pin, and 208-pin LQFP packages.
Page 6: Ordering Options
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 4.1 Ordering options Table 2. LPC29xx part overview Part Flash SRAM LIN/ Pins UART I2C-bus Clkout number...
Page 7 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information 5. Block diagram JTAG interface TEST/DEBUG LPC2917/01 INTERFACE LPC2919/01 ITCM DTCM 8 kB SRAM 16 kB 16 kB ARM968E-S 1 × master 2 × slave master slave VECTORED AHB TO DTL INTERRUPT...
Page 8 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2921/2923/2925 INTERFACE ITCM DTCM 8 kB SRAM 16 kB 16 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 9 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2927/2929 INTERFACE ITCM DTCM 8 kB SRAM 32 kB 32 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 10 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2930 INTERFACE ITCM DTCM 8 kB SRAM 32 kB 32 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 11 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2939 INTERFACE ITCM DTCM 8 kB SRAM 32 kB 32 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 12 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information 6. Functional blocks This chapter gives an overview of the functional blocks, clock domains, and power modes. Table 1–2 for availability of peripherals and blocks for specific LPC29xx parts. The functional blocks are explained in detail in the following chapters. Several blocks are gathered into subsystems and one or more of these blocks and/or subsystems are put into a clock domain.
Page 13 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information Table 4. Functional blocks and clock domains …continued Short Description Comment Timer Dedicated Sampling and Control Timer Quadrature encoder interface Clock domain networking subsystem Gateway Includes acceptance filter Master controller LIN master controller...
Page 14 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information Amongst the most compelling features of the ARM968E-S are: • Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces • Write buffers for the AHB and TCM buses Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed- •...
Page 15: Chapter 2: Lpc29Xx Memory Mapping
UM10316 Chapter 2: LPC29xx memory mapping Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The memory configuration varies for the different LPC29xx parts (see Table 2–5). In addition to the memory blocks, peripheral register blocks in memory region 7 are available only if the peripheral is implemented.
Page 16: Memory-Map View Of The Ahb
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping 2. Memory-map view of the AHB The LPC29xx uses an AHB multilayer bus with the CPU and the GPDMA as the bus masters. The AHB slaves are connected to the AHB-lite multilayer bus.The ARM968E-S CPU has access to all AHB slaves and hence to all address regions.
Page 17 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC29xx 4 GB 0xFFFF FFFF 0xE00A 0000 PCR/VIC control 0xFFFF 8000 0xFFFF FFFF reserved 0xE008 B000 reserved 0xFFFF F000...
Page 18: Region 0: Tcm/Shadow Area
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping 3.1 Region 0: TCM/shadow area The ARM968E-S processor has its exception vectors located at address logic 0. Since flash is the only non-volatile memory available in the LPC29xx, the exception vectors in the flash must be located at address logic 0 at reset (AHB_RST).
Page 19: Region 1: Embedded Flash Area
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping After reset, the region 1 embedded flash area is always available at the shadow area. After booting, any other region of the AHB system memory map (e.g. internal SRAM) can be re-mapped to region 0 by means of the shadow memory mapping register. For more...
Page 20 UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping Region 4 is reserved for internal SRAM. The LPC29xx has two internal SRAM instances. Instance #0 is 32 kB, instance #1 is 16 kB. See Section 7–1. 3.6 Regions 5 and 6 Regions 5 and 6 are not used.
Page 21 UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping Note that the ARM stores the pre-fetch abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents the accidental aborts that could be caused by pre-fetches occurring when code is executed very near to a memory boundary.
Page 22 UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping Table 9. Peripherals base-address overview …continued Base address Base name AHB peripherals E004 A000h GPIO RegBase General-Purpose I/O 0 E004 B000h GPIO RegBase General-Purpose I/O 1 E004 C000h GPIO RegBase General-Purpose I/O 2...
Page 23: How To Read This Chapter
UM10316 Chapter 3: LPC29xx Clock Generation Unit (CGU) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter This chapter describes the base clock generation for all LPC29xx parts. Table 10. LPC29xx base clock options Part CGU0 base clocks CGU1 base clocks LPC2917/19/01...
Page 24: Chapter 4: Lpc29Xx Clock Generation Unit (Cgu)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) BASE_ICLK0_CLK BASE_SYS_CLK BASE_USB_CLK BASE_ICLK1_CLK BASE_USB_I2C_CLK AHB MULTILAYER MATRIX BASE_OUT_CLK CLOCK AHB TO APB BRIDGES CGU1 BASE_IVNSS_CLK networking subsystem GPDMA branch CAN0/1 clocks FLASH/SRAM/SMC GLOBAL ACCEPTANCE USB REGISTERS branch FILTER clocks...
Page 25 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) • OSC1M (LP_OSC) – 1 MHz crystal oscillator • XO50M – up to 25 MHz oscillator • PL160M – PLL • FDIV0..6 – 7 Frequency Dividers • Output control The following clock output branches are generated (Table 3–11):...
Page 26 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) CLOCK GENERATION UNIT (CGU0) OUT 0 BASE_SAFE_CLK SAFE_CLK_CONF FDIV0 OUT 1 BASE_SYS_CLK 400 kHz LP_OSC FDIV_CONF0 clkout SYS_CLK_ clkout120 EXTERNAL CONF OUT 2 BASE_PCR_CLK FDIV1 OSCLLLATOR clkout240 PLL_CONTROL PCR_CLK_CONF FDIV_CONF1...
Page 27: Controlling The Xo50M Oscillator (External Oscillator)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) OSC1M FDIV0..6 XO50M PLL160M clkout / clkout120 / clkout240 Output Control Clock outputs Fig 11. Structure of the clock generation scheme 3.1 Controlling the XO50M oscillator (external oscillator) The XO50M oscillator can be disabled using the ENABLE field in the oscillator control register.
Page 28 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) PSEL P23EN clkout120 / clkout240 Input clock / 2PDIV clkout Bypass Direct / MDIV MSEL Fig 12. PLI60MPLL control mechanisms The PLL reference input clock is provided by the external oscillator (XO50M). The PLLs accept an input clock frequency in the range of 10 MHz to 25 MHz only.
Page 29: Controlling The Frequency Dividers
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 3.3 Controlling the frequency dividers The seven frequency dividers are controlled by the FDIV0..6 registers. The frequency divider divides the incoming clock by (L/D), where L and D are both 12-bit values, and attempts to produce a 50% duty-cycle.
Page 30: Clock Detection
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 3.7 Clock detection All of the clock sources have a clock detector, the status of which can be read in a CGU register. This register indicates which sources have been detected.
Page 31 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) CLOCK GENERATION UNIT (CGU1) BASE_USB_CLK OUT 0 clkout USB_CLK_CONF BASE_ICLK0_CLK clkout120 FDIV0 clkout240 BASE_ICLK1_CLK OUT 1 BASE_USB_I2C_CLK FDIV_CONF0 PLL_CONTROL USB_I2C_CLK_CONF OUT 2 BASE_OUT_CLK OUT_CLK_CONF CLOCK DETECTION FREQUENCY MONITOR AHB TO DTL BRIDGE...
Page 32 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 13. CGU0 register overview (CGU0 base address: 0xFFFF 8000) …continued Address Access Reset value Name Description Reference offset 00Ch reserved Reserved 014h 0000 0000h FREQ_MON Frequency monitor register Table 3–15...
Page 33: Interrupt Set-Enable Register
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 13. CGU0 register overview (CGU0 base address: 0xFFFF 8000) …continued Address Access Reset value Name Description Reference offset 090h 0000 0000h ICLK1_CLK_STATUS Output-clock status register for Table 3–26 BASE_ICLK0_CLK...
Page 34: Frequency Monitor Register
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 14. CGU1 register overview (CGU1 base address: 0xFFFF B000) Address Access Reset value Name Description Reference offset 000h 7100 0011h reserved Reserved 004h 0000 0000h reserved Reserved 008h 0C00 0000h...
Page 35 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) value. Secondly, due to synchronization, the counters are not started and stopped at exactly the same time. Finally, the measured frequency can only be to the same level of precision as the reference frequency.
Page 36 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Remark: The clock selection in this register depends on whether the register is used for CGU0 or CGU1. In the CGU0, the low-power oscillator (LP_OSC) or the external crystal oscillator can be selected as input. In the CGU1, the two CGU0 base clocks BASE_ICLK0_CLK and BASE_ICLK1_CLK, can be selected instead.
Page 37: Crystal Oscillator Control Register (Cgu0)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 16. RDET register bit description (RDET, address 0xFFFF 8018 (CGU0) or 0xFFFF B018 (CGU1)) …continued * = reset value Symbol Access Value Description PLL_PRESENT Activity-detection register for normal PLL...
Page 38: Pll Status Register (Cgu0 And Cgu1)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 18. XTAL_OSC_CONTROL register bit description (XTAL_OSC_CONTROL, address 0xFFFF 8020) * = reset value Symbol Access Value Description 31 to 3 reserved Reserved Oscillator HF pin Oscillator high-frequency mode (crystal or...
Page 39: Feedback-Divider Ratio Programming
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Feedback-divider ratio programming The feedback-divider division ratio is controlled by MSEL[4:0] in the PLL_CONTROL register. The division ratio between the PLL output clock and the input clock is the decimal value on MSEL[4:0] plus one.
Page 40 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 20. PLL_CONTROL register bit description (PLL_CONTROL, address 0xFFFF 8028 (CGU0) and 0xFFFF B028 (CGU1)) * = reset value Symbol Access Value Description 31 to 24 CLK_SEL Clock-source Selection for clock generator to be connected to the input of the PLL.
Page 41: Frequency Divider Status Register
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Changing the divider ratio while the PLL is running is not recommended. Since there is no way of synchronizing the change of the MSEL and PSEL values with the divider the risk exists that the counter will read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output clock.
Page 42 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 22. FDIV_CONF_n register bit description (FDIV_CONF_n, address 0xFFFF 8030/38/40/48/50/58/60 (CGU0) and FDIV_CONF_0, address 0xFFFF B028 (CGU1)) * = reset value Symbol Access Value Description 31 to 24 CLK_SEL Selected source clock for FDIV n...
Page 43: Base_Safe_Clk And Base_Pcr_Clk
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 24. SAFE_CLK_CONF (address 0xFFFF 8068), PCR_CLK_CONF (address 0xFFFF 8078) register bit description * = reset value Symbol Access Value Description 31 to 24 CLK_SEL Selected source clock 00h* LP_OSC...
Page 44 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 26. XX_CLK_CONF register bit description (XX = SYS (address 0xFFFF 8070), IVNSS (address 0xFFFF 8080), MSCSS (address 0xFFFF 8088), UART (address 0xFFFF 8098), SPI (address 0xFFFF 80A0), TMR (address 0xFFFF 80A8), ADC (address...
Page 45 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 5.14 Output-clock configuration register for CGU1 clocks There is one configuration register for each CGU1 output clock generated. All output generators have the same register bits. The CGU1 output clock can be generated directly from the two CGU0 base clocks BASE_ICLK0_CLK and BASE_ICLK1_CLK or from the CGU1 PLL.
Page 46 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 29. BUS_DISABLE register bit description (BUS_DISABLE, address 0xFFFF 8FF4 (CGU0) and 0xFFFF BFF4 (CGU1)) * = reset value Symbol Access Value Description 31 to 1 reserved Reserved; do not modify. Read as logic 0, write...
Page 47: Chapter 5: Lpc29Xx Reset Generation Unit (Rgu)
UM10316 Chapter 4: LPC29xx Reset Generation Unit (RGU) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. The USB reset is not available on the LPC2917/19/01 parts. 2.
Page 48: Reset Hierarchy
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 31. Reset output configuration …continued Reset output Reset source Parts of the device reset when activated QEI_RST WARM_RST Quadrature encoder DMA_RST WARM_RST GPDMA controller USB_RST WARM_RST USB controller VIC_RST...
Page 49: Rgu Register Overview
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 32. Reset priority Priority Reset OSC1M Flash CFID Memory all other controller controllers peripherals (SRAM,SMC) RESET Cold Warm 4. RGU register overview The Reset Generation Unit (RGU) registers are shown in Table 4–33.
Page 50: Rgu Reset Control Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 33. RGU register overview (base address: 0xFFFF 9000) …continued Address Access Reset value Name Description Reference offset 4B0h 0000 0040h TMR_RST_SRC Source register for Timer reset Table 4–46 4B4h...
Page 51: Rgu Reset Status Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 35. RESET_CONTROL1 register bit description (RESET_CONTROL1, 0xFFFF 9104) * = reset value Symbol Access Value Description 31 and reserved Reserved; do not modify, write as logic 0 AHB_RST_CTRL Activate AHB_RST...
Page 52 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 36. RESET_STATUS0 register bit description (RESET_STATUS0, address 0xFFFF 9110) * = reset value Symbol Access Value Description 31 to 10 reserved Reserved; do not modify. Read as logic 0,...
Page 53 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 38. RESET_STATUS2 register bit description (RESET_STATUS2, address 0xFFFF 9118) * = reset value Symbol Access Value Description 31 and 30 IVNSS_CAN_RST_STAT Reset IVNSS CAN status No reset activated since RGU last...
Page 54 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 38. RESET_STATUS2 register bit description (RESET_STATUS2, address 0xFFFF 9118) …continued * = reset value Symbol Access Value Description 19 and 18 PESS_A2V_RST_STAT Reset PeSS AHB2APB status No reset activated since RGU last...
Page 55 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 38. RESET_STATUS2 register bit description (RESET_STATUS2, address 0xFFFF 9118) …continued * = reset value Symbol Access Value Description 1 and 0 SCU_RST_STAT Reset SCU status No reset activated since RGU last...
Page 56 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 39. RESET_STATUS3 register bit description (RESET_STATUS3, address 0xFFFF 911C) …continued * = reset value Symbol Access Value Description 13 and 12 MSCSS_QEI_STAT Reset MSCSS QEI status No reset activated since RGU last...
Page 57: Rgu Reset Active Status Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 39. RESET_STATUS3 register bit description (RESET_STATUS3, address 0xFFFF 911C) …continued * = reset value Symbol Access Value Description 1 and 0 IVNSS_LIN_RST_STAT Reset IVNSS LIN status No reset activated since RGU last...
Page 58 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 41. RST_ACTIVE_STATUS1 register bit description (RST_ACTIVE_STATUS1, address 0xFFFF 9154) …continued * = reset value Symbol Access Value Description SPI_RST_STAT Current state of SPI_RST TMR_RST_STAT Current state of TMR_RST UART_RST_STAT...
Page 59 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 43. PCR_RST_SRC register bit description (PCR_RST_SRC, address 0xFFFF 9408) * = reset value Symbol Access Value Description 31 to 4 reserved Reserved; do not modify. Read as logic 0...
Page 60 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) 4.5 RGU bus-disable register The BUS_DISABLE register prevents any register in the CGU from being written to. Table 47. BUS_DISABLE register bit description (BUS_DISABLE, address 0xFFFF 9FF4) * = reset value...
Page 61: Chapter 6: Lpc29Xx Power Management Unit (Pmu)
UM10316 Chapter 5: LPC29xx Power Management Unit (PMU) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The implementation of some branch clocks for power control depends on the peripheral and memory configuration of each LPC29xx part, see Table 5–48.
Page 62 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 49. Branch clock overview …continued Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’...
Page 63: Pmu Clock-Branch Run Mode
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 49. Branch clock overview …continued Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’...
Page 64: Pmu Clock Branch Overview
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Clocks that have been programmed to enter sleep mode follow the chosen setting of the PD field in register PM. This means that with a single write-action all of these domains can be set either to sleep or to wake up.
Page 65 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. PMU register overview (base address: FFFF A000h) …continued Address Access Reset value Name Description Reference offset 228h 0000 0001h CLK_CFG_RAM1 AHB clock to embedded memory Table 5–53 controller 1 configuration register...
Page 66 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. PMU register overview (base address: FFFF A000h) …continued Address Access Reset value Name Description Reference offset 284h 0000 0001h CLK_STAT_GPIO4 APB clock to General-Purpose I/O 4 Table 5–54...
Page 67 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. PMU register overview (base address: FFFF A000h) …continued Address Access Reset value Name Description Reference offset 450h reserved -4FCh 500h 0000 0001h CLK_CFG_MSCSS_APB APB clock to MSCSS module- Table 5–53...
Page 68 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. PMU register overview (base address: FFFF A000h) …continued Address Access Reset value Name Description Reference offset 558h - 0000 0001h reserved Reserved 5FFh 600h 0000 0001h CLK_CFG_OUT_CLK clock out configuration register Table 5–53...
Page 69: Power Mode Register (Pm)
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. PMU register overview (base address: FFFF A000h) …continued Address Access Reset value Name Description Reference offset C04h 0000 0001h CLK_STAT_USB_I2C IP clock to USB I2C status register Table 5–54...
Page 70: Pmu Clock Configuration Register For Output
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 52. BASE_STAT register bit description (BASE_STAT, address 0xFFFF A004) * = reset value Symbol Access Value Description BASE2_STAT Indicator for BASE_PCR_CLK BASE1_STAT Indicator for BASE_SYS_CLK BASE0_STAT Indicator for BASE_SAFE_CLK 4.3 PMU clock configuration register for output branches...
Page 71 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 54. CLK_STAT_XXX register bit description (CLK_STAT_SAFE to CLK_STAT_USB_CLK, addresses 0xFFFF A104 to 0xFFFF AD04) * = reset value Symbol Access Value Description 31 to 10 reserved Reserved; do not modify. Read as logic 0...
Page 72 UM10316 Chapter 6: LPC29xx System Control Unit (SCU) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. See Table 6–55 for available GPIO pins and registers that are part specific. Table 55.
Page 73 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 56. SCU register overview (base address: 0xE000 1000) …continued Name Address Access Reset value Description Reference offset SFSP4_BASE 400h 0000 0000h Function-select port 4 base Table 6–57 address SFSP5_BASE...
Page 74 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 57. SCU port function select register overview (base address: 0xE000 1000 (port 0), 0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4), 0xE000 1500 (port 5)) Ports not pinned out are reserved;...
Page 75 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 57. SCU port function select register overview (base address: 0xE000 1000 (port 0), 0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4), 0xE000 1500 (port 5)) …continued...
Page 76 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 58. SFSPn_m register bit description (base address: 0xE000 1000 (port 0), 0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4), 0xE000 1500 (port 5)) …continued...
Page 77 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 60. SFSP5_18 function select register bit description (SFSP_5_18, address 0xE000 1548) Symbol Access Value Description 31:5 reserved VBUS <tbd> port 1 in host or device mode port 1 in OTG mode...
Page 78 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) 3.2 JTAG security registers Table 61. Security disable register bit description (SEC_DIS, address 0xE000 1B00) Symbol Access Value Description 31:2 reserved JTAG security enable/disable Disables JTAG security and clears bit 1 on SEC_STA...
Page 79 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) All masters with the same priority are scheduled on a round-robin basis. Table 64. SMPx register bit description (SMP0/1/2/3, addresses: 0xE000 1D00 (ARM), 0xE000 1D04 (DMA0), 0xE000 1D08 (DMA1), 0xE000 1D0C (USB))
Page 80 UM10316 Chapter 7: LPC29xx Chip Feature ID (CFID) Rev. 00.06 — 17 December 2008 User manual 1. Introduction The CFID module contains registers that show and control the functionality of the chip. It contains an ID to identify the silicon and registers containing information about the features enabled/disabled on the chip.
Page 81: Configuration Register 1
UM10316 NXP Semiconductors Chapter 7: LPC29xx Chip Feature ID (CFID) Table 7–67 shows the bit assignment of the FEAT0 register. Table 67. FEAT0 register bit description (FEAT0, address 0xE000 0100) Symbol Access Value Description 31 to 4 reserved Reserved; do not modify. Read as...
Page 82 UM10316 NXP Semiconductors Chapter 7: LPC29xx Chip Feature ID (CFID) Table 70. FEAT3 register bit description (FEAT3, address 0xE000 010C) Symbol Access Value Description JTAGSEC The setting of this bit is determined by the setting of the JTAG security in the flash...
Page 83 UM10316 Chapter 8: LPC29xx event router Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Not all event sources are connected to pins. Table 8–71 shows the event router connections that vary for different LPC29xx parts.
Page 84 UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Input events are processed in event slices; one for each event signal. Each of these slices generates one event signal and is visible in the RSR (Raw Status Register). These events are then AND-ed with enables from the MASK register to give PEND (PENDing register) event status.
Page 85: Event-Status Clear Register
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 72. Event-router pin connections …continued Symbol Direction Bit position Description Default polarity UART1 RXD UART1 receive data input <tbd> USB_I2C_SCL IN <tbd> <tbd> CAN interrupt (internal) VIC FIQ (internal) VIC IRQ (internal)
Page 86 UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 74. PEND register bit description * = reset value Symbol Access Value Description 31 to 27 reserved Reserved; do not modify. Read as logic 0 PEND[26] An event has occurred on a corresponding pin,...
Page 87: Event-Enable Clear Register
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 8–77 shows the bit assignment of the MASK register. Table 77. MASK register bit description * = reset value Symbol Access Value Description 31 to 27 reserved Reserved; do not modify. Read as logic 0...
Page 88: Activation Polarity Register
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router 3.7 Activation polarity register The APR is used to configure which level is the active state for the event source. Table 8–80 shows the bit assignment of the APR register. Table 80.
Page 89 UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 82. RSR register bits Symbol Access Value Description 31 to 27 reserved Reserved; do not modify. Read as logic 0 RSR[26] Corresponding event has occurred Corresponding event has not occurred RSR[0]...
Page 90: Chapter 10: Lpc29Xx Vectored Interrupt Controller (Vic)
UM10316 Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. See xxx for interrupt requests that are not implemented in all parts. All other interrupt requests are available in all LPC29xx parts (see Table 9–90).
Page 91 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) • The IRQ exception has a lower priority than FIQ and is masked out when an FIQ exception occurs. IRQ service routines should take care of saving and/or restoring the used registers themselves.
Page 92: Non-Nested Interrupt Service Routine
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) If the level-sensitive interrupt request line of the VIC is enabled (depending on the polarity setting), the request is forwarded to the interrupt selection. The interrupt selection part selects the interrupt request line with the highest priority, based on the target and priority of the interrupt request and priority masks.
Page 93: Vic Register Overview
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) 4. VIC register overview The VIC registers have an offset from the base address VIC RegBase which can be found in the memory map; see Table 2–7. Table 84. Vectored Interrupt Controller register overview (base address: FFFF F000h)
Page 94 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 84. Vectored Interrupt Controller register overview (base address: FFFF F000h) …continued Address Access Reset value Name Description Reference 43Ch INT_REQUEST_15 Interrupt Request 15 control register Table 9–91 440h INT_REQUEST_16 Interrupt Request 16 control register Table 9–91...
Page 95 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 84. Vectored Interrupt Controller register overview (base address: FFFF F000h) …continued Address Access Reset value Name Description Reference 498h INT_REQUEST_38 Interrupt Request 38 control register Table 9–91 49Ch INT_REQUEST_39 Interrupt Request 39 control register Table 9–91...
Page 96 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 85. INT_PRIORITYMASK_n registers bit description (INT_PRIORITYMASK_0/1, addresses 0xFFFF F000 and 0xFFFF F004) Symbol Access Reset Description value 31 to 4 reserved Reserved; do not modify. Read as logic 3 to 0 PRIORITY_LIMITER[3:0] Priority limiter.
Page 97 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Interrupt service routine 2 Entry point Interrupt service routine 1 Index Priority limiter 2 010h Vector 2 Entry point Pointer 00Ch Priority limiter 1 008h Vector 1 "no interrupt" handler...
Page 98 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) 4.3 Interrupt-pending register 1 The interrupt-pending register gathers the pending bits of interrupt requests 1 to 31. Software can make use of this feature to gain a faster overview of pending interrupts than it would get by reading the individual interrupt request registers.
Page 99 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 89. INT_FEATURES register bit description (INT_FEATURES, address 0xFFFF F300) * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; read as don’t care 21 to 16 T...
Page 100 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 90. Interrupt source and request reference …continued Interrupt Interrupt source Description request Event Router Event, wake up tick interrupt from Event Router LIN master controller 0 General interrupt from LIN master controller 0...
Page 101 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 91. INT_REQUESTn register bit description (INT_REQUEST1 to 56, addresses 0xFFFF F404 to 0xFFFF F4E0). * = reset value Symbol Access Value Description PENDING Pending interrupt request. This reflects the state of the interrupt source channel.
Page 102 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 91. INT_REQUESTn register bit description (INT_REQUEST1 to 56, addresses 0xFFFF F404 to 0xFFFF F4E0). * = reset value Symbol Access Value Description ACTIVE_LOW Active-LOW interrupt line. This selects the polarity of the interrupt request line.
Page 103 UM10316 Chapter 10: LPC29xx general system control Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction This chapter contains power control, interrupt, and wake-up features that pertain to various functions and peripherals on the LPC29xx.
Page 104 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control Setting the power mode and configuring the clock domains is handled by the CGU, see Section 3–3. Configuration of wake-up events is handled by the Event Router, see Section 8–2. 4. Reset and power-up behavior The LPC29xx contains external reset input and internal power-up reset circuits.
Page 105 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control UART Interrupt Requests Fig 22. Interrupt (UART) causing an IRQ Event Router Events Interrupt Requests Fig 23. Event causing an IRQ 6. Interrupt device architecture In the LPC29xx a general approach is taken to generate interrupt requests towards the CPU.
Page 106 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control Interrupt Request >1 & STATUS ENABLE >1 Event CLEAR CLEAR STATUS STATUS ENABLE ENABLE Control Interface Fig 24. Interrupt device architecture A set of software-accessible variables is provided for each interrupt source to control and observe interrupt request generation.
Page 107 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control 6.1.1 Interrupt clear-enable register Write ‘1’ actions to this register set one or more ENABLE variables in the INT_ENABLE register. INT_SET_ENABLE is write-only. Writing a 0 has no effect. Table 93.
Page 108 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control Table 97. INT_CLR_STATUS register bit description Variable Name Access Value Description CLR_STATUS[i] Clears STATUS[i] variable in INT_STATUS register (set to 0) 6.1.6 Interrupt set-status register Write ‘1’ actions to this register set one or more STATUS variables in the INT_STATUS register.
Page 109 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control – Initialization of the interrupt functionality (outside the scope of this driver) – Installation of the event-dispatcher interrupt function – Initialization of the ESR driver • Installation of the ESR: – Configure the signal specifications for external interrupts With this API the edge/level sensitivity can be programmed –...
Page 110 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control wake-up Event UART Router Events Interrupt Requests Fig 26. Event causing a wake-up UM10316_0 © NXP B.V. 2008. All rights reserved. User manual Rev. 00.06 — 17 December 2008 110 of 571...
Page 111: Chapter 11: Lpc29Xx Pin Configuration
UM10316 Chapter 11: LPC29xx pin configuration Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter Table 11–99 for pin configurations of all LPC29xx parts. Table 99. Feature overview Part Pin configuration Pin assignment LPC2917/19/01 Figure 11–27 Table 11–100 LPC2921/23/25 Figure 11–28...
Page 112 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P0[26]/TXD1/ GPIO 0, pin 26 UART1 TXD SPI2 SDI SDI2 P0[27]/RXD1/ GPIO 0, pin 27...
Page 113 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P2[27]/CAP0[3]/ GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7 MAT0[3]/EI7 P1[27]/CAP1[2]/ GPIO 1, pin 27...
Page 114 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P1[14]/CAP2[0]/ GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0 SCS0[3]/D0 P1[13]/SCL1/ GPIO 1, pin 13...
Page 115 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 1.8 V supply for oscillator DD(OSC) ground for PLL SS(PLL) P2[7]/MAT1[3]/ GPIO 2, pin 7...
Page 116 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P2[13]/ GPIO 2, pin 13 PWM0 MAT5 SPI0 SDO PMAT0[5]/ SDO0 P0[4]/PMAT0[2]/ GPIO 0, pin 4...
Page 117 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P0[17]/IN2[1]/ GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23 RXD0/A23 1.8 V power supply for digital core...
Page 118: Lpc2921/23/25 Pin Configuration
UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration 3. LPC2921/23/25 pin configuration LPC2921FBD100 LPC2923FBD100 LPC2925FBD100 002aae242 Fig 28. Pin configuration for SOT407-1 (LQFP100) The LPC2921/23/25 uses three ports: port 1 with 32 pins, port 1 with 28 pins, and port 5 with 2 pins.
Page 119 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 P1[27]/CAP1[2]/ GPIO 1, pin 27 TIMER1 CAP2, PWM TRAP2 PWM3 MAT3 TRAP2/PMAT3[3] ADC2 EXT START...
Page 120 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 P1[8]/SCS1[0]/ GPIO 1, pin 8 SPI1 SCS0 TXDL1/CS0 P1[7]/SCS1[3]/RXD1 GPIO 1, pin 7...
Page 121 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 VREFN LOW reference for ADC P0[8]/IN1[0] GPIO 0, pin 8 ADC1 IN0 P0[9]/IN1[1]...
Page 122 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 P0[23]/IN2[7]/ GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 PMAT2[5]/A19 IEEE 1149.1 data in, pulled up internally Bidirectional Pad;...
Page 123 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 102. LPC2927/29 LQFP144 pin assignment …continued Pin name Description Default function Function 0 Function 1 Function 2 Function 3 P0[28]/CAP0[0]/ GPIO 0, pin 28 GPIO 0, pin 28 TIMER0 CAP0 TIMER0 MAT0...
Page 124 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 102. LPC2927/29 LQFP144 pin assignment …continued Pin name Description Default function Function 0 Function 1 Function 2 Function 3 3.3 V power supply for I/O DD(IO) P1[25]/ GPIO 1, pin 25...
Page 125 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 102. LPC2927/29 LQFP144 pin assignment …continued Pin name Description Default function Function 0 Function 1 Function 2 Function 3 P1[12]/SDA1/ GPIO 1, pin 12 GPIO 1, pin 12 EXTINT2 I2C1 SDA...
Page 126 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 102. LPC2927/29 LQFP144 pin assignment …continued Pin name Description Default function Function 0 Function 1 Function 2 Function 3 P2[7]/MAT1[3]/ GPIO 2, pin 7 GPIO 2, pin 7 TIMER1 MAT3 EXTINT3...
Page 127 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 102. LPC2927/29 LQFP144 pin assignment …continued Pin name Description Default function Function 0 Function 1 Function 2 Function 3 P2[12]/IN0[4] GPIO 2, pin 12 GPIO 2, pin 12 ADC0 IN4 PWM0 MAT4...
Page 128 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 102. LPC2927/29 LQFP144 pin assignment …continued Pin name Description Default function Function 0 Function 1 Function 2 Function 3 P0[15]/IN1[7]/ GPIO 0, pin 15 GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5...
Page 129 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration 5. LPC2930/30 pin configuration LPC2939FBD208 002aae253 Fig 30. Pin configuration for LQFP208 package The LPC2930/29 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each, port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins.
Page 130 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P0[31]/CAP0[3]/ GPIO 0, pin 31 TIMER0 CAP3 TIMER0 MAT3 MAT0[3] P2[24]/SCS1[1]/ GPIO 2, pin 24...
Page 131 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P1[26]/PMAT2[0]/ GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2 TRAP3/PMAT3[2] P4[20]/...
Page 132 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P3[10]/SDI2/ GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 USB_PWRD1 PMAT1[4]/ USB_PWRD1 ground for core SS(CORE) 1.8 V power supply for digital core...
Page 133 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P1[9]/SDO1/ GPIO 1, pin 9 SPI1 SDO LIN1 RXD/UART RXD EXTBUS CS1 RXDL1/CS1...
Page 134 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P2[10]/USB_INT1/ GPIO 2, pin 10 USB_INT1 PWM0 MAT2 SPI0 SCS0 PMAT0[2]/SCS0[0] P2[11]/USB_RST1/ GPIO 2, pin 11...
Page 135 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P5[14]/ GPIO 5, pin 14 USB_SSPND1 UART0 RS USB_SSPND1/RTS0 3.3 V power supply for I/O...
Page 136 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P0[14]/IN1[6]/ GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 EXTBUS A12 PMAT1[4]/A12 P5[11]/D23/DCD0...
Page 137 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P0[22]/IN2[6]/ GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18 PMAT2[4]/A18 ground for I/O...
Page 138: Chapter 12: Lpc29Xx External Static Memory Controller (Smc)
UM10316 Chapter 12: LPC29xx external Static Memory Controller (SMC) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to parts LPC2917/19/01, LPC2927/29, LPC2930, and LPC2939. The LPC2921/23/25 does not have an external static memory controller. 2.
Page 139: External Memory Interface
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) 3. External memory interface The external memory interface depends on the bank width: 32, 16 or 8 bits selected via MW bits in the corresponding SMBCR register. Choice of memory chips requires an adequate set-up of the RBLE bit in the same register.
Page 140 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CS0 .. CS n OE_N WE_N BLS3 BLS1 BLS2 BLS0 D[31:16] D[15:0] IO[15:0] IO[15:0] A[x:0] A[x:0] A[x+2:2] 32-bit bank using 16-bit devices Fig 33. External memory interface: 32-bit banks with 16-bit devices CS0 ..
Page 141 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CS0 .. CS n OE_N BLS1 BLS0 D[15:8] D[7:0] IO[7:0] IO[7:0] A[x:0] A[x:0] A[x+1:1] 16-bit bank using 8-bit devices Fig 35. External memory interface: 16-bit banks with 8-bit devices CS0 ..
Page 142 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CS0 .. CS n OE_N BLS0 D[7:0] IO[7:0] A[x:0] A[x:0] 8-bit bank using 8-bit device Fig 37. External memory interface: 8-bit banks with 8-bit devices Memory is available in various speeds, so the numbers of wait-states for both read and write access must be set up.
Page 143 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CLK(SYS) WE_N / BLS ADDR DATA WSTWEN WST2 WSTWEN=3, WST2=7 Fig 39. Writing to external memory Figure 12–40 usage of the idle/turn-around time (IDCY) is demonstrated. Extra wait-states are added between a read and a write cycle in the same external memory device.
Page 144: External Smc Register Overview
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) 4. External SMC register overview The external SMC memory-bank configuration registers are shown in Table 12–105. The memory-bank configuration registers have an offset to the base address SMC RegBase which can be found in the memory map.
Page 145 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 105. External SMC register overview (base address 6000 0000h) …continued Offset Access Width Reset Symbol Description Reference Address value 048h SMBWSTWENR2 Write-enable assertion delay control register for memory bank 2 Table 12–110...
Page 146 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 105. External SMC register overview (base address 6000 0000h) …continued Offset Access Width Reset Symbol Description Reference Address value 09Ch SMBWSTWENR5 Write-enable assertion delay control register for memory bank 5 Table 12–110...
Page 147: Bank Wait-State 1 Control Registers
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 12–106 shows the bit assignment of the SMBIDCYR0 to SMBIDCYR7 registers. Table 106. SMBIDCYRn register bit description (SMBIDCYR0 to 7, addresses 0x6000 0000, 0x6000 001C, 0x6000 0038, 0x6000 0054, 0x6000 0070, 0x6000 008C, 0x6000 00A8,...
Page 148 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Sequential-access burst-reads from burst-flash devices of the same type as for burst ROM are supported. Due to sharing of the SMBWST2R register between write and burst- read transfers it is only possible to have one setting at a time for burst flash; either write delay or the burst-read delay.
Page 149 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 109. SMBWSTOENRn register bit description (SMBWSTOENR0 to SMBWSTOENR7, addresses 0x6000 000C, 0x6000 0028, 0x6000 0044, 0x6000 0060, 0x6000 007C, 0x6000 0098, 0x6000 00B4, 0x6000 00D0) * = reset value...
Page 150 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 12–111 shows the bit assignment of the SMBCR0 to SMBCR7 registers. Table 111. SMBCRn register bit description (SMBCR0 toSMBCR7, addresses 0x6000 0014, 0x6000 0030, 0x6000 004C, 0x6000 0068, 0x6000 0084, 0x6000 00A0, 0x6000 00BC,...
Page 151 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 112. SMBSRn register bit description (SMBSR0 toSMBSR7, addresses 0x6000 0018, 0x6000 0034, 0x6000 0050, 0x6000 006C, 0x6000 0088, 0x6000 00A4, 0x6000 00C0, 0x6000 00DC) * = reset value...
Page 152: Chapter 13: Lpc29Xx Usb Device
UM10316 Chapter 13: LPC29xx USB device Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The USB device controller is used in parts LPC2921/23/25, LPC2927/29, LPC2930, and LPC2939. 2. Introduction The Universal Serial Bus (USB) is a four-wire bus that supports communication between a host and one or more (up to 127) peripherals.
Page 153: Features
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 113. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description Random Access Memory Start-Of-Frame Serial Interface Engine SRAM Synchronous RAM UDCA USB Device Communication Area Universal Serial Bus 3.
Page 154: Functional Description
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 114. Fixed endpoint configuration Logical Physical Endpoint type Direction Packet size (bytes) Double buffer endpoint endpoint Isochronous 1 to 1023 Interrupt 1 to 64 Interrupt 1 to 64 Bulk 8, 16, 32, 64...
Page 155: Analog Transceiver
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 5.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional D+ and D- signals of the USB bus. 5.2 Serial Interface Engine (SIE) The SIE implements the full USB protocol layer.
Page 156: Goodlink
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 5.8 GoodLink Good USB connection indication is provided through GoodLink technology. When the device is successfully enumerated and configured, the LED indicator will be permanently ON. During suspend, the LED will be OFF.
Page 157: Clocking And Power Management
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 8. Clocking and power management This section describes the clocking and power management features of the USB Device Controller. 8.1 Power requirements The USB protocol insists on power management by the device. This becomes very critical if the device draws power from the bus (bus-powered device).
Page 158: Remote Wake-Up
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is set. When the device controller is not in use, all of the device controller clocks may be disabled by clearing PCUSB.
Page 159 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 117. USB device register map Name Description Access Reset value Address USBEpIntSet USB Endpoint Interrupt Set 0x0000 0000 0xE010 C23C USBEpIntPri USB Endpoint Priority 0x0000 0000 0xE010 C240 Endpoint realization registers...
Page 160: Usb Clock Control Register (Usbclkctrl - 0Xe010 Cff4)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.1 Clock control registers 9.1.1 USB Clock Control register (USBClkCtrl - 0xE010 CFF4) This register controls the clocking of the USB Device Controller. Whenever software wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN must be set.
Page 161: Device Interrupt Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 119. USB Clock Status register (USBClkSt - 0xE010 CFF8) bit description Symbol Description Reset value PORTSEL_CLK_ON Port select register clock on. AHB_CLK_ON AHB clock on. 31:5 Reserved, user software should not write ones to reserved bits.
Page 162: Usb Device Interrupt Enable Register (Usbdevinten - 0Xe010 C204)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Symbol Symbol ERR_INT EP_RLZED Symbol TxENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME ENDPKT Table 122. USB Device Interrupt Status register (USBDevIntSt - address 0xE010 C200) bit description Symbol Description Reset value FRAME The frame interrupt occurs every 1 ms.
Page 163: Usb Device Interrupt Clear Register (Usbdevintclr - 0Xe010 C208)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Symbol TxENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME ENDPKT Table 124. USB Device Interrupt Enable register (USBDevIntEn - address 0xE010 C204) bit description Symbol Value Description Reset value 31:0 No interrupt is generated.
Page 164: Usb Device Interrupt Priority Register (Usbdevintpri - 0Xe010 C22C)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 127. USB Device Interrupt Set register (USBDevIntSet - address 0xE010 C20C) bit allocation Reset value: 0x0000 0000 Symbol Symbol Symbol ERR_INT EP_RLZED Symbol TxENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME ENDPKT Table 128.
Page 165 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a read only register. Note that for Isochronous endpoints, handling of packet data is done when the FRAME interrupt occurs.
Page 166: Usb Endpoint Interrupt Enable Register (Usbepinten - 0Xe010 C234)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 131. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE010 C230) bit description Symbol Description Reset value EP12TX Endpoint 12, Isochronous endpoint. EP13RX Endpoint 13, Data Received Interrupt bit. EP13TX Endpoint 13, Data Transmitted Interrupt bit or sent a NAK.
Page 167: Usb Endpoint Interrupt Set Register (Usbepintset - 0Xe010 C23C)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device • While setting multiple bits in USBEpIntClr simultaneously is possible, it is not recommended; only the status of the endpoint corresponding to the least significant interrupt bit cleared will be available at the end of the operation.
Page 168: Usb Endpoint Interrupt Priority Register
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 137. USB Endpoint Interrupt Set register (USBEpIntSet - address 0xE010 C23C) bit description Symbol Value Description Reset value 31:0 No effect. USBEpIntSet Sets the corresponding bit in USBEpIntSt. bit allocation table above 9.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0xE010 C240)
Page 169: Usb Realize Endpoint Register (Usbreep - 0Xe010 C244)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device The EP_ RAM space (in words) required for the physical endpoint can be expressed as ⎛ ⎞ MaxPacketSize × EPRAMspace ------------------------------------------------- - dbstatus ⎝ ⎠ where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.
Page 170: Usb Endpoint Index Register (Usbepin - 0Xe010 9.7.16 C248)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device On reset, only the control endpoints are realized. Other endpoints, if required, are realized by programming the corresponding bits in USBReEp. To calculate the required EP_RAM space for the realized endpoints, see Section 13–9.4.1.
Page 171: Usb Maxpacketsize Register (Usbmaxpsize - 0Xe010 C24C)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.4.4 USB MaxPacketSize register (USBMaxPSize - 0xE010 C24C) On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer addresses within the EP_RAM to be recalculated.
Page 172: Usb Receive Packet Length Register (Usbrxplen - 0Xe010 C220)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.5.2 USB Receive Packet Length register (USBRxPLen - 0xE010 C220) This register contains the number of bytes remaining in the endpoint buffer for the current packet being read via the USBRxData register, and a bit indicating whether the packet is valid or not.
Page 173: Usb Control Register (Usbctrl - 0Xe010 C228)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write only register.
Page 174: Usb Command Code Register (Usbcmdcode - 0Xe010 C210)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.6.1 USB Command Code register (USBCmdCode - 0xE010 C210) This register is used for sending the command and write data to the SIE. The commands written here are propagated to the SIE and executed there. After executing the command, the register is empty, and the CCEMPTY bit of USBDevIntSt register is set.
Page 175 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 151. USB DMA Request Status register (USBDMARSt - address 0xE010 C250) bit allocation Reset value: 0x0000 0000 Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24 Symbol EP23 EP22 EP21 EP20...
Page 176: C280)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device This register allows software to raise a DMA request. This can be useful when switching from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is not raised by hardware.
Page 177 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 156. USB EP DMA Status register (USBEpDMASt - address 0xE010 C284) bit description Symbol Value Description Reset value EP0_DMA_ENABLE Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).
Page 178: Usb Dma Interrupt Status Register (Usbdmaintst - 0Xe010 C290)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 158. USB EP DMA Disable register (USBEpDMADis - address 0xE010 C28C) bit description Symbol Value Description Reset value EP0_DMA_DISABLE Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).
Page 179: Usb End Of Transfer Interrupt Status Register (Usbeotintst - 0Xe010 C2A0)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 160. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xE010 C294) bit description Symbol Value Description Reset value NDDR New DD Request Interrupt enable bit. The New DD Request Interrupt is disabled.
Page 180: Usb New Dd Request Interrupt Status Register (Usbnddrintst - 0Xe010 C2Ac)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 163. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0xE010 C2A8) bit description Symbol Value Description Reset value Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0...
Page 181: Usb System Error Interrupt Status Register (Usbsyserrintst - 0Xe010 C2B8)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0xE010 C2B8) If a system error (AHB bus error) occurs when transferring the data or when fetching or updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read only register.
Page 182: Slave Mode
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet has been successfully transmitted or when a NAK...
Page 183 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device interrupt event on Slave mode from other Endpoints USBEpIntSt USBDevIntSt FRAME EP_FAST EP_SLOW USBDevIntPri[0] USBEpIntEn[n] USBEpIntPri[n] USBDevIntPri[1] ERR_INT USBDMARSt USBIntSt USB_INT_REQ_HP to NVIC USB_INT_REQ_LP USB_INT_REQ_DMA to DMA engine EN_USB_INTS USBEoTIntST DMA Mode...
Page 184: Serial Interface Engine Command Description
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11. Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action).
Page 185: Set Address (Command: 0Xd0, Data: Write 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 170. SIE command code table Command name Recipient Code (Hex) Data phase Device commands Set Address Device Write 1 byte Configure Device Device Write 1 byte Set Mode Device Write 1 byte...
Page 186: Set Mode (Command: 0Xf3, Data: Write 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 172. Configure Device Register bit description Symbol Description Reset value CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0).
Page 187: Read Current Frame Number
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number returns least significant byte first. In case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read.
Page 188: Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 174. Set Device Status Register bit description Bit Symbol Value Description Reset value SUS_CH Suspend (SUS) bit change indicator. The SUS bit can toggle because: • The device goes into the suspended state.
Page 189: Read Error Status (Command: 0Xfb, Data: Read 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 175. Get Error Code Register bit description Symbol Value Description Reset value Error Code. 0000 No Error. 0001 PID Encoding Error. 0010 Unknown PID. 0011 Unexpected Packet - any packet sequence violation from the specification.
Page 190: Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional)) The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM. Optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s).
Page 191: Select Endpoint/Clear Interrupt
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 177. Select Endpoint Register bit description Bit Symbol Value Description Reset value B_2_FULL The buffer 2 status. Buffer 2 is empty. Buffer 2 is full. Reserved, user software should not write ones to reserved bits.
Page 192: Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 178. Set Endpoint Status Register bit description Bit Symbol Value Description Reset value Disabled endpoint bit. The endpoint is enabled. The endpoint is disabled. RF_MO Rate Feedback Mode. Interrupt endpoint is in the Toggle mode.
Page 193: Usb Device Controller Initialization
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the Validate Buffer command and cleared when the data has been sent on the USB bus and the buffer is empty.
Page 194: Slave Mode Operation
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device – Set EOT, DDR, and ERR bits in USBDMAIntEn. 9. Install USB interrupt handler in the NVIC by writing its address to the appropriate vector table location and enabling the USB interrupt in the NVIC.
Page 195: Data Transfer For In Endpoints
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 13.3 Data transfer for IN endpoints When writing data to an endpoint buffer, WR_EN (Section 13–9.5.5 “USB Control register (USBCtrl - 0xE010 C228)”) is set and software writes to the number of bytes it is going to...
Page 196: Triggering The Dma Engine
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs for unrealized endpoints and endpoints disabled for DMA operation are ignored and can be set to a NULL (0x0) value.
Page 197: Next_Dd_Pointer
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device DDs are placed in the USB RAM. These descriptors can be located anywhere in the USB RAM at word-aligned addresses. USB RAM is part of the system memory that is used for the USB purposes.
Page 198 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 180. DMA descriptor Word Access Access Description position (H/W) (S/W) position DD_retired (To be initialized to 0) DD_status (To be initialized to 0000): 0000 - NotServiced 0001 - BeingServiced 0010 - NormalCompletion...
Page 199: Dd_Retired
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.4.6 DMA_buffer_length This indicates the depth of the DMA buffer allocated for transferring the data. The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor.
Page 200: Ls_Byte_Extracted
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.4.11 LS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length has been extracted. The extracted size is reflected in the DMA_buffer_length field, bits 23:16.
Page 201: Transferring The Data
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device If a new descriptor has to be read, the DMA engine will calculate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD start address at location zero is considered invalid.
Page 202: Setting Up Dma Transfers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device USB transfer end completion - If the current packet is fully transferred and its size is less than the Max_packet_size field, and the end of the DMA buffer is still not reached, the USB transfer end completion occurs.
Page 203: Out Endpoints
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device The isochronous packet size is stored in memory as shown in figure 32. Each word in the packet size memory shown is divided into fields: Frame_number (bits 31 to 17), Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet size memory for a given DD should be DMA_buffer_length words in size –...
Page 204: Out Transfers In Atle Mode
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Next_DD_Pointer NULL DMA_buffer_length Max_packet_size Isochronous_endpoint Next_DD_Valid DMA_mode 0x000A DMA_buffer_start_addr 0x80000000 Present_DMA_Count ATLE settings Packet_Valid DD_Status DD_Retired Isocronous_packetsize_memory_address 0x60000000 after 4 packets 0x000A0010 FULL 0x80000035 frame_ number Packet_Valid Packet_Length EMPTY 0x60000010 data memory packet size memory Fig 45.
Page 205 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device data to be sent data in packets data to be stored in USB by host driver as seen on USB RAM by DMA engine DMA_buffer_start_addr 160 bytes 64 bytes of DD1 160 bytes...
Page 206: In Transfers In Atle Mode
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer.
Page 207: Ending The Packet Transfer
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from the USB RAM. Then the EOT interrupt will be generated.
Page 208 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2.
Page 209: Isochronous Endpoints
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For...
Page 210 UM10316 Chapter 14: LPC29xx USB Host controller Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The USB host controller is available on LPC2030 and LPC2939 only. 2. Introduction This section describes the host portion of the USB 2.0 OTG dual role core which integrates the host controller (OHCI compliant), device controller and I2C.
Page 211: Pin Description
UM10316 NXP Semiconductors Chapter 14: LPC29xx USB Host controller 2.2 Architecture The architecture of the USB host controller is shown below in Figure 14–47. register interface (AHB slave) REGISTER INTERFACE port port 1 HOST CONTROL port 2 CONTROLLER LOGIC/ DMA interface...
Page 212: Usb Host Usage Note
UM10316 NXP Semiconductors Chapter 14: LPC29xx USB Host controller Table 182. USB OTG port pins Pin name Direction Description Pin category U2PWRD2 Port power status Host power switch USB_OVRCR2 Over-current status Host power switch USB_HSTEN2 Host enabled status Control 3.1.1 USB host usage note Both ports can be configured as USB hosts.
Page 213: Usb Host Register Definitions
UM10316 NXP Semiconductors Chapter 14: LPC29xx USB Host controller Table 183. USB Host register address definitions …continued Name Address Function Reset value HcDoneHead 0xE010 C030 Contains the physical address of the last transfer descriptor added to the ‘Done’ queue. HcFmInterval...
Page 214 UM10316 Chapter 15: LPC29xx USB OTG interface Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The USB device controller is available in LPC2927/29, LPC2930, and LPC2939 only. Note that the host controller is not implemented on the LPC2927 and LPC2929. Depending on the LPC29xx part, different USB port configurations are available.
Page 215 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface For USB connections that use the device or host controller only (not OTG), the ports use an embedded USB Analog Transceiver (ATX). TRANSCEIVER register interface CONTROLLER (AHB slave) REGISTER INTERFACE port...
Page 216 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 185. USB OTG port pins Pin name Direction Description Interfacing USB_OVRCR1 Over-current status USB host Port 2 USB_VBUS2 status input. When this function is not enabled via its corresponding SFSP register, it is driven HIGH internally.
Page 217 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 5.1 Suggested USB interface solutions DD(IO) VBUS USB_RST1 RESET_N ADR/PSW 33 Ω OE_N/INT_N DD(IO) Mini-AB SPEED 33 Ω connector ISP1302 SUSPEND SS(IO), USB_SCL1 SS(CORE) USB_SDA1 USB_INT1 INT_N USB_D+1 USB_D−1 DD(IO) USB_UP_LED1...
Page 218 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface DD(IO) USB_UP_LED1 SS(IO), SS(CORE) 33 Ω USB_D+1 33 Ω USB_D−1 D− USB-A connector 15 kΩ 15 kΩ DD(IO) USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA OUTA DD(IO) LM3526-L OUTB LPC293X USB_PPWR2 FLAGB USB_OVRCR2 USB_PWRD2 33 Ω...
Page 219 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface DD(IO) USB_UP_LED1 SS(IO), SS(CORE) 33 Ω USB_D+1 33 Ω USB_D−1 D− USB-A connector 15 kΩ 15 kΩ DD(IO) USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA OUTA LM3526-L LPC293X USB_UP_LED2 DD(IO) USB_CONNECT2 SS(IO), SS(CORE) 33 Ω...
Page 220: Usb Interrupt Status Register (Usbintst - )
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 186. USB OTG and I C register address definitions Name Address Access Function OTGTmr 0xE010 C114 OTG Timer C registers I2C_RX 0xE010 C300 I2C Receive I2C_TX 0xE010 C300 I2C Transmit...
Page 221: Otg Interrupt Enable Register (Otginten - 0Xe010 C104)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 188. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description Symbol Description Reset Value Timer time-out. REMOVE_PU Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.
Page 222: Otg Timer Register (Otgtmr - 0Xe010 C114)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 189. OTG Status Control register (OTGStCtrl - address 0xE010 C110) bit description Symbol Description Reset Value PORT_FUNC Controls port function. Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds.
Page 223: Otg Clock Control Register
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 6.8 OTG Clock Control Register (OTGClkCtrl - 0xE010 CFF4) This register controls the clocking of the OTG controller. Whenever software wants to access the registers, the corresponding clock control bit needs to be set. The software does not have to repeat this exercise for every register access, provided that the corresponding OTGClkCtrl bits are already set.
Page 224: Otg Clock Status Register
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 192. OTG_clock_status register (OTGClkSt - address 0xE010 CFF8) bit description Symbol Value Description Reset Value I2C_CLK_ON I2C clock status. I2C clock is not available. I2C clock is available. OTG_CLK_ON OTG clock status.
Page 225: I2C Status Register (I2C_Sts - 0Xe010 C304)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 6.12 I2C Status Register (I2C_STS - 0xE010 C304) The I2C_STS register provides status information on the TX and RX blocks as well as the current state of the external buses. Individual bits are enabled as interrupts by the I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.
Page 226: I2C Control Register (I2C_Ctl - 0Xe010 C308)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 195. I2C status register (I2C_STS - address 0xE010 C304) bit description Symbol Value Description Reset Value The current value of the SDA signal. Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data.
Page 227: I2C Clock High Register (I2C_Clkhi - 0Xe010 C30C)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 196. I2C Control register (I2C_CTL - address 0xE010 C308) bit description Symbol Value Description Reset Value DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.
Page 228 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 6.15 I2C Clock Low Register (I2C_CLKLO - 0xE010 C310) The CLK register holds a terminal count for counting 48 MHz clock cycles to create the low period of the slower I C serial clock, SCL.
Page 229 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 7. HNP support This section describes the hardware support for the Host Negotiation Protocol (HNP) provided by the OTG controller. When two dual-role OTG devices are connected to each other, the plug inserted into the mini-AB receptacle determines the default role of each device.
Page 230 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface OHCI HOST STACK CONTROLLER USB BUS CONTROLLER STACK DEVICE DEVICE CONTROLLER STACK ISP1301 CONTROLLER Fig 53. USB OTG controller with software stack 7.1 B-device: peripheral to host switching In this case, the default role of the OTG controller is peripheral (B-device), and it switches roles from Peripheral to Host.
Page 231 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface idle B_HNP_TRACK = 0 B_HNP_TRACK = 1 ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED bus suspended ? disconnect device controller from U1 PU_REMOVED set? set REMOVE_PU PU_REMOVED set? reconnect port U1 to the...
Page 232 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK REMOVE_PU set? remove D+ pull-up, set PU_REMOVED go to go to b_wait_acon b_peripheral HNP_FAILURE set? add D+ pull-up HNP_SUCCESS set? go to b_host Fig 55.
Page 233 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x006;...
Page 234 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface idle A_HNP_TRACK = 0 A_HNP_TRACK = 1 ? set HNP_FAILURE, clear A_HNP_TRACK disconnect host controller from U1 bus suspended ? resume detected ? connnect host controller back to U1 bus reset detected?
Page 235 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend TMR set? HNP_SUCCESS set?
Page 236 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210;...
Page 237 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0)
Page 238 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface ahb_slave_clk cclk REGISTER PCUSB INTERFACE ahb_master_clk CLOCK SWITCH AHB_CLK_ON ahb_need_clk AHB_CLK_EN CLOCK dev_dma_need_clk DEVICE USB CLOCK SWITCH CONTROLLER DIVIDER usbclk dev_need_clk DEV_CLK_ON (48 MHz) DEV_CLK_EN CLOCK host_dma_need_clk HOST SWITCH CONTROLLER host_need_clk...
Page 239 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk.
Page 240 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface ahb_slave_clk cclk REGISTER PCUSB INTERFACE ahb_master_clk CLOCK SWITCH AHB_CLK_ON ahb_need_clk AHB_CLK_EN CLOCK dev_dma_need_clk DEVICE USB CLOCK SWITCH CONTROLLER DIVIDER usbclk dev_need_clk DEV_CLK_ON (48 MHz) DEV_CLK_EN CLOCK host_dma_need_clk HOST SWITCH CONTROLLER host_need_clk...
Page 241 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk.
Page 242 UM10316 Chapter 16: LPC29xx General Purpose Input/Output (GPIO) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Available ports depend on the pin configuration for each part. Table 199.
Page 243: Chapter 16: Lpc29Xx General Purpose Input/Output (Gpio)
UM10316 NXP Semiconductors Chapter 16: LPC29xx General Purpose Input/Output (GPIO) The signal line is normally pulled up to a HIGH voltage level (logic 1) by an external resistor. Each of the devices connected to the signal line can either drive the signal line to a LOW voltage level (logic 0) or stay at high impedance (open-drain).
Page 244 UM10316 NXP Semiconductors Chapter 16: LPC29xx General Purpose Input/Output (GPIO) Table 201. PINS register bit description (PINS0 to 5, addresses 0xE004 A000 (GPIO0), 0xE004 B000 (GPIO1), 0xE004 C000 (GPIO2), 0xE004 D000 (GPIO3), 0xE004 E000 (GPIO4), 0xE004 F000 (GPIO5)) Symbol Access Value...
Page 245 UM10316 NXP Semiconductors Chapter 16: LPC29xx General Purpose Input/Output (GPIO) Table 203. DR register bit description (DR0 to 5, addresses 0xE004 A008 (GPIO0), 0xE004 B008 (GPIO1), 0xE004 C008 (GPIO2), 0xE004 D008 (GPIO3), 0xE004 E008 (GPIO4), 0xE004 F008 (GPIO5)) * = reset value...
Page 246: Chapter 17: Lpc29Xx Timer 0/1/2/3
UM10316 Chapter 17: LPC29xx timer 0/1/2/3 Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Note that capture pins CAP0 and CAP1 on timer 1 are not pinned out for LPC2927/29 and LPC2921/23/25. 2.
Page 247: Timer Counter And Interrupt Timing
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 3. Timer counter and interrupt timing Each timer consists of a prescale counter (PR register) and a timer counter (TC register). The prescale counter is incremented at every cycle of the system clock. As soon as the prescale counter matches the prescale value contained in the PV register it is reset to 0 and the timer counter is incremented.
Page 248: Timer Match Functionality
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 CLK(SYS) Prescale Counter (PC) Timer Counter (TC) Timer Counter (TC) reached Timer Interrupt Match Value (MRx=6) (active low) PR=2, MRx=6 Fig 63. Stop-on-match timing 4. Timer match functionality The timer block contains four match circuits, each of which can be programmed with an individual match value and a specific action-on-match.
Page 249: Timer Register Overview
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 5. Timer register overview The timer registers are shown in table Table 17–204. They have an offset to the base address TMR RegBase which can be found in the memory map, see Section 2–2.
Page 250: Timer Control Register (Tcr)
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 204. Timer register overview (base address: E004 1000h (timer 0), E004 2000h (timer 1), E004 3000h (timer 2), E004 4000h (timer 3), E00C 0000h (MSCSS timer 0, E00C1000h (MSCSS timer 1)) …continued...
Page 251 UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 5.3 Timer prescale register The timer prescale register determines the number of clock cycles used as a prescale value for the timer counter clock. When the Prescale_Register value is not equal to zero the internal prescale counter first counts the number of CLK_TMRx cycles as defined in this register plus one, then increments the TC_value.
Page 252 UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 208. MCR register bits …continued * = reset value Variable name Access Value Description RESET_2 Reset on match MR2 and TC. When logic 1 the timer counter is reset if MR2 matches TC STOP_1 Stop on match MR1 and TC.
Page 253 UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 209. EMR register bits …continued * = reset value Variable name Access Value Description 5 and 4 CTRL_0[1:0] External match control 0 Do nothing Set logic 0 Set logic 1 Toggle...
Page 254 UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 211. CCR register bits …continued * = reset value Variable name Access Value Description RISE_3 Capture on capture input 3 rising. When logic 1, a sequence of logic 0 followed by...
Page 255 UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 212. CR register bits * = reset value Variable name Access Value Description 31 to 0 CR[31:0] Capture register. This reflects the timer-counter captured value after a capture event 0000 00 00h* 5.9 Timer interrupt bit description...
Page 256: Chapter 18: Lpc29Xx Spi0/1/2
UM10316 Chapter 18: LPC29xx SPI0/1/2 Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The LPC29xx contains three Serial Peripheral Interface (SPI) modules to enable synchronous serial communication with slave or master peripherals that have either Motorola SPI or Texas Instruments synchronous serial interfaces.
Page 257 UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 In normal transmission mode software programs the settings of the SPI module, writes data to the transmit FIFO and then enables the SPI module. The SPI module transmits until all data has been sent, or until it gets disabled with data still unsent. When data needs to be transmitted to another slave software has to re-program the settings of the SPI module, write new data and enable the SPI module again.
Page 258: Spi Register Overview
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Transmit FIFO Slave 1 Slave 2 Slave 3 Slave 4 Fig 64. Sequential-slave mode: example It is possible to temporarily suspend or skip one or more of the slaves in a transfer. To do...
Page 259 UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 214. SPI register overview (base address: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) Address Access Reset value Name Description Reference offset 000h 0001 0000h SPI_CONFIG Configuration register Table 18–215 004h...
Page 260: Spi Configuration Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 3.1 SPI configuration register The SPI configuration register configures SPI operation mode. Table 215. SPI_CONFIG register bit description (SPI_CONFIG0/1/2, addresses: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) * = reset value...
Page 261: Spi Slave-Enable Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 215. SPI_CONFIG register bit description (SPI_CONFIG0/1/2, addresses: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) …continued * = reset value Symbol Access Value Description SLAVE_DISABLE Slave-output disable (only relevant in slave...
Page 262 UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 216. SLV_ENABLE register bit description (SLV_ENABLE0/1/2, addresses: 0xE004 7004 (SPI0), 0xE004 8004 (SPI1), 0xE004 9004 (SPI2)) * = reset value Symbol Access Value Description 31 to 8 reserved Reserved; do not modify. Read as logic 0...
Page 263: Spi Receive-Fifo Read-Mode Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 218. FIFO_DATA register bit description (FIFO_DATA0/1/2: addresses 0xE004 700C (SPI0), 0xE004 800C (SPI1), 0xE004 900C (SPI2)) * = reset value Symbol Access Value Description 31 to reserved Reserved; do not modify. Read as logic 0...
Page 264: Spi Dma Settings Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 220. RX_FIFO_READMODE register bit description (RX_FIFO_READMODE0/1/2: addresses 0xE004 7014 (SPI0), 0xE004 8014 (SPI1), 0xE004 9014 (SPI2)) * = reset value Symbol Access Value Description 31 to 1 reserved Reserved; do not modify. Read as logic 0...
Page 265: Spi Status Register (Status)
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 221. DMA_SETTINGS register bit description (DMA_SETTINGS0/1/2: addresses 0xE004 7018 (SPI0), 0xE004 8018 (SPI1), 0xE004 9018 (SPI2)) …continued * = reset value Symbol Access Value Description RX_DMA_BURST 000* - Defines when the SPI will request a Rx burst DMA transfer.
Page 266: Spi Slave-Settings 1 Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 222. SPI status-register bit description (STATUS0/1/2, addresses: 0xE004 701C (SPI0), 0xE004 801C (SPI1), 0xE004 901C (SPI2)) …continued * = reset value Symbol Access Value Description TX_FIFO_FULL Transmit FIFO full bit Transmit FIFO full...
Page 267: Spi Slave-Settings 2 Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 3.10 SPI slave-settings 2 register The SPI second slave-settings register configures several other parameters for each slave of the SPI module. Remark: Some bits in this register are only relevant in master mode, and each individual slave has its own register with parameters.
Page 268: Spi Fifo Interrupt Threshold Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 224. SLVn_SETTINGS2 register bit description (SLV0/1/2_SETTINGS2, addresses: 0xE004 7028/30/38/40 (SPI0), 0xE004 8028/30/38/40 (SPI1), 0xE004 9028/30/38/40 (SPI2)) …continued * = reset value Symbol Access Value Description Serial clock phase (only used if Motorola SPI mode is selected).
Page 269 UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 225. INT_THRESHOLD register bit description (INT_THRESHOLD, addresses: 0xE004 7FD4 (SPI0), 0xE004 8FD4 (SPI1), 0xE004 9FD4 (SPI2)) * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0...
Page 270: Chapter 19: Lpc29Xx Universal Asynchronous Receiver/Transmitter (Uart)
UM10316 Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter (UART) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. The modem control features are pinned out on the LPC2939/30 only. Therefore, registers MCR, MSR and RS485DLY are available on LPC2939/30 only 2.
Page 271: Register Description
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 227. UART0/1 Pin description Type Description UART0/1 DCD Input Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged. In normal operation of the modem interface (MCR[4]=0), the complement value of this signal is stored in MSR[7].
Page 272 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 228. UART Register Map ( base address 0xE004 5000 (UART0) and 0xE004 6000 (UART1)) Generic Description Bit functions and addresses...
Page 273 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 228. UART Register Map ( base address 0xE004 5000 (UART0) and 0xE004 6000 (UART1)) Generic Description Bit functions and addresses...
Page 274: Uartn Receiver Buffer Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 4.1 UARTn Receiver Buffer Register The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest”...
Page 275: Uartn Interrupt Enable Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 232. UARTn Divisor Latch MSB Register (U0DLM - address 0xE004 5004, U1DLM - 0xE004 6004 when DLAB = 1) bit description Symbol Description Reset Value DLMSB The UARTn Divisor Latch MSB Register, along with the U0DLL 0x00 register, determines the baud rate of the UARTn.
Page 276 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 234. UARTn Interrupt Identification Register (U0IIR - address 0xE004 5008, U1IIR - 0xE004 6008, Read Only) bit description Symbol Value Description Reset Value IntStatus Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].
Page 277 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in 3.5 to 4.5 character times.
Page 278: Uartn Fifo Control Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 4.6 UARTn FIFO Control Register The UnFCR controls the operation of the UARTn Rx and TX FIFOs. Table 236. UARTn FIFO Control Register (U0FCR - address 0xE004 5008, U1FCR - 0xE004 6008, Write Only) bit description...
Page 279: Uart0/1 Modem Control Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 237. UARTn Line Control Register (U0LCR - address 0xE004 500C, U1LCR - 0xE004 600C) bit description Bit Symbol Value Description Reset Value 1:0 Word Length 5 bit character length Select...
Page 280: Auto-Flow Control
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 238: UART0/1 Modem Control Register (U0MCR - address 0xE004 5010, U1MCR - 0xE004 6010) bit description Symbol Value Description Reset value Loopback The modem loopback mode provides a mechanism to perform Mode diagnostic loopback testing.
Page 281: Auto-Cts
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Example: Suppose the UART operating in type 550 has trigger level in FCR set to 0x2 then if Auto-RTS is enabled the UART will deassert the RTS output as soon as the receive FIFO contains 8 bytes.
Page 282: Uartn Line Status Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter UART1 TX start bits0..7 stop start bits0..7 stop start bits0..7 stop CTS1 pin Fig 66. Auto-CTS Functional Timing While starting transmission of the initial character the CTS1 signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS1 is deasserted (high).
Page 283: Uart0/1 Modem Status Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 240. UARTn Line Status Register (U0LSR - address 0xE004 5014, U1LSR - 0xE004 6014, Read Only) bit description Bit Symbol Value Description Reset Value Framing Error When the stop bit of a received character is a logic 0, a (FE) framing error occurs.
Page 284: Uartn Scratch Pad Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 241: UARTn Modem Status Register (U0MSR - address 0xE004 5018, U1MSR - 0xE004 6018, Read Only) bit description Bit Symbol Value Description Reset Value Delta Set upon state change of input CTS. Cleared on an MSR read.
Page 285 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 243. UARTn Auto-baud Control Register (U0ACR - 0xE004 5020, U1ACR - 0xE004 6020) bit description Symbol Value Description Reset value Start This bit is automatically cleared after auto-baud completion. Auto-baud stop (auto-baud is not running).
Page 286 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter • The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn is set and the auto-baud rate measurement counter overflows). • The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn is set and the auto-baud has completed successfully).
Page 287 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
Page 288 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 244. UARTn Fractional Divider Register (U0FDR - address 0xE004 5028, U1FDR - 0xE004 6028) bit description Function Value Description Reset value DIVADDVAL Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
Page 289 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 290 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 245. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538...
Page 291 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 19–246 describes how to use TXEn bit in order to achieve software flow control. Table 246. UARTn Transmit Enable Register (U0TER - address 0xE004 5030, U1TER - 0xE004 6030) bit description...
Page 292 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 4.16 UART0 RS485 Address Match register Table 248. UART0 RS485 Address Match register (U0/1RS485ADRMATCH - 0xE004 50450/0xE004 6050) bit description Symbol Description Reset value ADRMATCH Contains the address match value. 0x00 4.17 UART1 RS-485 Delay value register...
Page 293 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO.
Page 294 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by the UARTn TX block. The UnBRG clock input source is the APB clock (BASE_UART_CLK). The main clock is divided down per the divisor specified in the UnDLL and UnDLM registers.
Page 295 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter UnTX NTXRDY TXDn UnTHR UnTSR UnBRG UnDLL NBAUDOUT UnDLM RCLK UnRX NRXRDY INTERRUPT RXDn UnRBR UnRSR UnIER UnINTR UnIIR UnFCR UnLSR UnSCR UnLCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE UART_CLK Fig 69.
Page 296: Chapter 20: Lpc29Xx Watchdog Timer (Wdt)
UM10316 Chapter 20: LPC29xx WatchDog Timer (WDT) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The purpose of the Watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state.
Page 297: Watchdog Register Overview
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 250. Watchdog programming steps Step Normal mode Debug mode Write 0x251D8951 (key exor Write time-out value (e.g.0x0000FFFF) counter_enable) to the Watchdog Timer to the Watchdog time-out register. Control register. The timer is now started This indicates time-out reset at 65,536 clock cycles.
Page 298: Watchdog Timer-Control Register
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 251. Watchdog timer register overview (base address 0xE004 0000) Address Access Reset value Name Description Reference offset FD4h 0000 00C8h reserved Reserved FD8h 0000 0101h INT_CLR_ENABLE Interrupt clear-enable register Table 10–93...
Page 299: Watchdog Timer Counter
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 252. WTCR register bit description (WTCR, address: 0xE004 0000) …continued * = reset value Variable name Access Value Description COUNTER_RESET Reset timer and prescale counter. If this bit is set the counters remain reset until it is...
Page 300 UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) 4.4 Watchdog timer key register The Watchdog timer key register contains a protection code to be used when accessing the other Watchdog timer registers to prevent accidental alteration of these registers. The value is hard-wired and can only be read, not modified.
Page 301 UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 257. WD_DEBUG register bit description (WD_DEBUG, address: 0xE004 0040) * = reset value Variable name Access Value Description 31 to 1 WD_KEY Protection key, see above. Writes to the WD_DEBUG register are ignored if a value...
Page 302: Chapter 21: Lpc29Xx Can 0/1
UM10316 Chapter 21: LPC29xx CAN 0/1 Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. CAN functional description Figure 21–70 gives a brief overview of the main blocks in the CAN gateway controller. This consists of two identical CAN controllers working as independent CAN nodes.
Page 303: Can Bus Timing
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 4. CAN bus timing 4.1 Baud-rate prescaler The period of the CAN system clock, t , is programmable and determines individual bit timing. The CAN system clock is calculated using the following equation:...
Page 304: Can Transmit Buffers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 clk(sys) Baud rate prescaler clk(sys) CAN: SYNCSEG TSEG1 TSEG2 nominal bit time TSEG1 Sync. TSEG1 TSEG2 Sync. Seg. Seg . e.g. BRP = 00000001b TSEG1 = 0101b TSEG2 = 010b Fig 71. General structure of a bit-period 5.
Page 305: Automatic Transmit-Priority Protection
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 5.2 Automatic transmit-priority protection To allow uninterrupted streams of transmit messages, the CAN controller provides automatic transmit-priority detection for all transmit buffers. Depending on the selected transmit priority mode (TPM) in the mode register, internal prioritization is based on the CAN identifier or a user-defined local priority.
Page 306: Can Controller Self-Test
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 7. CAN controller self-test The CAN controller supports two options for self-tests: • Global self-test: setting the self-reception request bit in normal operating mode • Local self-test: setting the self-reception request bit in self-test mode Both self-tests use the self-reception feature of the CAN controller.
Page 307: Can Global Acceptance Filter
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 TX Buffer TX Buffer TX Buffer Transceiver RX Buffer Fig 73. Local self-test (example for high-speed CAN bus) A message transmission is initiated by setting the self-reception request bit SRR in conjunction with the selected message buffer(s) STB3, STB2 and STB1.
Page 308 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11-BIT index 0 11-BIT index 1 11-BIT index 2 11-BIT index 3 standard frame h entries format FullCAN identifier section 11-BIT index (h−2) 11-BIT index (h−1) CASFESA 11-BIT index (h) 11-BIT index (h+1)
Page 309 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 260. Standard frame-format FullCAN identifier section …continued Symbol Description 15 to 13 SCC Odd index: CAN controller number Odd index: message disable bit. Logic 0 is message enabled and logic 1 is message disabled...
Page 310 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 The semaphore operates in the following manner: • SEM[1:0] = 01: Acceptance filter is in the process of updating the buffer • SEM[1:0] = 11: Acceptance Filter has finished updating the buffer •...
Page 311 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 262. Standard frame-format explicit identifier section …continued Symbol Description Odd index: message disable bit. Logic 0 is message enabled and logic 1 is message disabled Not used 10 to 0 ID[28:18] Odd index: 11-bit CAN 2.0 B identifier...
Page 312: Can Acceptance Filter Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 264. Extended frame-format explicit identifier section Symbol Description EFF_GRP_ start address 31 to 29 SCC CAN controller number 28 to 0 ID[28:0] 29-bit CAN 2.0 B identifier 8.5 Extended frame-format group identifier section...
Page 313: Section Start-Registers Of The Id Look-Up Table Memory
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Use the ID ready interrupt IDI and the receive interrupt RI. In this mode all CAN messages are accepted and stored in the receive buffers of active CAN Controllers. With the activated FullCAN Mode, received FullCAN messages are automatically stored by the acceptance filter in the FullCAN message-object section (see also Section 21–13...
Page 314 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Each CAN identifier is linked to an ID Index number (see also Figure 21–76 Figure 21–86). For a CAN identifier match, the matching ID index is stored in the identifier index IDI of the message info register CCRXBMI for the appropriate CAN controller (see Section 21–6.1...
Page 315 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 It is possible to disable the 5Ah identifier in the FullCAN section. Then, the screening process would be finished with the match in the explicit identifier section. The first group in the group identifier section has been defined so that incoming CAN messages with identifiers of 5Ah up to 5Fh are accepted on SCC 0.
Page 316 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 266. CAN register overview …continued Address Access Reset value Name Description Reference offset 0000 0000h CCRXBID CAN controller receive- buffer identifier register Table 21–277 0000 0000h CCRXBDA CAN controller receive- buffer data A register Table 21–278...
Page 317 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 266. CAN register overview …continued Address Access Reset value Name Description Reference offset 000h CAEFESA CAN acceptance-filter extended frame explicit Table 21–287 start-address register 000h CAEFGSA CAN acceptance-filter extended frame group Table 21–288...
Page 318 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 267. CCMODE register bit description (CCMODE, address 0xE008 0000 (CAN0) and 0xE008 1000 (CAN1)) * = reset value; **both reset value and soft reset mode value Symbol Access Value Description 31 to 6 reserved Reserved;...
Page 319: Can Controller Command Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 9.2 CAN controller command register The CAN controller command register initiates an action in the transfer layer of the CAN controller. The CCCMD register is write-only. Table 21–268 shows the bit assignment of the CCCMD register.
Page 320: Can Controller Global Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 It is possible to select more than one message buffer for transmission. If more than one buffer is selected (TR = 1 or SRR = 1) the internal transmit-message queue is organized so that, depending on the transmit- priority mode TPM, the transmit buffer with the lowest CAN identifier (ID) or the lowest 'local priority' (TXPRIO) wins the prioritization and is sent first.
Page 321 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 269. CCGS register bit description (CCGS, address 0xE008 0008 (CAN0) and 0xE008 1008 (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value Description...
Page 322: Can Controller Interrupt And Capture Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 When the transmit error counter exceeds the limit of 255 the BS bit is set to 1(bus-off), the CAN controller sets the soft reset mode bit to 1 (present) and an error warning interrupt is generated if enabled. Afterwards the transmit error counter is set to 127 and the receive error counter is cleared.
Page 323 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 270. CAN controller interrupt and capture register bit description (CCIC, address 0xE008 000C (CAN0) and 0xE008 100C (CAN1)) * = reset value; **both reset value and soft reset mode value Symbol...
Page 324 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 270. CAN controller interrupt and capture register bit description (CCIC, …continued address 0xE008 000C (CAN0) and 0xE008 100C (CAN1)) * = reset value; **both reset value and soft reset mode value...
Page 325 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 271. Bus error capture code values ERRCC [4:0] Function 0 0000 Reserved 0 0001 Reserved 0 0010 Identifier bits 21 to 28 0 0011 Start of frame 0 0100 Standard frame RTR bit...
Page 326: Can Controller Interrupt-Enable Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 9.5 CAN controller interrupt-enable register The CAN controller interrupt-enable register CCIE enables the different types of CAN controller interrupts. Table 21–272 shows the bit assignment of the CCIE register. Table 272. CAN controller interrupt-enable register bit descriptioN (CCIE, address 0xE008...
Page 327: Can Controller Bus Timing Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 272. CAN controller interrupt-enable register bit descriptioN (CCIE, address 0xE008 0010 (CAN0) and 0xE008 1010 (CAN1)) * = reset value Symbol Access Value Description EWIE Error warning interrupt-enable An interrupt is generated if either the error...
Page 328: Can Controller Error-Warning Limit Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 273. CAN controller bust timing register bit description (CCBT, address 0xE008 0014 (CAN0) and 0xE008 1014 (CAN1)) …continued * = reset value Symbol Access Value Description 13 to 10 reserved Reserved; do not modify. Read as logic 0...
Page 329: Can Controller Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 9.8 CAN controller status register The CAN controller status register CCSTAT reflects the transmit status of all three transmit buffers, and also the global status of the CAN controller itself. The register is read-only.
Page 330 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 275. CAN controller status register bit description (CCSTAT, address 0xE008 001C (CAN0) and 0xE008 101C (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value...
Page 331: Can Controller Receive-Buffer Message Info Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 275. CAN controller status register bit description (CCSTAT, address 0xE008 001C (CAN0) and 0xE008 101C (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value...
Page 332: Can Controller Receive Buffer Identifier Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 276. CAN controller receive-buffer message info register bit description (CCRXBMI, address 0xE008 0020 (CAN0) and 0xE008 1020 (CAN1)) * = reset value Symbol Access Value Description Frame format An extended frame-format message has been...
Page 333: Can Controller Receive Buffer Data A Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 277. CAN controller receive buffer identifier register bit description (CCRXBID, address 0xE008 0024 (CAN0) and 0xE008 1024 (CAN1)) * = reset value Symbol Access Value Description 31 to 29 reserved Reserved; do not modify. Read as logic 0...
Page 334: Can Controller Transmit-Buffer Message Info Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 279. CAN controller receive-buffer data B register bit description (CCRXBDB, address 0xE008 002C (CAN0) and 0xE008 102C (CAN1)) * = reset value Symbol Access Value Description 31 to 24 DB8[7:0] Data byte 8. If the data-length code value is...
Page 335: Can Controller Transmit-Buffer Identifier Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 280. CAN controller transmit-buffer message info register bit description (CCTXB1/2/3MI, addresses 0xE008 0030, 0xE008 0040, 0xE008 0050 (CAN0), and 0xE008 1030, 0xE008 1040, 0xE008 1050 (CAN1)) …continued * = reset value...
Page 336 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 21–282 shows the bit assignment of the CCTXB1DA, CCTXB2DA and CCTXB3DA registers. Table 282. CAN controller transmit-buffer data A registers register bit description (CCTXB1/2/3DA, addresses 0xE008 0038, 0xE008 0048, 0xE008 0058 (CAN0), and...
Page 337: Can Acceptance-Filter Register Overview
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 283. CAN controller transmit-buffer data B register bit description (CCTX1/2/3DB, addresses 0xE008 003C, 0xE008 004C, 0xE008 005C (CAN0), and 0xE008 103C, 0xE008 104C, 0xE008 105C (CAN1)) …continued * = reset value...
Page 338: Can Acceptance-Filter Standard-Frame Explicit 12.1 Start-Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 10.2 CAN acceptance-filter standard-frame explicit start-address register The CAN acceptance filter standard-frame explicit start-address register CASFESA defines the start address of the section of explicit standard identifiers in the acceptance-filter look-up table. It also indicates the size of the section of standard identifiers which the acceptance filter will search.
Page 339: Can Acceptance-Filter Extended-Frame Explicit 12.3 Start-Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 286. CAN acceptance-filter standard-frame group start-address register bit description (CASFGSA, address 0xE008 7008) * = reset value Symbol Access Value Description 31 to 12 reserved Reserved; do not modify. Read as logic 0...
Page 340: Can Acceptance-Filter Extended-Frame Group Start-Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 287. CAEFESA register bit description (CAEFESA, address 0xE008 700C) …continued * = reset value Symbol Access Value Description 11 to 2 EFESA[9:0] Extended-frame explicit start address. This register defines the start address of the section of explicit extended identifiers in acceptance-filter look-up table.
Page 341: Can Acceptance-Filter End Of Look-Up Table Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 10.6 CAN acceptance-filter end of look-up table address register The CAN acceptance filter end of look-up table address register CAEOTA contains the end-address of the acceptance-filter look-up table. Table 21–289 shows the bit assignment of the CAEOTA register.
Page 342: Global Fullcaninterrupt Enable Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 290. CAN acceptance-filter look-up table error address register bit description (CALUTEA, address 0xE008 7018) * = reset value Symbol Access Value Description 31 to 11 reserved Reserved; do not modify. Read as logic 0...
Page 343: Can Controller Central Transmit-Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 293. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0xE008 7024) bit description Symbol Description Reset Value IntPnd0 FullCan Interrupt Pending bit 0. IntPndx (0<x<31) FullCan Interrupt Pending bit x.
Page 344: Can Controller Central Receive-Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 10.12 CAN controller central receive-status register The CAN controller central receive-status register CCCRS provides bundled access to the reception status of all CAN controllers. The status flags are the same as those in the status register of the corresponding CAN controller.
Page 345: Fullcan Mode
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 297. CAN controller central miscellaneous-status register bit description * = reset value Symbol Access Value Description 31 to 10 reserved Reserved; do not modify. Read as logic 0 CAN controller 1 bus status...
Page 346: Fullcan Message Layout
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 • The Standard Frame Individual Start Address Register (SFF_sa) must be greater than or equal to the number of IDs for which automatic receive storage is to be done, times two. SFF_sa must be rounded up to a multiple of 4 if necessary.
Page 347 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 299. FullCAN semaphore operation SEM1 SEM0 activity Acceptance Filter is updating the content Acceptance Filter has finished updating the content CPU is in process of reading from the Acceptance Filter Prior to writing the first data byte into a message object, the Acceptance Filter will write the FrameInfo byte into the according buffer location with SEM[1:0] = 01.
Page 348 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 START read 1st word SEM == 01? this message has not been SEM == 11? received since last check clear SEM, write back 1 st word read 2nd and 3rd words read 1st word...
Page 349: Fullcan Interrupts
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only.
Page 350: Message Lost Bit And Can Channel Number
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Message Message disable bit disable bit Index 0, 1 11-bit CAN ID 11-bit CAN ID FullCAN Explicit Index 2, 3 11-bit CAN ID 11-bit CAN ID Standard Frame Index 4, 5 11-bit CAN ID...
Page 351: Setting The Interrupt Pending Bits (Intpnd 63 To 0)
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set).
Page 352: Scenario 2: Message Lost
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx Write write write write read clear read read read look-up ID, SEM table access MsgLostx message processor handler access access Fig 80. Normal case, no messages lost 11.3.2 Scenario 2: Message lost...
Page 353: Scenario 3: Message Gets Overwritten Indicated By Semaphore Bits
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler.
Page 354: Scenario 3.2: Message Gets Overwritten Indicated By Message Lost
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx write write clear write write write read clear write write write read read read read read read look-up table access 1st Object 2nd Object write write 2nd Object 1st Object read...
Page 355: Scenario 4: Clearing Message Lost Bit
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx look-up write write write write write write read write write write clear read read read write write write table access 1st Object 2nd Object 3rd Object write write write...
Page 356: Can Configuration Example 1
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx write write write write write write write write write read clear read read write write write read look-up table access 1st Object 2nd Object 3rd Object write write write...
Page 357: Group Of Standard Frame-Format Identifier Section (11-Bit Can Id)
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 12.2 Group of standard frame-format identifier section (11-bit CAN ID) The start address of the group of the standard frame-format section is defined in the CASFGSA register with a value of 10h. The end of this section is defined in the CAEFESA register.
Page 358 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Message Message disable bit disable bit Index CASFESA ID28 ID28 ID18 ID18 = 00h Explicit Standard ID28 ID18 ID18 ID28 Frame Format ID28 ID18 ID28 ID18 Identifier Section Disabled, 7 ID28 ID28...
Page 359: Fullcan Explicit Standard Frame-Format Section (11-Bit Can Id)
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 301. Used ID look-up table sections of example 2 ID-look-up table section Usage Group of standard frame format Not Activated Explicit extended frame format Not Activated Group of extended frame format Not Activated 13.1 FullCAN explicit standard frame-format section (11-bit CAN ID)
Page 360 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Message Message disable bit disable bit Index FullCAN Disabled, 1 ID28 ID28 ID18 ID18 Explicit Standard ID28 ID18 ID18 ID28 Frame Format ID28 ID28 ID18 ID18 Identifier Section ID28 ID28 ID18 ID18...
Page 361 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 • To disable a group of identifiers the message-disable bit must be set for both the upper and lower bounds. UM10316_0 © NXP B.V. 2008. All rights reserved. User manual Rev. 00.06 — 17 December 2008...
Page 362: Lin Functional Description
UM10316 Chapter 22: LPC29xx LIN 0/1 Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The LIN block is identical for all LPC29xx parts. 2. LIN functional description Each LIN master controller can be used as a dedicated LIN master with additional support for sync-break generation.
Page 363: Lin Sync-Break Generation
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 When the LIN master is sending response fields (master sending; slave receiving), the specified number of data fields stored in the message buffer is transmitted automatically. The checksum field is generated and sent after the data fields.
Page 364: Line-Clamped Detection Versus Bit-Error Detection
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 • RXD/TXD line-clamped errors All wake-up or error conditions can be enabled as interrupts. Bit-errors and RXD/TXD line-clamped errors can only be detected when the LIN master is actively transmitting. The only exception to this is that during reception of slave responses stop-bit errors can also be detected.
Page 365: Slave-Not-Responding Error And The Lin Master Time-Out Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 The wake-up interrupt service routine should be written so that the wake-up response frame from the LIN Master is not sent immediately. To give a slave-ready time the LIN master has to wait for about 100 ms before sending the wake-up response frame (according to the LIN specification, see Ref.
Page 366: Lin Master-Controller Mode Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 303. LIN master-controller register overview (base address: 0xE008 8000 (LIN0), 0xE008 9000 (LIN1)) Address Access Reset value Name Description Reference 0000 0000h LDATA LIN master-controller message buffer data A Table 22–314...
Page 367: Lin Master-Controller Command Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 305. LIN master-controller configuration register bit description * = reset value Symbol Access Value Description 31 to 8 reserved Reserved; do not modify. Read as logic 0 SWPA Software ID parity...
Page 368 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 306. LIN master-controller command register register bit description …continued * = reset value Symbol Access Value Description Transmit request Transmission of a complete LIN message will be initiated. This bit is cleared automatically 4.4 LIN master-controller fractional baud rate generator register...
Page 369 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 307. LIN master-controller fractional baud-rate generator register bit description …continued Symbol Access Value Description 19 to 16 FRAC Fractional value. Contains the 4-bit fraction of the baud division 15 to 0 Integer value.
Page 370 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Header fields Response fields Case 1: Master: sending, Slave: receiving Master: sending, Slave: receiving DD = 0 Transmit message complete interrupt Case 2: Master: sending, Slave: receiving Master: sending, Slave: receiving DD = 1...
Page 371 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 308. LIN master-controller status register bit description …continued * = reset value Symbol Access Value Description Idle status The LIN bus is idle The LIN bus is active Error status A bit-error or line-clamped error condition was detected No errors have been detected.
Page 372 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 309. LIN master-controller interrupt and capture register bit description * = reset value Symbol Access Value Description 31 to 12 reserved Reserved; read as logic 0 11 to 8 EC[3:0] Error capture...
Page 373 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 309. LIN master-controller interrupt and capture register bit description …continued * = reset value Symbol Access Value Description Bit-error interrupt The error-capture bits represent detailed status in the case of •...
Page 374 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 310. LIN master-controller interrupt enable register bit description …continued * = reset value Symbol Access Value Description NRIE Slave-not-responding error interrupt enable Results in the corresponding interrupt when the slave response has not completed within the...
Page 375 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 311. LIN master-controller checksum register bit description * = reset value Symbol Access Value Description 31 to 8 reserved Reserved; do not modify. Read as logic 0 7 to 0 LIN message checksum. When the LIN master...
Page 376 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Figure 22–92 below shows, the time-out period depends on the response time of the LIN slaves, and also on the number of data fields and the checksum field. +40% response(nominal) Header Slave Response: Data Field(s) + Checksum Field...
Page 377 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 message buffer the CPU should always read the message-buffer access bit first to determine whether an access is possible or not. In cases where the message buffer is locked a write-access will not succeed, but a read-access will deliver logic 0 as a result.
Page 378 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 313. LIN message-identifier register bit description …continued * = reset value Symbol Access Value Description LIN message-parity bit 1 LIN message-parity bit 0 5 to 0 LIN message identifier 00h* The rest of the message buffer contains the LIN message-data registers LDATA, LDATB, LDATC and LDATD.
Page 379 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 Table 316. LDATC register bit description …continued * = reset value Symbol Access Value Description 23 to 16 DF11[7:0] LIN message-data field 11 00h* 15 to 8 DF10[7:0] LIN message-data field 10...
Page 380 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN 0/1 All LIN message activity is initiated by the LIN master. By sending a LIN header (see Ref. 32–6) the LIN master determines the configuration of the response. The response can be sent either by the master or the slave.
Page 381: Chapter 23: Lpc2Xx I2C-Interface
UM10316 Chapter 23: LPC2xx I2C-interface Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Features • C0 and I C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I C-bus) and do not support powering off of individual devices connected to the same bus lines.
Page 382: Pin Description
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I C bus will not be released. Each of the two I...
Page 383: Master Transmitter Mode
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the master mode, the I C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer.
Page 384: Master Receiver Mode
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 6.2 Master Receiver mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition...
Page 385: Slave Transmitter Mode
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 321. I2CnCONSET used to configure Slave mode Symbol I2EN Value I2EN must be set to 1 to enable the I C function. AA bit must be set to 1 to acknowledge its own slave address or the general call address. The STA, STO and SI bits are set to 0.
Page 386: C Implementation And Operation
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface SLAVE ADDRESS DATA DATA “0” - write “1” - read data transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) from Master to Slave A = Not acknowledge (SDA high) from Slave to Master...
Page 387 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface ADDRESS REGISTER I2ADR COMPARATOR INPUT FILTER OUTPUT SHIFT REGISTER STAGE I2DAT BIT COUNTER/ ARBITRATION & SYNC LOGIC PCLK INPUT TIMING & FILTER CONTROL LOGIC interrupt OUTPUT SERIAL CLOCK STAGE GENERATOR I2CONSET CONTROL REGISTER & SCL DUTY...
Page 388: Address Register I2Addr
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 7.2 Address Register I2ADDR This register may be loaded with the 7 bit slave address (7 most significant bits) to which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (0x00) recognition.
Page 389: Serial Clock Generator
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space”...
Page 390: Status Decoder And Status Register
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface The contents of the I C control register may be read as I2CONSET. Writing to I2CONSET will set bits in the I C control register that correspond to ones in the value written.
Page 391: I 2 C Control Set Register
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 322. I C register map (base address 0xE008 2000 (I2C0) and 0xE008 3000 (I2C1)) Generic Description Access Reset Cn Register Name value Name & Address I2CONCLR I2C Control Clear Register. When a one is written to...
Page 392 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 323. I C Control Set Register (I2C[0/1]CONSET - addresses: 0xE008 2000, 0xE008 3000) bit description Bit Symbol Description Reset Value 1:0 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 393: I 2 C Status Register
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface SI is the I C Interrupt Flag. This bit is set when the I C state changes. However, entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case.
Page 394: C Slave Address Register (I2C[0/1]Adr - 0Xe008 200C, 0Xe008 300C)
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 325. I C Data Register ( I2C[0/1]DAT - addresses 0xE008 2008, 0xE008 3008) bit description Bit Symbol Description Reset Value 7:0 Data This register holds data values that have been received, or are to be transmitted.
Page 395 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I C bus specification defines the SCL low time and high time at different values for a 400 kHz I rate.
Page 396: C Monitor Mode Control Register (I2Mmctrl: I2C0, I2Cmmctrl0 - 0Xe008 201C; I2C1, I2C1Mmctrl- 0Xe008 301C)
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET register. Writing 0 has no effect. I2ENC is the I C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the I2CONSET register.
Page 397: Interrupt In Monitor Mode
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode). 8.8.1 Interrupt in Monitor mode All interrupts will occur as normal when the module is in monitor mode. This means that...
Page 398: C Slave Address Registers (I2Adr0 To 3: I2C0, I2C0Adr[0, 1, 2, 3]- 0Xe008 20[0C, 20, 24, 28]; I2C1, I2C1Adr[0, 1, 2, 3] - Address 0Xe008 30[0C, 20, 24, 28])
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 332. I C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER - 0xE008 202C; I2C1, I2C1DATA_BUFFER- 0xE008 302C) bit description Bit Symbol Description Reset value 7:0 Data This register holds contents of the 8 msb’s of the I2DAT shift register.
Page 399: Details Of I C Operating Modes
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 334. I C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] - 0xE008 20[30, 34, 38, 3C]; I2C1, I2C1MASK[0, 1, 2, 3] - address 0xE008 30[30, 34, 38, 3C]) bit...
Page 400 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 336. I2CONSET used to initialize Master Transmitter mode Symbol I2EN Value The I C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be set to logic 1 to enable the I C block.
Page 401 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface The upper 7 bits are the address to which the I C block will respond when addressed by a master. If the LSB (GC) is set, the I C block will respond to the general call address (0x00);...
Page 402 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR Data byte...
Page 403 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
Page 404 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
Page 405 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface reception of the own Slave address and one or more Data DATA DATA P OR S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched...
Page 406 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 339. Master Transmitter mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 407 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 340. Master Receiver mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 408 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 341. Slave Receiver Mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 409 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 341. Slave Receiver Mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 410 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 342. Tad_105: Slave Transmitter mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 411: Miscellaneous States
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 9.5 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I C hardware state (see Table 23–343). These are discussed below. 23.9.5.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set.
Page 412: Some Special Cases
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface Table 343. Miscellaneous states Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI 0xF8...
Page 413: C Bus Obstructed By A Low Level On Scl Or Sda
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I C bus is possible.
Page 414: C State Service Routines
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface time limit STA flag STO flag SDA line SCL line start condition Fig 107. Forced access to a busy I C bus STA flag SDA line SCL line start condition (1) Unsuccessful attempt to send a start condition.
Page 415: I 2 C Interrupt Service
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface The I C hardware now begins checking the I C bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information.
Page 416: I 2 C Interrupt Routine
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up the Master Receive buffer.
Page 417: Master Transmitter States
UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 10.7 Master Transmitter states 10.7.1 State : 0x18 Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK has been received.
Page 418 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 10.7.5 State : 0x38 Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new Start condition will be transmitted when the bus is free again.
Page 419 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 1. Read data byte from I2DAT into Master Receive buffer. 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit 10.9 Slave Receiver states...
Page 420 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit 10.9.5 State : 0x80 Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read.
Page 421 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.10 Slave Transmitter States 10.10.1 State : 0xA8 Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received.
Page 422 UM10316 NXP Semiconductors Chapter 23: LPC2xx I2C-interface 3. Exit 10.10.5 State : 0xC8 The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit.
Page 423: Chapter 24: Lpc29Xx Modulation And Sampling Control Subsystem (Mscss)
UM10316 Chapter 24: LPC29xx Modulation and Sampling Control Subsystem (MSCSS) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Note that the ADC0 is available on LPC2927/29, LPC2930, and LPC2939 only.
Page 424 UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of MSCSS timer 0 to start the PWM after a pre-programmed delay. This sync signal is cascaded through all PWMs, allowing a programmable delay offset between subsequent PWMs.
Page 425: Mscss Miscellaneous Operations
UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem ADC2_EXT_START ADC1_EXT_START ADC0_EXT_START pause_0 ADC0 pause ADC1 MSCSS TIMER 0 ADC2 pause_0 PWM0 MSCSS PWM1 TE_i TIMER 1 PWM2 TE_o TE_i trap PWM3 TE_o TE_i trap TE_o TE_i trap...
Page 426 UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem • Capture inputs to measure time between events • Synchronization between several PWM signals • Synchronization between ADCs • Synchronization between PWMs and ADCs • Timed and synchronized renewal of settings •...
Page 427 UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem To generate a sine wave, the sine period can be divided into N periods. In each of these a fixed voltage is generated via PWM0, having a much shorter period compared to the sine itself.
Page 428: Chapter 25: Lpc29Xx Pulse Width Modulator (Pwm)
UM10316 Chapter 25: LPC29xx Pulse Width Modulator (PWM) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The MSCSS contains four PWM blocks to allow generation and capture of all kinds of square waveforms.
Page 429: Functional Description
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) TRANS_EN_IN pin is high (update triggered by MSCSS Timer0 match3 output of TRANS_EN_OUT of previous PWM block). If TRANS_ENA_SEL is low shadowing is controlled via software. PWM in continuous mode, sync_out...
Page 430: Pwm Counter Synchronization
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) MTCHDEACT 16-bit internal counter PWM0 MTCHACT PWM0 output Sync_in_0 Sync_out_0 Global programmable sync_delay PWM1 output Sync_in_1 Sync_out_1 Sync_out_0 Fig 111.PWM operation 4.1 PWM counter synchronization Several PWMs can be synchronized using TRANS_ENABLE_IN and TRANS_ENABLE_OUT (see Section 25–5.1...
Page 431: Center-Aligned Pwm
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) PWM in continuous mode, sync_out Write first configuration Configure PWM0 output 0, activated, sync_in to PWM, duty cycle 25% disable trap and carrier and shadow-register update triggered by timer match...
Page 432: Pwm Register Overview
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Timer1 output Internal PWM output Fig 113.Modulation of PWM and timer carrier Figure 25–113 illustrates the carrier signal (Timer1, 50% duty cycle) the internal PWM signal and the modulated output signal of the PWM. The flowchart below shows how to...
Page 433 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 345. PWM register overview (base address: 0xE00C 5000 (PWM0), 0xE00C 6000 (PWM1), 0xE00C …continued 7000 (PWM2), 0xE00C 8000 (PWM3)) Address Access Reset Name Description Reference Value 014h 0000 FFFF The cycle period (minus 1) of all PWM Table 25–352...
Page 434 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 345. PWM register overview (base address: 0xE00C 5000 (PWM0), 0xE00C 6000 (PWM1), 0xE00C …continued 7000 (PWM2), 0xE00C 8000 (PWM3)) Address Access Reset Name Description Reference Value 800h 0000 0000h MODECTLS Mirror the synchronized MODECTL Table 25–359...
Page 435: Pwm Shadow Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 345. PWM register overview (base address: 0xE00C 5000 (PWM0), 0xE00C 6000 (PWM1), 0xE00C …continued 7000 (PWM2), 0xE00C 8000 (PWM3)) Address Access Reset Name Description Reference Value A14h 0000 0000h MTCHDEACTS(5) Mirror the de-activation match shadowed Table 25–368...
Page 436 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) The counting process starts once the CNT_ENA bit is set. The counting process can be reset by setting the CNT_RESET bit. The PWM counter and prescale counter remain in the reset state as long as the CNT_RESET bit is active.
Page 437: Pwm Trap Control Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 346. MODECTL register bit description …continued * = reset value Symbol Access Value Description RUN_ONCE PWM counter stops at the end of current cycle CNT_RESET Synchronously reset PWM counter and prescale counter.
Page 438: Pwm Capture Control Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.4 PWM capture control register The APB PWM has three capture registers, and the capture behavior of the associated CAPT registers and pins is controlled by the CAPCTL register. The CNT register value is captured synchronously with the system clock.
Page 439: Pwm Control Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 350. CAPSRC register bit description …continued * = reset value Symbol Access Value Description 1 and 0 CAPT_SRC0[1:0] Select the source of capture channel 0 to trigger capture of the PWM...
Page 440: Pwm Prescale Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 25–352 shows the bit assignment of the PRD register. Table 352. PRD register bit description * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0...
Page 441: Pwm Match Active Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 355. CNT register bit description * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0 15 to 0 PWM counter value 0000h* 5.11 PWM match active registers...
Page 442: Pwm Capture Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.13 PWM capture registers There are four CAPT registers per PWM, one for each external PWM capture channel. Section 25–5.5 for selecting the source for each capture register and the limitations of capture channel 3.
Page 443: Pwm Capture Control Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 25–360 shows the bit assignment of the TRPCTLS register. Table 360. TRPCTLS register bit description * = reset value Symbol Access Value Description 30 to 17 reserved Reserved; do not modify. Read as logic 0...
Page 444: Pwm Control Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 362. CAPTSRCS register bit description * = reset value Symbol Access Value Description 30 to 6 reserved reserved; do not modify. Read as logic 0 7 and 6 CAPT_SRC_SYNC3[1:0]...
Page 445: Pwm Prescale Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.20 PWM prescale shadow register The PRSCS register is the shadow register of the PRSC register. It mirrors the values used in the PWM domain. See Section 25–5.1 for more information on the principle of shadow registers.
Page 446: Pwm Match Deactive Shadow Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.23 PWM match deactive shadow registers The MTCHDEACTS registers are the shadow registers of the MTCHDEACT registers. They mirror the values used in the PWM domain. See Section 25–5.1 for more information about the principle of the shadow registers.
Page 447 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 370. PWM Match interrupt sources Register Interrupt source Description 31 to 12 unused Unused MTCHDEACT5 PWM counter value matching MTCHDEACT5 MTCHDEACT0 PWM counter value matching MTCHDEACT0 MTCHACT5 PWM counter value matching MTCHACT5...
Page 448: Chapter 26: Lpc29Xx Analog-To-Digital Converter (Adc)
UM10316 Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. ADC0 is available in LPC2927/29, LPC2930, and LPC2939 only. 2.
Page 449: Clock Distribution
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) The main control of the ADC is via the ADC control register (ACON). This register allows enabling or disabling the ADC, defining the scan mode – single-shot or continuous – and the channel trigger mode, and it also contains the notification of whether a conversion is running or finished.
Page 450: Register Overview
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) 3. Register overview The ADC registers are shown in Table 26–372. They have an offset to the base address ADC RegBase which can be found in the memory map; see Section 2–2.
Page 451 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 372. ADC register overview (base address: 0xE00C 2000 (ADC0), 0xE00C 3000 (ADC1), 0xE00C 4000 …continued Address Access Reset Name Description Reference value 110h 0000h COMP4 ADC channel 4 compare register Table 26–374...
Page 452 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 372. ADC register overview (base address: 0xE00C 2000 (ADC0), 0xE00C 3000 (ADC1), 0xE00C 4000 …continued Address Access Reset Name Description Reference value 22Ch 0000h ACD11 ADC channel 11 conversion data register Table 26–375...
Page 453 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 373. ACCn register bit description (ACC0 to 15, addresses 0xE00C 2000 to 0xE00C203C (ADC0), 0xE00C 3000 to 0xE00C303C (ADC1), 0xE00C 4000 to 0xE00C403C (ADC2)) * = reset value Symbol Access Value...
Page 454 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 374. COMPn register bit description (COMP0 to 15, addresses 0xE00C 2100 to 0xE00C213C (ADC0), 0xE00C 3100 to 0xE00C313C (ADC1), 0xE00C 4100 to 0xE00C413C (ADC2)) * = reset value Symbol Access Value...
Page 455 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 376. COMP_STATUS register bit description(COMP_STATUS addresses 0xE00C 2300 (ADC0), 0xE00C 3300 (ADC1), 0xE00C 4300 (ADC2)) …continued * = reset value Symbol Access Value Description COMP_STATUS_0 Compare match of channel 0 No compare match of channel 0 3.5 Compare-status clear register...
Page 456 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 378. ADC_CONFIG register bit description (ADC_CONFIG addresses, 0xE00C 2400 (ADC0), 0xE00C 3400 (ADC1), 0xE00C 4400 (ADC2) * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0...
Page 457 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) • The start bit (0): when set to 1 the ADC conversion is started. • The stop bit (1): when set to 1 the conversion is stopped at the end of the next scan.
Page 458 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 380. ADC_STATUS register bit description (ADC_STATUS addresses, 0xE00C 2408 (ADC0), 0xE00C 3408 (ADC1), 0xE00C 4408 (ADC2) * = reset value Symbol Access Value Description 31 to 2 reserved Reserved; do not modify. Read as logic 0...
Page 459: Chapter 27: Lpc29Xx Quadrature Encoder Interface (Qei)
UM10316 Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The MSCSS includes a quadrature encoder interface (QEI) with the following features: •...
Page 460 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) VELOCITY velocity interrupt TIMER (TIM_Int) VELOCITY RELOAD low velocity interrupt VELOCITY (LVEL_Int) COMPARE VELOCITY CAPTURE index Ph A VELOCITY DIGITAL QUAD COUNTER FILTER Ph B DECODER BASE_MSCSS_CLK encoder clock interrupt...
Page 461: Quadrature Input Signals
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 4. Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel.
Page 462: Digital Input Filtering
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 384. Encoder direction DIR bit DIRINV bit direction forward reverse reverse forward 4.1.2 Digital input filtering All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of sample clocks is user programmable from 1 to 4,294,967,295.
Page 463: Velocity Compare
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Fig 117.Encoder and velcoity divider operation The following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges) where: •...
Page 464: Pin Description
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 5. Pin description Table 385. QEI pin description Pin name Description 6. Register description 6.1 Register summary Table 386. Register summary Symbol Address Description Control registers QEICON 0xE00C 9000 Control register...
Page 465: Control Registers
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 6.2 Control registers 6.2.1 QEI Control (QEICON) This register contains bits which control the operation of the position and velocity counters of the QEI module. This register can be set by software, but only hardware can reset the register bits.
Page 466: Position, Index And Timer Registers
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 6.3 Position, index and timer registers 6.3.1 QEI Position (QEIPOS) This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.
Page 467 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 394: QEI Position Compare Register 2 (CMPOS2 - 0xE00C 901C) Symbol Description Reset value 0:31 Current position value. 6.3.6 QEI Index Count (INXCNT) This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.
Page 468 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 399: QEI Velocity Register (QEIVEL - 0xE00C 9030) Symbol Description Reset value 0:31 Current velocity pulse count. 6.3.11 QEI Velocity Capture (QEICAP) This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer...
Page 469 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 403: QEI Interrupt Status Register (QEIINTSTAT - 0xE00C 9FE0) Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occured VELC_Int Indicates that captured velocity is less than compare velocity.
Page 470 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 404: QEI Interrupt Set Register (QEISET - 0xE00C 9FEC) Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occured VELC_Int Indicates that captured velocity is less than compare velocity.
Page 471 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 405: QEI Interrupt Clear Register (QEICLR - 0xE00C 9FE8) Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occured VELC_Int Indicates that captured velocity is less than compare velocity.
Page 472 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 406: QEI Interrupt Enable Register (QEIIE - 0xE00C 9FE4) Symbol Description Reset value INX_Int Indicates that an index pulse was detected. TIM_Int Indicates that a velocity timer overflow occured VELC_Int Indicates that captured velocity is less than compare velocity.
Page 473 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 407: QEI Interrupt Enable Set Register (QEIIES - 0xE00C 9FDC) Symbol Description Reset value INX_EN Indicates that an index pulse was detected. TIM_EN Indicates that a velocity timer overflow occured VELC_EN Indicates that captured velocity is less than compare velocity.
Page 474 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 408: QEI Interrupt Enable Clear Register (QEIIEC - 0xE00C 9FD8) Symbol Description Reset value INX_EN Indicates that an index pulse was detected. TIM_EN Indicates that a velocity timer overflow occured VELC_EN Indicates that captured velocity is less than compare velocity.
Page 475: Chapter 28: Lpc29Xx Flash/Eeprom
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM UM10316 Chapter 28: LPC29xx Flash/EEPROM Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter Flash configurations vary for the different LPC29xx parts. Table 409. Feature overview Part Flash size...
Page 476: Flash Memory Layout
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM In the following sections access to the Flash Memory Controller via software is described. Access via the JTAG interface is described in Section 29–1. 2.1 Flash memory layout The flash memory is arranged into sectors, pages and flash-words Figure 28–119.
Page 477: Flash Memory Writing
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM For optimal read performance the flash memory contains two internal 128-bit buffers. The configuration of these buffers and the number of wait-states for unbuffered reads can be set in the FMC, see Ref.
Page 478: Flash Signature Generation
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM • Protect sectors (optional). Remark: During the burn process the internal clock of the flash module must be enabled. Remark: Only erased flash-word locations can be written to. Remark: A complete page should be burned at one time. Before burning it again the corresponding sector should be erased.
Page 479: Flash Memory Index-Sector Features
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM • END_OF_BURN; indicates the completion of burning a page. • END_OF_ERASE; indicates the completion of erasing one or more sectors. • END_OF_MISR; indicates the completion of signature generation. Generation of an interrupt can be enabled (INT_SET_ENABLE register) or disabled (INT_CLR_ENABLE register) for each of these interrupt sources.
Page 480: Index Sector Programming
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM • Sector security Remark: It is not possible to erase the index sector. As a result the sector is write-only and enabled features cannot be disabled again. In the following sections these features and the procedures to enable them are described in detail.
Page 481 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM register to ‘1’ (see Section 6–3.2) before the Reset Timer times out. If the counter has expired before the SEC_DIS is set, the JTAG will remain locked. The counter runs off OSC1M, and the counter register is 1024 bits.
Page 482: Eeprom Functional Description
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 413. Sector security values Flash-word value Description All bits ‘1’ Corresponding sector is Read/Write (default) All bits ‘0’ Corresponding sector is Read-Only Remark: After enabling flash memory security, this feature is not activated until the next reset.
Page 483: Eeprom Operations
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM At power-up the reset should be applied for at least 100 μs. However a normal reset (not at power-up) period is only 40 ns. The longer reset period at power-up relates to the bandgap of the FLASH and EEPROM devices.
Page 484 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM write command register write address register - or - write address register write command register write data register write data register write operation on EEPROM now starts Fig 123. Starting a write operation A write operation causes an automatic post-increment of the address.
Page 485: Programming
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM • In case the default address post-incrementing is used the upper boundary of the page register may not be crossed. • Before reading the just written data the contents of the page register needs to be programmed into non-volatile memory.
Page 486: Error Responses
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM write address register (address A) write command register operation on E E P R O M now starts read readdata register Fig 126. Starting a read operation (read from address A) If the read data register is read while the read operation is still pending, then the read transfer on the system bus is stalled by de-asserting the ready signal until the previous read operation is finished.
Page 487 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 414. Flash Memory Controller register overview (base address 0x2020 0000) Address Access Reset Name Description Reference offset Value Flash registers 000h 0005h FCTR Flash control register Table 28–415 004h reserved Reserved register; do...
Page 488: Flash Memory Control Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 414. Flash Memory Controller register overview (base address 0x2020 0000) …continued Address Access Reset Name Description Reference offset Value 098h EEPWRDWN <tbd> EEPROM power-down/start DCM register 09Ch EEMSSTART EEPROM BIST start address register...
Page 489: Preset Data Latches
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 415. FCTR register bit description (FTCR, address: 0x2020 0000) * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0 FS_LOADREQ Data load request.
Page 490: Flash Memory Program-Time Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 415. FCTR register bit description (FTCR, address: 0x2020 0000) …continued * = reset value Symbol Access Value Description FS_WEB Program and erase enable. Program and erase disabled. Program and erase enabled. FS_WRE Program and erase selection.
Page 491: Flash Test Control Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Burn time (t ) to be programmed can be calculated from the following formula: wr pg -------------------------------- - × clk sys Table 28–416 shows the bit assignment of the FPTR register. Table 416. FPTR register bit description (FPTR, address: 0x2020 0008)
Page 492: Flash Bridge Wait-States Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 417. FTCTR - FLASH test control register (FTCTR, address 0x2020 000C) Bits Acce Reset Field name Description value 13:1 FS_HVSS(1:0) FS_HVSS(1:0) selects which internal signal will be on pin 000 enppsc 001 enpndc...
Page 493: Flash-Memory Clock Divider Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Asynchronous reading: acc addr > --------------------- - – tclk sys Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active.
Page 494: Flash-Memory Bist Control Registers
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.6 Flash-memory BIST control registers The flash-memory Built-In Self Test (BIST) control registers control the embedded BIST signature generation. This is implemented via the BIST start-address register FMSSTART and the stop-address register FMSSTOP.
Page 495: Flash Interrupts
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 421. FMSSTOP register bit description (FMSSTOP, address: 0x2020 0024) * = reset value Symbol Access Value Description 31 to 18 reserved Reserved; do not modify. Read as logic 0, write as logic 0.
Page 496: Fmc Interrupt Bit Description
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Completion of these operations is checked via the interrupt status register (INT_STATUS). This can be done either by polling the corresponding interrupt status or by enabling the generation of an interrupt via the interrupt enable register (INT_SET_ENABLE).
Page 497: Eeprom Address Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 427. EEPROM command register bit description (EECMD - address 0x2020 0080) Bits Access Reset Field name Description value Command 000 : 8-bit read 001 : 16-bit read 010 : 32-bit read 011 : 8-bit write...
Page 498: Eeprom Write Data Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.11 EEPROM write data register The EEPROM write data register is used to write data into the page register (write operations). Writing this register will start the write operation as side-effect. If the post-increment bit in the command register is set, consecutive writes to this register can be done to write a burst of data.
Page 499: Eeprom Wait State Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.13 EEPROM wait state register The EEPROM controller has no awareness of absolute time, while for EEPROM operations several minimum absolute timing constraints have to be met. Therefore it can only derive time from its clock by frequency division. The user must program the wait state fields to appropriate values in this wait state register.
Page 500: Eeprom Clock Divider Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM wait state 1 wait state 2 wait state 3 su_a_we_n VALID DATA VALID DATA VALID DATA su_di_we_n VALID DATA VALID DATA VALID DATA BE_N su_be_n_we_n BE_N WE_N hw_we_n WE_N h_i_we_n Fig 127. Wait states in a write operation 3.14 EEPROM clock divider register...
Page 501 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Fclk ≈ ± ---------------------------------------------- - 375kH 6.67% divisionfactor Table 432. EEPROM clock divider register bit description (EECLKDIV - address 0x2020 0094) Bits Access Reset Field name Description value 15:0 CLKDIV Division factor (minus 1 encoded)
Page 502 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 435. EEPROM BIST stop address register bit description (EEMSSTOP - address 0x2020 00A0) Bits Access Reset Field name Description value STOPA BIST stop address: Bit 0 is fixed zero since only even addresses are allowed.
Page 503 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM • presetting data latches • writing • loading • burning • protecting In the remainder of this chapter these are described in more detail. UM10316_0 © NXP B.V. 2008. All rights reserved. User manual Rev.
Page 504 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM UNPROTECT sector(s) ERASE sector(s) PRESET data latches WRITE Word by hardware FlashWord complete? (auto) LOAD FlashWord Page complete? last FlashWord incomplete? LOAD FlashWord BURN page Sector(s) complete? PROTECT sector(s) Figure 1: flash programming Fig 128.
Page 505 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 437. Un(protect) trigger LOADREQ PROGREQ (un)protect A sector gets protected by writing an odd value to its base address, followed by the same trigger as for unprotecting. Although the flash module does not need the CRA clock to select a sector for (un)protecting, the CRA clock must already be enabled to ensure an active APB clock.
Page 506 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Although the flash module does not need the CRA clock to select a sector for erasure, the CRA clock must already be enabled to ensure an active APB clock. 4.1.4 Presetting data latches When only a part of a page has to be programmed, the data latches for the rest of the page must be preset to logical 1’s.
Page 507 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM ⋅ ⋅ ≥ 512 FPTR.TR tlw_web_write which is true for: tlw_web_write ----------------------------------- - FPTR.TR ⋅ 512 t The burning is started by writing a trigger value to the FCTR register. Table 442. Burn trigger value...
Page 508 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM tp_cl_ry_rr × ----------------------------- MISR duration FMSSTOP - FMSSTART + 1 clock period When signature generation is triggered via AHB or VPB, the duration is expressed in ahb_clk cycles. Polling the INT_STATUS.END_OF_MISR bit can also be used to check the completion of the signature generation.
Page 509 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM sign = 0 FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP FOR i = 0 TO 126 nextSign[i] = f_Q[address][i] XOR sign[i+1] nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR sign[27] XOR sign[29] sign = nextSign signature128 = sign Fig 130.
Page 510 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM sign = 0 FOR address = EEMSSTART.STARTA TO EEMSSTOP.STOPA FOR i = 0 TO 14 nextSign[i] = readdata[address][i] XOR sign[i+1] nextSign[15] = readdata[address][15] XOR sign[0] XOR sign[4] XOR sign[13] XOR sign[15] sign = nextSign signature16 = sign Fig 132.
Page 511: Chapter 29: Lpc29Xx Flash And Eeprom Jtag Programming
UM10316 Chapter 29: LPC29xx Flash and EEPROM JTAG programming Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter are <tbd>. UM10316_0 © NXP B.V. 2008. All rights reserved. User manual Rev.
Page 512: Chapter 30: Lpc29Xx General Purpose Dma (Gpdma) Controller
UM10316 Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions.
Page 513: Functional Description
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 4. Functional description This section describes the major functional blocks of the DMA Controller.
Page 514: Channel Logic And Channel Register Bank
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 4.1.4 Channel logic and channel register bank The channel logic and channel register bank contains registers and logic required for each DMA channel. 4.1.5 Interrupt request The interrupt request generates the interrupt to the ARM processor.
Page 515 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 443. Endian behavior Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[7:0] 21212121...
Page 516: Error Conditions
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 443. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane 1/[31:24] 1/[15:0] 12341234 2/[23:16]...
Page 517: Channel Hardware
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 4.1.7 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic.
Page 518: Dma Response Signals
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 4.2.1 DMA request signals The DMA request signals are used by peripherals to request a data transfer. The DMA request signals indicate whether a single or burst transfer of data is required and whether the transfer is the last in the data packet.
Page 519 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 445. Register summary …continued Address Name Description Reset state Access 0xE014 0028 DMACSoftLBReq DMA Software Last Burst Request Register 0xE014 002C DMACSoftLSReq DMA Software Last Single Request Register...
Page 520 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 445. Register summary …continued Address Name Description Reset state Access Channel 6 registers 0xE014 01C0 DMACC6SrcAddr DMA Channel 6 Source Address Register 0xE014 01C4 DMACC6DestAddr DMA Channel 6 Destination Address Register...
Page 521: Dma Interrupt Terminal Count Request Clear
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 5.3 DMA Interrupt Terminal Count Request Clear Register (DMACIntTCClear - 0xE014 0008) The DMACIntTCClear Register is write-only and clears one or more terminal count interrupt requests. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register (DMACIntTCStat) to be cleared.
Page 522: Dma Raw Error Interrupt Status Register (Dmacrawinterrstat - 0Xe014 0018)
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 451. DMA Raw Interrupt Terminal Count Status Register (DMACRawIntTCStat - 0xE014 0014) Name Function RawIntTCStat Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request.
Page 523: Dma Software Single Request Register (Dmacsoftsreq - 0Xe014 0024)
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 454. DMA Software Burst Request Register (DMACSoftBReq - 0xE014 0020) Name Function 15:0 SoftBReq Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 30–444...
Page 524: Dma Software Last Single Request Register (Dmacsoftlsreq - 0Xe014 002C)
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 5.12 DMA Software Last Single Request Register (DMACSoftLSReq - 0xE014 002C) The DMACSoftLSReq Register is read/write and enables DMA last single requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit.
Page 525: Dma Channel Registers
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 459. DMA Synchronization Register (DMACSync - 0xE014 0034) Name Function 15:0 DMACSync Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are disabled.
Page 526: Dma Channel Linked List Item Registers (Dmaccxlli - 0Xe014 01X8)
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller enabled. When the DMA channel is enabled the register is updated as the destination address is incremented and by following the linked list when a complete packet of data has been transferred.
Page 527 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 463. DMA channel control registers (DMACCxControl - 0xE014 01xC) Name Function Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.
Page 528: Channel Configuration Registers (Dmaccxconfig - 0Xe014 01X0)
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 463. DMA channel control registers (DMACCxControl - 0xE014 01xC) …continued Name Function 17:15 DBSize Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size.
Page 529 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Table 464. Channel Configuration registers (DMACCxConfig - 0xE014 01x0) Name Function 31:19 Reserved Reserved, do not modify, masked on read. Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests.
Page 530: Lock Control
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 5.20.1 Lock control The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig Register. When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock is deasserted.
Page 531: Disabling A Dma Channel
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 6.1.4 Disabling a DMA channel A DMA channel can be disabled in three ways: • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used.
Page 532 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 7. Write the channel configuration information into the DMACCxConfig register. If the enable bit is set then the DMA channel is automatically enabled. 6.2 Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMA Controller where the packet length is programmed by software before the DMA channel is enabled.
Page 533 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence occurs: 1. Program and enable the DMA channel. 2. Wait for a DMA request.
Page 534 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 9. If the transfer has completed it is indicated by the transfer count reaching 0 if the DMA Controller is performing flow control, or by the sending a DMA request if the peripheral is performing flow control.
Page 535 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller 1. Read the DMACIntTCStat Register to determine whether the interrupt was generated due to the end of the transfer (terminal count). A HIGH bit indicates that the transfer completed. If more than one request is active, it is recommended that the highest priority channels be checked first.
Page 536: Linked List Items
UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller The data to be transferred described by a LLI (referred to as the packet of data) usually requires one or more DMA bursts (to each of the source and destination).
Page 537 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Fig 134. LLI example The first LLI, stored at 0x20000, defines the first block of data to be transferred, which is the data stored between addresses 0x0A200 and 0x0AE00: •...
Page 538 UM10316 NXP Semiconductors Chapter 30: LPC29xx General Purpose DMA (GPDMA) controller Because the next LLI address is set to zero, this is the last descriptor, and the DMA channel is disabled after transferring the last item of data. The channel is probably set to generate an interrupt at this point to indicate to the ARM processor that the channel can be reprogrammed.
Page 539 UM10316 Chapter 31: LPC29xx ETM/ETB interface Rev. 00.06 — 17 December 2008 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Features • Closely tracks the instructions that the ARM core is executing. •...
Page 540: Etb Configuration
UM10316 NXP Semiconductors Chapter 31: LPC29xx ETM/ETB interface Table 467. ETM configuration Resource description Qty. Pairs of address comparators Data Comparators Memory Map Decoders Counters Sequencer Present External Inputs 4 (Not brought out) External Outputs 4 (Not brought out) FIFOFULL Present...
Page 541: Register Description
UM10316 NXP Semiconductors Chapter 31: LPC29xx ETM/ETB interface 6. Register description 6.1 ETM registers Please refer to ARM9 Embedded Trace Macrocell (ETM9) Technical Reference manual published by ARM 6.2 ETB registers Please refer to Embedded Trace Buffer Technical Reference manual published by ARM.
Page 542 UM10316 Chapter 32: LPC29xx Supplementary information Rev. 00.06 — 17 December 2008 User manual 1. Abbreviations Table 468. Abbreviations Acronym Description Analog to Digital Converter BEMF Back Electromotive Force BIST Built-In Self Test BLDCM Brushless Direct Current Motor BSDL Boundary-Scan Description Language Controller Area Network, see Ref.
Page 543 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 33. Glossary ADC — Analog to Digital Converter; converts an FMC — Flash Memory Controller; controller for the analog input value to a discrete integer value. internal flash memory. Atomic action — A number of software instructions GPIO —...
Page 544 [10] Maxon EC-max Datasheet, Maxon Motor AG 2005, [11] TrenchMos transistor BUK7528-55A Datasheet, NXP 2000 [12] MSCSS Requirement Specification v0.1, Rolf van de Burgt, NXP Semiconductors - ABL 2005 [13] OsCan performance measurements on SJA2510 and SJA2020, Janett Honko, NXP...
Page 545: Disclaimers
Notice: All referenced brands, product names, service names and trademarks information. are the property of their respective owners. Right to make changes — NXP Semiconductors reserves the right to make SoftConnect — is a trademark of NXP B.V. changes to information published in this document, including without C-bus —...
Page 546 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Notes UM10316_0 © NXP B.V. 2008. All rights reserved. User manual Rev. 00.06 — 17 December 2008 546 of 571...
Page 547: Tables
UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 2. Tables Table 1. Ordering information .....5 8030/38/40/48/50/58/60 (CGU0) and Table 2.
Page 548 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 46. RESET_STATUS3 register bit description (SFSP_5_18, address 0xE000 1548) ..85 (RESET_STATUS3, address 0xFFFF 911C) .63 Table 68. Security disable register bit description Table 47. RST_ACTIVE_STATUS0 register bit description (SEC_DIS, address 0xE000 1B00) .
Page 549 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information definitions used in this chapter... . 152 Table 96. INT_FEATURES register bit description Table 114. Fixed endpoint configuration ... . . 153 (INT_FEATURES, address 0xFFFF F300) .
Page 550 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 135.USB Endpoint Interrupt Clear register address 0xE010 C28C) bit description ..178 (USBEpIntClr - address 0xE010 C238) bit Table 159.USB DMA Interrupt Status register (USBDMAIntSt description ......167 - address 0xE010 C290) bit description .
Page 551 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 205.TCR register bits ..... . 250 Table 187.USB Interrupt Status register - (USBIntSt - Table 206.TC register bits .
Page 552 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 225.INT_THRESHOLD register bit description description ......288 (INT_THRESHOLD, addresses: 0xE004 7FD4 Table 245.Fractional Divider setting look-up table .
Page 553 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information and 0xE008 100C (CAN1))....323 start-address register bit description (CASFESA, Table 271.Bus error capture code values ... .325 address 0xE008 7004) .
Page 554 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 309.LIN master-controller interrupt and capture 0xE008 30[0C, 20, 24, 28]) bit description. . . 398 register bit description ....372 Table 334.I...
Page 555 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 373.ACCn register bit description (ACC0 to 15, 0xE00C 9018) ......466...
Page 556 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Table 421.FMSW0 register bit description (FMSW0, (DMACIntErrClr - 0xE014 0010) ..520 address: 0x2020 002C) ....494 Table 450.DMA Raw Interrupt Terminal Count Status...
Page 557: Figures
UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 3. Figures Fig 1. LPC2917/19/01 block diagram ....7 Fig 40. Reading/writing external memory ... 143 Fig 2.
Page 558 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Fig 78. FullCAN section example of the ID look-up table . . Fig 120. Flash-memory burn sequence ... . . 478 Fig 121. Index sector layout ..... . 479 Fig 79.
Page 559: Table Of Contents
UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 4. Contents Chapter 1: LPC29xx Introductory information Introduction ......3 Block diagram .
Page 560 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Frequency divider status register ..49 5.12 Output-clock configuration register for CGU0 Frequency divider configuration register..49 clocks ....... 51 Output-clock status register for 5.13...
Page 561 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Activation type register ....96 Raw status register ....96 Chapter 10: LPC29xx Vectored Interrupt Controller (VIC) How to read this chapter .
Page 562 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 9.3.1 USB Endpoint Interrupt Status register 9.7.9 USB DMA Interrupt Enable register (USBEpIntSt - 0xE010 C230) ... 164 (USBDMAIntEn - 0xE010 C294)..178 9.3.2...
Page 563 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte 14.5.1 Setting up DMA transfers....200 (optional)) ......192 14.5.2...
Page 564 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information OTG Interrupt Clear Register (OTGIntClr - 6.16 Interrupt handling ..... 228 0xE010 C10C) ..... . . 221 HNP support .
Page 565 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 3.11 SPI FIFO interrupt threshold register ..268 3.12 SPI interrupt bit description ... . . 269 Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter (UART) How to read this chapter .
Page 566 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Section start-registers of the ID look-up table 10.11 CAN controller central transmit-status register . . memory......313 CAN ID look-up table memory .
Page 567 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information LIN master ......362 LIN master-controller fractional baud rate generator register.
Page 568 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 9.10 C Bus obstructed by a Low level on SCL or SDA 10.7.5 State : 0x38 ......418 10.8...
Page 569 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 5.23 PWM match deactive shadow registers ..446 5.24 PWM interrupt bit description... . 446 Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) How to read this chapter .
Page 570 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information Flash memory control register ... 488 3.15 EEPROM power-down register ..500 Unprotect sector ..... . .489 3.16...
Page 571 UM10316 NXP Semiconductors Chapter 32: LPC29xx Supplementary information 5.14 DMA Synchronization Register (DMACSync - Disabling a DMA channel and losing data in the 0xE014 0034) ......523 FIFO.

This manual is also suitable for:

Lpc2917/01 Lpc2919/01 Lpc2927 Lpc2929 Lpc2921 Lpc2923 ... Show all