NXP Semiconductors LPC18xx series User Manual
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NXP Semiconductors LPC18xx series User Manual

Arm cortex-m3
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UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 3.0 — 26 July 2017
Document information
Info
Content
LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x,
Keywords
LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20,
LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3,
SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual
LPC18xx user manual
Abstract
User manual

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Summary of Contents for NXP Semiconductors LPC18xx series

  • Page 1 UM10430 LPC18xx ARM Cortex-M3 microcontroller Rev. 3.0 — 26 July 2017 User manual Document information Info Content LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x, Keywords LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20, LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3, SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual LPC18xx user manual Abstract...
  • Page 2 UM10430 NXP Semiconductors LPC18xx User manual Revision history Date Description 20170726 LPC18xx user manual • Modifications: Updated Section 12.2.1.1 “Changing the BASE_M3_CLK after power-up, reset, or deep power-down mode”. Added list item 4. • Updated Section 12.2.1.2 “Changing the BASE_M3_CLK after waking up from deep-sleep or power-down modes”.
  • Page 3 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description 20151104 LPC18xx user manual Modifications: • Added S parts to Table 1 “Ordering information”, Table 2 “Ordering options (flashless parts)”, Table 3 “Ordering information (parts with on-chip flash)”, and Table 4 “Ordering options (parts with on-chip flash)”.
  • Page 4 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description • Modifications: Updated Table 48 “IAP Copy RAM to Flash command”. • Added a bullet to Section 5.2 “Basic configuration”. If the application uses the IAP interface, it must reserve the SRAM space used by IAP as outlined in Section 5.4.5.8 “RAM used by IAP command...
  • Page 5 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description • Modifications: Signal polarity of signals EMC_CKEOUT and EMC_DQMOUT corrected in Table 346 “EMC pin description”. Both signals are active HIGH. • Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 335 “SPIFI control register (CTRL, address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in...
  • Page 6 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description 20140127 LPC18xx user manual Modifications: • C_CAN CLKDIV register description corrected and clock divider values updated. See Table 1011. • Priorities of the EMC SDRAM ports added. See Section 21.4.
  • Page 7 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description • Modifications: Description of the SDIS bit updated in for USB0 stream mode in Table 410/Table 411 and for USB1 stream mode in Table 471/Table 472. • Updated description of access types to the USB descriptors. See Table 421 “Endpoint capabilities and characteristics”...
  • Page 8 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description 20121203 LPC18xx user manual. • Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to ADC0 and ADC1. See Table 117, Table 118, Table 959, and Section 14.1.
  • Page 9 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description • Modifications: DMA mux control register bit descriptions corrected. See Table 39. • ETM time stamping feature not implemented. See Chapter 46 “LPC18xx JTAG, Serial Wire Debug (SWD), and trace functions”.
  • Page 10 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description 20120607 LPC18xx user manual. Modifications: • Description of CCU auto mode updated (see Section 11.5.3). • Parameter t updated in Table 16. • Examples updated for ISP “Copy RAM to flash” and ISP “Go” commands in Table 948 and Table 952.
  • Page 11 UM10430 NXP Semiconductors LPC18xx User manual Revision history …continued Date Description 20120329 LPC18xx user manual. Modifications: • Chapter 18 updated. • EEPROM memory location corrected in Figure 5. • EEPROM memory access explained (Section 2.3.4). • SDRAM low-power mode removed in Chapter 20.
  • Page 12 UM10430 Chapter 1: LPC18xx Introductory information Rev. 3.0 — 26 July 2017 User manual 1.1 Introduction The LPC18xx are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
  • Page 13 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information – In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot loader software. – Up to 136 kB SRAM for code and data use. – Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually.
  • Page 14 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information – LCD controller with DMA support and a programmable display resolution of up to 1024H  768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.
  • Page 15 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information – Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain. – Brownout detect with four separate thresholds for interrupt and forced reset.
  • Page 16 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information Table 2. Ordering options (flashless parts) Type number Total LCD Ethernet USB0 USB1 GPIO Package SRAM (Host, (Host, channels Device, Device)/ OTG) ULPI interface LPC1830FBD144 200 kB yes/no LQFP144 LPC18S30FET256 200 kB...
  • Page 17 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information Table 3. Ordering information (parts with on-chip flash) Type number Package Name Description Version Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm LPC1823JBD144 LQFP144 SOT486-1 TFBGA100 Plastic thin fine-pitch ball grid array package;...
  • Page 18 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information Table 4. Ordering options (parts with on-chip flash) LPC1827JBD144 1 MB 512 kB 512 kB 136 kB no/no LPC1827JET100 1 MB 512 kB 512 kB 136 kB no/no LPC1825JBD144 768 kB 384 kB...
  • Page 19 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information 1.5 Block diagram (flashless parts LPC1850/30/20/10) SWD/TRACE PORT/JTAG LPC1850/30/20/10 HIGH-SPEED PHY TEST/DEBUG HIGH- INTERFACE ETHERNET SPEED 10/100 USB1 USB0 HOST/ HOST/ IEEE 1588 DEVICE CORTEX-M3 DEVICE/ masters slaves AHB MULTILAYER MATRIX SPIFI...
  • Page 20 UM10430 NXP Semiconductors Chapter 1: LPC18xx Introductory information 1.6 Block diagram (parts with on-chip flash) SWD/TRACE PORT/JTAG LPC185x/3x 64 kB ROM HIGH-SPEED PHY 32 kB LOCAL SRAM 40 kB LOCAL SRAM TEST/DEBUG HIGH- INTERFACE ETHERNET 32 kB AHB SRAM SPEED...
  • Page 21 UM10430 Chapter 2: LPC18xx Memory mapping Rev. 3.0 — 26 July 2017 User manual 2.1 How to read this chapter The following peripherals and memory blocks are only available on selected parts and are reserved otherwise: • Ethernet: available only on LPC185x/3x. USB0: available only on LPC185x/3x/2x.
  • Page 22 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping Table 5. LPC18xx SRAM configuration Part Local SRAM Local SRAM SRAM SRAM SRAM /ETB SRAM LPC1850 96 kB 40 kB 32 kB 16 kB 16 kB Figure 3 LPC1830 96 kB 40 kB...
  • Page 23 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping The flash memory interface includes an intelligent buffering scheme. It can be beneficial to locate code and static data over the two flash memories to enable parallel code and data access or to avoid that interrupts corrupt buffer content. The buffers are aligned on 32-byte boundaries.
  • Page 24 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping The access permission bits, TEX, C, B, AP, and XN, of the Region Access Control Register control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a permission fault is raised. For more information, see the ARMv7-M Architecture Reference Manual.
  • Page 25 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping 2.4 Memory map (flashless parts LPC1850/30/20/10) LPC1850/30/20/10 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3...
  • Page 26 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC1850/30/20/10 0x400F 0000 reserved 0x400E 5000 0xFFFF FFFF APB3 ADC1 external memories and 0x400E 4000 peripherals ARM private bus ADC0...
  • Page 27 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping 2.5 Memory map (parts with on-chip flash) LPC18xx 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3...
  • Page 28 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC18xx 0x400F 0000 0x4006 0000 reserved reserved 0x400E 5000 0xFFFF FFFF 0x4005 4000 APB3 ADC1 0x400E 4000 external memories and...
  • Page 29 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping 2.6 AHB multilayer matrix configuration The multilayer AHB matrix enables all bus masters to access any embedded memory as well as external SPI flash memory connected to the SPIFI interface. When two or more bus masters try to access the same slave, a round robin arbitration scheme is used;...
  • Page 30 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping TEST/DEBUG INTERFACE HIGH-SPEED PHY CORTEX-M3 GPDMA ETHERNET USB0 USB1 masters System I-code D-code slaves 64 kB ROM 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM 32 kB AHB SRAM 16 kB AHB SRAM...
  • Page 31 UM10430 NXP Semiconductors Chapter 2: LPC18xx Memory mapping TEST/DEBUG INTERFACE HIGH-SPEED PHY CORTEX-M3 ETHERNET USB0 USB1 masters System I-code D-code slaves 256/512 kB FLASH A 256/512 kB FLASH B 16 kB EEPROM 64 kB ROM 32 kB LOCAL SRAM 40 kB LOCAL SRAM...
  • Page 32 UM10430 Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API Rev. 3.0 — 26 July 2017 User manual 3.1 How to read this chapter This chapter applies to all LPC18xx parts with the following exceptions: AES keys and AES support are available on LPC18Sxx parts only. •...
  • Page 33 UM10430 NXP Semiconductors Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API 3.3 General description The OTP memory contains four memory banks of 128 bits each. The first memory bank (OTP bank 0) is reserved. The other three OTP banks are programmable. In non-secure parts, OTP banks 1 and 2 are available for general-purpose data.
  • Page 34 UM10430 NXP Semiconductors Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API 3.4 Register description Table 9. OTP memory description (OTP base address 0x4004 5000) Word Access Address Size Description Reference bank offset Pre-programmed; cannot 0x000 32 bit First 32 bit word of the unique part ID for be changed by the user.
  • Page 35 UM10430 NXP Semiconductors Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API Table 10. OTP memory bank 3, word 0 - Customer control data (address offset 0x030) Symbol Value Description 22:0 Reserved USB_ID_ENABLE Setting this bit allows to enable OTP defined USB vendor and product IDs.
  • Page 36 UM10430 NXP Semiconductors Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API 3.5 OTP API The OTP memory is controlled through a set of simple API calls located in the LPC18xx ROM. The API calls to the ROM are performed by executing functions which are pointed to by pointer within the ROM driver table.
  • Page 37 UM10430 NXP Semiconductors Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API 3.5.1 OTP function allocation Remark: See Section 3.1 for availability of OTP function for different boot ROM versions. Table 14. OTP function allocation Function Offset Description OTP bank...
  • Page 38 UM10430 NXP Semiconductors Chapter 3: LPC18xx One-Time Programmable (OTP) memory and API Table 14. OTP function allocation Function Offset Description OTP bank OTP memory programmed name otp_ProgGP2_0 0x20 Programs the general purpose OTP memory GP2 word 0. 3 (word 1) General Use for customer-specific data.
  • Page 39 UM10430 Chapter 4: LPC18xx Boot ROM Rev. 3.0 — 26 July 2017 User manual 4.1 How to read this chapter This chapter applies to all LPC18xx parts. AES support is available on LPC18Sxx parts only. Flash-based parts boot from on-chip flash by default (see Chapter 5), but other boot modes described in this chapter are also supported.
  • Page 40 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM The ARM core is configured to start executing code, upon reset, with the program counter being set to the value 0x0000 0000. The LPC18xx contains a shadow pointer that allows areas of memory to be mapped to address 0x0000 0000. The default value of the shadow pointer is 0x1040 0000, ensuring that the code contained in the boot ROM is executed at reset.
  • Page 41 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM Table 16. Boot mode when OTP BOOT_SRC bits are zero Boot mode P2_9 P2_8 P1_2 P1_1 Description USART0 Boot from device connected to USART0 using pins P2_0 and P2_1. For flash parts, enter UART ISP mode.
  • Page 42 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM 4.3.1 Boot process for parts with internal flash If pin P2_7 is sampled LOW, the boot loader checks the OTP bits and/or the external boot pins to determine the communication port. If the OTP bits and boot pins are set to USART0 or USART3, the part enters UART ISP mode.
  • Page 43 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM RESET INITIALIZE CRP1/2/3 ENABLED? ENABLE DEBUG USER CODE VALID in FLASH BANK A? CRP3 ENABLED? USER CODE VALID in FLASH Enter ISP BANK B? USER CODE VALID? MODE? (P2_7=LOW) EXECUTE INTERNAL USER CODE...
  • Page 44 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM As shown in Figure 11, the boot ROM determines the boot mode based on the OTP BOOT_SRC value or reset state of the pins P1_1, P1_2, P2_8, and P2_9. The boot ROM copies the image to internal SRAM at location 0x1000 0000 and jumps to that location (sets ARM's shadow pointer to 0x1000 0000) after image verification.
  • Page 45 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM CPU clock disable capable and RESET = IRC IRQ & key1 programmed? 12MHz load AES enable JTAG CPU clock ISP pin P2_7 96MHz LOW ? check BOOT _SRC enter ISP =2..5 mode (USART0) =6...
  • Page 46 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM 4.3.3 AES capable parts AES capable parts will normally always boot from a secure (encrypted) image and use CMAC authentication. However a special development mode allows booting from a plain text image. This development mode is active when the AES key1 has not been programmed.
  • Page 47 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM Table 18. Boot image header description Address Name Description size [bits] AES_ACTIVE AES encryption active 0x25 (100101): AES encryption active 0x1A (011010): AES encryption not active all other values: invalid image HASH_ACTIVE...
  • Page 48 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM << 1)  0x87 – If msb(K ) = 0 then K = (K << 1) else K = (K 2. Divide message into 128-bit blocks M = M || ... || M...
  • Page 49 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM 512B ENCRYPTION 512B 512B 512B <512B partition data in 512 Byte frames encrypt data with CBC AES AES key = User Key IV = AES (User Key,1) HASH VALUE define temporary 0x3456...
  • Page 50 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM After the boot image is downloaded, it is checked (based on header information) to be a valid or invalid image and OK respectively FAILED is sent to a host followed by CR and LF.
  • Page 51 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM If no header is present it is assumed that the image is located on address 0x1C000000 and is executed from there. Setup Pin Configuration Read Image EMC _A[13:0] Header EMC_CS0 Image size >...
  • Page 52 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM checks for the type of SPI flash device. For an SPI flash, the part boots with a 18 MHz clock. For a quad SPI flash device, the part boots with a 32 MHz clock. If the detected device is unknown, the SPIFI clock is reduced to 18 MHz.
  • Page 53 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM Table 19. QSPI devices supported by the boot code and the SPIFI API Manufacturer Device Exit from no opcode Comment mode Chingis PM25LD040, PM25LD010C, PM25LD020C, PM25LD512C, PM25LD256C, PM25LQ032C Giga Device GD25Q80 Macronix...
  • Page 54 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM 4.3.6.5 USB boot mode For booting from USB, two USB interfaces are available. USB0 supports high-speed and full-speed while USB1 supports only full-speed. This boot mode requires that a 12 MHz external crystal is connected to the XTAL1/2 pins. The boot code configures the CGU accordingly.
  • Page 55 UM10430 NXP Semiconductors Chapter 4: LPC18xx Boot ROM For flashless parts LPC1850/30/20/10. For parts with on-chip flash; booting from flash. For parts with on-chip flash; booting from an external source. IRC12 IRC12 stable starts IRC12 RESET VDDREG valid threshold 22 μs 0.5μs;...
  • Page 56 UM10430 Chapter 5: LPC18xx flash programming/ISP and IAP Rev. 3.0 — 26 July 2017 User manual 5.1 How to read this chapter The flash programming ISP is available for parts with on-chip flash. A reduced set of In-System-Programming (ISP) commands is supported for flashless parts (see Table 27).
  • Page 57 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.4 General description The boot loader controls initial operation after reset and also provides the tools for programming the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.
  • Page 58 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.4.1 Sampling of pin P2_7 Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated, it may take up to 3 ms before P2_7 is sampled and the decision on whether to continue with user code or ISP handler is made.
  • Page 59 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.4.3 Boot process for parts with internal flash If pin P2_7 is sampled LOW, the boot loader checks the OTP bits and/or the external boot pins to determine the communication port. If the OTP bits and boot pins are set to USART0 or USART3, the part enters UART ISP mode.
  • Page 60 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.4.5.2 ISP response format "Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> … Response_n<CR><LF>" "Data" (Data only for Read commands). 5.4.5.3 ISP data format The data stream is in UU-encoded format. The UU-encode algorithm converts 3 B of binary data in to 4 B of printable ASCII character set.
  • Page 61 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.4.6 Flash signature generation For parts with on-chip flash, a hardware flash signature generation capability is built into the flash memory. This feature can be used to create a signature that can then be used to verify flash contents.
  • Page 62 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.5 Sector numbers Some IAP and ISP commands operate on sectors and specify sector numbers. The following table indicates the correspondence between sector numbers and memory addresses for LPC18xx device. IAP and ISP routines are located in the Boot ROM.
  • Page 63 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.6 Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted.
  • Page 64 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 26. Code Read Protection hardware/software interaction CRP option User Code P2_7 pin at JTAG enabled LPC18xx partial flash Valid reset enters ISP update in ISP mode mode None High...
  • Page 65 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
  • Page 66 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7.2 Set Baud Rate <Baud Rate> <stop bit> The UART PCLK is derived from the IRC at 12 MHz. Table 29. ISP Set Baud Rate command Command Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200...
  • Page 67 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 31. ISP Write to RAM command Command Input Start Address: RAM address where data bytes are to be written. This address should be a word boundary. Number of Bytes: Number of bytes to be written. Count should be a multiple of 4...
  • Page 68 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7.6 Prepare sectors for write operation <start sector number> <end sector number> <flash bank> This command is the first step in the two-step flash write/erase operation. Table 33. ISP Prepare sectors for write operation command...
  • Page 69 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7.7 Copy RAM to Flash <flash address> <RAM address> <no of bytes> Before executing this command, perform the “Prepare sectors for write operation” command. Table 34. ISP Copy command Command...
  • Page 70 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7.8 Go <address> <mode> Table 35. ISP Go command Command Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary.
  • Page 71 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7.10 Blank check sectors <sector number> <end sector number> <flash bank> Table 37. ISP Blank check sector command Command Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number.
  • Page 72 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 39. LPC18xx part identification numbers Device Hex coding Word0 Word1 LPC18S30FET256 0xF000DA60 0xXXXX XX00 LPC18S30FET100 0xF000DA60 0xXXXX XX00 LPC18S30FBD144 0xF000DA60 0xXXXX XX00 LPC1820FET100 0xF00A DB3C 0xXXXX XX00 LPC1820FBD144 0xF00A DB3C...
  • Page 73 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 39. LPC18xx part identification numbers Device Hex coding Word0 Word1 LPC1815JET100 0xF001 DB3F 0xXXXX XX22 LPC1813JBD144 0xF00B DB3F 0xXXXX XX44 LPC1813JET100 0xF00B DB3F 0xXXXX XX44 LPC1812JBD144 0xF00B DB3F 0xXXXX XX80...
  • Page 74 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.7.15 Set active boot flash bank <flash bank> This command is only valid if two flash banks exist on the part and selects one of the two banks for booting from flash. The command inserts a valid signature (see Section 5.4.4.1)
  • Page 75 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.8 IAP commands Remark: IAP commands are not supported for flash-less parts. For in-application programming, call the IAP routine with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters.
  • Page 76 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Command Parameter Array Command code command_param[0] command_param[1] Param 0 Param 1 command_param[2] ARM REGISTER r0 command_param[n] Param n ARM REGISTER r1 Status Result Array Status code status_result[0] Result 0 status_result[1]...
  • Page 77 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 4. Set the function pointer: IAP iap_entry=(IAP)IAP_LOCATION; 5. Use the following statement to call the IAP: iap_entry (command_param,status_result); The IAP call can be simplified further by using the symbol definition file feature supported by ARM Linker in RVDS (Realview Development Suite).
  • Page 78 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 45. IAP Initialization command Command Init IAP Result None Description Initializes and prepares the flash for erase and write operations. Stack usage 88 B 5.8.2 Prepare sectors for write operation This command is the first step in the two-step flash write/erase operation.
  • Page 79 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.8.3 Copy RAM to Flash Before executing this command, perform the “Prepare sectors for write” command. Table 47. IAP Copy RAM to Flash command Command Copy RAM to Flash Input Command code: 51 (decimal) Param0(DST): Destination flash address where data bytes are to be written.
  • Page 80 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.8.5 Blank check sectors Table 49. IAP Blank check sectors command Command Blank check sectors Input Command code: 53 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
  • Page 81 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 51. IAP Read Boot Code version number command Command Read boot code version number Result Result0: 2 bytes of boot code version number. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>...
  • Page 82 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.8.10 Re-invoke ISP Table 54. IAP Re-invoke ISP Command Compare Input Command code: 57 (decimal) Return Code None Result None. Description This command is used to invoke the boot loader in ISP mode. It configures UART0 pins U0_RX and U0_TX.
  • Page 83 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 56. IAP Set active boot flash bank Command Set active boot flash bank Input Command code: 60 (decimal) Param0: Flash bank (0 = flash bank A, 1 = flash bank B).
  • Page 84 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 57. ISP Return Codes Summary Return Code Mnemonic Description 0x0000 0012 INVALID_STOP_BIT Invalid stop bit setting. 0x0000 0013 CODE_READ_PROTECTION_ Code read protection enabled. ENABLED 0x0000 0014 INVALID_FLASH_UNIT Invalid flash unit.
  • Page 85 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.11.1.1 Signature generation address and control registers These registers control automatic signature generation. A signature can be generated for any part of the flash memory contents. The address range to be used for generation is defined by writing the start address to the signature start address register (FMSSTART) and the stop address to the signature stop address register (FMSSTOP.
  • Page 86 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP Table 62. FMSW1 register bit description (FMSW1, address: 0x4000 C030 (flash A) and 0x4000 D030 (flash B)) Symbol Description Reset Value 31:0 SW1[63:32] Word 1 of 128-bit signature (bits 63 to 32).
  • Page 87 UM10430 NXP Semiconductors Chapter 5: LPC18xx flash programming/ISP and IAP 5.11.2 Algorithm and procedure for signature generation Signature generation A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register.
  • Page 88 UM10430 Chapter 6: LPC18xx Security API Rev. 3.0 — 26 July 2017 User manual 6.1 How to read this chapter AES encryption and decryption and the AES API are supported for parts LPC18Sxx only. 6.2 Features • Decryption of external image data. Encryption of data.
  • Page 89 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API OTP, a second key stored in the OTP (this key is not encrypted), a software supplied key, or a key generated by an on-chip random number generator. For encryption and decryption of data, an API is provided.
  • Page 90 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API Remark: The randomly generated and software defined keys are not retained during Deep power-down and reset and must be reloaded. Remark: To update the Random Number Generator (RNG) and load a new random...
  • Page 91 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API 6.4.1 AES functions The ROM-based security AES API controls the AES block. AES API functions are provided to encrypt or decrypt data from memory to memory using an ECB or CBC algorithm. If the CBC algorithm is selected, a user-defined initialization vector can be defined.
  • Page 92 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API Table 67. AES API calls Function Offset relative to Description the API entry point aes_LoadKeySW 0x14 Loads 128-bit AES software defined user key Parameter - unsigned char *key(16 bytes) Return - unsigned: see general error codes.
  • Page 93 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API Table 67. AES API calls Function Offset relative to Description the API entry point aes_Config_DMA 0x2C Checks for valid AES configuration of the chip and setup DMA channel to process an AES data block.
  • Page 94 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API 6.4.3 AES API error codes For general error codes, see Chapter 48 “LPC18xx API General error codes”. /* Security API related errors */ ERR_SEC_AES_BASE = 0x00030000, /*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_AES_BASE+1, /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED, /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,...
  • Page 95 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API 3. If using CBC encode or decode, load an initialization vector: – aes_LoadIV_SW loads a vector generated by the user code. – aes_LoadIV_IC loads a vector generated from the unique part id.
  • Page 96 UM10430 NXP Semiconductors Chapter 6: LPC18xx Security API RAM Offset IV and Key: Always little endian IV: 000102030405060708090a0b0c0d0e0f 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 Key: 2b7e151628aed2a6abf7158809cf4f3c 4F CF 09 88 15 F7 AB A6 D2 AE 28 16 15 7E 2B...
  • Page 97 UM10430 Chapter 7: LPC18xx Boot ROM for secure parts Rev. 3.0 — 26 July 2017 User manual 7.1 How to read this chapter This chapter applies to all LPC18Sxx parts (secure parts) only. Flash-based parts boot from on-chip flash by default (see Chapter 5), but other boot modes described in this chapter are also supported.
  • Page 98 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts a. Use a 128-bit key to encrypt the image using Cypher Block Chaining (CBC) encryption and an initialization vector of 0101010... (binary). After the first block of data, each following (plain-text) block is XORed with the previous encrypted block of data.
  • Page 99 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts 512B ENCRYPTION 512B 512B 512B <512B partition data in 512 Byte frames encrypt data with CBC AES AES key = User Key IV = AES (User Key,1) HASH VALUE...
  • Page 100 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts CPU clock disable key1 RESET = IRC IRQ & programmed? 12MHz load AES enable JTAG CPU clock ISP pin P2_7 96MHz LOW ? boot source = boot source UART, USB, SSP...
  • Page 101 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts 7.3.2.1 Development mode A special development mode allows booting from a plain text image. This development mode is active until the AES key1 has been programmed. Once the AES key1 is programmed in the OTP, the development mode is terminated and JTAG access is automatically disabled for flashless parts.
  • Page 102 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts Can only be active if device is AES capable, else is considered an invalid image. 16 extra bytes are required for the header bytes. The image size should be set to no more than the size of the SRAM located at 0x1000 0000.
  • Page 103 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts Fig 28. CMAC generation 7.3.5 Boot process timing The following parameters describe the timing of the boot process: Table 69. Typical boot process timing parameters Parameter Description Value < 1.25 s Check boot selection pins 250 s...
  • Page 104 UM10430 NXP Semiconductors Chapter 7: LPC18xx Boot ROM for secure parts IRC12 IRC12 stable starts IRC12 RESET VDDREG valid threshold 22 μs 0.5μs; IRC stability count supply boot time ramp up user code μs μs μs processor status check boot...
  • Page 105 UM10430 Chapter 8: LPC18xx Nested Vectored Interrupt Controller (NVIC) Rev. 3.0 — 26 July 2017 User manual 8.1 How to read this chapter The NVIC interrupt sources vary for different parts. Ethernet interrupt: available only on LPC185x/3x. • USB0 interrupt: available only on LPC185x/3x/2x. •...
  • Page 106 UM10430 NXP Semiconductors Chapter 8: LPC18xx Nested Vectored Interrupt Controller (NVIC) 8.6 Interrupt sources Table 71 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source, as noted.
  • Page 107 UM10430 NXP Semiconductors Chapter 8: LPC18xx Nested Vectored Interrupt Controller (NVIC) Table 71. Connection of interrupt sources to the NVIC Interrupt Exception Vector Function Flag(s) Number Offset 0xB0 I2S0 0xB4 I2S1 0xB8 Reserved 0xBC Reserved 0xC0 PIN_INT0 GPIO pin interrupt 0...
  • Page 108 UM10430 NXP Semiconductors Chapter 8: LPC18xx Nested Vectored Interrupt Controller (NVIC) Table 72. Register overview: NVIC (base address 0xE000 E000) …continued Name Access Address Description Reset offset value ICER1 0x184 Interrupt Clear-Enable Register 1. This register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions.
  • Page 109 UM10430 Chapter 9: LPC18xx Event router Rev. 3.0 — 26 July 2017 User manual 9.1 How to read this chapter The event router sources vary for different parts. • Ethernet: available only on LPC185x/3x. • USB0: available only on LPC185x/3x/2x. USB1: available only on LPC185x/3x.
  • Page 110 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Each event input to the event router can be configured to trigger an output signal on rising or falling edges or on HIGH or LOW levels. The event router combines all events to an output signal which is used as follows: •...
  • Page 111 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 74. Event router inputs Event # Source Description Ethernet peripheral Wake-up packet indicator. Not active in Deep-sleep, Power-down, and Deep power-down mode. Use for wake-up from Sleep mode. USB0 peripheral Wake-up request signal. Not active in power-down and deep power-down mode.
  • Page 112 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router 9.5 Pin description Table 75. Event router pin description Direction Description WAKEUP0/1 External wake-up input; can raise an event router interrupt and can cause wake-up from any of the power-down modes. These pins can be configured to monitor the event...
  • Page 113 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 77. Level configuration register (HILO - address 0x4004 4000) bit description Symbol Value Description Reset value WAKEUP1_L Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.
  • Page 114 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 77. Level configuration register (HILO - address 0x4004 4000) bit description Symbol Value Description Reset value WWDT_L Level detect mode for WWDT event. Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0.
  • Page 115 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 77. Level configuration register (HILO - address 0x4004 4000) bit description Symbol Value Description Reset value TIM2_L Level detect mode for combined timer output 2 event. Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0.
  • Page 116 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router 9.6.2 Edge configuration register This register works in combination with the level configuration register HILO (see Table 77) to configure the level or edge detection for each input to the event router.
  • Page 117 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 79. Edge configuration register (EDGE - address 0x4004 4004) bit description Symbol Value Description Reset value ATIMER_E Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.
  • Page 118 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 79. Edge configuration register (EDGE - address 0x4004 4004) bit description Symbol Value Description Reset value SDMMC_E Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.
  • Page 119 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 79. Edge configuration register (EDGE - address 0x4004 4004) bit description Symbol Value Description Reset value BODRESET_E Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.
  • Page 120 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 80. Clear event enable register (CLR_EN - address 0x4004 4FD8) bit description Symbol Description Reset value TIM2_CLREN Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register.
  • Page 121 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 81. Event set enable register (SET_EN - address 0x4004 4FDC) bit description Symbol Description Reset value SDMMC_SETEN Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register.
  • Page 122 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 82. Event status register (STATUS - address 0x4004 4FE0) bit description Symbol Description Reset value ETH_ST A 1 in this bit indicates that the ETHERNET event has been raised. USB0_ST A 1 in this bit indicates that the USB0 event has been raised. 1 USB1_ST A 1 in this bit indicates that the USB1 event has been raised.
  • Page 123 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 83. Event enable register (ENABLE - address 0x4004 4FE4) bit description Symbol Description Reset value WAKEUP3_EN A 1 in this bit indicates that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
  • Page 124 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 83. Event enable register (ENABLE - address 0x4004 4FE4) bit description Symbol Description Reset value QEI_EN A 1 in this bit indicates that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
  • Page 125 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 84. Clear event status register (CLR_STAT - address 0x4004 4FE8) bit description Symbol Description Reset value USB0_CLRST Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register.
  • Page 126 UM10430 NXP Semiconductors Chapter 9: LPC18xx Event router Table 85. Set event status register (SET_STAT - address 0x4004 4FEC) bit description Symbol Description Reset value WWDT_SETST Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register.
  • Page 127 UM10430 Chapter 10: LPC18xx Configuration Registers (CREG) Rev. 3.0 — 26 July 2017 User manual 10.1 How to read this chapter The available peripherals vary for different parts. • Ethernet: available only on LPC185x/3x. • USB0: available only on LPC185x/3x/2x. USB1: available only on LPC185x/3x.
  • Page 128 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) 10.3 Features Multiple functions of the LPC18xx are controlled in the CREG block: • ETB SRAM configuration BOD trip settings • RTC Oscillator output • DMA-to-peripheral muxing • Ethernet mode •...
  • Page 129 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) 10.4 Register description Table 87. Register overview: Configuration registers (base address 0x4004 3000) Name Access Address Description Reset Reset Reset Reference offset value value after value EMC, after UART0/3 USB0/1 boot...
  • Page 130 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) 10.4.1 CREG0 control register Table 88. CREG0 register (CREG0, address 0x4004 3004) bit description Symbol Value Description Reset Access value EN1KHZ Enable 1 kHz output. 1 kHz output disabled. 1 kHz output enabled.
  • Page 131 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 88. CREG0 register (CREG0, address 0x4004 3004) bit description …continued Symbol Value Description Reset Access value 13:12 SAMPLECTRL SAMPLE pin input/output control Reserved Sample output from the event monitor/recorder. Output from the event router.
  • Page 132 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) 10.4.3 ARM Cortex-M3 memory mapping register The reset value for this register depends on the execution of the boot loader. See Table 87. All memory mapped addresses must be located on a 4 kB boundary.
  • Page 133 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 92. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value DMAMUXPER1 Select DMA to peripheral connection for DMA peripheral 1 Timer0 match 0...
  • Page 134 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 92. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value 17:16 DMAMUXPER8 Select DMA to peripheral connection for DMA peripheral 8. Timer3 match 1...
  • Page 135 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 92. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value 31:30 DMAMUXPER15 Select DMA to peripheral connection for DMA peripheral 15. SCT match 3...
  • Page 136 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 93. Flash Accelerator Configuration for flash bank A register (FLASHCFGA - address 0x4004 3120) bit description Symbol Value Description Reset value 11:0 Reserved. Do not change these bits from the reset value.
  • Page 137 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 94. Flash Accelerator Configuration for flash bank B register (FLASHCFGB - address 0x4004 3124) bit description Symbol Value Description Reset value 11:0 Reserved. Do not change these bits from the reset value.
  • Page 138 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Bit 4 selects the functionality of SCT outputs connected to the CTOUT_n pins and • selected GIMA inputs: – SCT output ORed with timer match output (default). See Table 636. – SCT output only.
  • Page 139 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) 10.4.10 Chip ID register Table 97. Chip ID register (CHIPID, address 0x4004 3200) bit description Symbol Description Reset Access value 31:0 Boundary scan ID code 0x5284 E02B or 0x6284 E02B = LPC1850/30/20/10...
  • Page 140 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 98. USB0 frame length adjust register (USB0FLADJ, address 0x4004 3500) bit description Symbol Description Reset Access value FLTV Frame length timing value 0x20 The frame length is given in the number of high-speed bit times in decimal format.
  • Page 141 UM10430 NXP Semiconductors Chapter 10: LPC18xx Configuration Registers (CREG) Table 99. USB1 frame length adjust register (USB1FLADJ, address 0x4004 3600) bit description Symbol Description Reset Access value FLTV Frame length timing value 0x20 The frame length is given in the number of high-speed bit times in decimal format.
  • Page 142 UM10430 Chapter 11: LPC18xx Power Management Controller (PMC) Rev. 3.0 — 26 July 2017 User manual 11.1 How to read this chapter The power management controller is identical on all LPC18xx parts. 11.2 General description The PMC implements the control sequences to enable transitioning between different power modes and controls the power state of each peripheral.
  • Page 143 UM10430 NXP Semiconductors Chapter 11: LPC18xx Power Management Controller (PMC) 11.2.3 Deep-sleep mode In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power; logic states and SRAM memory are maintained. All analog blocks and the BOD control circuit are powered down.
  • Page 144 UM10430 NXP Semiconductors Chapter 11: LPC18xx Power Management Controller (PMC) value. When the LPC18xx wakes up from Deep power-down mode, the boot loader configures the PLL1 as the clock source running at 96 MHz and attempts to boot similar as after a reset or power-up.
  • Page 145 UM10430 NXP Semiconductors Chapter 11: LPC18xx Power Management Controller (PMC) 11.3.1 Hardware sleep event enable register PD0_SLEEP0_HW_ENA Table 102. Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address 0x4004 2000) bit description Symbol Description Reset Access value ENA_EVENT0 Writing a 1 enables the Power-down modes for the Cortex-M3 (see the PD0_SLEEP0_MODE register for selecting the mode).
  • Page 146 UM10430 Chapter 12: LPC18xx Clock Generation Unit (CGU) Rev. 3.0 — 26 July 2017 User manual 12.1 How to read this chapter Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See Section 1.3. The corresponding clock control registers are reserved. 12.2 Basic configuration The CGU is configured as follows: Table 105...
  • Page 147 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 1. Select the IRC an BASE_M3_CLK source. 2. Enable the crystal oscillator (see Table 112). 3. Wait 250 s. 4. Set the AUTOBLOCK bit (bit 11). This bit re-synchronizes the clock output during frequency changes that prevents glitches when switching clock frequencies.
  • Page 148 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) BASE_M3_CLK BASE_M3_CLK PLL1 clock source = (crystal osc) 180 MHz outPLL 50 μs 110 MHz outPLL/2 90 MHz PLL1 lock time 250 μs 12 MHz enable set PLL1 M, N dividers,...
  • Page 149 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) PLL0 WWDT BASE_SAFE_CLK IDIVA OUTCLK1, 3 - 6, 9 - 10 branch clocks to core 12 MHz IRC IDIVB CCU1 PLL0 (BASE_xxx_CLK) and peripherals AUDIO RTCX1 32 kHz OSC IDIVC...
  • Page 150 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) – Integer divider A: maximum division factor = 4 (see Table 124). – Integer dividers B, C, D: maximum division factor = 16 (see Table 125). – Integer divider E: maximum division factor = 256 (see Table 126).
  • Page 151 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 107. Clock sources for clock generators with selectable inputs Clock generators Clock sources PLL0 PLL0 PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE AUDIO /256 32 kHz oscillator IRC 12 MHz...
  • Page 152 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 108. Clock sources for output stages Output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) Clock sources PLL1...
  • Page 153 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.5 Pin description Table 109. CGU pin description Pin name/ Direction Description function name XTAL1 Crystal oscillator input XTAL2 Crystal oscillator output RTCX1 RTC 32 kHz oscillator input RTCX2 RTC 32 kHz oscillator output...
  • Page 154 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 110. Register overview: CGU (base address 0x4005 0000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot...
  • Page 155 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 110. Register overview: CGU (base address 0x4005 0000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot...
  • Page 156 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 110. Register overview: CGU (base address 0x4005 0000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot...
  • Page 157 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 111. FREQ_MON register (FREQ_MON, address 0x4005 0014) bit description …continued Symbol Value Description Reset Access value MEAS Measure frequency RCNT and FCNT disabled Frequency counters started 28:24 CLK_SEL Clock-source selection for the clock to be measured.
  • Page 158 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 112. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit description Symbol Value Description Reset Access value BYPASS Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and...
  • Page 159 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 114. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description …continued Symbol Value Description Reset Access value DIRECTO PLL0 direct output CLKEN PLL0 clock enable Reserved Free running mode Reserved Reserved.
  • Page 160 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) /* multiplier: compute mdec from msel */ unsigned mdec_new (unsigned msel) { unsigned x=0x4000, im; switch (msel) { case 0: return 0xFFFFFFFF; case 1: return 0x18003; case 2: return 0x10003;...
  • Page 161 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.6.3.4 PLL0USB NP-divider register Remark: The PLL NP-divider register does not use the direct binary representations of N = nsel and P = psel directly. Instead, it uses encoded versions NDEC and PDEC of N and P respectively.
  • Page 162 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.6.4 PLL0AUDIO registers The PLL0AUDIO provides a wide range of frequencies for audio applications and can be connected to multiple base clocks. The PLL0AUDIO can be used with or without a fractional divider.
  • Page 163 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 118. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description …continued Symbol Value Description Reset Access value PLLFRACT_ Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit.
  • Page 164 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) /* multiplier: compute mdec from msel */ unsigned mdec_new (unsigned msel) { unsigned x=0x4000, im; switch (msel) { case 0: return 0xFFFFFFFF; case 1: return 0x18003; case 2: return 0x10003;...
  • Page 165 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) unsigned x=0x10, ip; switch (psel) { case 0: return 0xFFFFFFFF; case 1: return 0x62; case 2: return 0x42; default:for (ip = psel; ip <= PLL0_PSEL_MAX; ip++) x = ((x ^ x>>2) & 1) << 4 | x>>1 & 0x3F;...
  • Page 166 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.6.5.2 PLL1 control register Table 123. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description Symbol Value Description Reset Access value PLL1 power down PLL1 enabled PLL1 powered down BYPASS Input clock bypass control CCO clock sent to post-dividers.
  • Page 167 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 123. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description …continued Symbol Value Description Reset Access value 23:16 MSEL Feedback-divider division ratio (M) 11000 R/W 00000000 = 1 00000001 = 2...
  • Page 168 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 124. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description …continued Symbol Value Description Reset Access value IDIV Integer divider A divider values (1/(IDIV + 1)) 1 (default) 10:4...
  • Page 169 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 125. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description Symbol Value Description Reset Access value AUTOBLOCK Block clock automatically during frequency...
  • Page 170 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 126. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. All other values are 0x01 reserved. 0x00 32 kHz oscillator...
  • Page 171 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 128. BASE_USB0_CLK control register (BASE_USB0_CLK, address 0x4005 0060) bit description Symbol Value Description Reset Access value Output stage power down Output stage enabled (default) power-down 10:1 Reserved AUTOBLOCK Block clock automatically during frequency...
  • Page 172 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 129. BASE_USB1_CLK control register (BASE_USB1_CLK, address 0x4005 0068) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved. 0x00...
  • Page 173 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 130. BASE_M3_CLK to BASE_UART3_CLK control registers (BASE_M3_CLK to BASE_UART3_CLK, address 0x4005 006C to 0x4005 00A8) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved.
  • Page 174 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 131. BASE_OUT_CLK control register (BASE_OUT_CLK, addresses 0x4005 00AC) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default)
  • Page 175 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 132. BASE_AUDIO_CLK control register (BASE_AUDIO_CLK, addresses 0x4005 00C0) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default)
  • Page 176 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 133. BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK control register (BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK, addresses 0x4005 00C4 to 0x4005 00C8) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01...
  • Page 177 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.7.4.1 Features Input frequency: 14 kHz to 150 MHz. The input from an external crystal is limited to • 25 MHz. • CCO frequency: 275 MHz to 550 MHz. Output clock range: 4.3 MHz to 550 MHz.
  • Page 178 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Direct Output Bypass CTRL[1] CTRL[3] 32kHz CLKOUT ENET_RX_CLK ENET_TX_CLK GP_CLKIN CRYSTAL P-DIVIDER N-DIVIDER Filter PLL1 CLKIN IDIVA “1” IDIVB IDIVC IDIVD Bandwidth Select P,I,R NP_DIV[6:0] NP_DIV[21:12] IDIVE MDIV[31:17] Direct Input...
  • Page 179 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) mode 1a: Normal operating mode without post-divider and without pre-divider • • mode 1b: Normal operating mode with post-divider and without pre-divider mode 1c: Normal operating mode without post-divider and with pre-divider •...
  • Page 180 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-divider In normal operating mode 1d none of the dividers are bypassed. The operating frequencies are: Fout = Fcco /(2 x P) = M x Fin /(N x P)  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150...
  • Page 181 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) the fractional part of the PLLFRACT_CTRL register (PLLFRACT[14:0]). Consecutive M and M+1 values are then further encoded into appropriate MENC values before being presented as input to the M-divider. Bypass...
  • Page 182 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.7.6.2 PLL1 description P-divider PSEL<1:0> NSEL<1:0> ÷2xP LOCK FCLKOUT LOCK DETECT BYPASS DIRECT analog section FBSEL MSEL<7:0> Fig 36. PLL1 block diagram The block diagram of this PLL is shown in Figure 36.
  • Page 183 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.
  • Page 184 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) FCLKIN      --------------------- - FCCO FCLKOUT Non-integer mode In this mode the post-divider is enabled and the feedback divider is set to run directly on the CCO clock, which gives the following frequency dividers:...
  • Page 185 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) 12.8 Example CGU configurations 12.8.1 Programming the CGU for Deep-sleep and Power-down modes Before the LPC18xx enters Deep-sleep or Power-down mode, the IRC must be programmed as the clock source in the control registers for all output stages (OUTCLK_0 to OUTCLK_27).
  • Page 186 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 136. PLL0 (for USB) settings for 480 MHz output clock Fclkin [MHz] PLL0USB_MDIV PLL0USB_NP_DIV Table 115 Table 116 0x073E 56C9 0x0030 2062 0x073E 2DAD 0x0030 2062 0x0B3E 34B1 0x0030 2062...
  • Page 187 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 137. PLL0AUDIO divider settings for 12 MHz input Fs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRL Table 120 Table 121 88.2 22.5792 451.584 0x0000100e 0x1c3958 16.384...
  • Page 188 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 137. PLL0AUDIO divider settings for 12 MHz input Fs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRL Table 120 Table 121 24.576 540.672 0x0000201d 0x16872b 22.05 22.5792...
  • Page 189 UM10430 NXP Semiconductors Chapter 12: LPC18xx Clock Generation Unit (CGU) Table 138. PLL0AUDIO divider setting for 12 MHz with fractional divider bypassed Fout Fcco Error PLL0AUDIO_ PLL0AUDIO_ [KHz] [MHz] [MHz] [Hz] NDEC MDEC PDEC MDIV NP_DIV Table 119 Table 120 88.2...
  • Page 190 UM10430 Chapter 13: LPC18xx Clock Control Unit (CCU) Rev. 3.0 — 26 July 2017 User manual 13.1 How to read this chapter Flash/EEPROM, Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See Table 2 Table 13.2 Basic configuration The CCU1/2 are configured as follows: Table 139...
  • Page 191 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 140. CCU1 branch clocks Base clock Branch clock Description BASE_APB3_CLK CLK_APB3_BUS APB3 bus clock. CLK_APB3_I2C1 Clock to the I2C1 register interface and I2C1 peripheral clock. CLK_APB3_DAC Clock to the DAC register interface.
  • Page 192 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 140. CCU1 branch clocks Base clock Branch clock Description BASE_M3_CLK CLK_M3_TIMER1 Clock to the timer1 register interface and timer1 peripheral clock. CLK_M3_SCU Clock to the System control unit register interface.
  • Page 193 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) 13.5 Register description Table 142. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset 0x000 CCU1 power mode register 0x0000 0000 Table 144 BASE_STAT...
  • Page 194 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 142. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_M3_SPIFI_STAT 0x40C CLK_M3_SPIFI status register 0x0000 0001 Table 150 CLK_M3_GPIO_CFG 0x410 CLK_M3_GPIO configuration register...
  • Page 195 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 142. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_M3_WWDT_STAT 0x504 CLK_M3_WWDT status register 0x0000 0001 Table 150 CLK_M3_USART0_CFG 0x508 CLK_M3_UART0 configuration register...
  • Page 196 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 142. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset 0x908 to Reserved 0xAFC 0xB00 Reserved 0xB04 Reserved Table 143. Register overview: CCU2 (base address 0x4005 2000)
  • Page 197 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) 13.5.1 Power mode register This register contains a single bit, PD, that disables all output clocks with Wake-up enabled (W = 1 in the CCU branch clock configuration registers, Section 13.5.3).
  • Page 198 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 145. CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit description …continued Symbol Description Reset Access value BASE_USB0_ Base clock indicator for BASE_USB0_CLK CLK_IND 0 = All branch clocks switched off.
  • Page 199 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) RUN — The WAKEUP, PD, and AUTO control bits determine the activation of the branch clock. If register bit AUTO is set, the AHB disable protocol must complete before the clock is switched off.
  • Page 200 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 148. CCU1 branch clock configuration register (CLK_M3_EMCDIV_CFG, addresses 0x4005 1478) bit description …continued Symbol Value Description Reset Access value AUTO Auto (AHB disable mechanism) enable Auto is disabled. Auto is enabled.
  • Page 201 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) these signals. All output clock Status Registers follow the format as described in Table 150 Table 151. Remark: The divider value for the CLK_M3_EMCDIV_CFG register is not reflected in the status register.
  • Page 202 UM10430 NXP Semiconductors Chapter 13: LPC18xx Clock Control Unit (CCU) Table 151. CCU2 branch clock status register (CLK_XXX_STAT, addresses 0x4005 2104, 0x4005 2204,..., 0x4005 2804) bit description …continued Symbol Description Reset Access value Reserved. RUN_N Clock disable status. This bit has same functionality as the RUN bit except with the opposite polarity.
  • Page 203 UM10430 Chapter 14: LPC18xx Reset Generation Unit (RGU) Rev. 3.0 — 26 July 2017 User manual 14.1 How to read this chapter Flash/EEPROM, Ethernet, USB0, USB1, and LCD and their related resets are not available on all packages or parts. See Section 1.3.
  • Page 204 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) RTC POWER DOMAIN alarm timer, RTC, CREG (partial), PMC RESET WWDT CORE_RST BOD reset CREG (partial), PMC GENERATOR WWDT reset Bus bridges, memory controllers PERIPH_RST APB peripherals, GPIO GENERATOR Cortex-M3 core...
  • Page 205 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 153. Reset output configuration …continued Reset generator Reset Reset source Parts of the device reset when output activated USB1_RST MASTER_RST USB1 reset DMA_RST MASTER_RST DMA reset SDIO_RST MASTER_RST SDIO reset...
  • Page 206 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 153. Reset output configuration …continued Reset generator Reset Reset source Parts of the device reset when output activated CAN0_RST PERIPH_RST C_CAN0 reset Reserved Reserved Reserved 58 - 63 The RGU monitors the reset cause for each reset output using the RESET_STATUS0 to RESET_STATUS3 registers.
  • Page 207 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) TRSTn TRSTn_loc RESET CORE_RST BOD reset delay=3 WWDT reset PMC reset CORE_RST WWDT_RST delay=3 no sw CREG_RST delay=3 no sw PERIPH_RST delay=5 PERIPH_RST spi,etc ..delay=2 MASTER_RST delay=5 MASTER_RST m3,usb,lcd,etc...
  • Page 208 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 155. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT5 0x414 Reset external status register 5 for Table 166 CREG_RST RESET_EXT_STAT6...
  • Page 209 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 155. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT33 0x484 Reset external status register 33 for Table 167 TIMER1_RST RESET_EXT_STAT34...
  • Page 210 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 155. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT57 0x4E4 Reserved RESET_EXT_STAT58 0x4E8 Reserved RESET_EXT_STAT59 0x4EC Reserved RESET_EXT_STAT60 0x4F0 Reserved...
  • Page 211 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 156. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description …continued Symbol Description Reset Access value Reserved LCD_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
  • Page 212 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 157. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description …continued Symbol Description Reset Access value MOTOCONPWM_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
  • Page 213 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) 14.4.2 RGU reset status register The reset status register shows which source (if any) caused the last reset activation per individual reset output of the RGU. When one (or more) inputs of the RGU caused the...
  • Page 214 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 158. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Symbol Description Reset Access value 23:22 Reserved 25:24 Reserved 27:26 M3_RST Status of the M3_RST reset generator output...
  • Page 215 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 159. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description …continued Symbol Description Reset Access value 11:10 EMC_RST Status of the EMC_RST reset generator output 00 = No reset activated...
  • Page 216 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 160. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description Symbol Description Reset Access value TIMER0_RST Status of the TIMER0_RST reset generator output 00 = No reset activated...
  • Page 217 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 160. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued …continued Symbol Description Reset Access value 17:16 ADC0_RST Status of the ADC0_RST reset generator output 00 = No reset activated...
  • Page 218 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 161. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description Symbol Description Reset Access value I2C0_RST Status of the I2C0_RST reset generator output 00 = No reset activated...
  • Page 219 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 161. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description …continued Symbol Description Reset Access value 19:18 Reserved 21:20 Reserved 23:22 Reserved 25:24 Reserved 27:26 Reserved 29:28 Reserved...
  • Page 220 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 162. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued Symbol Description Reset Access value Reserved M3_RST Current status of the M3_RST 0 = Reset asserted...
  • Page 221 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 162. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued Symbol Description Reset Access value FLASHB_RST Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset...
  • Page 222 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 163. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued Symbol Description Reset Access value DAC_RST Current status of the DAC_RST 0 = Reset asserted 1 = No reset...
  • Page 223 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 163. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued Symbol Description Reset Access value Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. 14.4.4 Reset external status registers The external status registers indicate which input to the reset generator caused the reset output to go active.
  • Page 224 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) 14.4.4.2 Reset external status register 2 for MASTER_RST Table 165. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit description Symbol Description Reset Access value Reserved. Do not modify; read as logic 0.
  • Page 225 UM10430 NXP Semiconductors Chapter 14: LPC18xx Reset Generation Unit (RGU) Table 168. Reset external status registers y (RESET_EXT_STATy, address 0x4005 34yy) bit description Symbol Description Reset Access value Reserved. Do not modify; read as logic 0. MASTER_RESET Reset activated by MASTER_RST output.
  • Page 226 UM10430 Chapter 15: LPC18xx Pin configuration Rev. 3.0 — 26 July 2017 User manual 15.1 How to read this chapter For flashless parts LPC1850/30/20/10, see Table 169. For flash-based parts LPC185x, Table 170. 15.2 Pin description On the LPC18xx, digital pins are grouped into 16 pin groups, named P0 to P9 and PA to PF, with up to 20 pins used per group.
  • Page 227 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description Multiplexed digital pins P0_0 N; PU I/O GPIO0[0] — General purpose digital input/output pin.
  • Page 228 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_1 N; PU I/O GPIO0[8] — General purpose digital input/output pin. Boot...
  • Page 229 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_5 N; PU I/O GPIO1[8] — General purpose digital input/output pin.
  • Page 230 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_8 N; PU I/O GPIO1[1] — General purpose digital input/output pin.
  • Page 231 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_12 N; PU I/O GPIO1[5] — General purpose digital input/output pin.
  • Page 232 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_16 N; PU I/O GPIO0[3] — General purpose digital input/output pin.
  • Page 233 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_20 K10 70 N; PU I/O GPIO0[15] — General purpose digital input/output pin.
  • Page 234 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_2 N; PU - R — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode.
  • Page 235 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_5 D10 91 N; PU - R — Function reserved.
  • Page 236 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_8 N; PU - R — Function reserved. Boot pin (see Table CTOUT_0 —...
  • Page 237 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_12 N; PU I/O GPIO1[12] — General purpose digital input/output pin.
  • Page 238 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_1 N; PU I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave.
  • Page 239 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_4 N; PU I/O GPIO1[14] — General purpose digital input/output pin.
  • Page 240 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_7 N; PU - R — Function reserved. R — Function reserved.
  • Page 241 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_2 N; PU I/O GPIO2[2] — General purpose digital input/output pin.
  • Page 242 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_5 N; PU I/O GPIO2[5] — General purpose digital input/output pin.
  • Page 243 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_9 N; PU - R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3.
  • Page 244 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P5_2 N; PU I/O GPIO2[11] — General purpose digital input/output pin.
  • Page 245 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P5_6 M11 - N; PU I/O GPIO2[15] — General purpose digital input/output pin.
  • Page 246 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_2 N; PU I/O GPIO3[1] — General purpose digital input/output pin.
  • Page 247 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_5 N; PU I/O GPIO3[4] — General purpose digital input/output pin.
  • Page 248 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_9 N; PU I/O GPIO3[5] — General purpose digital input/output pin.
  • Page 249 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_0 N; PU I/O GPIO3[8] — General purpose digital input/output pin.
  • Page 250 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_4 N; PU I/O GPIO3[12] — General purpose digital input/output pin.
  • Page 251 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_7 N; PU I/O GPIO3[15] — General purpose digital input/output pin.
  • Page 252 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_3 N; PU I/O GPIO4[3] — General purpose digital input/output pin.
  • Page 253 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_7 N; PU I/O GPIO4[7] — General purpose digital input/output pin.
  • Page 254 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P9_2 N; PU I/O GPIO4[14] — General purpose digital input/output pin.
  • Page 255 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P9_6 N; PU I/O GPIO4[11] — General purpose digital input/output pin.
  • Page 256 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PA_3 N; PU I/O GPIO4[10] — General purpose digital input/output pin.
  • Page 257 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PB_2 N; PU - R — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.
  • Page 258 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PB_6 N; PU - R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
  • Page 259 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_3 N; PU I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.
  • Page 260 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_7 N; PU - R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
  • Page 261 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_11 N; PU - R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction.
  • Page 262 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_0 N; PU - R — Function reserved. CTOUT_15 — SCT output 15. Match output 3 of timer 3.
  • Page 263 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_4 N; PU - R — Function reserved. CTOUT_8 — SCT output 8. Match output 0 of timer 2.
  • Page 264 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_8 N; PU - R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3.
  • Page 265 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_12 N; PU - R — Function reserved. R — Function reserved.
  • Page 266 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_16 N; PU - R — Function reserved. R — Function reserved.
  • Page 267 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_3 N; PU - R — Function reserved. CAN0_TD — CAN transmitter output.
  • Page 268 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_7 N; PU - R — Function reserved. CTOUT_5 — SCT output 5. Match output 3 of timer 3.
  • Page 269 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_11 N; PU - R — Function reserved. CTOUT_12 — SCT output 12. Match output 3 of timer 3.
  • Page 270 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_15 N; PU - R — Function reserved. CTOUT_0 — SCT output 0. Match output 0 of timer 0.
  • Page 271 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_3 N; PU - R — Function reserved. U3_RXD — Receiver input for USART3.
  • Page 272 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_6 N; PU - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
  • Page 273 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_9 N; PU - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
  • Page 274 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description Clock pins CLK0 O; PU O EMC_CLK0 — SDRAM clock 0.
  • Page 275 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description Debug pins DBGEN JTAG interface control signal. Also used for boundary scan.
  • Page 276 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description [11] WAKEUP2 I; IA External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes.
  • Page 277 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 169. LPC1850/30/20/10 Pin description (flashless parts) …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description VBAT RTC power supply: 3.3 V on this pin supplies power to the RTC.
  • Page 278 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength.
  • Page 279 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) Pin name Description Multiplexed digital pins P0_0 I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
  • Page 280 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P1_1 I/O GPIO0[8] — General purpose digital input/output pin. External boot pin (see Table 16). CTOUT_7 — SCT output 7. Match output 3 of timer 1.
  • Page 281 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P1_5 I/O GPIO1[8] — General purpose digital input/output pin. CTOUT_10 — SCT output 10. Match output 3 of timer 3. R — Function reserved.
  • Page 282 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P1_9 I/O GPIO1[2] — General purpose digital input/output pin. U1_RTS — Request to Send output for UART1. CTOUT_11 — SCT output 11. Match output 3 of timer 2.
  • Page 283 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P1_13 I/O GPIO1[6] — General purpose digital input/output pin. U1_TXD — Transmitter output for UART1. R — Function reserved. I/O EMC_D6 — External memory data line 6.
  • Page 284 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P1_17 I/O GPIO0[12] — General purpose digital input/output pin. I/O U2_UCLK — Serial clock input/output for USART2 in synchronous mode. R — Function reserved.
  • Page 285 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P2_0 R — Function reserved. U0_TXD — Transmitter output for USART0. See Table 15 ISP mode. I/O EMC_A13 — External memory address line 13.
  • Page 286 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P2_3 R — Function reserved. I/O I2C1_SDA — I C1 data input/output (this pin does not use a specialized I C pad).
  • Page 287 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P2_6 R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O EMC_A10 — External memory address line 10.
  • Page 288 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P2_10 I/O GPIO0[14] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U2_TXD — Transmitter output for USART2.
  • Page 289 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P3_0 I/O I2S0_RX_SCK — I S receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I S-bus specification.
  • Page 290 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P3_3 R — Function reserved. R — Function reserved. I/O SSP0_SCK — Serial clock for SSP0. SPIFI_SCK — Serial clock for SPIFI.
  • Page 291 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P3_6 I/O GPIO0[6] — General purpose digital input/output pin. R — Function reserved. I/O SSP0_SSEL — Slave Select for SSP0. I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.
  • Page 292 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P4_1 I/O GPIO2[1] — General purpose digital input/output pin. CTOUT_1 — SCT output 1. Match output 3 of timer 3. LCD_VD0 — LCD data.
  • Page 293 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P4_4 I/O GPIO2[4] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. LCD_VD1 — LCD data.
  • Page 294 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P4_7 LCD_DCLK — LCD panel clock. GP_CLKIN — General purpose clock input to the CGU. R — Function reserved. R — Function reserved.
  • Page 295 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P5_0 I/O GPIO2[9] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. I/O EMC_D12 — External memory data line 12.
  • Page 296 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P5_4 I/O GPIO2[13] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. I/O EMC_D8 — External memory data line 8.
  • Page 297 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P6_0 R — Function reserved. I2S0_RX_MCLK — I S receive master clock. R — Function reserved. R — Function reserved. I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and received by the slave.
  • Page 298 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P6_3 I/O GPIO3[2] — General purpose digital input/output pin. USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH).
  • Page 299 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P6_7 R — Function reserved. I/O EMC_A15 — External memory address line 15. R — Function reserved. USB0_IND1 — USB0 port indicator LED control output 1.
  • Page 300 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P6_11 I/O GPIO3[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. EMC_CKEOUT0 — SDRAM clock enable 0.
  • Page 301 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P7_2 I/O GPIO3[10] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. I/O I2S0_TX_SDA — I S transmit data.
  • Page 302 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P7_5 I/O GPIO3[13] — General purpose digital input/output pin. CTOUT_12 — SCT output 12. Match output 3 of timer 3. R — Function reserved.
  • Page 303 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P8_0 I/O GPIO4[0] — General purpose digital input/output pin. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition).
  • Page 304 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P8_4 I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved.
  • Page 305 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P8_8 R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. R — Function reserved.
  • Page 306 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description P9_3 I/O GPIO4[15] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. USB1_IND1 — USB1 Port indicator LED control output 1.
  • Page 307 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PA_0 R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved.
  • Page 308 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PA_4 R — Function reserved. CTOUT_9 — SCT output 9. Match output 3 of timer 3. R — Function reserved. I/O EMC_A23 — External memory address line 23.
  • Page 309 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PB_3 R — Function reserved. I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. LCD_VD20 — LCD data. R — Function reserved.
  • Page 310 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PC_0 R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. R — Function reserved.
  • Page 311 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PC_3 I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. R — Function reserved. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.
  • Page 312 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PC_7 R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved. ENET_RXD3 — Ethernet receive data 3 (MII interface).
  • Page 313 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PC_11 R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. U1_DCD — Data Carrier Detect input for UART1.
  • Page 314 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PD_0 R — Function reserved. CTOUT_15 — SCT output 15. Match output 3 of timer 3. EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices.
  • Page 315 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PD_4 R — Function reserved. CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18.
  • Page 316 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PD_8 R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22.
  • Page 317 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PD_12 R — Function reserved. R — Function reserved. EMC_CS2 — LOW active Chip Select 2 signal. R — Function reserved.
  • Page 318 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PD_16 R — Function reserved. R — Function reserved. I/O EMC_A16 — External memory address line 16. R — Function reserved.
  • Page 319 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PE_3 R — Function reserved. CAN0_TD — CAN transmitter output. ADCTRIG1 — ADC trigger input 1. I/O EMC_A21 — External memory address line 21.
  • Page 320 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PE_7 R — Function reserved. CTOUT_5 — SCT output 5. Match output 3 of timer 3. U1_CTS — Clear to Send input for UART1.
  • Page 321 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PE_11 R — Function reserved. CTOUT_12 — SCT output 12. Match output 3 of timer 3. U1_TXD — Transmitter output for UART1.
  • Page 322 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PE_15 R — Function reserved. CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O I2C1_SCL — I C1 clock input/output (this pin does not use a specialized I C pad).
  • Page 323 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PF_3 R — Function reserved. U3_RXD — Receiver input for USART3. I/O SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved.
  • Page 324 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PF_6 R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1.
  • Page 325 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description PF_9 R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. CTOUT_1 — SCT output 1. Match output 3 of timer 3.
  • Page 326 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description CLK0 EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. I/O SD_CLK — SD/MMC card clock.
  • Page 327 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description Debug pins DBGEN JTAG interface control signal. Also used for boundary scan. TCK/SWDCLK I; F Test Clock for JTAG interface (default) or Serial Wire (SW) clock.
  • Page 328 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description [11] WAKEUP1 I; IA External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part.
  • Page 329 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration Table 170. LPC18xx Pin description (flash-based parts) …continued Pin name Description USB0_VSSA Dedicated analog ground for clean reference for termination _TERM resistors. USB0_VSSA Dedicated clean analog ground for generation of reference _REF currents and voltages.
  • Page 330 UM10430 NXP Semiconductors Chapter 15: LPC18xx Pin configuration N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA = inactive;...
  • Page 331 UM10430 Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Rev. 3.0 — 26 July 2017 User manual 16.1 How to read this chapter The following peripherals are not available on all parts, and the corresponding bit values that select those functions in the SFSP registers are reserved: Ethernet: available on LPC185x/3x only.
  • Page 332 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration VDDIO enable output driver data output from core slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN...
  • Page 333 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration 16.3.3 Input buffer To be able to receive a digital signal, the input buffer must be enabled through bit EZI in the pin configuration registers (see Figure 39). By default, the input buffer is disabled.
  • Page 334 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration 16.3.10 EMC signal delay control The SCU contains a programmable delay control for the EMC SDRAM clocks (see Table 185). 16.3.11 Pin multiplexing Multiplexed digital pins are grouped into 16 pin groups, named P0 to P9 and PA to PF, with up to 20 pins used per group.
  • Page 335 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog P0_0 GPIO0[0] SSP1_MISO ENET_RXD1 I2S0_TX_WS I2S1_TX_WS P0_1 GPIO0[1]...
  • Page 336 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog P2_1 U0_RXD EMC_A12 USB0_PWR_F GPIO5[1] T3_CAP1 AULT P2_2...
  • Page 337 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog P4_4 GPIO2[4] CTOUT_2 LCD_VD1 LCD_VD20 U3_DIR P4_5 GPIO2[5]...
  • Page 338 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog P6_10 GPIO3[6] MCABORT EMC_DQMOUT P6_11 GPIO3[7] EMC_CKEOUT T2_MAT3...
  • Page 339 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog P9_4 MCOB0 USB1_IND0 GPIO5[17] ENET_TXD2 U3_RXD P9_5 MCOA1...
  • Page 340 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog PC_10 R USB1_ULPI_ST U1_DSR GPIO6[9] T3_MAT3 SD_CMD PC_11 R...
  • Page 341 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog PE_4 EMC_A22 GPIO7[4] PE_5 CTOUT_3 U1_RTS EMC_D24 GPIO7[5]...
  • Page 342 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 172. Pin multiplexing MODE bits = name Analog CLK1 EMC_CLK1 CLKOUT CGU_OUT0 I2S1_TX_MCLK - CLK2 EMC_CLK3 CLKOUT...
  • Page 343 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration 16.4 Register description The system control unit contains the registers to configure the pin function of multiplexed digital pins, the EMC clock delays, and the GPIO pin interrupts.
  • Page 344 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 345 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 346 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 347 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 348 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 349 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 350 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 173. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART...
  • Page 351 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 174. Pin configuration registers for normal-drive pins (SFS, address 0x4008 6000 (SPSP0_0) to 0x4008 67AC (SFSPF_11)) bit description Symbol Value Description Reset Access value MODE Select pin function.
  • Page 352 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration P8_0 to P8_2 • • PA_1 to PA_3 Table 175. Pin configuration registers for high-drive pins (SFS, address 0x4008 60C4 (SFSP1_17) to 0x4008 650C (SFSPA_3) bit description Symbol...
  • Page 353 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration 16.4.3 Pin configuration registers for high-speed pins Each digital pin and each clock pin on the LPC18xx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The assigned...
  • Page 354 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 177. Pin configuration for pins USB1_DP/USB1_DM register (SFSUSB, address 0x4008 6C80) bit description Symbol Value Description Reset Access value USB_AIM Differential data input AIP/AIM. Going LOW with full speed edge rate...
  • Page 355 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 178. Pin configuration for open-drain I C-bus pins register (SFSI2C0, address 0x4008 6C84) bit description …continued Symbol Value Description Reset Access value SCL_EZI Enable the input receiver for the SCL pin.
  • Page 356 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 179. Pins controlled by the ENAIO0 register ADC function ENAIO0 register bit P4_3 ADC0_0 P4_1 ADC0_1 PF_8 ADC0_2 P7_5 ADC0_3 P7_4 ADC0_4 PF_10 ADC0_5 PB_6 ADC0_6 By default, all pins are connected to their digital function 0 and only the digital pad is available.
  • Page 357 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 180. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description Symbol Value Description Reset Access value ADC0_6 Select ADC0_6 Digital function selected on pin PB_6. Analog function ADC0_6 selected on pin PB_6.
  • Page 358 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 182. ADC1 function select register (ENAIO1, address 0x4008 6C8C) bit description Symbol Value Description Reset Access value ADC1_0 Select ADC1_0 Digital function selected on pin PC_3. Analog function ADC1_0 selected on pin PC_3.
  • Page 359 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration To select the analog function, the pad must be set as follows using the corresponding SFSP register: 1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in input mode.
  • Page 360 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 185. EMC clock delay register (EMCDELAYCLK, address 0x4008 6D00) bit description Symbol Description Reset Access value 15:0 CLK_DELAY EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 ...
  • Page 361 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 187. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description Symbol Value Description Reset value INTPIN0 Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register.
  • Page 362 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 187. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description Symbol Value Description Reset value 31:29 PORTSEL3 Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.
  • Page 363 UM10430 NXP Semiconductors Chapter 16: LPC18xx System Control Unit (SCU)/ IO configuration Table 188. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description Symbol Value Description Reset value 15:13 PORTSEL5 Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.
  • Page 364 UM10430 Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Rev. 3.0 — 26 July 2017 User manual 17.1 How to read this chapter The GIMA is identical for all parts. 17.2 Basic configuration The GIMA is configured as follows: • Table 189 for clocking and power control.
  • Page 365 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) I2S0/1 MWS signal • • USART0/2/3 RX/TX active signal USB0/1 SOF signal • The following peripheral functions are connected to GIMA outputs: Timer0/1/2/3 capture inputs • SCT inputs •...
  • Page 366 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 190. GIMA outputs GIMA GIMA output GIMA inputs Reference output connected to T0 capture channel 0 pin CTIN_0 Reserved pin T0_CAP0 Table 193 T0 capture channel 1 pin CTIN_1...
  • Page 367 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 190. GIMA outputs GIMA GIMA output GIMA inputs Reference output connected to Event router input 14 SCT output 6 or T1 Reserved T1 match Table 218 match channel 2...
  • Page 368 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) GIMA outputs 16 to 23: BASE_M3_CLK using SCT branch clock. • • GIMA outputs 25 to 27: no synchronization clock required because the event router can capture a signal with edge or level sensitivity.
  • Page 369 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 192. Register overview: GIMA (base address: 0x400C 7000) Name Access Address Description Reset Reference offset value CAP0_3_IN 0x00C Timer 0 CAP0_3 capture input multiplexer (GIMA Table 196 output 3)
  • Page 370 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 192. Register overview: GIMA (base address: 0x400C 7000) Name Access Address Description Reset Reference offset value EVENTROUTER_16_IN 0x06C Event router input 16 multiplexer (GIMA output 27) Table 219...
  • Page 371 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 194. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
  • Page 372 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) 17.4.4 Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN) Table 196. Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN, address 0x400C 700C) bit description Symbol Value Description Reset value Invert input Not inverted.
  • Page 373 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 197. Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN, address 0x400C 7010) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTIN_0...
  • Page 374 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 199. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
  • Page 375 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) 17.4.9 Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN) Table 201. Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN, address 0x400C 7020) bit description Symbol Value Description Reset value Invert input Not inverted.
  • Page 376 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 202. Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN, address 0x400C 7024) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. CTIN_1...
  • Page 377 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 204. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled.
  • Page 378 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) 17.4.14 Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN) Table 206. Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN, address 0x400C 7034) bit description Symbol Value Description Reset value Invert input Not inverted.
  • Page 379 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 207. Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN, address 0x400C 7038) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. 0...
  • Page 380 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 209. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled.
  • Page 381 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) 17.4.19 SCT CTIN_2 capture input multiplexer (CTIN_2_IN) Table 211. SCT CTIN_2 capture input multiplexer (CTIN_2_IN, address 0x400C 7048) bit description Symbol Value Description Reset value Invert input Not inverted.
  • Page 382 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 212. SCT CTIN_3 capture input multiplexer (CTIN_3_IN, address 0x400C 704C) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. CTIN_3 USART0 TX active...
  • Page 383 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 214. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
  • Page 384 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) 17.4.24 SCT CTIN_7 capture input multiplexer (CTIN_7_IN) Table 216. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit description Symbol Value Description Reset value Invert input Not inverted.
  • Page 385 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 217. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTOUT_2 or T0_MAT2...
  • Page 386 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 219. Event router input 16multiplexer (EVENTROUTER_16_IN, address 0x400C 706C) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation.
  • Page 387 UM10430 NXP Semiconductors Chapter 17: LPC18xx Global Input Multiplexer Array (GIMA) Table 221. ADC start1 input multiplexer (ADCSTART1_IN, address 0x400C 7074) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled.
  • Page 388 UM10430 Chapter 18: LPC18xx GPIO Rev. 3.0 — 26 July 2017 User manual 18.1 How to read this chapter All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO registers are reserved.
  • Page 389 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO 18.3 Features 18.3.1 GPIO pin interrupt features • Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC.
  • Page 390 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO 18.4.3 GPIO port The GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output.
  • Page 391 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 225. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000) Name Access Address Description Reset value Reference offset CTRL 0x000 GPIO grouped interrupt control register Table 238 PORT_POL0 R/W 0x020 GPIO grouped interrupt port 0 polarity register...
  • Page 392 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 227. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 222). Name Access Address Description Reset Width Reference offset value...
  • Page 393 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 227. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 222). Name Access Address Description Reset Width Reference offset value...
  • Page 394 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 227. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 222). Name Access Address Description Reset Width Reference offset value...
  • Page 395 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 229. Pin interrupt level (rising edge) interrupt enable register (IENR, address 0x4008 7004) bit description Symbol Description Reset Access value ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn.
  • Page 396 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO 18.5.1.5 Pin interrupt active level (falling edge) interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 187 Table 188), one bit in the IENF register enables the falling edge interrupt or the configures...
  • Page 397 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is • selected. Table 234. Pin interrupt active level (falling edge) interrupt clear register (CIENF, address 0x4008 7018) bit description...
  • Page 398 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 236. Pin interrupt falling edge register (FALL, address 0x4008 7020) bit description Symbol Description Reset Access value FDET Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn.
  • Page 399 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 238. GPIO grouped interrupt control register (CTRL, addresses 0x4008 8000 (GROUP0 INT) and 0x4008 9000 (GROUP1 INT)) bit description Symbol Value Description Reset value COMB Combine enabled inputs for group interrupt OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
  • Page 400 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO 18.5.3 GPIO port register description 18.5.3.1 GPIO port byte pin registers Each GPIO pin GPIOn[m] has a byte register in this address range. The byte pin registers of GPIO port 0 correspond to registers B0 to B31, the byte pin registers of GPIO port 1 correspond to registers B32 to B63, etc.
  • Page 401 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO 18.5.3.3 GPIO port direction registers Each GPIO port n (n = 0 to 7) has one direction register for configuring the port pins as inputs or outputs. Table 243. GPIO port direction register (DIR, addresses 0x400F 6000 (DIR0) to 0x400F 601C...
  • Page 402 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 246. GPIO masked port pin register (MPIN, addresses 0x400F 6180 (MPIN0) to 0x400F 619C (MPIN7)) bit description Symbol Description Reset Access value 31:0 MPORT Masked port register (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]).
  • Page 403 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 249. GPIO port toggle register (NOT, addresses 0x400F 6300 (NOT0) to 0x400F 632C (NOT7)) bit description Symbol Description Reset Access value 31:0 NOTP0 Toggle output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit 31 = GPIOn[31]): 0 = no operation.
  • Page 404 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO The state of a port’s output bits can be read from its SET register. Reading any of the registers described in 18.6.1 returns the state of pins, regardless of their direction or alternate functions.
  • Page 405 UM10430 NXP Semiconductors Chapter 18: LPC18xx GPIO Table 250. Pin interrupt registers for edge- and level-sensitive pins Name Edge-sensitive function Level-sensitive function IENR Enables rising-edge interrupts. Enables level interrupts. SIENR Write to enable rising-edge interrupts. Write to enable level interrupts.
  • Page 406 UM10430 Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Rev. 3.0 — 26 July 2017 User manual 19.1 How to read this chapter The GPDMA is available on all LPC18xx parts. The AES DMA request lines are only available on secure parts. 19.2 Basic configuration The GPDMA is configured as follows: Table 251...
  • Page 407 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Programmable DMA burst size. The DMA burst size can be programmed to more • efficiently transfer data. Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions.
  • Page 408 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 252. Peripheral connections to the DMA controller and matching flow control signals Peripheral SREQ BREQ Number muxing option (see Table SPIFI SPIFI SCT CTOUT_2 Reserved Reserved Timer3 match 1...
  • Page 409 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 252. Peripheral connections to the DMA controller and matching flow control signals Peripheral SREQ BREQ Number muxing option (see Table SSP0 receive SSP0 receive I2S0 DMA request 1 SCT DMA request 1 n.c.
  • Page 410 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller SREQ[15:0] — Single transfer request signals. These cause a single data to be transferred. The DMA controller transfers a single transfer to or from the peripheral. LBREQ[15:0] — Last burst request signals.
  • Page 411 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 253. Register overview: GPDMA (base address 0x4000 2000) …continued Name Access Address Description Reset value Reference offset SRCADDR0 0x100 DMA Channel 0 Source Address Register 0x0000 0000 Table 268...
  • Page 412 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 253. Register overview: GPDMA (base address 0x4000 2000) …continued Name Access Address Description Reset value Reference offset CONFIG6 0x1D0 DMA Channel 6 Configuration Register 0x0000 0000 Table 272...
  • Page 413 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.6.3 DMA Interrupt Terminal Count Request Clear Register The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt requests. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register (IntTCStat) to be cleared.
  • Page 414 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 258. DMA Interrupt Error Clear Register (INTERRCLR, address 0x4000 2010) bit description Symbol Description Reset Access value INTERRCLR Writing a 1 clears the error interrupt request (IntErrStat) 0x00 for DMA channels.
  • Page 415 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.6.8 DMA Enabled Channel Register The ENBLDCHNS Register is read-only and indicates which DMA channels are enabled, as indicated by the Enable bit in the CCONFIG Register. A HIGH bit indicates that a DMA channel is enabled.
  • Page 416 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 263. DMA Software Single Request Register (SOFTSREQ, address 0x4000 2024) bit description Symbol Description Reset Access value 15:0 SOFTSREQ Software single transfer request flags for each of 16 0x00 possible sources.
  • Page 417 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 265. DMA Software Last Single Request Register (SOFTLSREQ, address 0x4000 202C) bit description Symbol Description Reset Access value 15:0 SOFTLSREQ Software last single transfer request flags for each of 0x00 16 possible sources.
  • Page 418 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 267. DMA Synchronization Register (SYNC, address 0x4000 2034) bit description Symbol Description Reset Access value 15:0 DMACSYNC Controls the synchronization logic for DMA request 0x00 signals. Each bit represents one set of DMA request...
  • Page 419 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.6.17 DMA Channel Destination Address registers The eight read/write DESTADDR Registers contain the current destination address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the channel is enabled.
  • Page 420 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 271. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description Symbol Value Description Reset Access value 11:0 TRANSFERSIZE Transfer size in number of transfers. A write to this field sets the size of the transfer when the DMA Controller is the flow controller.
  • Page 421 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 271. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description …continued Symbol Value Description Reset Access value 20:18 SWIDTH Source transfer width. Transfers wider than the AHB master bus width are illegal.
  • Page 422 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 271. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description …continued Symbol Value Description Reset Access value Terminal count interrupt enable bit. The terminal count interrupt is disabled.
  • Page 423 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 272. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value SRCPERIPHERAL Source peripheral. This value selects the DMA source request peripheral.
  • Page 424 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 272. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value 10:6 DESTPERIPHERAL Destination peripheral. This value selects the DMA destination request peripheral.
  • Page 425 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 272. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value Active: 0 = there is no data in the FIFO of the channel.
  • Page 426 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.7 Functional description 19.7.1 DMA controller functional description The DMA Controller enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive.
  • Page 427 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit quantities. This means that when performing mixed-endian activity, where the endianness of the source and destination are different, byte swapping of the data within the 32-bit data bus is observed.
  • Page 428 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Table 274. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[31:0]...
  • Page 429 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.7.1.6.3 Error conditions An error during a DMA transfer is flagged directly by the peripheral by asserting an Error response on the AHB bus during the transfer. The DMA Controller automatically disables the DMA stream after the current transfer has completed, and can optionally generate an error interrupt to the CPU.
  • Page 430 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.8.1.4 Disabling a DMA channel A DMA channel can be disabled in three ways: • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used.
  • Page 431 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 19.8.2 Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMA Controller where the packet length is programmed by software before the DMA channel is enabled.
  • Page 432 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 1. Program and enable the DMA channel. 2. Wait for a DMA request. 3. The DMA Controller starts transferring data when: – The DMA request goes active. – The DMA stream has the highest pending priority.
  • Page 433 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller – The DMA Controller responds with a DMA acknowledge to the destination peripheral. – The terminal count interrupt is generated (this interrupt can be masked). – If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI, and CCONTROL Registers and go to back to step 2.
  • Page 434 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 4. For a terminal count interrupt, write a 1 to the relevant bit of the INTTCCLR Register. For an error interrupt write a 1 to the relevant bit of the INTERRCLR Register to clear the interrupt request.
  • Page 435 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller 3. CLLI 4. CCONTROL Note: The CCONFIG DMA channel Configuration Register is not part of the linked list item. 19.8.5.1.1 Programming the DMA controller for scatter/gather DMA To program the DMA Controller for scatter/gather DMA: 1.
  • Page 436 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Linked List Array LLI 1 Source address 0x2000 A200 0x2000 0000 0x2000 A200 Destination address = peripheral 0x2000 0010 Next LLI address Control information = length 3072 3072 bytes of data...
  • Page 437 UM10430 NXP Semiconductors Chapter 19: LPC18xx General Purpose DMA (GPDMA) controller Source and destination burst sizes, 16 transfers. • • Next LLI address, 0x2000 0020. A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x2000 0000, is programmed into the DMA Controller.
  • Page 438 UM10430 Chapter 20: LPC18xx SD/MMC interface Rev. 3.0 — 26 July 2017 User manual 20.1 How to read this chapter The SD/MMC card interface is available on all parts. 20.2 Basic configuration The SD/MMC interface is configured as follows: • The SD/MMC is reset by the SDIO_RST (reset # 20).
  • Page 439 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.4 General description The SD/MMC controller interface consists of the following main functional blocks: • Bus Interface Unit (BIU) - Provides AHB and DMA interfaces for register and data read/writes. Card Interface Unit (CIU) - Handles the card protocols and provides clock •...
  • Page 440 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.5 Pin description Table 277. SD/MMC pin description Pin function Direction Description SD_CLK SD/SDIO/MMC clock SD_CD SDIO card detect for single slot SD_WP SDIO card write protect SD_LED LED On signal. This signal cautions the user not to remove the SD card while it is accessed.
  • Page 441 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 278. Register overview: SDMMC (base address: 0x4000 4000) Name Access Address Description Reset value Reference offset FIFOTH 0x04C FIFO Threshold Watermark Register 0x0F80 0000 Table 298 CDETECT 0x050 Card Detect Register...
  • Page 442 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 279. Control Register (CTRL, address 0x4000 4000) bit description Symbol Value Description Reset value FIFO_RESET Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.
  • Page 443 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 279. Control Register (CTRL, address 0x4000 4000) bit description Symbol Value Description Reset value SEND_CCSD Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device.
  • Page 444 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.2 Power Enable Register (PWREN) Table 280. Power Enable Register (PWREN, address 0x4000 4004) bit description Symbol Description Reset value POWER_ENABLE Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.
  • Page 445 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.4 SD Clock Source Register (CLKSRC) Table 282. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description Symbol Description Reset value CLK_SOURCE Clock divider source for SD card. 00 - Clock divider 0...
  • Page 446 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.7 Card Type Register (CTYPE) Table 285. Card Type Register (CTYPE, address 0x4000 4018) bit description Symbol Description Reset value CARD_WIDTH0 Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode...
  • Page 447 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 288. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description Symbol Description Reset value TXDR Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.
  • Page 448 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.12 Command Register (CMD) Table 290. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value CMD_INDEX Command index RESPONSE_EXPECT Response expect No response expected from card Response expected from card...
  • Page 449 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 290. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value STOP_ABORT_CMD Stop abort cmd. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state.
  • Page 450 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 290. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value CCS_EXPECTED CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit.
  • Page 451 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.14 Response Register 1 (RESP1) Table 292. Response Register 1 (RESP1, address 0x4000 4034) bit description Symbol Description Reset value 31:0 RESPONSE1 Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register.
  • Page 452 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 295. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description Symbol Description Reset value DRTO Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.
  • Page 453 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 296. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description Symbol Description Reset value RCRC Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.
  • Page 454 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.19 Status Register (STATUS) Table 297. Status Register (STATUS, address 0x4000 4048) bit description Symbol Description Reset value FIFO_RX_ FIFO reached Receive watermark level; not qualified with data transfer. WATERMARK FIFO_TX_ FIFO reached Transmit watermark level; not qualified with data transfer.
  • Page 455 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.20 FIFO Threshold Watermark Register (FIFOTH) Table 298. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Symbol Value Description Reset value 11:0 TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised.
  • Page 456 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 298. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Symbol Value Description Reset value 30:28 DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter.
  • Page 457 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.23 Transferred CIU Card Byte Count Register (TCBCNT) Table 301. Transferred CIU Card Byte Count Register (TCBCNT, address 0x4000 405C) bit description Symbol Description Reset value Number of bytes transferred by CIU unit to card.
  • Page 458 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.27 Bus Mode Register (BMOD) Table 305. Bus Mode Register (BMOD, address 0x4000 4080) bit description Symbol Value Description Reset value Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write.
  • Page 459 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.6.29 Descriptor List Base Address Register (DBADDR) Table 307. Descriptor List Base Address Register (DBADDR, address 0x4000 4088) bit description Symbol Description Reset value 31:0 Start of Descriptor List. Contains the base address of the First Descriptor.
  • Page 460 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 308. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description Symbol Description Reset value 12:10 EB Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.
  • Page 461 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 309. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit description Symbol Description Reset value Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled.
  • Page 462 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface The card detection signal is debounced based on the number of blocks specified in the Debounce Count Register (DEBNCE). When this signal is connected to the card detect pin of the card slot, then CDETECT register's bit 0 state will be filtered by the number of debounce cycles specified in DEBNCE.
  • Page 463 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface The condition under which the transfer mode is set to block transfer and byte_count is equal to block size is treated as a single-block data transfer command for both MMC and SD cards. If byte_count = n...
  • Page 464 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Before issuing a new data transfer command, the software should ensure that the card is not busy due to any previous data transfer command. Before changing the card clock frequency, the software must ensure that there are no data or command transfers in progress.
  • Page 465 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface One data-transfer requirement between the FIFO and cpu is that the number of transfers should be a multiple of the FIFO data width (F_DATA_WIDTH), which is 32. So if you want to write only 15 bytes to an SD/MMC/CE-ATA card (BYTCNT), the cpu should write 16 bytes to the FIFO or program the DMA to do 16-byte transfers, if DMA mode is enabled.
  • Page 466 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Enumerates all connected cards • • Sets the RCA for the connected cards Reads card-specific information • Stores card-specific information locally • Enumerate_Card_Stack - Enumerates the card connected on the module. The card can be of the type MMC, CE-ATA, SD, or SDIO.
  • Page 467 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface CLKDIV @0x08 = 0x0 (bypass of clock divider). • • CLKSRC @0x0C = 0x0 CLKENA @0x10 =0x0 or 0x1. This register enables or disables clock for the card and • enables low-power mode, which automatically stops the clock to a card when the card is idle for more than 8 clocks.

  • Page 468: Start_Cmd

    UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface – Check if response_timeout error, response_CRC error, or response error is set. This can be done either by responding to an interrupt raised by these errors or by polling bits 1, 6, and 8 from the RINTSTS register @0x44. If no response error is received, then the response is valid.
  • Page 469 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface For the data transfer commands, it is important that the same bus width that is programmed in the card should be set in the card type register @0x18. Therefore, in order to change the bus width, you should always use the following supplied APIs as...

  • Page 470: Transfer_Mode

    UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 5. Software should look for Receive_FIFO_Data_request and/or data starvation by cpu time-out conditions. In both cases, the software should read data from the FIFO and make space in the FIFO for receiving more data.
  • Page 471 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 3. Program CMDARG register @0x28 with the data address to which data should be written. 4. Write data in the FIFO; it is usually best to start filling data the full depth of the FIFO.

  • Page 472: User-Selectable Wait_Prvdata_Complete

    UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 315. CMD register settings for Single-block or Multiple-block write Name Value Comments User-selectable Wait_prvdata_complete Before sending command on command line, cpu should wait for completion of any data command in process, if any (recommended to...
  • Page 473 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Send STOP command - Can be sent on the command line while a data transfer is in • progress; this command can be sent at any time during a data transfer. For information on sending this command, refer to "No-Data Command With or Without...
  • Page 474 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface The following functions can be implemented by programming the appropriate bits in the CCCR register (Function 0) of the SDIO card. To read from or write to the CCCR register, use the CMD52 command.
  • Page 475 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface If the DF flag is 0, then in case of a read, the Module waits for data. After the data time-out period, it gives a data time-out error. Table 317. Parameters for CMDARG register...
  • Page 476 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.7.5.2.2 ATA Task File Transfer ATA task file registers are mapped to addresses 0x00h-0x10h in the MMC register space. RW_REG is used to issue the ATA command, and the ATA task file is transmitted in a single RW_REG MMC command sequence.

  • Page 477: Comment

    UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 319. CMD register settings Name Value Comment start_cmd Css_expect Command Completion Signal is not expected Read_ceata_device 1 – If RW_BLK or RW_REG read update_clock_ registers_only No clock parameters update command card_number Card number in use.

  • Page 478: Table Of Contents

    UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 1. Write the data size in bytes in the BYTCNT register @0x20. 2. Write the block size in bytes in the BLKSIZ register @0x1C. The Module expects a single/multiple block transfer. 3. Program the CMDARG register @0x28 to indicate the Data Unit Count.
  • Page 479 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Program the block size (BLKSIZ) register as shown below. • Table 324. BLKSIZ register Bits Value Comment 31:16 Reserved bits as zeroes (0) 15:0 512, 1024, 4096 MMC block size can be 512, 1024, or 4096 bytes as negotiated by CPU Program the Byte Count (BYTCNT) register as shown below.
  • Page 480 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface IDENTIFY DEVICE - Returns 512-byte data structure to the cpu that describes • device-specific information and capabilities. The cpu issues the IDENTIFY DEVICE command only if the MMC block size is set to 512 bytes; any other MMC block size has indeterminate results.
  • Page 481 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface – Command field of the ATA task file set to E0h – Reserved fields of the task file cleared to 0 BLKSIZ register bits [15:0] and BYTCNT register - Set to 16 •...
  • Page 482 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Generic DMA mode - Simultaneously sets controller_reset, fifo_reset, and dma_reset; • clears the RAWINTS register @0x44 by using another write in order to clear any resultant interrupt. If a "graceful" completion of the DMA is required, then it is recommended to poll the status register to see whether the dma request is 0 before resetting the DMA interface control and issuing an additional FIFO reset.
  • Page 483 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface CRC Error on Command - If a CRC error is detected for a command, the CE-ATA • device does not send a response, and a response time-out is expected from the Module. The ATA layer is notified that an MMC transport layer error occurred.
  • Page 484 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Data Buffer Descriptor A Data Buffer Descriptor B Data Buffer Descriptor C Fig 46. Chain descriptor structure 20.7.6.1 SD/MMC DMA descriptors 20.7.6.1.1 SD/MMC DMA descriptor DESC0 The DES0 descriptor contains control and status information.
  • Page 485 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 326. SD/MMC DMA DESC0 descriptor Symbol Description 29:6 Reserved Card Error Summary These error bits indicate the status of the transaction to or from the card. These bits are also present in RINTSTS Indicates the logical OR of the following bits: •...
  • Page 486 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface Table 329. SD/MMC DMA DESC3 descriptor Symbol Description 31:0 BAP2 Buffer Address Pointer 2/ Next Descriptor Address These bits indicate the physical address of the second buffer when the dual-buffer structure is used. If the Second Address Chained (DES0[4]) bit is set, then this address contains the pointer to the physical memory where the Next Descriptor is present.
  • Page 487 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 20.7.6.6 Transmission The SD/MMC transmission occurs as follows: 1. The Host sets up the Descriptor (DES0-DES3) for transmission and sets the OWN bit (DES0[31]). The Host also prepares the data buffer. 2. The Host programs the write data command in the CMD register in BIU.
  • Page 488 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface 7. The SD/MMC DMA engine will now wait for a DMA interface request (dw_dma_req) from BIU. This request will be generated based on the programmed receive threshold value. For the last bytes of data which can’t be accessed using a burst, SINGLE transfers are performed on AHB.
  • Page 489 UM10430 NXP Semiconductors Chapter 20: LPC18xx SD/MMC interface In case of a write abort, only the current descriptor during which an abort occurred is • closed by the SD/MMC DMA . The remaining unread descriptors are not closed by the IDMAC.
  • Page 490 UM10430 Chapter 21: LPC18xx SPI Flash Interface (SPIFI) Rev. 3.0 — 26 July 2017 User manual 21.1 How to read this chapter The SPIFI is available on all LPC18xx parts. A software driver library is available on LPCware.com. Section 4.3.6.4 “SPIFI boot mode” for details on the SPIFI boot process.
  • Page 491 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) Many SPI flash devices use serial commands for device setup/initialization, and then move to dual or quad commands for normal operation. Different serial Flash vendors and devices accept or require different commands and command formats. SPIFI includes sufficient flexibility to be compatible with many market-leading devices plus extensions to help insure compatibility with future devices.
  • Page 492 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) Table 334. Register overview: SPIFI (base address 0x4000 3000) Name Access Address Description Reset value offset CTRL 0x000 SPIFI control register 0x400F FFFF 0x004 SPIFI command register 0x0000 0000 ADDR...
  • Page 493 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) Table 335. SPIFI control register (CTRL, address 0x4000 3000) bit description Symbol Value Description Reset value PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.
  • Page 494 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) Table 336. SPIFI command register (CMD, address 0x4000 3004) bit description Symbol Value Description Reset value 13:0 DATALEN Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command.
  • Page 495 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) 21.6.3 SPIFI address register Before writing a command that includes an address field to the Command register, software should write the address to this register. The most significant byte of the address is sent first.
  • Page 496 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) After initiating a command that includes a data input field by writing to the Command Register, software should read input data from this register. Load Byte instructions deliver one data byte to software, Load Halfword instructions deliver two bytes, and Load Word instructions deliver 4 bytes of input data.
  • Page 497 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) Table 341. SPIFI memory command register (MCMD, address 0x4000 3018) bit description Symbol Value Description Reset value 20:19 FIELDFORM This field controls how the fields of the command are sent.
  • Page 498 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) 21.7 Functional description 21.7.1 Data transfer Serial SPI uses the the signals SPIFI_SCK, SPIFI_CS,SPIFI_MISO, and SPIFI_MISO, while quad mode adds the two IO signals SPIFI_SIO[3:2]. The SPIFI implements basic, dual, and quad SPI in half-duplex mode, in which the SPIFI always sends a command to a serial flash memory at the start of each frame.
  • Page 499 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) SPIFI_CS SPIFI_SCK SPIFI_MOSI Opcode-only command in SPI mode SPIFI_CS SPIFI_SCK IO0 (SPIFI_IO0) IO1 (SPIFI_IO1) IO2 (SPIFI_SIO2) IO3 (SPIFI_SIO3) Opcode-only command in quad mode Fig 47. Opcode only commands Figure 48...
  • Page 500 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) 21.7.2 Software requirements and capabilities During device set-up, software should initialize the external serial flash device using those commands that place it in its highest-performance mode. When this sequence is complete, software should write the command that will be issued in response to a read from the serial flash region of the memory map, to the Memory Command Register.
  • Page 501 UM10430 NXP Semiconductors Chapter 21: LPC18xx SPI Flash Interface (SPIFI) When erasing or programming completes, software can do further programming or erasing, or return to normal (memory mode) operation. 21.7.3 Peripheral mode DMA operation The SPIFI inserts wait states when necessary during read and write operations by the core to maintain synchronization between core accesses and serial data transfer with the serial flash.
  • Page 502 UM10430 Chapter 22: LPC18xx External Memory Controller (EMC) Rev. 3.0 — 26 July 2017 User manual 22.1 How to read this chapter The EMC is available on all LPC18xx parts. The memory and address bus widths depend on package size. Table 343.
  • Page 503 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Program the SDRAM Delay value for the EMC_CLKn lines in the EMCDELAYCLK • register in the SCU block. (See Section 16.4.9.) Add the SDRAM delay for most SDRAM devices running at frequencies above 96 MHz under typical conditions. Add the SDRAM delay at any frequency to compensate for variations over temperature.
  • Page 504 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Remark: Synchronous static memory devices (synchronous burst mode) are not supported. 22.4 General description The LPC18xx External Memory Controller (EMC) is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.
  • Page 505 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Dynamic memories are mapped above 0x1FFF FFFF. This memory area is addressed by the M3 S-bus. When the M3 core is executing from SDRAM not much bandwidth is remaining for lower priority bus masters (other bus masters except for the LCD controller).
  • Page 506 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) 22.5 Pin description Table 346. EMC pin description Pin function Direction Description EMC_A[23:0] Address bus EMC_D[31:0] Data bus EMC_BLS[3:0] Byte lane select EMC_CS[3:0] Static RAM memory bank select EMC_OE Output enable...
  • Page 507 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 347. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot DYNAMICRAS 0x034 Selects the active to precharge command Table 355 period.
  • Page 508 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 347. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot DYNAMICRASCAS3 0x164 Selects the RAS and CAS latencies for...
  • Page 509 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 347. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot STATICWAITOEN2 0x248 Selects the delay from chip select 2 or...
  • Page 510 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 348. EMC Control register (CONTROL - address 0x4000 5000) bit description Symbol Value Description Reset value EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed.
  • Page 511 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 349. EMC Status register (STATUS - address 0x4000 5004) bit description Symbol Value Description Reset value Self-refresh acknowledge. This bit indicates the operating mode of the EMC: Normal mode Self-refresh mode (POR reset value).
  • Page 512 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 351. Dynamic Control register (DYNAMICCONTROL - address 0x4000 5020) bit description Symbol Value Description Reset value Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode.
  • Page 513 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 352. Dynamic Memory Refresh Timer register (DYNAMICREFRESH - address 0x4000 5024) bit description Symbol Description Reset value 10:0 REFRESH Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles.
  • Page 514 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 353. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG - address 0x4000 5028) bit description Symbol Value Description Reset value Read data strategy. Do not use. POR reset value. Command delayed by 1/2 EMC_CCLK.
  • Page 515 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) 22.6.9 Dynamic Memory Self Refresh Exit Time register This register enables you to program the self-refresh exit time, tSREX. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions.
  • Page 516 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 358. Dynamic Memory Data In to Active Command Time register (DYNAMICDAL - address 0x4000 5040) bit description Symbol Description Reset value TDAL Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles.
  • Page 517 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) 22.6.14 Dynamic Memory Auto-refresh Period register This register enables you to program the auto-refresh period, and auto-refresh to active command period, tRFC. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions.
  • Page 518 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 363. Dynamic Memory Active Bank A to Active Bank B Time register (DYNAMICRRD - address 0x4000 5054) bit description Symbol Description Reset value TRRD Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
  • Page 519 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) For example, for a static memory read/write transfer time of 16 µs, and a EMC_CCLK frequency of 50 MHz, the following value must be programmed into this register: (16 x 10 x 50 x 10 ) / 16 - 1 = 49.
  • Page 520 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 367. Address mapping 11:9 8:7 Description 16 bit external bus address mapping (Row, Bank, Column) 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9 16 Mb (1Mx16), 2 banks, row length = 11, column length = 8...
  • Page 521 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 367. Address mapping 11:9 8:7 Description 16 Mb (1Mx16), 2 banks, row length = 11, column length = 8 64 Mb (8Mx8), 4 banks, row length = 12, column length = 9...
  • Page 522 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 368. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS[0:3], address 0x4000 5104 (DYNAMICRASCAS0), 0x4000 5124 (DYNAMICRASCAS1), 0x4000 5144 (DYNAMICRASCAS2), 0x4000 5164 (DYNAMICRASCAS3)) bit description Symbol Value Description Reset value RAS latency (active to read/write delay).
  • Page 523 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 369. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200 (STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240 (STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description Symbol Value Description Reset value Page mode. In page mode the EMC can burst up to four external accesses.
  • Page 524 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 369. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200 (STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240 (STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description Symbol Value Description Reset value Write protect. Writes not protected (POR reset value).
  • Page 525 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 371. Static Memory Output Enable delay registers (STATICWAITOEN[0:3], address 0x4000 5208 (STATICWAITOEN0), 0x4000 5228 (STATICWAITOEN1), 0x4000 5248 (STATICWAITOEN2), 0x4000 5268 (STATICWAITOEN3)) bit description Symbol Description Reset value WAITOEN Wait output enable.
  • Page 526 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 373. Static Memory Page Mode Read Delay registers (STATICWAITPAGE[0:3], address 0x4000 5210 (STATICWAITPAGE0), 0x4000 5230 (STATICWAITPAGE1), 0x4000 5250 (STATICWAITPAGE2), 0x4000 5270 (STATICWAITPAGE3)) bit description Symbol Description Reset value WAITPAGE Asynchronous page mode read after the first read wait states.
  • Page 527 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 375. Static Memory Turn-around Delay registers (STATICWAITTURN[0:3], address 0x4000 5218 (STATICWAITTURN0), 0x4000 5238 (STATICWAITTURN1), 0x4000 5258 (STATICWAITTURN2), 0x4000 5278 (STATICWAITTURN3)) bit description Symbol Description Reset value WAITTURN Bus turn-around cycles.
  • Page 528 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) 22.7 Functional description Figure 49 shows a block diagram of the EMC. The functions of the EMC blocks are described in the following sections: AHB slave register interface. • AHB slave memory interfaces.
  • Page 529 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) For static memory larger delays are defined by in steps of one EMC clock cycle by the STATICWAIT registers (see Section 22.6.22 Section 22.6.27). 22.7.4 Data buffers The AHB interface reads and writes via buffers to improve memory bandwidth and reduce transaction latency.
  • Page 530 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Convert all read transactions into quadword bursts on the external memory interface. This enhances transfer efficiency for dynamic memory. Reduce external memory traffic. This improves memory bandwidth and reduces •...
  • Page 531 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) Table 376. SDRAM mode register description Address line SDRAM mode Value Description register bit Burst type Sequential Interleaved A6:A4 Latency mode Reserved Reserved Reserved Reserved Reserved Reserved A8:A7 Operating mode. All other values are reserved.
  • Page 532 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) – This is the number of bits needed to indicate the number of banks. Most SDRAM devices use 2 bank select bits for four banks. Select the SDRAM memory mapped address DYCSX.
  • Page 533 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) 22.7.6 External static memory interface External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding StaticConfig register). If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines.
  • Page 534 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) BLS[3] BLS[2] BLS[1] BLS[0] IO[31:0] D[31:0] A[a_m:0] A[a_b:2] c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 51. 32 bit bank external memory interfaces ( bits MW = 10) 22.7.6.2 16 bit wide memory bank connection...
  • Page 535 UM10430 NXP Semiconductors Chapter 22: LPC18xx External Memory Controller (EMC) 22.7.6.3 8 bit wide memory bank connection IO[7:0] D[7:0] A[a_m:0] A[a_b:0] Fig 53. 8 bit bank external memory interface (bits MW = 00) UM10430 All information provided in this document is subject to legal disclaimers.
  • Page 536 UM10430 Chapter 23: LPC18xx USB0 Host/Device/OTG controller Rev. 3.0 — 26 July 2017 User manual 23.1 How to read this chapter The USB0 Host/Device/OTG controller is available on parts LPC185x, LPC183x and LPC182x. USB frame length adjustment is available for parts with on-chip flash only. 23.2 Basic configuration The USB0 Host/Device/OTG controller is configured as follows: Table 377...
  • Page 537 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Supports software HNP and SRP for OTG peripherals. • • Supports power management. Supports six logical endpoints including one control endpoint for a total of 12 physical • endpoints. • This module has its own, integrated DMA engine.
  • Page 538 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.4.3 USB acronyms and abbreviations Table 378. USB related acronyms Acronym Description Analog Transceiver Device Controller Driver device Endpoint Queue Head device Transfer Descriptor End Of Packet End Point Full Speed...
  • Page 539 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 379. Fixed endpoint configuration Logical Physical Endpoint type Direction endpoint endpoint Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Table 380. USB Packet size Endpoint type Speed Packet size (byte) Control Low-speed Full-speed...
  • Page 540 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 381. USB0 pin description Pin function Direction Description USB0_VBUS VBUS pin (power on USB cable). This pin includes an internal pull-down resistor of 64 kOhm (typical) ± 16 kOhm. For maximum load C = 6.5 uF and maximum...
  • Page 541 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 383. Register overview: USB0 OTG controller (register base address 0x4000 6000) Name Access Address Description Reset Reset value Reference offset value after USB0 boot 0x000 - Reserved 0x0FF Device/host capability registers...
  • Page 542 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 383. Register overview: USB0 OTG controller (register base address 0x4000 6000) …continued Name Access Address Description Reset Reset value Reference offset value after USB0 boot BINTERVAL 0x174 Length of virtual frame...
  • Page 543 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Hardware reset or USBCMD RST bit = 1 IDLE MODE = 00 write 10 to USBMODE write 11 to USBMODE DEVICE HOST MODE = 10 MODE = 11 Fig 55. USB controller modes The following registers and register bits are used for OTG operations.
  • Page 544 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.6.2 Device/host capability registers Table 384. System bus interface configuration register (SBUSCFG - address 0x4000 6090) bit description Symbol Value Description Access Reset value AHB_BRST The burst length used by the USB controller can be selected using these bits.
  • Page 545 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 386. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) …continued Symbol Description Reset Access value 15:12 N_CC Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller.
  • Page 546 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 389. DCCPARAMS (address 0x4000 6124) Symbol Description Reset value Access Device Endpoint Number. These bits are reserved and should be set to zero. Device Capable. Host Capable. 31:9 These bits are reserved and should be set to zero.
  • Page 547 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 390. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description …continued Symbol Value Description Access Reset value SUTW Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted.
  • Page 548 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 391. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Symbol Value Description Access Reset value Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the host/device controller when the reset process is complete.
  • Page 549 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 391. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Symbol Value Description Access Reset value Reserved. ASPE Asynchronous Schedule Park Mode Enable Park mode is disabled.
  • Page 550 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.6.4.1 Device mode Table 393. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB interrupt R/WC This bit is cleared by software writing a one to it.
  • Page 551 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 393. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB reset received R/WC This bit is cleared by software writing a one to it.
  • Page 552 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.6.4.2 Host mode Table 394. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB interrupt (USBINT) R/WC This bit is cleared by software writing a one to it.
  • Page 553 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 394. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued Symbol Value Description Reset Access value Not used by the Host controller. 11:9 Reserved.
  • Page 554 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 394. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued Symbol Value Description Reset Access value USB host periodic interrupt (USBHSTPERINT) R/WC This bit is cleared by software writing a one to it.
  • Page 555 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 395. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description …continued Symbol Description Reset Access value SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt.
  • Page 556 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 396. USB Interrupt register in host mode (USBINTR_H - address 0x4000 6148) bit description …continued Symbol Description Reset Access value Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold.
  • Page 557 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.6.6.2 Host mode This register is used by the host controller to index the periodic frame list. The register updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution.
  • Page 558 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 400. USB Device Address register in device mode (DEVICEADDR - address 0x4000 6154) bit description Symbol Value Description Reset Access value 23:0 Reserved USBADRA Device address advance Any write to USBADR are instantaneous.
  • Page 559 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 402. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 6158) bit description Symbol Description Reset Access value 10:0 Reserved 31:11 EPBASE31_11 Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 12 Queue Heads (QH).
  • Page 560 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 405. USB burst size register (BURSTSIZE - address 0x4000 6160) bit description - device/host mode Symbol Description Reset Access value RXPBURST Programmable RX burst length 0x10 This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
  • Page 561 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 406. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 6164) bit description Symbol Description Reset Access value TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.
  • Page 562 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.6.13 USB Endpoint NAK register (ENDPTNAK) 23.6.13.1 Device mode This register indicates when the device sends a NAK handshake on an endpoint. Each Tx and Rx endpoint has a bit in the EPTN and EPRN field respectively.
  • Page 563 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 409. USB Endpoint NAK Enable register (ENDPTNAKEN - address 0x4000 617C) bit description Symbol Description Reset Access value EPRNE Rx endpoint NAK enable 0x00 Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set.
  • Page 564 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 410. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Symbol Value Description Reset Access value Reserved Force port resume After the device has been in Suspended state for 5 ms or more, software must set this bit to one to drive resume signaling before clearing.
  • Page 565 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 410. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Symbol Value Description Reset Access value 19:16 PTC3_0 Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode.
  • Page 566 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.6.15.2 Host mode The host controller uses one port. The register is only reset when power is initially applied or in response to a controller reset. The initial conditions of the port are: No device connected •...
  • Page 567 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 411. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value Port disable/enable change R/WC For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification).
  • Page 568 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 411. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, Table 412.
  • Page 569 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 411. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on).
  • Page 570 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 411. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value WKOC Wake on over-current enable (WKOC_E) Disables the port to wake up on over-current events.
  • Page 571 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller The status inputs are debounced using a 1 msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the status input register or cause an OTG interrupt.
  • Page 572 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 413. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Symbol Value Description Reset Access value IDIS USB ID interrupt status R/WC This bit is set when a change on the ID input has been detected.
  • Page 573 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 413. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Symbol Value Description Reset Access value MS1E 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt.
  • Page 574 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 414. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: Disabling stream mode substantially limits the overall USB performance that can be achieved.
  • Page 575 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 415. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: Disabling stream mode substantially limits the overall USB performance that can be achieved.
  • Page 576 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 417. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 61B0) bit description Symbol Description Reset Access value PERB Prime endpoint receive buffer for physical OUT endpoints 5 to 0. R/WS...
  • Page 577 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 418. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description Symbol Description Reset Access value 15:6 Reserved R/WC 21:16 FETB Flush endpoint transmit buffer for physical IN endpoints 5 to 0.
  • Page 578 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Writing a one will clear the corresponding bit in this register. Table 420. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 61BC) bit description Symbol Description Reset Access value ERCE Endpoint receive complete event for physical OUT endpoints 5 to 0.
  • Page 579 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 421. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description …continued Symbol Value Description Reset Access value Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host.
  • Page 580 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 422. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Symbol Value Description Reset Access value Reserved Endpoint type...
  • Page 581 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 422. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Symbol Value Description Reset Access value Tx data toggle inhibit This bit is only used for test and should always be written as zero.
  • Page 582 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.7.5 ATX transceiver The USB-OTG has a USB transceiver with UTMI+ interface. It contains the required transceiver OTG functionality; this includes: VBUS sensing for producing the session-valid and VBUS-valid signals. •...
  • Page 583 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller consumption rate, then software can reduce the SOF length using the USB0FLADJ register. The USB bit clock is still running at the normal rate so no bus errors occur. The host only changes when it introduces the next SOF token - earlier or later on a bit-time resolution boundary.
  • Page 584 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller The hardware assist consists of the following steps: 1. Hardware resets the OTG controller (writes 1 to the RST bit in USBCMD). 2. Hardware selects the device mode (writes 10 to bits CM[1:0] in USBMODE).
  • Page 585 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller block in the system, the transaction translator function normally associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The embedded transaction translator function is an extension to EHCI interface but makes use of the standard data structures and operational models that exist in the EHCI specification to support full and low speed devices.
  • Page 586 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.8.1.4 Data structures The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root Hub with an embedded Transaction Translator. Here it is...
  • Page 587 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.8.1.6 Split state machines The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simply an internal operation to the embedded Transaction Translator.
  • Page 588 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller There is no data schedule mechanism for these transactions other than micro-frame pipeline. The embedded TT assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior may result.
  • Page 589 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Software writes a ‘1’ to the port reset bit in the PORTSC1 register to reset the device. • • Software writes a ‘0’ to the port reset bit in the PORTSC1 register after 10 ms.
  • Page 590 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Endpoint Transfer Endpoint Queue Heads Descriptors dTD Endpoint dQH5 - IN Endpoint dQH5 - OUT TRANSFER transfer buffer BUFFER pointer TRANSFER BUFFER transfer buffer Endpoint dQH1 - OUT pointer TRANSFER Control Endpoint dQH0 - IN...
  • Page 591 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller device Queue Head (dQH) transfer overlay offset ENDPOINT CAPABILITIES/CHARACTERISTICS 0x00 0x04 CURRENT dTD POINTER endpoint transfer descriptor (dTD) 0x08 NEXT dTD POINTER NEXT dTD POINTER 0x0C Total_bytes MulO STATUS Total_bytes MulO...
  • Page 592 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 425. Endpoint capabilities and characteristics Access Name Description 31:30 MULT Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD.
  • Page 593 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.9.1.3 Transfer overlay descriptor fields The seven DWords in the overlay area represent a transaction working space for the device controller. The general operational model is that the device controller can detect whether the overlay area contains a description of an active transfer.
  • Page 594 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 429. dTD token Access Name Description reserved 30:16 Total_bytes Total bytes This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction and it is decremented only when the transaction has been completed successfully.
  • Page 595 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 430. dTD buffer page pointer list Access Name Description 31:12 BUFF_P Selects the page offset in memory for the packet buffer. Non-virtual memory systems will typically set the buffer pointers to a series of incrementing integers.
  • Page 596 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Remark: Transitioning from host mode to device mode requires a device controller reset before modifying USBMODE. 2. Allocate and Initialize device queue heads in system memory (see Section 23.9). Minimum: Initialize device queue heads 0 Tx & 0 Rx.
  • Page 597 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller active state Powered inactive state set Run/Stop bit to Run mode power interruption Attached reset bus inactive Default Suspended FS/HS FS/HS bus activity when the host resets, the device returns to default...
  • Page 598 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller It is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HS state and the Address/Configured states. Change of state from Default to Address and the configured states is part of the enumeration process described in the Device Framework section of the USB 2.0 Specification.
  • Page 599 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the data rate issue, there is no difference in DCD operation between FS and HS modes.
  • Page 600 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.10.5 Managing endpoints The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a uniquely addressable portion of a USB device that can source or sink data in a communications channel between the host and the device.
  • Page 601 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.10.5.2 Stalling There are two occasions where the device controller may need to return to the host a STALL: 1. The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0 device framework (chapter 9).
  • Page 602 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Setting the data toggle Inhibit bit active (‘1’) causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state.
  • Page 603 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller transaction starts. The FIFO must be sized to account for the maximum latency that can be incurred by the system memory bus. On the LPC18xx, 128 x 36 bit dual port memory FIFOs are used for each IN endpoint.
  • Page 604 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller RX-dTD is complete when: All packets described in the dTD were successfully received. The Total_bytes field in • the dTD will equal zero when this occurs. • A short packet (number of bytes < maximum packet length) was received. This is a successful transfer completion;...
  • Page 605 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures that while software is reading the setup packet stored in the queue head, that data is not written as it is being read potentially causing an invalid setup packet.
  • Page 606 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller f. Process setup packet using local software byte array copy and execute status/handshake phases. g. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’. A poll loop should be used to wait until ENDPTSETUPSTAT transitions to ‘0’ after step •...
  • Page 607 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 436. Control endpoint bus response matrix Token Endpoint state Setup type lockout STALL Not primed Primed Underflow Overflow Setup SYSERR STALL Transmit BS error STALL Receive and NYET/ACK Ping STALL...
  • Page 608 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs the device controller will force-retire the ISO-dTD and move to the next ISO-dTD.
  • Page 609 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Remark: Priming an endpoint towards the end of (micro) frame N-1 will not guarantee delivery in (micro) frame N. The delivery may actually occur in (micro) frame N+1 if the device controller does not have enough time to complete the prime before the SOF for packet N is received.
  • Page 610 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller software is required to track all transfer descriptors since pointers will no longer exist within the queue head once the dTD is retired (see Section 23.10.11.1). In addition to the current and next pointers and the dTD overlay examined in section Section 23.10.6, the dQH also contains the following parameters for the associated...
  • Page 611 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.10.11 Managing transfers with transfer descriptors 23.10.11.1 Software link pointers It is necessary for the DCD software to maintain head and tail pointers to the linked list of dTDs for each respective queue head. This is necessary because the dQH only maintains pointers to the current working dTD and the next dTD to be executed.
  • Page 612 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 23.10.11.3 Executing a transfer descriptor To safely add a dTD, the DCD must follow this procedure which will handle the event where the device controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list.
  • Page 613 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in the Device Error Matrix (see Table 438). In addition to checking the status bit, the DCD must read the Total_bytes field to determine the actual bytes transferred.
  • Page 614 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 438. Device error matrix Error Direction Packet type Data buffer error Transaction error bit Overflow ISO packet error ISO fulfillment Both error 23.10.12 Servicing interrupts The interrupt service routine must consider different types of interrupts for high-frequency and low-frequency, and error operations and specify the priorities accordingly.
  • Page 615 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Table 441. Error interrupt events Interrupt Action USB error interrupt This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt (w/ ENDPTCOMPLETE).
  • Page 616 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller A device may go into the Suspended state either autonomously by disconnecting from the USB, or in response to USB suspend signaling. 23.12.1 USB power states The USB provides a mechanism to place segments of the USB or the entire USB into a low-power Suspended state.
  • Page 617 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller Host directed Autonomous operational 3 ms Low-power idle request resume interrupt received prepare disconnect Suspend SW sets SW sets user-defined Suspend bit Suspend bit wakeup disconnect Suspend Suspend Lock power states...
  • Page 618 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller 2. If the host puts resume signaling on the bus, it will clear the Suspend bit and generate a port change interrupt when the resume is finished. The Suspend interrupt is generated by the USB block whenever it detects that Remark: the bus is idle for more than 3 ms.
  • Page 619 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller external event could clear the suspend bit and start the transceiver clock running again. The software can then initiate a resume by setting the resume bit in the port controller, or force a reconnect by setting the reset bit in the port controller.
  • Page 620 UM10430 NXP Semiconductors Chapter 23: LPC18xx USB0 Host/Device/OTG controller a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed). • The vbusvalid and bvalid signals coming from the transceiver are not filtered in the SUSP_CTRL module. Any change on those signals will cause a wake-up event. Hence for USB0, it is recommended that the OTG_DISCHARGE resistor be enabled, by setting OTGSC.VD bit, before entering low power mode.
  • Page 621 UM10430 Chapter 24: LPC18xx USB1 Host/Device controller Rev. 3.0 — 26 July 2017 User manual 24.1 How to read this chapter The USB1 Host/Device controller is available on parts LPC185x and LPC183x. USB frame length adjustment is available for parts with on-chip flash only. 24.2 Basic configuration The USB1 controller is configured as follows: •...
  • Page 622 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Supports all full-speed USB-compliant peripherals. • • Complies with Universal Serial Bus specification 2.0. Complies with Enhanced Host Controller Interface Specification. • Supports auto USB 2.0 mode discovery. • Supports three logical endpoints plus one control endpoint for a total of 8 physical •...
  • Page 623 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller LPC18xx SYSTEM ARM Cortex-M3 MEMORY master slave TX-BUFFER USB1_VBUS INTERNAL (DUAL-PORT RAM) USB1_DP FULL-SPEED USB 2.0 Mobile/ USB1_DM RX-BUFFER GROUND (DUAL-PORT RAM) Fig 64. USB1 block diagram with internal full-speed PHY 24.5 Pin description...
  • Page 624 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Remark: For requirements when connecting the USB1_VBUS signal to a USB powered device-only product or an OTG product, see Section 23.5.1 24.6 Register description Remark: For Full-speed operation with on-chip Full-speed PHY, the pads of the PHY need to be configured.
  • Page 625 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 445. Register overview: USB1 host/device controller (register base address 0x4000 7000) …continued Name Access Address Description Reset value Reference offset TTCTRL 0x15C Asynchronous buffer status for 0x0000 0000 Table 465...
  • Page 626 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 447. HCSPARAMS register (HCSPARAMS - address 0x4000 7104) bit description Symbol Description Reset value Access N_PORTS Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller.
  • Page 627 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 448. HCCPARAMS register (HCCPARAMS - address 0x4000 7108) bit description Symbol Description Reset value Access 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. Programmable Frame List Flag. If set to one, then...
  • Page 628 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller 24.6.2.1 Device mode Table 451. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description Symbol Value Description Reset Access value Run/Stop Writing a 0 to this bit will cause a detach event.
  • Page 629 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 451. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value Not used in device mode. 23:16 Interrupt threshold control.
  • Page 630 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 452. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value This bit controls whether the host controller skips processing the periodic schedule.
  • Page 631 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 452. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value Bit 2 of the Frame List Size bits. See Table 453.
  • Page 632 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller 24.6.3.1 Device mode Table 454. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB interrupt R/WC This bit is cleared by software writing a one to it.
  • Page 633 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 454. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB reset received R/WC This bit is cleared by software writing a one to it.
  • Page 634 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller 24.6.3.2 Host mode Table 455. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB interrupt (USBINT) R/WC This bit is cleared by software writing a one to it.
  • Page 635 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 455. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued Symbol Value Description Reset Access value Not used by the Host controller. 11:9 Reserved.
  • Page 636 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 455. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued Symbol Value Description Reset Access value USB host periodic interrupt (USBHSTPERINT) R/WC This bit is cleared by software writing a one to it.
  • Page 637 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 456. USB Interrupt register in device mode (USBINTR_D - address 0x4000 7148) bit description …continued Symbol Description Reset Access value SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt.
  • Page 638 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 457. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description …continued Symbol Description Access Reset value Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold.
  • Page 639 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller 24.6.5.2 Host mode This register is used by the host controller to index the periodic frame list. The register updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution.
  • Page 640 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 461. USB Device Address register in device mode (DEVICEADDR - address 0x4000 7154) bit description Symbol Value Description Reset Access value 23:0 reserved USBADRA Device address advance Any write to USBADR are instantaneous.
  • Page 641 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 463. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 7158) bit description Symbol Description Reset Access value 10:0 reserved 31:11 EPBASE31_11 Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 8 Queue Heads (QH).
  • Page 642 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 466. USB burst size register in device/host mode (BURSTSIZE - address 0x4000 7160) bit description Symbol Description Reset Access value RXPBURST Programmable RX burst length 0x10 This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
  • Page 643 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 467. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 7164) bit description Symbol Description Reset Access value TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.
  • Page 644 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller operations will not be able execute. Undefined behavior will result if ULPISS = 0 and a read or write operation is performed. To execute a wakeup operation, write all 32-bits of the ULPI Viewport where ULPIPORT is constructed appropriately and the ULPIWU bit is a 1 and ULPIRUN bit is a 0.
  • Page 645 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller 24.6.12 BINTERVAL register This register defines the bInterval value which determines the length of the virtual frame (see Section 23.7.7). Remark: The BINTERVAL register is not related to the bInterval endpoint descriptor field in the USB specification.
  • Page 646 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller 24.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN) 24.6.14.1 Device mode Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx and Rx endpoint has a bit in the EPTNE and EPRNE field respectively.
  • Page 647 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 472. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value Current connect status Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register.
  • Page 648 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 472. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value 15:14 PIC1_0 Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.
  • Page 649 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 472. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value 27:26 PSPD Port speed This register field indicates the speed at which the port is operating.
  • Page 650 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 473. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value Port enable. Ports can only be enabled by the host controller as a part of the reset and enable.
  • Page 651 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 473. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, Table 474 “Port states as described by the PE and SUSP bits in the...
  • Page 652 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 473. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on).
  • Page 653 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 473. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value WKDC Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.
  • Page 654 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 474. Port states as described by the PE and SUSP bits in the PORTSC1 register PE bit SUSP bit Port state 0 or 1 disabled enabled suspend 24.6.16 USB Mode register (USBMODE) The USBMODE register sets the USB mode for the USB controller.
  • Page 655 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 475. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: Disabling stream mode substantially limits the overall USB performance that can be achieved.
  • Page 656 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 476. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: Disabling stream mode substantially limits the overall USB performance that can be achieved.
  • Page 657 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 478. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 71B0) bit description Symbol Description Reset Access value PERB Prime endpoint receive buffer for physical OUT endpoints. R/WS For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction.
  • Page 658 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 479. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description Symbol Description Reset Access value 15:4 Reserved R/WC 19:16 FETB Flush endpoint transmit buffer for physical IN endpoints.
  • Page 659 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Writing a one will clear the corresponding bit in this register. Table 481. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 71BC) bit description Symbol Description Reset Access value ERCE Endpoint receive complete event for physical OUT endpoints.
  • Page 660 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 482. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description …continued Symbol Value Description Reset Access value Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host.
  • Page 661 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 483. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Symbol Value Description Reset Access value Reserved Endpoint type...
  • Page 662 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller Table 483. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Symbol Value Description Reset Access value Tx data toggle inhibit This bit is only used for test and should always be written as zero.
  • Page 663 UM10430 NXP Semiconductors Chapter 24: LPC18xx USB1 Host/Device controller have a raw pin status register hence LOW level detection should be configured for this pin to detect when to turn the PLL off. Similarly, to detect resume signaling to leave low power state, software should configure this pin to detect a HIGH level in the event router.
  • Page 664 UM10430 Chapter 25: LPC18xx USB API Rev. 3.0 — 26 July 2017 User manual 25.1 How to read this chapter The USB ROM API is available on parts LPC185x/3x/2x. 25.2 Introduction The boot ROM contains a USB driver to simplify the USB application development. The USB driver implements the Communication Device Class (CDC), the Human Interface Device (HID), and the Mass Storage Device (MSC) device class.The USB on-chip drivers support composite device.
  • Page 665 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API – USB descriptors data structure (Table 500 “_USB_CORE_DESCS_T class structure”) – USB device stack initialization parameter data structure (Table 509 “USBD_API_INIT_PARAM class structure”). – USB device stack core API functions structure (Table 512 “USBD_CORE_API class structure”).
  • Page 666 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API const USBD_DFU_API_T* dfu; const USBD_HID_API_T* hid; const USBD_CDC_API_T* cdc; const uint32_t* reserved6; const uint32_t version; } USBD_API_T; Ptr to USB ROM Driver table Device 1 0x1040 011C Ptr to Function 0 Ptr to Function 1 Ptr to Function 2 …...
  • Page 667 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 485. _BM_T class structure Member Description Recipient uint8_t _BM_T::Recipient Recipient type. Type uint8_t _BM_T::Type Request type. uint8_t _BM_T::Dir Direction type. 25.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR Table 486. _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR class structure Member Description bFunctionLength uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bFunctionLength...
  • Page 668 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 489. _CDC_LINE_CODING class structure Member Description dwDTERate uint32_t _CDC_LINE_CODING::dwDTERate bCharFormat uint8_t _CDC_LINE_CODING::bCharFormat bParityType uint8_t _CDC_LINE_CODING::bParityType bDataBits uint8_t _CDC_LINE_CODING::bDataBits 25.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR Table 490. _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR::sUnion bSlaveInterfaces uint8_t _CDC_UNION_1SLAVE_DESCRIPTOR::bSlaveInterfaces[1][1] 25.5.8 _CDC_UNION_DESCRIPTOR...
  • Page 669 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 493. _HID_DESCRIPTOR class structure Member Description bLength uint8_t _HID_DESCRIPTOR::bLength Size of the descriptor, in bytes. bDescriptorType uint8_t _HID_DESCRIPTOR::bDescriptorType Type of HID descriptor. bcdHID uint16_t _HID_DESCRIPTOR::bcdHID BCD encoded version that the HID descriptor and device complies to.
  • Page 670 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 496. _MSC_CBW class structure Member Description dSignature uint32_t _MSC_CBW::dSignature dTag uint32_t _MSC_CBW::dTag dDataLength uint32_t _MSC_CBW::dDataLength bmFlags uint8_t _MSC_CBW::bmFlags bLUN uint8_t _MSC_CBW::bLUN bCBLength uint8_t _MSC_CBW::bCBLength uint8_t _MSC_CBW::CB[16][16] 25.5.14 _MSC_CSW Table 497. _MSC_CSW class structure...
  • Page 671 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 500. _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t * _USB_CORE_DESCS_T::device_desc Pointer to USB device descriptor string_desc uint8_t * _USB_CORE_DESCS_T::string_desc Pointer to array of USB string descriptors full_speed_desc uint8_t * _USB_CORE_DESCS_T::full_speed_desc Pointer to USB device configuration descriptor when device is operating in full speed mode.
  • Page 672 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 502. _USB_DFU_FUNC_DESCRIPTOR class structure Member Description bLength uint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength bDescriptorType uint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType bmAttributes uint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes wDetachTimeOut uint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut wTransferSize uint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize bcdDFUVersion uint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion 25.5.20 _USB_INTERFACE_DESCRIPTOR Table 503. _USB_INTERFACE_DESCRIPTOR class structure...
  • Page 673 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 504. _USB_OTHER_SPEED_CONFIGURATION class structure Member Description bLength uint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength Size of descriptor bDescriptorType uint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType Other_speed_Configuration Type wTotalLength uint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength Total length of data returned bNumInterfaces uint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces Number of interfaces supported by this speed configuration...
  • Page 674 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 506. _USB_STRING_DESCRIPTOR class structure Member Description bLength uint8_t _USB_STRING_DESCRIPTOR::bLength Size of this descriptor in bytes bDescriptorType uint8_t _USB_STRING_DESCRIPTOR::bDescriptorType STRING Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR::bString UNICODE encoded string 25.5.24 _WB_T Table 507. _WB_T class structure...
  • Page 675 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 508. USBD_API class structure Member Description const USBD_CDC_API_T* USBD_API::cdc Pointer to function table which exposes functions provided by CDC-ACM function driver module. reserved6 const uint32_t* USBD_API::reserved6 Reserved for future function driver module.
  • Page 676 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 509. USBD_API_INIT_PARAM class structure Member Description USB_Resume_Event USB_CB_T USBD_API_INIT_PARAM::USB_Resume_Event Event for USB wake up or resume. This event fires when a the USB device interface is suspended and the host wakes up the device by supplying Start Of Frame pulses. This is generally hooked to pull the user application out of a low power state and back into normal operating mode.
  • Page 677 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 509. USBD_API_INIT_PARAM class structure Member Description USB_Configure_Event USB_CB_T USBD_API_INIT_PARAM::USB_Configure_Event Event for USB configuration number changed. This event fires when a the USB host changes the selected configuration number. On receiving configuration change request from host, the stack enables/configures the endpoints needed by the new configuration before calling this callback function.
  • Page 678 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 510. USBD_CDC_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param, USBD_HANDLE_T *phCDC) Function to initialize CDC function driver module. This function is called by application layer to initialize CDC function driver module.
  • Page 679 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_CDC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller.
  • Page 680 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) Communication Interface Class specific set request call-back function. This function is provided by the application software. This function gets called when host sends a CIC management element requests.
  • Page 681 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description CDC_BulkOUT_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkOUT_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Communication Device Class specific BULK OUT endpoint handler. The application software should provide the BULK OUT endpoint handler. Applications should transfer data depending on the communication protocol type set in descriptors.
  • Page 682 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description GetEncpsResp ErrorCode_t(* USBD_CDC_INIT_PARAM::GetEncpsResp)(USBD_HANDLE_T hCDC, uint8_t **buffer, uint16_t *len) Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request call-back function. This function is provided by the application software. This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request.
  • Page 683 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description GetCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::GetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t **pBuffer, uint16_t *len) Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request.
  • Page 684 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description ClrCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature) Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a CLEAR_COMM_FEATURE request.
  • Page 685 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description SetCtrlLineState ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state) Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function. This function is provided by the application software. This function gets called when host sends a SET_CONTROL_LINE_STATE request.
  • Page 686 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding) Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. This function is provided by the application software. This function gets called when host sends a SET_LINE_CODING request.
  • Page 687 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 511. USBD_CDC_INIT_PARAM class structure Member Description CDC_Ep0_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user override-able function to replace the default CDC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
  • Page 688 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 512. USBD_CORE_API class structure Member Description RegisterEpHandler ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void *data) Function to register interrupt/event handler for the requested endpoint with USB device stack. The application layer uses this function to register the custom class's EP0 handler. The stack calls all the registered class handlers on any EP0 event before going through default handling of the event.
  • Page 689 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 512. USBD_CORE_API class structure Member Description DataOutStage void(*void USBD_CORE_API::DataOutStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in data_out state. This function is called by USB stack and the application layer to set the EP0 state machine in data_out state.
  • Page 690 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 512. USBD_CORE_API class structure Member Description StallEp0 void(*void USBD_CORE_API::StallEp0)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in stall state. This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint.
  • Page 691 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 513. USBD_DFU_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_DFU_API::GetMemSize)(USBD_DFU_INIT_PARAM_T *param) Function to determine the memory required by the DFU function driver module. This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used by DFU function driver module.
  • Page 692 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 514. USBD_DFU_INIT_PARAM class structure Member Description wTransferSize uint16_t USBD_DFU_INIT_PARAM::wTransferSize DFU transfer block size in number of bytes. This value should match the value set in DFU descriptor provided as part of the descriptor array (...
  • Page 693 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 514. USBD_DFU_INIT_PARAM class structure Member Description DFU_Detach void(* USBD_DFU_INIT_PARAM::DFU_Detach)(USBD_HANDLE_T hUsb) DFU detach callback function. This function is provided by the application software. This function gets called after USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH bit in DFU descriptor should define this function.
  • Page 694 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 515. USBD_HID_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HID_API::GetMemSize)(USBD_HID_INIT_PARAM_T *param) Function to determine the memory required by the HID function driver module. This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used by HID function driver module.
  • Page 695 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 516. USBD_HID_INIT_PARAM class structure Member Description mem_base uint32_t USBD_HID_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. Also this value should be aligned on 4 byte boundary.
  • Page 696 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 516. USBD_HID_INIT_PARAM class structure Member Description HID_SetReport ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) HID set report callback function. This function is provided by the application software. This function gets called when host sends a HID_REQUEST_SET_REPORT request.
  • Page 697 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 516. USBD_HID_INIT_PARAM class structure Member Description HID_SetIdle ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetIdle)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t idleTime) Optional callback function to handle HID_REQUEST_SET_IDLE request. The application software could provide this callback to handle HID_REQUEST_SET_IDLE requests sent by the host.
  • Page 698 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 516. USBD_HID_INIT_PARAM class structure Member Description HID_EpIn_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpIn_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt IN endpoint event handler. The application software could provide Interrupt IN endpoint event handler. Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member.
  • Page 699 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 516. USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt OUT endpoint event handler. The application software could provide Interrupt OUT endpoint event handler. Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member.
  • Page 700 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 516. USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default HID class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
  • Page 701 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HW_API::GetMemSize)(USBD_API_INIT_PARAM_T *param) Function to determine the memory required by the USB device stack's DCD and core layers. This function is called by application layer before calling pUsbApi->hw->...
  • Page 702 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description void(*void USBD_HW_API::ISR)(USBD_HANDLE_T hUsb) Function to USB device controller interrupt events. When the user application is active the interrupt handlers are mapped in the user flash space. The user application must provide an interrupt handler for the USB interrupt and call this function in the interrupt handler routine.
  • Page 703 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description WakeUpCfg void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg) Function to configure USB device controller to walk-up host on remote events. This function is called by application layer to configure the USB device controller to wake up on remote events.
  • Page 704 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description ConfigEP void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) Function to configure USB Endpoint according to descriptor. This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received by the stack from USB host. All the endpoints associated with the selected configuration are configured.
  • Page 705 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description EnableEP void(*void USBD_HW_API::EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to enable selected USB endpoint. This function enables interrupts on selected endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
  • Page 706 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description SetStallEP void(*void USBD_HW_API::SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to STALL selected USB endpoint. Generates STALL signalling for requested endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
  • Page 707 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description ReadEP uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) Function to read data received on the requested endpoint. This function is called by USB stack and the application layer to read the data received on the requested endpoint.
  • Page 708 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 517. USBD_HW_API class structure Member Description WriteEP uint32_t(*uint32_t USBD_HW_API::WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt) Function to write data to be sent on the requested endpoint. This function is called by USB stack and the application layer to send data on the requested endpoint.
  • Page 709 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 518. USBD_MSC_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_MSC_API::GetMemSize)(USBD_MSC_INIT_PARAM_T *param) Function to determine the memory required by the MSC function driver module. This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used by MSC function driver module.
  • Page 710 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 519. USBD_MSC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_MSC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller.
  • Page 711 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 519. USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t offset, uint8_t **dst, uint32_t length) MSC Read callback function. This function is provided by the application software. This function gets called when host sends a read command.
  • Page 712 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 519. USBD_MSC_INIT_PARAM class structure Member Description MSC_Verify ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Verify)(uint32_t offset, uint8_t buf[], uint32_t length) MSC Verify callback function. This function is provided by the application software. This function gets called when host sends a verify command.
  • Page 713 UM10430 NXP Semiconductors Chapter 25: LPC18xx USB API Table 519. USBD_MSC_INIT_PARAM class structure Member Description MSC_Ep0_Hdlr ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default MSC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
  • Page 714 UM10430 Chapter 26: LPC18xx Ethernet Rev. 3.0 — 26 July 2017 User manual 26.1 How to read this chapter The Ethernet controller is available on parts LPC185x and LPC183x. The MII is not available on the LQFP144 and TFBGA100 packages. 26.2 Basic configuration The Ethernet controller is configured as follows: •...
  • Page 715 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.4 General description The Ethernet block enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2005 standard. The Ethernet interface contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration.
  • Page 716 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.5 Pin description Table 521. Ethernet pin description Pin function Direction Description MIIM interface ENET_MDIO Ethernet MIIM Data Input and Output. ENET_MDC Ethernet MIIM Clock. RMII interface ENET_RXD[1:0] Ethernet Receive Data. ENET_TXD[1:0] Ethernet Transmit Data.
  • Page 717 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.6 Register description Table 522. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address Description Reset value Reference offset MAC_CONFIG 0x0000 MAC configuration register 0x0000 8000 Table 523 MAC_FRAME_FILTER...
  • Page 718 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 522. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address Description Reset value Reference offset DMA_TRANS_POLL_DEMAND 0x1004 Transmit poll demand 0x0000 0000 Table 553 register DMA_REC_POLL_DEMAND 0x1008 Receive poll demand...
  • Page 719 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 523. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will...
  • Page 720 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 523. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously.
  • Page 721 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 523. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.
  • Page 722 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 524. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description …continued Symbol Description Reset Access value Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.
  • Page 723 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet If the corresponding bit value of the register is 1, the frame is accepted. Otherwise, it is rejected. If the PM (Pass All Multicast) bit is set in the MAC_CONFIG register, then all multicast frames are accepted regardless of the multicast hash values.
  • Page 724 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 527. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description Symbol Description Reset Access value MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear).
  • Page 725 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 528. CSR clock range values Bits 5:2 CLK_M3_ETHERNET MDC clock 1010 CLK_M3_ETHERNET/16 1011 CLK_M3_ETHERNET/26 1100 CLK_M3_ETHERNET/102 1101 CLK_M3_ETHERNET/124 1110 CLK_M3_ETHERNET/42 1111 CLK_M3_ETHERNET/62 26.6.6 MAC MII Data register The MII Data register stores Write data to be written to the PHY register located at the address specified in the MAC_MII_ADDR register.
  • Page 726 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 530. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description Symbol Description Reset Access value Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear).
  • Page 727 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 530. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description …continued Symbol Description Reset Access value DZPQ Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
  • Page 728 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Remark: Reset values in this register are valid only if the clocks to the Ethernet block are present during the reset operation. Table 532. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description...
  • Page 729 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.6.10 MAC Remote wake-up frame filter register This is the address through which the remote Wake-up Frame Filter registers (WKUPFMFILTER) are written/read by the Application. WKUPFMFILTER is actually a pointer to eight (not transparent) such WKUPFMFILTER registers. Eight sequential Writes to this address (0x028) will write all WKUPFMFILTER registers.
  • Page 730 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 534. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description Symbol Description Reset Access value Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read.
  • Page 731 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 535. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description Symbol Description Reset Access value Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: •...
  • Page 732 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet If the MAC address registers are configured to be double-synchronized to the MII clock domains, then the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0] (in Big-Endian mode) of the MAC Address Low Register are written to.
  • Page 733 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 539. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Symbol Description Reset Access value TSENA Time Stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames.
  • Page 734 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 539. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Symbol Description Reset Access value TSIPENA Enable Time Stamp Snapshot for PTP over Ethernet frames When set, the time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also.
  • Page 735 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet In Coarse Update mode (TSCFUPDT bit in Table 539), the value in this register is added to the system time every clock cycle. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.
  • Page 736 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 543. System time nanoseconds register (NANOSECONDS, address 0x4001 070C) bit description Symbol Description Reset Access value 30:0 TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second.
  • Page 737 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 545. System time nanoseconds update register (NANOSECONDSUPDATE, address 0x4001 0714) bit description Symbol Description Reset Access value 30:0 TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second.
  • Page 738 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.6.24 Target time nanoseconds register This register contains the higher 32 bits of time to be compared with the system time for interrupt event generation. Table 548. Target time nanoseconds register (TARGETNANOSECONDS, address 0x4001...
  • Page 739 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 550. Time stamp status register (TIMESTAMPSTAT, address 0x4001 0728) bit description Symbol Description Reset Access value TSSOVF Time stamp seconds overflow When set, indicates that the seconds value of the time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF.
  • Page 740 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 551. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Symbol Description Reset Access value 13:8 Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction.
  • Page 741 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 551. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Symbol Description Reset Access value Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits.
  • Page 742 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.6.29 DMA Receive poll demand register The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is given to wake up the RxDMA from SUSPEND state. The RxDMA can go into SUSPEND state only due to the unavailability of descriptors owned by it.
  • Page 743 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 556. DMA Transmit descriptor list address register (DMA_TRANS_DES_ADDR, address 0x4001 1010) bit description Symbol Description Reset Access value 31:0 Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list.
  • Page 744 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 557. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state.
  • Page 745 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 557. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the...
  • Page 746 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 557. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface).
  • Page 747 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 558. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued Symbol Description Reset Access value Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).
  • Page 748 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 558. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued Symbol Description Reset Access value Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear).
  • Page 749 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 559. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued Symbol Description Reset Access value Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled.
  • Page 750 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 559. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued Symbol Description Reset Access value Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled.
  • Page 751 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.6.35 DMA Missed frame and buffer overflow counter register The DMA maintains two counters to track the number of missed frames during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes.
  • Page 752 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 561. DMA Receive interrupt watchdog timer register (DMA_REC_INT_WDT, address 0x4001 1024) bit description Symbol Description Reset Access value RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer...
  • Page 753 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 564. DMA Current host transmit buffer address register (DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit description Symbol Description Reset Access value 31:0 Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation.
  • Page 754 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.1.2 Example for a multicast MAC address MAC: 01-45-a2-6c-30-33 CRC32: 0x2CB41110 Last 2 bytes in binary: 0001 0000 Bit-wise reversal: 0000 1000 First 6 bits: 000010 ( 0=Hash Table Low / 00010 => 0x2 => bit 2 ) In the MAC_HASH_TABLE_LOW register, write a 1 to bit 2.
  • Page 755 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Filter 0 Byte Mask WKUPFMFILTER0 Filter 1 Byte Mask WKUPFMFILTER1 Filter 2 Byte Mask WKUPFMFILTER2 Filter 3 Byte Mask WKUPFMFILTER3 Filter 3 Filter 2 Filter 1 Filter 0 WKUPFMFILTER4 RSVD RSVD RSVD RSVD...
  • Page 756 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet PMT supports four programmable filters that allow support of different receive frame patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter CRC-16 matches the incoming examined pattern, then the wake-up frame is received.
  • Page 757 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.2.4 System considerations during power-down MAC neither gates nor stops clocks when Power-down mode is enabled. Power saving by clock gating must be done outside the core by the application. The receive data path must be clocked with ENET_RX_CLK during Power-down mode because it is involved in magic packet/wake-on-LAN frame detection.
  • Page 758 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 566. Priority scheme for transmit and receive DMA Bit 27 Bit 15 Bit 14 Bit 1 Priority scheme Rx has priority over Tx in the ratio 4:1. Tx always has priority over Rx.
  • Page 759 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Fig 69. Networked time synchronization As shown in Figure 69, the PTP uses the following process: 1. The master broadcasts the PTP Sync messages to all its nodes. The Sync message contains the master.s reference time information. The time at which this message leaves the master.s system is t1.
  • Page 760 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Most of the PTP implementation is done in the software above the UDP layer. However, the hardware support is required to capture the exact time when specific PTP packets enter or leave the Ethernet port at the MII. This timing information must be captured and returned to the software for the proper implementation of PTP with high accuracy.
  • Page 761 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet addend_val[31:0] addend_updt Addend register Accumulator register Constant value incr_sub_sec_reg Sub-second register incr_sec_reg Second register Fig 70. System update using fine method The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns accuracy.
  • Page 762 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This value is as follows: FreqCompensationValue0 = 232 / FreqDivisionRatio If MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages, the algorithm described below must be applied.
  • Page 763 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.4.4 Receive path functions The MAC captures the timestamp of all frames received on the MII. The MAC does not process the received frames to identify the PTP frames in the default mode, that is, when the Advanced Timestamp feature is not selected.
  • Page 764 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet The minimum PTP clock frequency depends on the time required between two consecutive SFD bytes. Because the MII clock frequency is fixed by IEEE specification, the minimum PTP clock frequency required for proper operation depends upon the operating mode and operating speed of the MAC as shown in Table 4-1.
  • Page 765 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet P2P TC A P2P TC B Delay Delay Requester Responder Time Time Timestamps known by Delay Requester Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up: Fig 71. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction As shown in...
  • Page 766 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.5.2 Clock types The Ethernet controller supports the following clock types defined in the IEEE 1588-2008 standard: Ordinary clock • Boundary clock • End-to-end transparent clock • Peer-to-peer transparent clock • 26.7.5.2.1 Ordinary clock The ordinary clock in a domain supports a single copy of the protocol.
  • Page 767 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet The residence time of a SYNC packet inside the end-to-end transparent clock is updated in the correction field of the associated Follow_Up PTP packet before it is transmitted. Similarly, the residence time of a Delay_Req packet inside the end-to-end transparent clock is updated in the correction field of the associated Delay_Resp PTP packet before it is transmitted.
  • Page 768 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 571. Message format defined in IEEE 1588-2008 Bits OCTETS OFFSET sequenceId controlField ( logMessageInterva Field is used in version 1. In version 2, messageType field is used for detecting different message types.
  • Page 769 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 572. IPv4-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Position Matched Value Description PTP Control Field 0x00/0x01/0x02/ 0x00 – SYNC, (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 – Follow_Up 0x03 –...
  • Page 770 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 573. IPv6-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Position Matched Value Description PTP Control Field 93 ( 0x00/0x01/0x02/ 0x00 – SYNC (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 –...
  • Page 771 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet The address match of destination addresses (DA) programmed in MAC address 1 to 31 is used if the control bit 18 (TSENMACADDR: Enable MAC address for PTP frame filtering) of the Timestamp Control register is set.
  • Page 772 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet (Section 26.6.16): When you select the advanced timestamp feature, the MAC processes the received • frames to identify valid PTP frames. You can control the snapshot of the time, to be sent to the application, by using the following options of the Timestamp Control Register.
  • Page 773 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Descriptor lists and data buffers. See Section 26.7.6.3. • The DMA transfers data frames received by the core to the Receive Buffer in the Host memory, and Transmit data frames from the Transmit Buffer in the Host memory.
  • Page 774 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.6.1 Initialization Follow these steps to initialize the ethernet controller: 1. Write to DMA Register Table 551 to set Host bus access parameters. 2. Write to DMA Register Table 559 to mask unnecessary interrupt causes.
  • Page 775 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet When the AHB interface is configured for address-aligned beats, both DMA engines ensure that the first burst transfer the AHB initiates is less than or equal to the size of the configured PBL. Thus, all subsequent beats start at an address that is aligned to the configured PBL.
  • Page 776 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet starting from address 0x1000, the software can program the buffer start address in the Receive descriptor to have a 0x1002 offset. The Receive DMA writes the frame to this buffer with dummy data in the first two locations (0x1000 and 0x1001). The actual frame is written from location 0x1002.
  • Page 777 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 8. Transmit Interrupt (DMA Register Table 557) is set after completing transmission of a frame that has Interrupt on Completion (TDES1[31]) set in its Last Descriptor. The DMA engine then returns to Step 3.
  • Page 778 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll demand error? TxDMA suspended bit set? Transfer data from buffer(s) (AHB) error? Frame xfer complete? Close intermediate Wait for Tx status descriptor Write time stamp to...
  • Page 779 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet immediately polls the Transmit Descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. In OSF mode, the Run state Transmit DMA operates in the following sequence: 1.
  • Page 780 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll error? demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) (AHB) Time stamp error? present? Frame xfer Second Write time stamp to...
  • Page 781 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.6.2.3 Transmit frame processing The Transmit DMA expects that the data buffers contain complete Ethernet frames, excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or PAD insertion, the buffer must have complete Ethernet frames (excluding preamble), including the CRC bytes.
  • Page 782 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet The driver must explicitly issue a Transmit Poll Demand command after rectifying the suspension cause. 26.7.6.2.5 Reception The Receive DMA engine’s reception sequence is shown in Figure 75 and proceeds as follows: 1. The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit (RDES0[31]).
  • Page 783 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Start RxDMA Start Stop RxDMA (Re-)Fetch next Poll demand / descriptor new frame available (AHB) RxDMA suspended error? Frame transfer Own bit set? complete? Frame data Flush disabled ? available ? Flush the...
  • Page 784 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet If software has enabled time stamping through CSR, when a valid time stamp value is not available for the frame (for example, because the receive FIFO was full before the time stamp could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise (that is, if time stamping is not enabled), the RDES2 and RDES3 remain unchanged.
  • Page 785 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet descriptor is still owned by the host, by default, the DMA discards the current frame at the top of the MTL Rx FIFO and increments the missed frame counter. If more than one frame is stored in the MTL Rx FIFO, the process repeats.
  • Page 786 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet 26.7.6.2.10 Error response to DMA For any data transfer initiated by a DMA channel, if the slave replies with an error response, that DMA stops all operations and updates the error bits and the Fatal Bus...
  • Page 787 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Ctrl Ctrl Status [16:0] TDES0 [30:26] [23:20] Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES1 Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES3...
  • Page 788 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet SLOT Ctrl Ctrl Reserved for Reserved for Number TDES0 [30:26] [23:20] Status [17:7] Status [3:0] [6:3] Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES1 Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES3 Fig 77.
  • Page 789 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 575. Transmit descriptor word 0 (TDES0) Symbol Description Excessive Collision When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the DR (Disable Retry) bit in the MAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted.
  • Page 790 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 575. Transmit descriptor word 0 (TDES0) Symbol Description Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care”...
  • Page 791 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 577. Transmit descriptor word 2 (TDES2) Symbol Description 31:0 B1ADD Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment. See Section 26.7.6.1.2...
  • Page 792 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Status [30:0] RDES0 Buffer 2 Byte Count CTRL Buffer 1 Byte Count CTRL RDES1 [30:29] [28:16] [15:14] [12:0] Buffer 1 Address [31:0] RDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] RDES3...
  • Page 793 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 581. Receive descriptor fields 0 (RDES0) Symbol Description Extended Status Available/Rx MAC Address When Advanced Timestamp is present, this bit, when set, indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when the Last Descriptor bit (RDES0[8]) is set.
  • Page 794 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 581. Receive descriptor fields 0 (RDES0) Symbol Description Length Error When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset.
  • Page 795 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 582. Receive descriptor fields 1 (RDES1) Symbol Description 12:0 RBS1 Receive Buffer 1 Size Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16, depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address pointer) is not aligned.
  • Page 796 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet The extended status written is as shown in Table 585. The extended status is written only when there is status related to IPC or timestamp available. The availability of extended status is indicated by bit-0 of RDES0. This status is available only when Advance Timestamp or IPC Full Offload feature is selected.
  • Page 797 UM10430 NXP Semiconductors Chapter 26: LPC18xx Ethernet Table 587. Receive descriptor fields 7 (RDES7) Symbol Description 31:0 RTSH Receive Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]).
  • Page 798 UM10430 Chapter 27: LPC18xx LCD Rev. 3.0 — 26 July 2017 User manual 27.1 How to read this chapter The LCD controller is available on parts LPC185x only. 27.2 Basic configuration The LCD controller is configured as follows: • Table 588 for clocking and power control.
  • Page 799 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD LCD panel clock may be generated from the peripheral clock, or from a clock input • pin. 27.4 General description The LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single or dual panel monochrome and color LCDs.
  • Page 800 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD LCD control Timing signals slave controller interface LCD panel Panel clock clock Upper generator panel LCDCLKIN FIFO Upper Upper Input Upper Pixel panel master FIFO palette panel serializer output interface control (128x32) formatter...
  • Page 801 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Display type: STN monochrome, STN color, or TFT • • STN 4 or 8-bit interface mode STN dual or single panel mode • Little-endian, big-endian, or Windows CE mode • Interrupt generation event •...
  • Page 802 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 16 bpp, direct 5:5:5 RGB, with 1 bpp not normally used. This pixel is still output, and • can be used as a brightness bit to connect to the Least Significant Bit (LSB) of RGB components of a 6:6:6 TFT panel.
  • Page 803 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 589. LCD controller pins Pin function Type Function LCDLP Output Line synchronization pulse (STN). Horizontal synchronization pulse (TFT) LCDVD[23:0] Output LCD panel data. Bits used depend on the panel configuration. GP_CLKIN Input General purpose CGU input clock.
  • Page 804 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 591. Pins used for dual panel STN displays Pin name 4-bit Monochrome 8-bit Monochrome Color (14 pins) (22 pins) (22 pins) LCDVD[11:8] LD[3:0] LD[3:0] LD[3:0] LCDVD[15:12] LD[7:4] LD[7:4] LCDVD[23:16] 27.5.1.3 Signals used for TFT displays...
  • Page 805 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 593. Register overview: LCD controller (base address: 0x4000 8000) …continued Name Access Address offset Description Reset Reference value 0x00C Line End Control register Table 597 UPBASE 0x010 Upper Panel Frame Base Address register...
  • Page 806 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 594. Horizontal Timing register (TIMH, address 0x4000 8000) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 807 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD PCD = 5 (LCDCLK / 7) • If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10, data does not corrupt for PCD = 4, the minimum value.
  • Page 808 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 596. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description Symbol Description Reset value PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this...
  • Page 809 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 596. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description Symbol Description Reset value Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines.
  • Page 810 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 597. Line End Control register (LE, address 0x4000 800C) bit description Symbol Description Reset value Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1.
  • Page 811 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 599. Lower Panel Frame Base register (LPBASE, address 0x4000 8014) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 812 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 600. LCD Control register (CTRL, address 0x4000 8018) bit description …continued Symbol Description Reset value LCDDUAL Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel.
  • Page 813 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 27.6.8 Interrupt Mask register The INTMSK register controls whether various LCD interrupts occur.Setting bits in this register enables the corresponding raw interrupt INTRAW status bit values to be passed to the INTSTAT register for processing as interrupts.
  • Page 814 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 602. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description Symbol Description Reset value VCOMPRIS Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register.
  • Page 815 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 604. Interrupt Clear register (INTCLR, address 0x4000 8028) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 816 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Each word location contains two palette entries. This means that 128 word locations are used for the palette. When configured for little-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. When configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry.
  • Page 817 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 608. Cursor Image registers (CRSR_IMG, address 0x4000 8800 (CRSR_IMG0) to 0x4000 8BFC (CRSR_IMG255)) bit description Symbol Description Reset value 31:0 CRSR_IMG Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors.
  • Page 818 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 610. Cursor Configuration register (CRSR_CFG, address 0x4000 8C04) bit description Symbol Description Reset value CRSRSIZE Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor.
  • Page 819 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 612. Cursor Palette register 1 (CRSR_PAL1, address 0x4000 8C0C) bit description Symbol Description Reset value Red color component 15:8 GREEN Green color component 23:16 BLUE Blue color component. 31:24 Reserved, user software should not write ones to reserved bits.
  • Page 820 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 614. Cursor Clip Position register (CRSR_CLIP, address 0x4000 8C14) bit description Symbol Description Reset value CRSRCLIPX Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor.
  • Page 821 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 27.6.24 Cursor Raw Interrupt Status register The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt controller.
  • Page 822 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 27.7.1.2 AMBA AHB master interface The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configured to obtain data from any on-chip SRAM on AHB, various types of off-chip static memory, or off-chip SDRAM.
  • Page 823 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 619 through Table 621 show the structure of the data in each DMA FIFO word corresponding to the endianness and bpp combinations. For each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word.
  • Page 824 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 620. FIFO bits for Big-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp UM10430 All information provided in this document is subject to legal disclaimers.
  • Page 825 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 621. FIFO bits for Little-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp Table 622 shows the structure of the data in each DMA FIFO word in RGB mode.
  • Page 826 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 622. RGB mode data formats FIFO data 24-bit RGB 16-bit (1:5:5:5 RGB) 16-bit (5:6:5 RGB) 16-bit (4:4:4 RGB) p1 intensity bit p1, Blue 4 p1, Blue 4 p1, Blue 3 p1, Blue 3...
  • Page 827 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Pixel data values can be written and verified through the AHB slave interface. For information on the supported colors, refer to the section on the related panel type earlier in this chapter. The palette RAM is a dual port RAM with independent controls and addresses for each port.
  • Page 828 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 624. Palette data storage for STN color modes. Bit(s) Name Description Name Description (RGB format) (RGB format) (BGR format) (BGR format) G[0] Unused G[0] Unused R[4:1] Red palette data B[4:1] Blue palette data...
  • Page 829 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD When the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. When the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image.
  • Page 830 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD With FrameSync inactive, the cursor responds immediately to any change in the programmed CRSR_XY value. Some transient smearing effects may be visible if the cursor is moved across the LCD scan line. With FrameSync active, the cursor only updates its position after a vertical synchronization has occurred.
  • Page 831 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 27.7.5.6 Cursor image format The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode.
  • Page 832 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 628 shows the buffer to pixel mapping for Cursor 0. Table 628. Buffer to pixel mapping for 32 x 32 pixel cursor format Offset into cursor memory Data bits (8 * y)
  • Page 833 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 629. Buffer to pixel mapping for 64 x 64 pixel cursor format Offset into cursor memory Data bits (16 * y) (16 * y) +4 (16 * y) + 8 (16 * y) + 12...
  • Page 834 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 631. Color display driven with 2 2/3 pixel data Byte CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] CLD[0] P2[Green] P2[Red] P1[Blue] P1[Green] P1[Red] P0[Blue] P0[Green] P0[Red] P5[Red] P4q[Blue] P4[Green] P4[Red] P3[Blue] P3[Green]...
  • Page 835 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Next base address update interrupt. • • FIFO underflow interrupt. Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the INT_MSK register. These interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked.
  • Page 836 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 1. When power is applied, the following signals are held LOW: LCDLP • LCDDCLK • • LCDFP LCDENAB/ LCDM • • LCDVD[23:0] LCDLE • 2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This...
  • Page 837 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD LCD on sequence LCD off sequence Minimum 0 ms Minimum 0 ms LCD Power Minimum 0 ms Minimum 0 ms LCDLP, LCDCP, LCDFP, LCDAC, LCDLE Contrast Voltage LCDPWR, LCD[23:0] Display specific delay Display specific delay Fig 83.
  • Page 838 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD 27.8 LCD timing diagrams one horizontal line pixel clock (internal) LCD_TIMH (HSW) LCDLP (line synch pulse) suppressed during LCDLP LCDDCLK (panel clock) 16  LCD_TIMH(PPL)  1 LCD_TIMH (HFP) LCD_TIMH (HBP) horizontal back porch...
  • Page 839 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD one frame LCDDCLK panel data clock active (panel clock) LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch all horizontal lines for one frame front porch (defined in line clocks)
  • Page 840 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD one frame LCDDCLK panel data clock active (panel clock) LCDENA data enable (data enable) LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch all horizontal lines for one frame...
  • Page 841 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 632. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC18xx pin LCD function LPC18xx pin LCD function...
  • Page 842 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 633. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC18xx pin LCD function LPC18xx pin LCD function...
  • Page 843 UM10430 NXP Semiconductors Chapter 27: LPC18xx LCD Table 634. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC18xx LPC18xx LPC18xx pin LPC18xx pin used...
  • Page 844 UM10430 Chapter 28: LPC18xx State Configurable Timer (SCT) Rev. 3.0 — 26 July 2017 User manual 28.1 How to read this chapter The SCT without the dither engine is available on all flashless LPC18xx parts (LPC1850/30/20/10). 28.2 Basic configuration The SCT is configured as follows: •...
  • Page 845 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) – 16 events – 32 states 28.4 General description The State Configurable Timer (SCT) allows a wide variety of timing, counting, output modulation, and input capture operations. The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter.
  • Page 846 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) SCT clock CLK_M3_SCT prescaler H counter Unified counter prescaler L counter Fig 89. SCT counter and select logic 28.5 Pin description The SCT inputs can originate from the external pins or from several internal sources.
  • Page 847 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 636. SCT inputs and outputs …continued Description Pin function Internal signal Default (see CTOUTCTRL GIMA, bit (see Table 190) Table SCT input 5 CTIN_5 USART2 TX active SCT input 6...
  • Page 848 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 636. SCT inputs and outputs …continued Description Pin function Internal signal Default (see CTOUTCTRL GIMA, bit (see Table 190) Table SCT output 12 CTOUT_12 SCT output 13 ORed with Timer3 match output 3...
  • Page 849 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 637. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset LIMIT_H 0x00A SCT limit register high counter 16-bit 0x0000 0000...
  • Page 850 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 637. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset MATCH0_H to 0x102 to SCT match value register of match channels 0 to...
  • Page 851 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 637. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset CAPCTRL0_L to 0x280 to CAPCTRL alias registers (see Section 28.7.9).
  • Page 852 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 637. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset OUTPUTCL1 0x50C SCT output 1 clear register 0x0000 0000 Table 664...
  • Page 853 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 638. SCT configuration register (CONFIG - address 0x4000 0000) bit description …continued Symbol Value Description Reset value CLKMODE SCT clock mode The bus clock clocks the SCT and prescalers.
  • Page 854 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.6.2 SCT control register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CTRL_L and CTRL_H.
  • Page 855 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 639. SCT control register (CTRL - address 0x4000 0004) bit description Symbol Value Description Reset value BIDIR_H Direction select The H counter counts up to its limit condition, then is cleared to zero.
  • Page 856 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 641. SCT halt condition register (HALT - address 0x4000 000C) bit description Symbol Description Reset value 15:0 HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
  • Page 857 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Attempting to write a counter while it is running does not affect the counter but produces a bus error. Software can read the counter registers at any time. Table 644. SCT counter register (COUNT - address 0x4000 0040) bit description...
  • Page 858 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 645. SCT state register (STATE - address 0x4000 0044) bit description Symbol Description Reset value STATE_L State variable. 15:5 Reserved. 20:16 STATE_H State variable. 31:21 Reserved. 28.6.9 SCT input register Software can read the state of the SCT inputs in this read-only register in two slightly different forms.
  • Page 859 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) The SCT contains 16 Match/Capture register pairs. The Register Mode register selects whether each register pair acts as a Match register (see Section 28.6.19) or as a Capture register (see Section 28.6.20).
  • Page 860 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 649. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Value Description Reset value SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
  • Page 861 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 649. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Value Description Reset value SETCLR10 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
  • Page 862 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 650. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O1RES Effect of simultaneous set and clear on output 1. No change.
  • Page 863 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 650. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O9RES Effect of simultaneous set and clear on output 9. No change.
  • Page 864 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 651. SCT DMA 0 request register (DMAREQ0 - address 0x4000 005C) bit description Symbol Description Reset value 15:0 DEV_0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).
  • Page 865 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.6.17 SCT conflict enable register This register enables the “no change conflict” events specified in the SCT conflict resolution register to request an IRQ. Table 655. SCT conflict enable register (CONEN - address 0x4000 00F8) bit description...
  • Page 866 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) There is no “write-through” from Reload registers to Match registers. Before starting a counter, software can write one value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle.
  • Page 867 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1) If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CAPCTRLn_L and CAPCTRLn_H.
  • Page 868 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) When the UNIFY bit is 0, each event is associated with a particular counter by the HEVENT bit in its event control register. An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register.
  • Page 869 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 662. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Symbol Value Description Reset value STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
  • Page 870 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.7 Functional description 28.7.1 Match logic Counter H Match Match Reload Match i H Reg i H UNIFY Match Match Reload Match i L Reg i L Counter L Fig 90. Match logic 28.7.2 Capture logic...
  • Page 871 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) H matches select L matches MATCHSELi inputs event i select outputs IOSELi OUTSELi IOCONDi COMBMODEi select STATEMASKi H STATE L STATE HEVENTi Fig 92. Event selection 28.7.4 Output generation Figure 93 shows one output slice of the SCT.
  • Page 872 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.7.6 Clearing the prescaler When enabled by a non-zero PRE field in the Control register, the prescaler acts as a clock divider for the counter, like a fractional part of the counter value. The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons: •...
  • Page 873 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) DMA access to more than one Reload or Capture register requires that they be consecutive registers. (Nothing else in the SCT constrains how these registers are assigned and used.) Remark: The SCT can also be used to launch timed or other event-determined transfers among other peripherals or between other peripherals and memory.
  • Page 874 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) Table 666. Alternate address map for DMA halfword access Match register Capture register Standard offset DMA halfword offset MATCHREL1_L CAPCTRL1_L 0x204 0x282 MATCHREL1_H CAPCTRL1_H 0x206 0x2C2 UM10430 All information provided in this document is subject to legal disclaimers.
  • Page 875 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.7.10 SCT operation In its simplest, single-state configuration, the SCT operates as an event controlled one- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior.
  • Page 876 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.7.10.1.3 Configure events and event responses 1. Define when each event can occur in the following way in the EVCTRL registers (up to 16, one register per event): – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE.
  • Page 877 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) 28.7.10.1.4 Configure multiple states 1. In the EVSTATEMASK register for each event (up to 16 events, one register per event), select the state or states (up to 31) in which this event is allowed to occur.
  • Page 878 UM10430 NXP Semiconductors Chapter 28: LPC18xx State Configurable Timer (SCT) – When the counter are halted, only a software write to clear the HALT bit can start the counter again. No events can occur. – When the counters are halted, software can set any SCT output HIGH or LOW directly by writing to the OUT register.
  • Page 879 UM10430 Chapter 29: LPC18xx State Configurable Timer (SCT) with dither engine Rev. 3.0 — 26 July 2017 User manual 29.1 How to read this chapter The SCT with dither engine is available on all flash-based LPC18xx parts. The SCT implemented here is identical to the SCT implemented for flashless parts except for the following additions: Dither engine and fractional match registers •...
  • Page 880 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither – Match register 0 to 5 support a fractional component for the dither engine 29.3 Register description The register addresses of the State Configurable Timer are shown in Table 667.
  • Page 881 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 667. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset DITHER_L 0x018 SCT dither condition register low counter 16-bit...
  • Page 882 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 667. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset FRACMAT0 to 5 0x140 to Fractional match registers 0 to 5 for SCT match...
  • Page 883 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 667. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset CAPCTRL0_L to 0x280 to CAPCTRL alias registers. SCT capture control...
  • Page 884 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 667. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset EVSTATEMSK15 0x378 SCT event state register 15 0x0000 0000...
  • Page 885 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 668. SCT configuration register (CONFIG - address 0x4000 0000) bit description Symbol Value Description Reset value UNIFY SCT operation The SCT operates as two 16-bit counters named L and H.
  • Page 886 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 668. SCT configuration register (CONFIG - address 0x4000 0000) bit description …continued Symbol Value Description Reset value AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event.
  • Page 887 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 669. SCT control register (CTRL - address 0x4000 0004) bit description Symbol Value Description Reset value 12:5 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock.
  • Page 888 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 670. SCT limit register (LIMIT - address 0x4000 0008) bit description Symbol Description Reset value 15:0 LIMMSK_L If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
  • Page 889 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither The bits in this register select which events, if any, clear the STOP bit in the Control register. (Since no events can occur when HALT is 1, only software can clear the HALT bit by writing the Control register.)
  • Page 890 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 674. SCT dither condition register (DITHER - address 0x4000 0018) bit description Symbol Description Reset value 15:0 DITHMSK_L If bit n is one, the event n causes the dither engine to advance...
  • Page 891 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither set and clear outputs • • limit, stop, and start the counter cause interrupts and DMA requests • modify the state variable • The value of a state variable is completely under the control of the application. If an application does not use states, the value of the state variable remains zero, which is the default value.
  • Page 892 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 677. SCT input register (INPUT - address 0x4000 0048) bit description Symbol Description Reset value SIN3 Input 3 state synchronized to the SCT clock. SIN4 Input 4 state synchronized to the SCT clock.
  • Page 893 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Software can read this register at any time to sense the state of the outputs. Table 679. SCT output register (OUTPUT - address 0x4000 0050) bit description Symbol...
  • Page 894 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 680. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Value Description Reset value SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
  • Page 895 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither 29.3.14 SCT conflict resolution register The registers OUTPUTSETn (Section 29.3.28) and OUTPUTCLn (Section 29.3.29) allow both setting and clearing to be indicated for an output in the same clock cycle, even for the same event.
  • Page 896 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 681. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O6RES Effect of simultaneous set and clear on output 6.
  • Page 897 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 681. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O14RES Effect of simultaneous set and clear on output 14.
  • Page 898 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 684. SCT flag enable register (EVEN - address 0x4000 00F0) bit description Symbol Description Reset value 15:0 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event...
  • Page 899 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 687. SCT conflict flag register (CONFLAG - address 0x4000 00FC) bit description Symbol Description Reset value 29:16 Reserved. BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted.
  • Page 900 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Fractional Match registers can be read at any time. Writing to a Fractional Match register while the associated counter is running will not affect the register and will result in a bus error.
  • Page 901 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither 29.3.23 SCT match reload registers 0 to 15 (REGMODEn bit = 0) A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the counter reaches 0.
  • Page 902 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 693. SCT capture control registers 0 to 15 (CAPCTRL[0:15] - address 0x4000 0200 (CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1) Symbol Description Reset...
  • Page 903 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 695. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Symbol Value Description Reset value MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
  • Page 904 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 695. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Symbol Value Description Reset value 22:21 DIRECTION Direction qualifier for event generation.
  • Page 905 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Dithering can be disabled on any of the match registers by loading all zeroes (the default value) into its FRACMAT register. 29.4.1.1 Dithering At the start of each new SCT counter cycle (i.e. when the counter counts-down to zero in bi-directional mode or is cleared to zero by a limit event), the dither engine determines which matches are to be delayed by one clock during the coming counter cycle.
  • Page 906 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither 29.4.2 Alternate addressing for match/capture registers The Match, Reload, Fractional match, Fractional match reload, Capture, and Capture Control registers are arranged as consecutive words, with the standard division of each word into two halfwords.
  • Page 907 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither same output but triggered by different match values. If input 0 is found HIGH by the next time the timer is reset, the associated event (EV5) causes the state to change back to state 0where the events EV0 and EV1 are enabled.
  • Page 908 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 700. SCT configuration example Configuration Registers Setting Define match values MATCH0/1/2/3/4 Set a match value MATCH0/1/2/3/4_L in each register. The match 0 register serves as an automatic limit event that resets the counter.
  • Page 909 UM10430 NXP Semiconductors Chapter 29: LPC18xx State Configurable Timer (SCT) with dither Table 700. SCT configuration example Configuration Registers Setting Configure states in which EVSTATEMSK3 Set STATEMSK3 bit 1 to 1. Set all other bits to 0. Event 3 is enabled event 3 is enabled in state 1.
  • Page 910 UM10430 Chapter 30: LPC18xx Timer0/1/2/3 Rev. 3.0 — 26 July 2017 User manual 30.1 How to read this chapter The timers are available on all LPC18xx parts. 30.2 Basic configuration The Timers are configured as follows: • Table 701 for clocking and power control. The Timer0/1/2/3 are reset by the TIMER0/1/2/3_RST (reset #32/33/34/35).
  • Page 911 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. Up to four external outputs corresponding to match registers, with the following •...
  • Page 912 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0] INTERRUPT CAP[3:0] STOP ON MATCH RESET ON MATCH LOAD[3:0] CAPTURE CONTROL REGISTER...
  • Page 913 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 30.5 Pin description Input signals to each timer capture channel can originate from the external pins or from several other internal sources. The GIMA (see Table 190) and (for capture channel 3 of each timer) the CTOUTCTRL bit of CREG6 determine which signal is captured by the timer.
  • Page 914 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 704. Timer1 inputs and outputs Input/output From/to From/to internal signal Default (see CTOUTCTRL multiplexed pin GIMA, bit (see function Table 190) Table Timer1 inputs CAP0 CTIN_0 T1_CAP0 CAP1 CTIN_3 T1_CAP1 USART0 TX active...
  • Page 915 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 705. Timer2 inputs and outputs …continued Input/output From/to From/to internal signal Default (see CTOUTCTRL multiplexed pin GIMA, bit (see function Table 190) Table CAP3 T2_CAP2 USART2 RX active I2S1_TX_MWS SCT output 7 OR T1 match...
  • Page 916 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 706. Timer3 inputs and outputs …continued Input/output From/to From/to internal signal Default (see CTOUTCTRL multiplexed pin GIMA, bit (see function Table 190) Table CAP3 T3_CAP3 SCT output 11 OR T2 match channel 3...
  • Page 917 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 707. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) Name Access Address Description Reset Reference offset value 0x010 Prescale Counter. The 32 bit PC is a counter which is Table 712 incremented to the value stored in PR.
  • Page 918 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 708. Timer interrupt registers (IR - addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) bit description Symbol Description Reset value MR3INT Interrupt flag for match channel 3.
  • Page 919 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 711. Timer prescale registers (PR - addresses 0x4008 400C (TIMER0), 0x4008 500C (TIMER1), 0x400C 300C (TIMER2), 0x400C 400C (TIMER3)) bit description Symbol Description Reset value 31:0 Prescale counter maximum value. 30.6.5 Timer prescale counter registers The 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter.
  • Page 920 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 713. Timer match control registers (MCR - addresses 0x4008 4014 (TIMER0), 0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit description …continued Symbol Value Description Reset value MR1R Reset on MR1 TC will be reset if MR1 matches it.
  • Page 921 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 714. Timer match registers (MR[0:3], addresses 0x4008 4018 (MR0) to 0x4008 4024 (M3) (TIMER0), 0x4008 5018 (MR0) to 0x4008 5024 (MR3)(TIMER1), 0x400C 3018 (MR0) to 0x400C 8024 (MR3) (TIMER2), 0x400C 4018 (MR0) to 0x400C 4024...
  • Page 922 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 715. Timer capture control registers (CCR - addresses 0x4008 4028 (TIMER0), 0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit description …continued Symbol Value Description Reset value CAP2RE Capture on CAPn.2 rising edge A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded...
  • Page 923 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 30.6.10 Timer external match registers The External Match Register provides both control and status of the external match pins. In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a Match number, 0 through 3.
  • Page 924 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Table 717. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0), 0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit description Symbol Value Description Reset value EMC2 External Match Control 2. Determines the functionality of External Match 2.
  • Page 925 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one quarter of the PCLK clock.
  • Page 926 UM10430 NXP Semiconductors Chapter 30: LPC18xx Timer0/1/2/3 Figure 98 shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and the match register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt indicating that a match occurred is generated.
  • Page 927 UM10430 Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Rev. 3.0 — 26 July 2017 User manual 31.1 How to read this chapter The Motor control PWM is not available on LPC1810FET100, LPC1820FET100, and LPC1830FET100 parts. 31.2 Basic configuration The PWM is configured as follows: •...
  • Page 928 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can control something off-chip, like one set of coils in a motor. Each channel includes a Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by an input pin (counter mode).
  • Page 929 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) 31.5.1 Block Diagram PCLK MCI0-2 Clock Event Clock Event Clock Event selection selection selection selection selection selection MCCNTCON MCCAPCON cntl cntl cntl MAT0 MAT1 MAT2 ACMODE ACMODE (write) (write) (write)
  • Page 930 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 721. MOTOCON PWM pin description Pin function Type Description MCOA0/1/2 Output A for channels 0, 1, 2 MCOB0/1/2 Output B for channels 0, 1, 2 MCABORT Low-active Fast Abort...
  • Page 931 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 722. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000) Name Access Address Description Reset value Reference offset CNTCON_SET 0x060 Count Control set address Table 740...
  • Page 932 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 723. MCPWM Control read address (CON - 0x400A 0000) bit description Symbol Value Description Reset value POLA1 Selects polarity of the MCOA1 and MCOB1 pins. Passive state is LOW, active state is HIGH.
  • Page 933 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 723. MCPWM Control read address (CON - 0x400A 0000) bit description Symbol Value Description Reset value DCMODE 3-phase DC mode select (see Section 31.8.6). 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e.
  • Page 934 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 725. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description Symbol Description Reset value DISUP0_CLR Writing a one clears the corresponding bit in the CON register. - Writing a one clears the corresponding bit in the CON register. - RUN1_CLR Writing a one clears the corresponding bit in the CON register.
  • Page 935 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 726. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description Symbol Description Reset value CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
  • Page 936 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 727. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit description Symbol Description Reset value CAP2MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. CAP2MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register.
  • Page 937 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 728. MCPWM Capture control clear register (CAPCON_CLR - address 0x400A 0014) bit description Symbol Description Reset value CAP1MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register.
  • Page 938 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, the match between TC and LIM switches the channel’s A output from “active” to “passive” state. If the channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches...
  • Page 939 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A output switches from “passive”...
  • Page 940 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) 31.7.7 MCPWM Communication Pattern register This register is used in DC mode only. The internal MCOA0 signal is routed to any or all of the six output pins under the control of the bits in this register. Like the Match and Limit registers, this register has “write”...
  • Page 941 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 735. Motor Control PWM interrupts Symbol Description ILIM0/1/2 Limit interrupts for channels 0, 1, 2. IMAT0/1/2 Match interrupts for channels 0, 1, 2. ICAP0/1/2 Capture interrupts for channels 0, 1, 2.
  • Page 942 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 736. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description Symbol Value Description Reset value ICAP2 Capture interrupt for channel 2. Interrupt disabled. Interrupt enabled. 14:11 Reserved.
  • Page 943 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 738. PWM interrupt enable clear register (INTEN_CLR - address 0x400A 0058) bit description Symbol Description Reset value ILIM0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
  • Page 944 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 739. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description Symbol Value Description Reset value TC0MCI0_FE Counter 0 falling edge mode, channel 0. A falling edge on MCI0 does not affect counter 0.
  • Page 945 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 739. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description Symbol Value Description Reset value TC2MCI1_RE Counter 2 rising edge mode, channel 1. A rising edge on MCI1 does not affect counter 2.
  • Page 946 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 740. MCPWM Count Control set address (CNTCON_SET - 0x400A 0060) bit description Symbol Description Reset value TC1MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. TC1MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register.
  • Page 947 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 741. MCPWM Count Control clear address (CNTCON_CLR - 0x400A 0064) bit description Symbol Description Reset value TC0MCI2_RE Writing a one clears the corresponding bit in the CNTCON register. TC0MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register.
  • Page 948 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 742. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description Symbol Value Description Reset value ILIM0_F Limit interrupt flag for channel 0. This interrupt source is not contributing to the MCPWM interrupt request.
  • Page 949 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) Table 742. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description Symbol Value Description Reset value ICAP2_F Capture interrupt flag for channel 2. This interrupt source is not contributing to the MCPWM interrupt request.
  • Page 950 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) 31.7.11.3 MCPWM Interrupt Flags clear address Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus clearing the corresponding interrupt request(s). This is typically done in interrupt service routines.
  • Page 951 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) 31.8 Functional description 31.8.1 Pulse-width modulation Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors to switch a controlled point between two power rails. Most of the time the two outputs have opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to delay both signals’...
  • Page 952 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) active active passive passive MCOB passive active passive active MCOA POLA = 0 Fig 101. Center-aligned PWM waveform without dead time, POLA = 0 Dead-time counter When the a channel’s DTE bit is set in CON, the dead-time counter delays the passive-to-active transitions of both MCO outputs.
  • Page 953 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) active active passive passive MCOB active active passive passive POLA = 0 MCOA Fig 103. Center-aligned waveform with dead time, POLA = 0 31.8.2 Shadow registers and simultaneous updates The Limit, Match, and Communication Pattern registers (LIM, MAT, and CP) are implemented as register pairs, each consisting of a write register and an operational register.
  • Page 954 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) A capture event on a channel causes the following: The current value of the TC is stored in the Capture register (CAP). • If the channel’s capture event interrupt is enabled (see...
  • Page 955 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) MCOB2 CCPB2 = 1, on-state CCPA2 = 1, on-state MCOA2 MCOB1 CCPB1 = 0, off-state MCOA1 CCPA1 = 1, on-state MCOB0 CCPB0 = 0, off-state CCPA0 = 1, on-state MCOA0 POLA0 = 0, INVBDC = 0 Fig 104.
  • Page 956 UM10430 NXP Semiconductors Chapter 31: LPC18xx Motor Control PWM (MOTOCONPWM) MCOB2 POLA2 = 0 MCOA2 MAT2 MAT2 MCOB1 POLA1 = 0 MCOA1 MAT1 MAT1 MCOB0 POLA0 = 0 MCOA0 MAT0 LIM0 LIM0 timer reset timer reset Fig 105. Three-phase AC mode sample waveforms, edge aligned PWM mode 31.8.8 Interrupts...
  • Page 957 UM10430 Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) Rev. 3.0 — 26 July 2017 User manual 32.1 How to read this chapter The QEI is available on parts LPC185x/3x. 32.2 Basic configuration The QEI is configured as follows: • Table 746 for clocking and power control.
  • Page 958 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.4 Introduction A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and velocity.
  • Page 959 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) tim _int Velocity Timer Velocity Reload gating velc _int Velocity Compare Digital Filter Velocity Capture Quad Decoder err _int Velocity Counter inx _int dir _int enclk _int Windowing max _pos _int...
  • Page 960 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.5 Pin description Table 747. QEI pin description Description function QEI_A Used as the Phase A (PhA) input to the Quadrature Encoder Interface. QEI_B Used as the Phase B (PhB) input to the Quadrature Encoder Interface.
  • Page 961 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) Table 748. Register overview: QEI (base address 0x400C 6000) Name Access Address Description Reset value Reference offset INTSTAT 0xFE0 Interrupt status register Table 772 0xFE4 Interrupt enable register Table 773...
  • Page 962 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.1 Control registers 32.6.1.1 QEI Control register This register contains bits which control the operation of the position and velocity counters of the QEI module. Table 749: QEI Control register (CON - address 0x400C 6000) bit description...
  • Page 963 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) Table 751: QEI Configuration register (CONF - address 0x400C 6008) bit description Symbol Description Reset value DIRINV Direction invert. When = 1, complements the DIR bit. SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs.
  • Page 964 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.2 Position, index and timer registers 32.6.2.1 QEI Position register This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.
  • Page 965 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.2.6 QEI Index Count register This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. Table 757. QEI Index Count register (INXCNT- address 0x400C 6020) bit description...
  • Page 966 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.2.11 QEI Velocity Capture register This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer...
  • Page 967 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.2.16 QEI Index acceptance window register This register contains the width of the index acceptance window, when the index and the phase / clock edges fall nearly together. If the activating phase / clock edge falls before the Index, but within the window, the (re)calibration will be activated on that clock/phase edge.
  • Page 968 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.3 Interrupt registers 32.6.3.1 QEI Interrupt Enable Clear register Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable register (QEIIE). Table 770: QEI Interrupt Enable Clear register (IEC - address 0x400C 6FD8) bit description...
  • Page 969 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) Table 771: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description Symbol Description Reset value POS2_INT Indicates that the position 2 compare value is equal to the current position.
  • Page 970 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.6.3.4 QEI Interrupt Enable register This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a 0 bit disables the corresponding interrupt. Table 773: QEI Interrupt Enable register (IE - address 0x400C 6FE4) bit description...
  • Page 971 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) Table 774: QEI Interrupt Status Clear register (CLR - 0x400C 6FE8) bit description Symbol Description Reset value POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set.
  • Page 972 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) 32.7 Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel.
  • Page 973 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) Table 778. Encoder direction DIR bit DIRINV bit direction forward reverse reverse forward Figure 107 shows how quadrature encoder signals equate to direction and count. direction position -1 -1 -1 -1...
  • Page 974 UM10430 NXP Semiconductors Chapter 32: LPC18xx Quadrature Encoder Interface (QEI) is then cleared. The velocity timer is loaded with the contents of the velocity reload register (LOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The number of edges counted in a given time period is directly proportional to the velocity of the encoder.
  • Page 975 UM10430 Chapter 33: LPC18xx Repetitive Interrupt Timer (RIT) Rev. 3.0 — 26 July 2017 User manual 33.1 How to read this chapter The RIT is available on all LPC18xx parts. 33.2 Basic configuration The RIT is configured as follows: • Table 779 for clocking and power control.
  • Page 976 UM10430 NXP Semiconductors Chapter 33: LPC18xx Repetitive Interrupt Timer (RIT) RESET CNT_ENA RESET 32-bit COUNTER ENABLE_TIMER PBUS ENABLE_BREAK BREAK ENABLE_CLK PBUS bit 32 compare RESET COMPARATOR SET_INT bit 0 32 X compare INTR PBUS write '1' to clear RESET CTRL...
  • Page 977 UM10430 NXP Semiconductors Chapter 33: LPC18xx Repetitive Interrupt Timer (RIT) 33.5.1 RI Compare Value register Table 781. RI Compare Value register (COMPVAL - address 0x400C 0000) bit description Symbol Description Reset value 31:0 RICOMP Compare register. Holds the compare value which is 0xFFFF FFFF compared to the counter.
  • Page 978 UM10430 NXP Semiconductors Chapter 33: LPC18xx Repetitive Interrupt Timer (RIT) 33.5.4 RI Counter register Table 784. RI Counter register (COUNTER - address 0x400C 000C) bit description Symbol Description Reset value 31:0 RICOUNTER 32-bit up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in CTRL).
  • Page 979 UM10430 Chapter 34: LPC18xx Alarm timer Rev. 3.0 — 26 July 2017 User manual 34.1 How to read this chapter The Alarm timer is available on all LPC18xx parts. 34.2 Basic configuration The Alarm timer is configured as follows: • Table 785 for clocking and power control.
  • Page 980 UM10430 NXP Semiconductors Chapter 34: LPC18xx Alarm timer 34.4 Register description Table 786. Register overview: Alarm timer (base address 0x4004 0000) Name Access Address Description Reset Reference offset value DOWNCOUNTER 0x000 Downcounter register 0x000 Table 787 PRESET 0x004 Preset value register...
  • Page 981 UM10430 NXP Semiconductors Chapter 34: LPC18xx Alarm timer 34.4.4 Interrupt set enable register Table 790. Interrupt set enable register (SET_EN - 0x4004 0FDC) bit description Symbol Description Reset value SET_EN Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register.
  • Page 982 UM10430 Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) Rev. 3.0 — 26 July 2017 User manual 35.1 How to read this chapter The WWDT is available on all LPC18xx parts. 35.2 Basic configuration The WWDT is configured as follows: • Table 795 for clocking and power control.
  • Page 983 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) Flag to indicate Watchdog reset. • • The WWDT uses the IRC as a fixed clock source. 35.4 Applications The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state.
  • Page 984 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) 35.5.2 WWDT behavior in the power-down modes The WWDT is running in Sleep mode. A watchdog triggered reset in Sleep mode resets and wakes up the chip. Likewise, a watchdog triggered interrupt wakes up the chip from Sleep mode if the interrupt is enabled in the NVIC.
  • Page 985 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) Table 797. Watchdog Mode register (MOD - 0x4008 0000) bit description Symbol Value Description Reset value WDEN Watchdog enable bit. This bit is Set Only. The watchdog timer is stopped.
  • Page 986 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) Table 798. Watchdog operating modes selection WDEN WDRESET Mode of Operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.
  • Page 987 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) Table 800. Watchdog Feed register (FEED - 0x4008 0008) bit description Symbol Description Reset value Feed Feed value should be 0xAA followed by 0x55. 35.7.4 Watchdog timer value register The WDTV register is used to read the current value of Watchdog timer counter.
  • Page 988 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) Table 803. Watchdog Timer Window register (WINDOW - 0x4008 0018) bit description Symbol Description Reset value 23:0 WDWINDOW Watchdog window value. 0xFF FFFF 31:24 Reserved, user software should not write ones to reserved bits.
  • Page 989 UM10430 NXP Semiconductors Chapter 35: LPC18xx Windowed Watchdog timer (WWDT) WDCLK / 4 Watchdog 125A 1259 1258 1257 Counter Early Feed Event Watchdog Reset Conditions : WINDOW = 0x1200 WARNINT = 0x3FF = 0x2000 Fig 110. Early Watchdog Feed with Windowed Mode Enabled...
  • Page 990 UM10430 Chapter 36: LPC18xx Real-Time Clock (RTC) Rev. 3.0 — 26 July 2017 User manual 36.1 How to read this chapter The RTC is available on all parts. 36.2 Basic configuration The RTC is configured as follows: • Table 804 for clocking and power control.
  • Page 991 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) 36.4 General description The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially in reduced power modes.
  • Page 992 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) 36.6 Register description Table 806. Register overview: RTC (base address 0x4004 6000) Name Access Address Description Reset Reference offset value 0x000 Interrupt Location Register Table 808 0x004 Reserved 0x00 0x008 Clock Control Register...
  • Page 993 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) 36.6.1 Interrupt Location Register The Interrupt Location Register is a 2-bit register that specifies which blocks are generating an interrupt. Writing a one to the appropriate bit clears the corresponding interrupt. Writing a zero has no effect. This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read.
  • Page 994 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) 36.6.3 Counter Increment Interrupt Register The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt every time a counter is incremented. This interrupt remains valid until cleared by writing a 1 to bit 0 of the Interrupt Location Register (ILR[0]).
  • Page 995 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) 36.6.5 Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The...
  • Page 996 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) 36.6.5.3 Consolidated Time Register 2 The Consolidate Time Register 2 contains just the Day of Year value. Table 814. Consolidated Time register 2 (CTIME2 - address 0x4004 601C) bit description Symbol...
  • Page 997 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) Table 817. Seconds register (SEC - address 0x4004 6020) bit description Symbol Description Reset value SECONDS Seconds value in the range of 0 to 59 31:6 Reserved, user software should not write ones to reserved bits.
  • Page 998 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) Table 822. Day of year register (DOY - address 0x4004 6034) bit description Symbol Description Reset value Day of year value in the range of 1 to 365 (366 for leap years).
  • Page 999 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) Table 825. Calibration register (CALIBRATION - address 0x4004 6040) bit description Symbol Value Description Reset value CALDIR Calibration direction Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.
  • Page 1000 UM10430 NXP Semiconductors Chapter 36: LPC18xx Real-Time Clock (RTC) Table 829. Alarm Hours register (AHRS - address 0x4004 6068) bit description Symbol Description Reset value HOURS Hours value in the range of 0 to 23 31:5 Reserved, user software should not write ones to reserved bits.

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