NXP Semiconductors LPC2919/01 Manuals

Manuals and User Guides for NXP Semiconductors LPC2919/01. We have 2 NXP Semiconductors LPC2919/01 manuals available for free PDF download: User Manual

NXP Semiconductors LPC2919/01 User Manual (566 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Chapter 1: Lpc29Xx Introductory Information

3
Introduction

3
About this User Manual

3
General Features

3
Ordering Information

5
Block Diagram

8
Functional Blocks

13
Architectural Overview

14
ARM968E-S Processor

14
On-Chip Flash Memory System

15
On-Chip Static RAM

15
Chapter 2: Lpc29Xx Memory Mapping

16
How to Read this Chapter

16
Memory-Map View of the AHB

16
Memory-Map Regions

17
Memory-Map Operating Concepts

21
Chapter 3: Lpc29Xx Clock Generation Unit (CGU)

24
How to Read this Chapter

24
Introduction

24
CGU0 Functional Description

25
- Controlling the XO50M Oscillator (External Oscillator)
  28
- Controlling the PL160M PLL
  28
- Controlling the Frequency Dividers
  30
- Controlling the Clock Output
  30
- Reading the Control Settings
  30
- Frequency Monitor
  30
- Clock Detection
  31
- Bus Disable
  31
- Clock-Path Programming
  31
CGU1 Functional Description

31
Register Overview

32
Chapter 4 : Lpc29Xx Reset Generation Unit (RGU)

48
How to Read this Chapter

48
Introduction

48
RGU Functional Description

48
- Reset Hierarchy
  49
Register Overview

50
- RGU Reset Control Register
  51
- RGU Reset Status Register
  52
- RGU Reset Active Status Register
  58
- RGU Reset Source Registers
  59
  - POR Reset
    59
  - RGU Reset
    59
  - PCR Reset
    59
  - Cold Reset
    60
  - Peripherals Activated by Cold Reset
    60
  - Peripherals Activated by Warm Reset
    60
- RGU Bus-Disable Register
  61
Chapter 5: Lpc29Xx Power Management Unit (PMU)

62
How to Read this Chapter

62
Introduction

62
PMU Functional Description

62
- PMU Clock-Branch Run Mode
  64
- PMU Clock Branch Overview
  65
Register Overview

65
Chapter 6: Lpc29Xx System Control Unit (SCU)

73
How to Read this Chapter

73
Introduction

73
Register Overview

73
Chapter 7: Lpc29Xx Chip Feature ID (CFID)

81
Introduction

81
Register Overview

81
Chapter 8: Lpc29Xx Event Router

83
How to Read this Chapter

83
Event Router Functional Description

83
- Event Router Pin Connections
  84
Register Overview

85
- Event Status Register
  85
- Event-Status Clear Register
  86
- Event-Status Set Register
  86
- Event Enable Register
  86
- Event-Enable Clear Register
  87
- Event-Enable Set Register
  87
- Activation Polarity Register
  88
- Activation Type Register
  88
- Raw Status Register
  88
Chapter 9: Lpc29Xx Vectored Interrupt Controller (VIC)

90
How to Read this Chapter

90
VIC Functional Description

90
- Non-Nested Interrupt Service Routine
  92
- Nested Interrupt Service Routine
  92
VIC Programming Example

92
Register Overview

93
Chapter 10: Lpc29Xx General System Control

103
How to Read this Chapter

103
Introduction

103
Power Modes

103
Reset and Power-Up Behavior

104
Functional Description of the Interrupt and Wake-Up Structure

104
Interrupt Device Architecture

105
- Interrupt Registers
  106
- Interrupt Clear-Enable Register
  107
- Interrupt Set-Enable Register
  107
- Interrupt Status Register
  107
- Interrupt Enable Register
  107
- Interrupt Clear-Status Register
  107
- Interrupt Set-Status Register
  108
ISR Functional Description

108
- ESR Functional Description
  108
Wake-Up

109
Chapter 11 : Lpc29Xx Pin Configuration

111
How to Read this Chapter

111
LPC2917/19/01 Pinning Information

111
LPC2921/23/25 Pin Configuration

118
LPC2927/29 Pin Configuration

122
LPC2930/30 Pin Configuration

129
LPC2930 Boot Control

137
Chapter 12: Lpc29Xx External Static Memory Controller (SMC)

140
How to Read this Chapter

140
SMC Functional Description

140
External Memory Interface

141
Register Overview

146
Chapter 13: Lpc29Xx USB Device

154
How to Read this Chapter

154
Introduction

154
Features

155
Fixed Endpoint Configuration

155
Functional Description

156
- Analog Transceiver
  157
- Serial Interface Engine (SIE)
  157
- Endpoint RAM (EP_RAM)
  157
- EP_RAM Access Control
  157
- DMA Engine and Bus Master Interface
  157
- Register Interface
  157
- Softconnect
  157
- Goodlink
  158
Operational Overview

158
Pin Description

158
Clocking and Power Management

159
- Power Requirements
  159
- Clocks
  159
- Power Management Support
  159
- Remote Wake-Up
  160
Register Overview

160
Interrupt Handling

183
- Slave Mode
  183
- DMA Mode
  183
Serial Interface Engine Command Description

186
USB Device Controller Initialization

195
Slave Mode Operation

196
- Interrupt Generation
  196
- Data Transfer for out Endpoints
  197
- Data Transfer for in Endpoints
  197
DMA Operation

197
- Transfer Terminology
  197
- USB Device Communication Area
  198
- Triggering the DMA Engine
  199
- The DMA Descriptor
  199
- Next_Dd_Pointer
  200
- Dma_Mode
  200
- Next_Dd_Valid
  200
- Isochronous_Endpoint
  201
- Max_Packet_Size
  201
- Dma_Buffer_Length
  201
- Dma_Buffer_Start_Addr
  201
- Dd_Retired
  201
- Dd_Status
  201
- Packet_Valid
  202
- Ls_Byte_Extracted
  202
- Ms_Byte_Extracted
  202
- Present_Dma_Count
  202
- Message_Length_Position
  202
- Isochronous_Packetsize_Memory_Address
  202
- Non-Isochronous Endpoint Operation
  202
- Setting up DMA Transfers
  202
- Finding DMA Descriptor
  203
- Transferring the Data
  203
  - Optimizing Descriptor Fetch
    203
- Ending the Packet Transfer
  203
- Packet DD
  204
- Isochronous Endpoint Operation
  204
- Setting up DMA Transfers
  204
- Finding the DMA Descriptor
  204
  - Transferring the Data
    205
  - OUT Endpoints
    205
  - IN Endpoints
    205
- DMA Descriptor Completion
  205
- Isochronous out Endpoint Operation Example
  205
- Auto Length Transfer Extraction (ATLE) Mode Operation
  206
  - OUT Transfers in ATLE Mode
    207
  - IN Transfers in ATLE Mode
    208
- Setting up the DMA Transfer
  208
- Finding the DMA Descriptor
  208
- Transferring the Data
  208
  - OUT Endpoints
    208
  - IN Endpoints
    208
- Ending the Packet Transfer
  209
  - OUT Endpoints
    209
  - IN Endpoints
    209
Double Buffered Endpoint Operation

209
- Bulk Endpoints
  209
- Isochronous Endpoints
  211
Chapter 14: Lpc29Xx USB Host Controller

212
How to Read this Chapter

212
Introduction

212
- Features
  212
- Architecture
  213
Interfaces

213
- Pin Description
  213
- USB Host Usage Note
  214
- Software Interface
  214
Register Overview

214
- USB Host Register Definitions
  215
Chapter 15: Lpc29Xx USB OTG Interface

216
How to Read this Chapter

216
Introduction

216
Features

216
Architecture

216
Pin Configuration

217
- Suggested USB Interface Solutions
  219
Register Overview

221
HNP Support

230
- B-Device: Peripheral to Host Switching
  231
- Remove D+ Pull-Up
  233
- Add D+ Pull-Up
  234
- A-Device: Host to Peripheral HNP Switching
  234
  - Set BDIS_ACON_EN in External OTG Transceiver
    237
  - Ceiver
    237
  - Discharge VBUS
    237
  - Load and Enable OTG Timer
    238
  - Stop OTG Timer
    238
  - Suspend Host on Port 1
    238
Clocking and Power Management

239
- Device Clock Request Signals
  240
- Host Clock Request Signals
  240
- Power-Down Mode Support
  240
USB OTG Controller Initialization

241
Chapter 16: Lpc29Xx General Purpose Input/Output (GPIO)

242
How to Read this Chapter

242
GPIO Functional Description

242
Register Overview

243
- GPIO Port Input Register
  243
- GPIO Port Output Register
  244
- GPIO Port Direction Register
  244
Chapter 17: Lpc29Xx Timer 0/1/2/3

245
How to Read this Chapter

245
Timer Functional Description

245
Timer Counter and Interrupt Timing

246
Timer Match Functionality

247
- Timer Capture Functionality
  247
- Timer Interrupt Handling
  247
Register Overview

248
- Timer Control Register (TCR)
  248
- Timer Counter
  249
- Timer Prescale Register
  249
- Timer Match-Control Register
  250
- Timer External-Match Register
  251
- Timer Match Register
  252
- Timer Capture-Control Register
  252
- Timer Capture Register
  253
- Timer Interrupt Bit Description
  254
Chapter 18: Lpc29Xx SPI0/1/2

255
How to Read this Chapter

255
Introduction

255
- SPI Functional Description
  255
- Modes of Operation
  255
- Slave Mode
  257
Register Overview

258
- SPI Configuration Register
  258
- SPI Slave-Enable Register
  260
- SPI Transmit-FIFO Flush Register
  261
- SPI FIFO Data Register
  261
- SPI Receive FIFO POP Register
  262
- SPI Receive-FIFO Read-Mode Register
  262
- SPI DMA Settings Register
  263
- SPI Status Register (Status)
  264
- SPI Slave-Settings 1 Register
  265
- SPI Slave-Settings 2 Register
  266
- SPI FIFO Interrupt Threshold Register
  267
- SPI Interrupt Bit Description
  268
Chapter 19: Lpc29Xx Universal Asynchronous Receiver/Transmitter (UART)

269
How to Read this Chapter

269
Features

269
Pin Description

269
Register Overview

271
- Uartn Receiver Buffer Register
  271
- Uartn Transmit Holding Register
  272
- Uartn Divisor Latch Registers
  272
- Uartn Interrupt Enable Register
  273
- Uartn Interrupt Identification Register
  273
- Uartn FIFO Control Register
  275
- Uartn Line Control Register
  276
- UART0/1 Modem Control Register
  277
- Auto-Flow Control
  278
- Auto-RTS
  278
- Auto-CTS
  279
- Uartn Line Status Register
  280
- UART0/1 Modem Status Register
  281
- Uartn Scratch Pad Register
  282
- Uartn Auto-Baud Control Register
  282
- Auto-Baud
  283
- Auto-Baud Modes
  284
- Uartn Fractional Divider Register
  285
- Baudrate Calculation
  286
- Example 1: BASE_UART_CLK = 14.7456 Mhz, BR = 9600
  288
- Example 2: BASE_UART_CLK = 12 Mhz, BR = 115200
  288
- Uartn Transmit Enable Register
  288
- Uartn RS485 Control Register
  289
- Uartn RS485 Address Match Register
  290
- Uartn RS-485 Delay Value Register
  290
- Modes of Operation
  290
Architecture

291
Chapter 20: Lpc29Xx Watchdog Timer (WDT)

294
How to Read this Chapter

294
Introduction

294
Watchdog Programming Example

294
Register Overview

295
- Watchdog Timer-Control Register
  295
- Watchdog Timer Counter
  296
- Watchdog Prescale Register
  296
- Watchdog Timer Key Register
  297
- Watchdog Time-Out Register
  297
- Watchdog Debug Register
  297
- Watchdog Interrupt Bit Description
  298
Chapter 21: Lpc29Xx CAN 0/1

299
How to Read this Chapter

299
CAN Functional Description

299
CAN Controller 0

299
CAN Bus Timing

300
- Baud-Rate Prescaler
  300
- Synchronization Jump Width
  300
- Time Segments 1 and 2
  300
CAN Transmit Buffers

301
- Transmit Buffer Layout
  301
- Automatic Transmit-Priority Protection
  302
CAN Receive Buffer

302
- Receive Buffer Layout
  302
CAN Controller Self-Test

303
- Global Self-Test
  303
- Local Self-Test
  303
CAN Global Acceptance Filter

304
Register Overview

312
CAN Acceptance-Filter Register Overview

334
Fullcan Mode

342
CAN Configuration Example 1

353
CAN Configuration Example 2

355
CAN Look-Up Table Programming Guidelines

357
Chapter 22 : Lpc29Xx LIN/UART 0/1

359
How to Read this Chapter

359

NXP Semiconductors LPC2919/01 User Manual (571 pages)

ARM9 microcontroller with CAN and LIN

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Chapter 1: Lpc29Xx Introductory Information

3
Chapter 32 : Lpc29Xx Supplementary Information

3
Introduction

3
About this User Manual

3
General Features

3
Ordering Information

5
- Ordering Options
  6
- Comparison with LPC2917/19 Devices
  6
Chapter 2: Lpc29Xx Memory Mapping

15
How to Read this Chapter

15
Memory-Map View of the AHB

16
Memory-Map Regions

16
Chapter 3 : Lpc29Xx General System Control

23
How to Read this Chapter

23
Introduction

23
Chapter 4: Lpc29Xx Clock Generation Unit (CGU)

24
CGU0 Functional Description

24
Chapter 5: Lpc29Xx Reset Generation Unit (RGU)

47
How to Read this Chapter

47
RGU Functional Description

47
- Reset Hierarchy
  48
RGU Register Overview

49
Chapter 6: Lpc29Xx Power Management Unit (PMU)

61
How to Read this Chapter

61
Introduction

61
PMU Functional Description

61
- PMU Clock-Branch Run Mode
  63
- PMU Clock Branch Overview
  64
PMU Register Overview

64
- Power Mode Register (PM)
  69
- PMU Clock Configuration Register for Output
  70
Chapter 7 : Lpc29Xx System Control Unit (SCU)

81
Chapter 8 : Lpc29Xx Chip Feature ID (CFID)

81
- Configuration Register 1
  81
- Configuration Register 2
  81
- Configuration Register 3
  81
Chapter 9 : Lpc29Xx Event Router

85
- Event-Status Clear Register
  85
- Event-Status Set Register
  85
- Event Enable Register
  85
- Event-Enable Clear Register
  87
- Event-Enable Set Register
  87
- Activation Polarity Register
  88
- Activation Type Register
  88
Chapter 10: Lpc29Xx Vectored Interrupt Controller (VIC)

90
How to Read this Chapter

90
VIC Functional Description

90
- Non-Nested Interrupt Service Routine
  92
- Nested Interrupt Service Routine
  92
VIC Programming Example

92
VIC Register Overview

93
Chapter 11: Lpc29Xx Pin Configuration

111
How to Read this Chapter

111
LPC2917/19/01 Pinning Information

111
LPC2921/23/25 Pin Configuration

118
Chapter 12: Lpc29Xx External Static Memory Controller (SMC)

138
How to Read this Chapter

138
SMC Functional Description

138
External Memory Interface

139
External SMC Register Overview

144
- Bank Wait-State 1 Control Registers
  147
- Bank Wait-State 2 Control Registers
  147
Chapter 13: Lpc29Xx USB Device

152
How to Read this Chapter

152
Introduction

152
Features

153
Fixed Endpoint Configuration

153
Functional Description

154
- Analog Transceiver
  155
- Serial Interface Engine (SIE)
  155
- Endpoint RAM (EP_RAM)
  155
- EP_RAM Access Control
  155
- DMA Engine and Bus Master Interface
  155
- Register Interface
  155
- Softconnect
  155
- Goodlink
  156
Operational Overview

156
Pin Description

156
Clocking and Power Management

157
- Power Requirements
  157
- Clocks
  157
- Power Management Support
  157
- Remote Wake-Up
  158
Register Description

158
Interrupt Handling

181
- Slave Mode
  182
- DMA Mode
  182
Serial Interface Engine Command Description

184
USB Device Controller Initialization

193
Slave Mode Operation

194
- Interrupt Generation
  194
- Data Transfer for out Endpoints
  194
- Data Transfer for in Endpoints
  195
DMA Operation

195
- Transfer Terminology
  195
- USB Device Communication Area
  195
- Triggering the DMA Engine
  196
- The DMA Descriptor
  196
- Next_Dd_Pointer
  197
- Dma_Mode
  197
- Isochronous_Endpoint
  197
- Max_Packet_Size
  197
- Dma_Buffer_Length
  197
- Dma_Buffer_Start_Addr
  197
- Dd_Retired
  199
- Dd_Status
  199
- Packet_Valid
  199
- Ls_Byte_Extracted
  200
- Ms_Byte_Extracted
  200
- Present_Dma_Count
  200
- Message_Length_Position
  200
- Isochronous_Packetsize_Memory_Address
  200
- Setting up DMA Transfers
  200
- Finding DMA Descriptor
  200
  - Transferring the Data
    201
- Optimizing Descriptor Fetch
  201
- Ending the Packet Transfer
  201
- Setting up DMA Transfers
  202
- Finding the DMA Descriptor
  202
- Transferring the Data
  202
  - OUT Endpoints
    203
  - IN Endpoints
    203
- DMA Descriptor Completion
  203
- Isochronous out Endpoint Operation Example
  203
  - OUT Transfers in ATLE Mode
    204
  - IN Transfers in ATLE Mode
    206
- Setting up the DMA Transfer
  206
- Finding the DMA Descriptor
  206
- Transferring the Data
  206
  - OUT Endpoints
    206
  - IN Endpoints
    206
- Ending the Packet Transfer
  207
  - OUT Endpoints
    207
  - IN Endpoints
    207
Double Buffered Endpoint Operation

207
- Bulk Endpoints
  207
- Isochronous Endpoints
  209
Chapter 14 : Lpc29Xx USB Host Controller

211
- Pin Description
  211
- USB Host Usage Note
  212
- Software Interface
  212
- Register Map
  212
- USB Host Register Definitions
  213
Chapter 15 : Lpc29Xx USB OTG Interface

220
Chapter 16: Lpc29Xx General Purpose Input/Output (GPIO)

243
GPIO Register Overview

243
Chapter 17: Lpc29Xx Timer 0/1/2/3

246
How to Read this Chapter

246
Timer Functional Description

246
Timer Counter and Interrupt Timing

247
Timer Match Functionality

248
- Timer Capture Functionality
  248
- Timer Interrupt Handling
  248
Timer Register Overview

249
- Timer Control Register (TCR)
  250
Chapter 18: Lpc29Xx SPI0/1/2

256
How to Read this Chapter

256
Introduction

256
- SPI Functional Description
  256
- Modes of Operation
  256
- Slave Mode
  256
SPI Register Overview

258
- SPI Configuration Register
  260
- SPI Slave-Enable Register
  261
- SPI Receive-FIFO Read-Mode Register
  263
- SPI DMA Settings Register
  264
- SPI Status Register (Status)
  265
- SPI Slave-Settings 1 Register
  266
- SPI Slave-Settings 2 Register
  267
- SPI FIFO Interrupt Threshold Register
  268
Chapter 19: Lpc29Xx Universal Asynchronous Receiver/Transmitter (UART)

270
How to Read this Chapter

270
Features

270
Pin Description

270
Register Description

271
- Uartn Receiver Buffer Register
  274
- Uartn Transmit Holding Register
  274
- Uartn Divisor Latch LSB Register
  274
- Uartn Interrupt Enable Register
  275
- Uartn Interrupt Identification Register
  275
- Uartn FIFO Control Register
  278
- Uartn Line Control Register
  278
- UART0/1 Modem Control Register
  279
- Auto-Flow Control
  280
- Auto-RTS
  280
- Auto-CTS
  281
- Uartn Line Status Register
  282
- UART0/1 Modem Status Register
  283
- Uartn Scratch Pad Register
  284
- Uartn Auto-Baud Control Register
  284
Chapter 20: Lpc29Xx Watchdog Timer (WDT)

296
How to Read this Chapter

296
Introduction

296
Watchdog Programming Example

296
Watchdog Register Overview

297
- Watchdog Timer-Control Register
  298
- Watchdog Timer Counter
  299
Chapter 21: Lpc29Xx CAN 0/1

302
How to Read this Chapter

302
CAN Functional Description

302
CAN Controller 0

302
CAN Bus Timing

303
- Baud-Rate Prescaler
  303
- Synchronization Jump Width
  303
- Time Segments 1 and 2
  303
CAN Transmit Buffers

304
- Transmit Buffer Layout
  304
- Automatic Transmit-Priority Protection
  305
CAN Receive Buffer

305
- Receive Buffer Layout
  305
CAN Controller Self-Test

306
- Global Self-Test
  306
- Local Self-Test
  306
CAN Global Acceptance Filter

307
CAN Acceptance-Filter Register Overview

337
Chapter 22: Lpc29Xx LIN

342
Fullcan Mode

345

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NXP Semiconductors LPC2919/01 Manuals

NXP Semiconductors LPC2919/01 User Manual (566 pages)

Table of Contents

Chapter 1: Lpc29Xx Introductory Information

Introduction

About this User Manual

General Features

Ordering Information

Block Diagram

Functional Blocks

Architectural Overview

ARM968E-S Processor

On-Chip Flash Memory System

On-Chip Static RAM

Chapter 2: Lpc29Xx Memory Mapping

How to Read this Chapter

Memory-Map View of the AHB

Memory-Map Regions

Memory-Map Operating Concepts

Chapter 3: Lpc29Xx Clock Generation Unit (CGU)

How to Read this Chapter

Introduction

CGU0 Functional Description

CGU1 Functional Description

Register Overview

Chapter 4 : Lpc29Xx Reset Generation Unit (RGU)

How to Read this Chapter

Introduction

RGU Functional Description

Register Overview

Chapter 5: Lpc29Xx Power Management Unit (PMU)

How to Read this Chapter

Introduction

PMU Functional Description

Register Overview

Chapter 6: Lpc29Xx System Control Unit (SCU)

How to Read this Chapter

Introduction

Register Overview

Chapter 7: Lpc29Xx Chip Feature ID (CFID)

Introduction

Register Overview

Chapter 8: Lpc29Xx Event Router

How to Read this Chapter

Event Router Functional Description

Register Overview

Chapter 9: Lpc29Xx Vectored Interrupt Controller (VIC)

How to Read this Chapter

VIC Functional Description

VIC Programming Example

Register Overview

Chapter 10: Lpc29Xx General System Control

How to Read this Chapter

Introduction

Power Modes

Reset and Power-Up Behavior

Functional Description of the Interrupt and Wake-Up Structure

Interrupt Device Architecture

ISR Functional Description

Wake-Up

Chapter 11 : Lpc29Xx Pin Configuration

How to Read this Chapter

LPC2917/19/01 Pinning Information

LPC2921/23/25 Pin Configuration

LPC2927/29 Pin Configuration

LPC2930/30 Pin Configuration

LPC2930 Boot Control

Chapter 12: Lpc29Xx External Static Memory Controller (SMC)

How to Read this Chapter

SMC Functional Description

External Memory Interface

Register Overview

Chapter 13: Lpc29Xx USB Device

How to Read this Chapter

Introduction

Features

Fixed Endpoint Configuration

Functional Description

Operational Overview

Pin Description