NXP Semiconductors LPC553 Series Hardware Design Manuallines
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NXP Semiconductors LPC553 Series Hardware Design Manuallines

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AN13707
Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers
Rev. 1 — 4 September 2023
Document Information
Information
Keywords
Abstract
Content
Hardware Design Guidelines, LPC553x
This document guides hardware engineers to design and test their LPC553x/S3x controller-based
designs. The document provides information about board layout recommendations and design
checklists.
Application note

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Summary of Contents for NXP Semiconductors LPC553 Series

  • Page 1 AN13707 Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Rev. 1 — 4 September 2023 Application note Document Information Information Content Keywords Hardware Design Guidelines, LPC553x Abstract This document guides hardware engineers to design and test their LPC553x/S3x controller-based designs. The document provides information about board layout recommendations and design checklists.

  • Page 2: Introduction

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 1 Introduction This document helps the hardware engineers to design and test their LPC553x/S3x controller-based designs. The document provides information about board layout recommendations and design checklists to ensure first- pass success and avoid any board bring-up problems.

  • Page 3: Two I/O Power Supplies

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers MCU MAIN MCU VBAT 1.9 V/3.3 V 1.9 V/3.3 V VDD_MAIN VBAT VDD_MAIN_PWR 47 pF 100 nF 4.7 μF 22 μF 100 nF 47 pF VDD_CORE(1.0-1.2 V) LPC553x 4.7 μH 22 μF...

  • Page 4: Separate Vbat

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Table 2. LPC553x/S3x power supply for pins ...continued GPIO pins PIO2_0 to PIO2_1 RESETN VDDIO_2 P0_0 P0_2 to P0_6 P0_9 P0_13 to P0_14 P0_18 to P0_22 P0_24 to P0_26 P0_28 to P0_30...

  • Page 5: Introduction

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 4.1 Introduction The LPC553x/S3x has the following clock sources: • Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to +/- 1 % accuracy over the entire voltage and 0 °C to 85 °C.

  • Page 6: Crystal Printed Circuit Board (Pcb) Design Guidelines

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers XTAL32M_P XTAL32M_N XTAL C X1 C X2 Figure 4. Reference oscillator circuit Table 3. Components of the oscillator circuit Symbol Description XTAL Quartz Crystal / Ceramic Resonator Stabilizing Capacitor Stabilizing Capacitor For best results, it is critical to select a matching crystal for the on-chip oscillator. Load Capacitance (CL), Series Resistance (RS), and Drive Level (DL) are important parameters to consider while choosing the crystal.

  • Page 7: Rtc Oscillator

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers • Do not lay out other signal lines under the crystal unit for multi-layered PCB. 4.4 RTC oscillator The crystal oscillator has an embedded capacitor bank that can be used as an integrated load capacitor for the crystal oscillators.

  • Page 8: Rtc Printed Circuit Board (Pcb) Design Guidelines

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 4.4.1 RTC Printed Circuit Board (PCB) design guidelines • Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip.

  • Page 9: Boot Mode Configuration

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 5 Boot mode configuration This section gives information about boot mode selection and configuration. 5.1 Boot mode selection The internal ROM memory is used to store the boot code called boot ROM. After a reset, the Arm processor starts its code execution from this memory.
  • Page 10 AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Table 5. ISP pin assignment ...continued ISP pin Port pin assignment SPI Flash Recovery mode FC0_TXD_SCL_MISO_WS PIO0_30 FC0_RXD_SDA_MOSI_DATA PIO0_24 FC0_CTS_SDA_SSELN0 PIO0_31 FC0_SCK PIO0_28 HS_SPI_SCK PIO1_2 HS_SPI_SSEL1 PIO1_1 HS_SPI_MISO PIO1_3 HS_SPI_MOSI PIO0_26 FC3_TXD_SCL_MISO_WS...

  • Page 11: Debug And Programing Interface

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Table 5. ISP pin assignment ...continued ISP pin Port pin assignment FLEXSPI_D6 PIO1_27 FLEXSPI_D7 PIO1_29 6 Debug and programing interface When developing your circuit board based on LPC553x/S3x device, use a standard debug signal arrangement to make the connection to the debugger easier.

  • Page 12: Debug Connector Pinouts

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 10 kΩ 10 kΩ 10 kΩ SWDIO SWDIO SWDCLK SWDCLK LPC55Sxx debug connector RESET RESET 10 kΩ Figure 7. SWD connector connections 6.1 Debug connector pinouts The JTAG interface on LPC553x/S3x’s is only used for BSDL scan; however, the user can use a smaller 0.05”...

  • Page 13: Communication Modules

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 7 Communication modules This section provides details about communication modules. 7.1 FlexSPI interface LPC553x/S3x has one instance of the FlexSPI module (Serial Peripheral Interface), this FlexSPI host controller supports 1 port and up to 2 external devices. It supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines).

  • Page 14: Usb Interface

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 7.2 USB interface Use the recommendations below for the USB: • Route the high-speed clocks and the DP and DM differential pair first. • Route the DP and DM signals on the top (or bottom) layer of the board.

  • Page 15: Analog

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers The LPC553x/S3x CAN-FD module is a full implementation of the CAN protocol specification, the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0 version B protocol, which supports both standard and extended message frames and long payloads up to 64 bytes transferred at faster rates up to 8 Mbit/s.

  • Page 16: Opamp Usage

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Table 7. ADC input resistance Symbol Parameter Conditions Typical Unit Input resistance Fast/Muxed ADC Input Channels (PIO0_1. PIO0_10. PIO0_11. PIO0_12, PIO0_15, PIO0_16, PIO01_0, PIO1_7) VDDA = 1.8 V kΩ VDDA = 3.0 V kΩ...

  • Page 17: Pin Pull-Up/Down And Open-Drain

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 9.1.1 Pin pull-up/down and open-drain All pins have all pull-ups, pull-downs, and inputs turned off at reset except PIO0_0, PIO0_2, PIO0_5, PIO0_9, PIO0_13, and PIO0_14 pins. It prevents power loss through pins before software configuration. Due to special pin functions, some pins have a different reset configuration.

  • Page 18: Printed Circuit Board

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Table 8. Termination of unused pins ...continued Default state Recommended termination of unused pins VREFP Tie to VDD_MAIN VREFN Tie to VSS VDDA Tie to VDD_MAIN VSSA Tie to VSS USBn_DP Float...

  • Page 19: Traces Recommendations

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Figure 12.  HLQFP soldering footprint guideline 9.4.2 Traces recommendations A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45°...

  • Page 20: Grounding

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers them. These vias add additional capacitance and inductance, and reflections occur due to the change in the characteristic impedance. Vias also increase the trace length. While using differential signals, use vias in both traces or compensate the delay in the other trace.
  • Page 21 AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers circuits. EMI is radio frequency energy that interferes with the operation of an electronic device. This radio frequency energy can be produced by the device itself or by other devices nearby. Studying EMC for your system allows testing the ability of your system to operate successfully counteracting the effects of unplanned electromagnetic disturbances coming from the devices and systems around it.

  • Page 22: Pcb Layer Stacking

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 9.4.5 PCB layer stacking To reach signal integrity and performance requirements, four-layer PCB is recommended for implementing Ethernet applications and systems. The following layer stack-ups are recommended for four, six, and eight-layer boards, although other options are possible.

  • Page 23: Revision History

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers 3. LPC553x/S3x Reference Manual (document LPC553xRM) 4. Using the DC-DC and LDO Features on the LPC553x/LPC55S3x Family (document AN13528) 5. LPC55(S)3x ADC with Hardware Trigger and ADC Calculator Tool (document AN13523) 6.

  • Page 24: Legal Information

    NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, Translations — A non-English (translated) version of a document, including punitive, special or consequential damages (including - without limitation - the legal information in that document, is for reference only.

  • Page 25: Table Of Contents

    AN13707 NXP Semiconductors Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers Contents Introduction ............2 LPC553x/S3x family comparison ....... 2 Power supply ............2 Introduction ............2 Two I/O power supplies ........3 Separate VBAT ..........4 Bulk and decoupling capacitors ......4 Clock circuitry ............. 4 Introduction ............

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Lpc55s3 series

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