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NXP Semiconductors LPC21 Series User Manual
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NXP Semiconductors LPC21 Series User Manual

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UM10114
LPC21xx and LPC22xx User manual
Rev. 03 — 2 April 2008
Document information
Info
Content
Keywords
LPC2109/00, LPC2109/01, LPC2119, LPC2119/01, LPC2129,
LPC2129/01, LPC2114, LPC2114/01, LPC2124, LPC2124/01, LPC2194,
LPC2194/01, LPC2210, LPC2220, LPC2210/01, LPC2212, LPC2212/01,
LPC2214, LPC2214/01, LPC2290, LPC2290/01, LPC2292, LPC2292/01,
LPC2294, LPC2294/01, ARM, ARM7, 32-bit, Microcontroller
Abstract
User manual for LPC2109/19/29/14/24/94 and
LPC2210/20/12/14/90/92/94 including /01 parts
User manual

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Summary of Contents for NXP Semiconductors LPC21 Series

  • Page 1 UM10114 LPC21xx and LPC22xx User manual Rev. 03 — 2 April 2008 User manual Document information Info Content Keywords LPC2109/00, LPC2109/01, LPC2119, LPC2119/01, LPC2129, LPC2129/01, LPC2114, LPC2114/01, LPC2124, LPC2124/01, LPC2194, LPC2194/01, LPC2210, LPC2220, LPC2210/01, LPC2212, LPC2212/01, LPC2214, LPC2214/01, LPC2290, LPC2290/01, LPC2292, LPC2292/01, LPC2294, LPC2294/01, ARM, ARM7, 32-bit, Microcontroller Abstract User manual for LPC2109/19/29/14/24/94 and...
  • Page 2 Integrated related parts into this manual and made numerous editorial and content updates throughout the document: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. •...

  • Page 3: Chapter 1: Introductory Information

    UM10114 Chapter 1: Introductory information Rev. 03 — 2 April 2008 User manual 1. Introduction The LPC21xx and LPC22xx are based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 64/128/256 kilobytes (kB) of embedded high speed flash memory.

  • Page 4: Features

    UM10114 NXP Semiconductors Chapter 1: Introductory information Table 1. LPC21xx and LPC22xx legacy/enhanced parts overview Legacy parts Enhanced parts LPC2109/00 LPC2109/01 LPC2119, LPC2119/00 LPC2119/01 LPC2129, LPC2129/00 LPC2129/01 LPC2114, LPC2114/00 LPC2114/01 LPC2124, LPC2124/00 LPC2124/01 LPC2194, LPC2194/00 LPC2194/01 LPC2210 LPC2210/01 LPC2220, LPC2220/G...

  • Page 5: Enhanced Features

    UM10114 NXP Semiconductors Chapter 1: Introductory information • Up to 12 edge or level sensitive external interrupt pins available. • 60 MHz maximum CPU clock available from programmable on-chip PLL with a possible input frequency of 10 MHz to 25 MHz and a settling time of 100 ms.

  • Page 6: Lpc2114/2124

    UM10114 NXP Semiconductors Chapter 1: Introductory information Table 2. LPC2109/2119/2129 Ordering information …continued Type number Package Name Description Version LPC2129FBD64 LQFP64 plastic low profile quad flat package; 64 leads; SOT314-2 body 10 × 10 × 1.4 mm LPC2129FBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;...

  • Page 7: Lpc2194

    UM10114 NXP Semiconductors Chapter 1: Introductory information Table 5. LPC2114/2124 Ordering options Type number Flash Fast GPIO/SSP/ Temperature range memory Enhanced UART, ADC, Timer −40 °C to +85 °C LPC2114FBD64 128 kB 16 kB −40 °C to +85 °C LPC2114FBD64/00...

  • Page 8: Lpc2212/2214

    UM10114 NXP Semiconductors Chapter 1: Introductory information Table 8. LPC2210/2220 Ordering information …continued Type number Package Name Description Version LPC2220FBD144 LQFP144 plastic low profile quad flat package; 144 SOT486-1 leads; body 20 × 20 × 1.4 mm LPC2220FET144 TFBGA144 plastic thin fine-pitch ball grid array package;...

  • Page 9: Lpc2290

    UM10114 NXP Semiconductors Chapter 1: Introductory information Table 11. LPC2212/2214 Ordering options Type number Flash memory Fast GPIO/ Temperature range SSP/ Enhanced UART, ADC, Timer −40 °C to +85 °C LPC2212FBD144 128 kB 16 kB −40 °C to +85 °C...
  • Page 10 UM10114 NXP Semiconductors Chapter 1: Introductory information Table 14. LPC2292/2294 Ordering information …continued Type number Package Name Description Version LPC2294HBD144 LQFP144 plastic low profile quad flat package; SOT486-1 144 leads; body 20 × 20 × 1.4 mm LPC2294HBD144/00 LQFP144 plastic low profile quad flat package;...

  • Page 11: Block Diagram

    UM10114 NXP Semiconductors Chapter 1: Introductory information 5. Block diagram XTAL2 TRST XTAL1 LPC21xx TEST/DEBUG LPC22xx INTERFACE SYSTEM FUNCTIONS ARM7TDMI-S system HIGH-SPEED P0, P1 VECTORED clock GPI/O AHB BRIDGE INTERRUPT CONTROLLER AMBA AHB (Advanced High-performance Bus) ARM7 local bus INTERNAL...

  • Page 12: Architectural Overview

    UM10114 NXP Semiconductors Chapter 1: Introductory information Table 16. LPC21xx/22xx part-specific configuration Part SRAM Flash Legacy Fast Enhanced Enhanced GPIO GPIO UART timers channels channels/ enhanced No-suffix and /00 parts LPC2109 8 kB 64 kB P0/1 LPC2119 16 kB 128 kB...

  • Page 13: Arm7Tdmi-S Processor

    UM10114 NXP Semiconductors Chapter 1: Introductory information AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC21xx/LPC22xx peripheral functions (other than the interrupt controller) are connected to the APB bus.

  • Page 14: On-Chip Static Ram (Sram)

    UM10114 NXP Semiconductors Chapter 1: Introductory information • using the serial built-in JTAG interface • using In System Programming (ISP) and UART • using In Application Programming (IAP) capabilities The application program, using the IAP functions, may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.

  • Page 15: Chapter 2: Lpc21Xx/22Xx Memory Map

    UM10114 Chapter 2: LPC21xx/22xx Memory map Rev. 03 — 2 April 2008 User manual 1. How to read this chapter Remark: The LPC21xx and LPC22xx contain different memory configurations and APB/AHB peripherals. See Table 2–17 for part-specific memory and peripherals. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this...
  • Page 16 UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map Table 17. LPC21xx and LPC22xx memory and peripheral configuration Part SRAM Flash Fast GPIO Table 2–18 Figure 2–2 Figure 2–2 Figure 2–2 Figure 2–2 Table 2–18 addresses size/ addresses size/ addresses APB base addresses...

  • Page 17: Memory Maps

    UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map Table 17. LPC21xx and LPC22xx memory and peripheral configuration Part SRAM Flash Fast GPIO Table 2–18 Figure 2–2 Figure 2–2 Figure 2–2 Figure 2–2 Table 2–18 addresses size/ addresses size/ addresses APB base addresses...
  • Page 18 UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 0xF000 0000 3.75 GB 0xEFFF FFFF APB PERIPHERALS 0xE000 0000 3.5 GB 0xDFFF FFFF 0xC000 0000 3.0 GB RESERVED ADDRESS SPACE 0x8400 0000 0x83FF FFFF EXTERNAL MEMORY BANKS 0 TO 4...
  • Page 19 UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 0xFFE0 0000 4.0 GB - 2 MB 0xFFDF FFFF RESERVED 0xF000 0000 3.75 GB 0xEFFF FFFF RESERVED 0xE020 0000 3.5 GB + 2 MB 0xE01F FFFF APB PERIPHERALS 3.5 GB...
  • Page 20 UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once.

  • Page 21: Lpc21Xx And Lpc22Xx Memory Re-Mapping And Boot Block

    UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map Table 18. APB peripheries and base addresses APB peripheral Base address Peripheral name 0xE000 0000 Watchdog timer 0xE000 4000 Timer 0 0xE000 8000 Timer 1 0xE000 C000 UART0 0xE001 0000 UART1 0xE001 4000...

  • Page 22: Memory Map Concepts And Operating Modes 21 3.2 Memory Re-Mapping

    UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map Table 19. ARM exception vector locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort (instruction fetch memory fault) 0x0000 0010 Data Abort (data access memory fault)

  • Page 23: Prefetch Abort And Data Abort Exceptions

    UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map 1. Minimize the need for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space. 2. To provide space to store constants for jumping beyond the range of single word branch instructions.
  • Page 24 UM10114 NXP Semiconductors Chapter 2: LPC21xx/22xx Memory map – Address space between the top of the boot block and the APB peripheral space, except space used for external memory (LPC2292/2294 only). This is the address range from 0x8000 0000 to 0xDFFF FFFF, labelled "Reserved Address Space" in Figure 2–2, and...

  • Page 25: Chapter 3: Lpc21Xx/22Xx Memory Accelerator Module (Mam)

    UM10114 Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The MAM is identical for all parts with flash memory. It is available in the following parts: • LPC2109, LPC2119, LPC2129, and /01 versions •...

  • Page 26: Mam Blocks

    UM10114 NXP Semiconductors Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM) When a branch outside the contents of the branch trail and prefetch buffers is taken, one flash access cycle is needed to load the branch trail buffers. Subsequently, there will typically be no further fetch delays until another such “Instruction Miss”...

  • Page 27: Instruction Latches And Data Latches

    UM10114 NXP Semiconductors Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM) FLASH FLASH MEMORY MEMORY BANK 0 BANK 1 ARM LOCAL BUS INTERFACE BANK SELECTION MEMORY DATA Fig 6. Simplified block diagram of the Memory Accelerator Module (MAM) 4.2 Instruction latches and data latches Code and data accesses are treated separately by the Memory Accelerator Module.There...

  • Page 28: Mam Operating Modes

    UM10114 NXP Semiconductors Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM) 5. MAM operating modes Three modes of operation are defined for the MAM, trading off performance for ease of predictability: Mode 0: MAM off. All memory requests result in a flash read operation (see...

  • Page 29: Mam Configuration

    UM10114 NXP Semiconductors Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM) 6. MAM configuration After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required.

  • Page 30: Mam Usage Notes

    UM10114 NXP Semiconductors Chapter 3: LPC21xx/22xx Memory Accelerator Module (MAM) Table 25. MAM Timing register (MAMTIM - address 0xE01F C004) bit description Symbol Value Description Reset value MAM_fetch_ 0 - Reserved. cycle_timing 1 - MAM fetch cycles are 1 processor clock (CCLK) in...

  • Page 31: Chapter 4: Lpc21Xx/22Xx External Memory Controller (Emc)

    UM10114 Chapter 4: LPC21xx/22xx External Memory Controller (EMC) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter This chapter applies to all parts with external memory controller. The EMC is identical for all these parts. It is available in the following parts (in all 144 pin packages): •...

  • Page 32: Pin Description

    UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) Table 27. Address ranges of the external memory banks Bank Address range Configuration register 0x8000 0000 - 0x80FF FFFF BCFG0 0x8100 0000 - 0x81FF FFFF BCFG1 0x8200 0000 - 0x82FF FFFF...

  • Page 33: Bank Configuration Registers

    UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) 5.1 Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C) Table 30. Bank Configuration Registers 0-3 (BCFG0-3 - 0xFFE0 0000 to 0xFFE0 000C) address description BCFG0-3 Name Function...

  • Page 34: Read Byte Lane Control (Rble)

    UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) Table 31. Default memory widths at reset Bank BOOT[1:0] during Reset BCFG[29:28] Reset value Memory width 8 bits 16 bits 32 bits 16 bits 32 bits 16 bits 8 bits 5.2 Read Byte Lane Control (RBLE)

  • Page 35: Accesses To Memory Banks Constructed From 16 Or 32 Bit Memory Devices

    UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) 5.2.2 Accesses to memory banks constructed from 16 or 32 bit memory devices For memory banks constructed from 16 bit or 32-bit memory devices, it is important that the RBLE bit is set to one within the respective memory bank configuraton register. This asserts all BLS[3:0] lines LOW during a read access to that particular bank.
  • Page 36 UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) BLS[3] BLS[2] BLS[1] BLS[0] IO[7:0] IO[7:0] IO[7:0] IO[7:0] D[31:24] D[23:16] D[15:8] D[7:0] A[a_m:0] A[a_m:0] A[a_m:0] A[a_m:0] A[a_b:2] a. 32 bit wide memory bank interfaced to 8 bit memory chips (RBLE = 0)

  • Page 37: Typical Bus Sequences

    UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) BLS[1] BLS[0] IO[7:0] IO[7:0] D[15:8] D[7:0] A[a_m:0] A[a_m:0] A[a_b:1] a. 16 bit wide memory bank interfaced to 8 bit memory chips (RBLE = 0) BLS[1] BLS[0] D[15:0] IO[15:0] A[a_m:0] A[a_b:1] b.
  • Page 38 UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) 1 wait state (WST1=0) XCLK WE/BLS addr data change valid data valid address 2 wait states (WST1=1) XCLK WE/BLS addr data change valid data valid address Fig 10. External memory read access (WST1 = 0 and WST1 = 1 examples)

  • Page 39: External Memory Selection

    UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) For example, when the first read access to the memory bank that has just been selected is performed, CS and OE lines may become low one XCLK cycle earlier than it is shown in Figure 4–11.
  • Page 40 UM10114 NXP Semiconductors Chapter 4: LPC21xx/22xx External Memory Controller (EMC) Table 32. External memory and system requirements Access Maximum frequency WST setting Required memory access cycle (WST>=0; round up to time integer) ≤ × Standard – WST2 – WST2 ≤...

  • Page 41: Chapter 5: Lpc21Xx/22Xx Vectored Interrupt Controller (Vic)

    UM10114 Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The VIC is identical for all parts. However, the interrupts routed to the VIC depend on the peripherals implemented on a specific part. See Table 5–33 for part specific interrupt sources.

  • Page 42: Features

    UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 33. LPC21xx/22xx part-specific interrupts Part UART Registers: Table 5–51, Table 5–35 LPC2210 TXRIS, RXRIS, RTRIS, RORRIS - ABTO, ABEO LPC2212 TXRIS, RXRIS, RTRIS, RORRIS - ABTO, ABEO LPC2214 TXRIS, RXRIS, RTRIS, RORRIS -...

  • Page 43: Register Description

    UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) All registers in the VIC are word registers. Byte and halfword reads and write are not supported. Additional information on the Vectored Interrupt Controller is available in the ARMPrimeCell Vectored Interrupt Controller (PL190) documentation.
  • Page 44 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 34. VIC register map Name Description Access Reset Address value VICVectAddr1 Vector address 1 register. 0xFFFF F104 VICVectAddr2 Vector address 2 register. 0xFFFF F108 VICVectAddr3 Vector address 3 register.

  • Page 45: Vic Registers

    UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) 5. VIC registers The following section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to those most abstracted for use by software.

  • Page 46: Raw Interrupt Status Register

    UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 38. Software Interrupt Clear Register (VICSoftIntClear - address 0xFFFF F01C) bit allocation Reset value: 0x0000 0000 Symbol CAN4 RX CAN3 RX CAN2 RX CAN1 RX Access Symbol CAN4 TX...

  • Page 47: Interrupt Enable Clear Register

    UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 41. Interrupt Enable Register (VICINtEnable - address 0xFFFF F010) bit description VICIntEnable Description Reset value 31:0 When this register is read, 1s indicate interrupt requests or software interrupts that are enabled to contribute to FIQ or IRQ.
  • Page 48 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) 5.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004) This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.
  • Page 49 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 48. Default Vector Address register (VICDefVectAddr - address 0xFFFF F034) bit description VICDefVectAddr Description Reset value 31:0 When an IRQ service routine reads the Vector Address register (VICVectAddr), and no IRQ slot responds as described above, this address is returned.
  • Page 50 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 51. Connection of interrupt sources to the Vectored Interrupt Controller Block Flag(s) VIC Channel # and Mask Watchdog Interrupt (WDINT) 0x0000 0001 Reserved for software interrupts only 0x0000 0002...
  • Page 51 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Table 51. Connection of interrupt sources to the Vectored Interrupt Controller Block Flag(s) VIC Channel # and Mask CAN common and acceptance filter (1 ORed CAN, 0x0008 0000 LUTerr) CAN1 TX...
  • Page 52 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) interrupt request, masking and selection non-vectored FIQ interrupt logic nVICFIQIN SOFTINTCLEAR INTENABLECLEAR [31:0] [31:0] FIQSTATUS[31:0] FIQSTATUS SOFTINT INTENABLE [31:0] nVICFIQ [31:0] [31:0] VICINT SOURCE non-vectored IRQ interrupt logic [31:0] IRQSTATUS[31:0]...
  • Page 53 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Furthermore, It is possible that the VIC state has changed during step 3. For example, VIC was modified so that the interrupt that triggered the sequence starting with step 1) is no longer pending -interrupt got disabled in the executed code.
  • Page 54 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) SUBS pc, lr, #4 The SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set, and therefore execution will continue with all interrupts disabled. However, this can cause...
  • Page 55 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) This is the best workaround where the maximum time for which FIQs are disabled is critical (it does not increase this time at all). However, it does not solve problem one, and requires extra instructions at every point where IRQs and FIQs are disabled together.
  • Page 56 UM10114 NXP Semiconductors Chapter 5: LPC21xx/22xx Vectored Interrupt Controller (VIC) Example: Assuming that UART0 and SPI0 are generating interrupt requests that are classified as vectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I C are generating non-vectored IRQs, the following could be one possibility for VIC...
  • Page 57 UM10114 Chapter 6: LPC21xx/22xx System control Rev. 03 — 2 April 2008 User manual 1. How to read this chapter Remark: The LPC21xx and LPC22xx have different features and peripherals enabled depending on part number and version. Refer to Table 6–52 for registers that need to be configured for each specific part and peripheral.
  • Page 58 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 52. LPC21xx/22xx part-specific register bits Power control for Hi-Speed GPIO Peripheral Clock Memory mapping peripherals modes PCONP bit, Table 6–74 SCS bit, Table 6–61 APBDIV bit, MEMMAP mode, Table 6–76 Table 6–62...
  • Page 59 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 53. Pin summary Pin name Pin description direction EINT1 Input External Interrupt Input 1 - See the EINT0 description above. Pins P0.3 and P0.14 can be selected to perform EINT1 function.
  • Page 60 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 5. Crystal oscillator While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by the LPC21xx/22xx if supplied to its input XTAL1 pin, this microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only.
  • Page 61 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 55. Recommended values for C in oscillation mode (crystal and external X1/X2 components parameters) Fundamental Crystal load Maximum crystal External load oscillation frequency capacitance C series resistance R capacitors C 1 MHz - 5 MHz...
  • Page 62 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 6. External interrupt inputs The LLPC21xx/LPC22xx includes four external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 6.1 Register description The external interrupt function has four registers associated with it.
  • Page 63 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control For example, if a system wakes up from power-down using a low level on external interrupt 0 pin, its post-wakeup code must reset the EINT0 bit in order to allow future entry into the power-down mode.
  • Page 64 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 6.3 External interrupt Wakeup register (EXTWAKE - 0xE01F C144) Enable bits in the EXTWAKE register allow the external interrupts and other sources to wake up the processor if it is in Power-down mode. The related EINTn function must be mapped to the pin in order for the wakeup process to take place.
  • Page 65 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 59. External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit description Symbol Value Description Reset value EXTMODE2 0 Level-sensitivity is selected for EINT2. EINT2 is edge sensitive. EXTMODE3 0 Level-sensitivity is selected for EINT3.
  • Page 66 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 6.6 Multiple external interrupt pins Software can select multiple pins for each of EINT3:0 in the Pin Select registers, which are described in Section 8–6. The external interrupt logic for each of EINT3:0 receives the state of all of its associated pins from the pins’...
  • Page 67 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control wakeup enable APB Read (one bit of EXTWAKE) of EXTWAKE EINTi to wakeup APB Bus Data timer GLITCH EINTi PCLK FILTER interrupt flag EXTPOLARi (one bit of EXTINT) to VIC EXTMODEi APB read of...
  • Page 68 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 61. System Control and Status flags register (SCS - address 0xE01F C1A0) bit description Symbol Value Description Reset value GPIO1M GPIO port 1 mode selection. GPIO port 1 is accessed via APB addresses in a fashion compatible with previous LCP2000 devices.
  • Page 69 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 8.2 Memory mapping control usage notes The Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling ARM exceptions (interrupts). For example, whenever a Software Interrupt request is generated, the ARM core will always fetch 32-bit data "residing"...
  • Page 70 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 63. PLL registers Name Description Access Reset Address value PLLCON PLL Control Register. Holding register for updating PLL control bits. 0xE01F C080 Values written to this register do not take effect until a valid PLL feed sequence has taken place.
  • Page 71 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 9.2 PLL Control register (PLLCON - 0xE01F C080) The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
  • Page 72 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 9.4 PLL Status register (PLLSTAT - 0xE01F C088) The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in...
  • Page 73 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 67. PLL Control bit combinations PLLC PLLE PLL Function PLL is turned off and disconnected. The CCLK equals (system runs from) the unmodified clock input. The PLL is active, but not yet connected. The PLL can be connected after PLOCK is asserted.
  • Page 74 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 69. Elements determining PLL’s frequency Element Description CCLK the PLL output frequency (also the processor clock frequency) PLL Multiplier value from the MSEL bits in the PLLCFG register PLL Divider value from the PSEL bits in the PLLCFG register The PLL output frequency (when the PLL is both active and connected) is given by: CCLK = M ×...
  • Page 75 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 71. PLL Multiplier values MSEL Bits (PLLCFG bits [4:0]) Value of M 00000 00001 00010 00011 11110 11111 9.11 PLL configuring examples Example: System design asks for F = 10 MHz and requires CCLK = 60 MHz.
  • Page 76 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 72. Power control registers Name Description Access Reset Address value PCON Power Control Register. This register contains 0x00 0xE01F C0C0 control bits that enable the two reduced power operating modes of the microcontroller. See Table 6–73.
  • Page 77 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control Table 74. Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 78 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control 11. Reset Reset has two sources on the LPC21xx/LPC22xx: the RESET pin and Watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wakeup timer (see description in Section 6–13...
  • Page 79 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control sequencing DD(3V3) DD(1V8) (no sequencing requirements) oscillator starts valid clocks 0.5 ms oscillator DD(3V3) 3.0 V DD(1V8) 1.65 V reset boot time clock stability 1000 lock time time reset time boot jump to user code = 100 μs...
  • Page 80 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control reset to the external on-chip circuitry reset watchdog reset to reset PCON.PD WAKE-UP TIMER START power down COUNT 2 EINT0 wake-up oscillator output (F EINT1 wake-up EINT2 wake-up write “1” from APB...
  • Page 81 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control The connection of the APB Divider relative to the oscillator and the processor clock is shown in Figure 6–20. Because the APB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
  • Page 82 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control crystal oscillator or processor clock external clock source PLL0 (CCLK) APB clock APB DIVIDER (PCLK) Fig 20. APB divider connections 13. Wakeup timer On the LPC21xx/LPC22xx, the wakeup timer enforces a minimum reset duration based on the crystal oscillator and is activated whenever there is a wakeup from Power-down mode or any type of reset.
  • Page 83 UM10114 NXP Semiconductors Chapter 6: LPC21xx/22xx System control The pin multiplexing on the LPC21xx/LPC22xx (see Section 7–2, Section 7–3, and Section 8–6) allows peripherals that share pins with external interrupts to, in effect, bring the device out of Power-down mode. The following pin-function pairings allow interrupts...
  • Page 84 UM10114 Chapter 7: LPC21xx/22xx Pin configuration Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The pin configurations are identical for all 64-pin packages and all 144-pin packages with the exception of the CAN pins which depend on the CAN configuration for each part, see Table 7–77 Table 7–78.
  • Page 85 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration • LPC2194/01 • LPC2210/01, LPC2220 • LPC2212/01, LPC2214/01 • LPC2290/01 • LPC2292/01, LPC2294/01 For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 86 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 79. LPC21xx Pin description (64-pin packages) Symbol Type Description P0[0] to P0[31] Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block.
  • Page 87 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 79. LPC21xx Pin description (64-pin packages) …continued Symbol Type Description P0[12]/DSR1/ DSR1 — Data Set Ready input for UART1. MAT1[0]/RD4 MAT1[0] — Match output for Timer 1, channel 0. RD4 — CAN4 receiver input.
  • Page 88 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 79. LPC21xx Pin description (64-pin packages) …continued Symbol Type Description P0[22]/TD3/ TD3 — CAN3 transmitter output. CAP0[0]/MAT0[0] CAP0[0] — Capture input for Timer 0, channel 0. MAT0[0] — Match output for Timer 0, channel 0.
  • Page 89 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 79. LPC21xx Pin description (64-pin packages) …continued Symbol Type Description P1[25]/EXTIN0 External Trigger Input. Standard I/O with internal pull-up. P1[26]/RTCK Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies.
  • Page 90 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration 3. Pin configuration for 144-pin packages LPC22xx (1) Pin configuration is identical for devices with and without /00 and /01 suffixes. Fig 22. LQFP144 pinning ball A1 LPC22xx index area Transparent top view (1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
  • Page 91 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 80. LPC22xx Ball allocation Row Column P2[22]/ P1[28]/ P2[21]/ P2[18]/ P2[14]/ P1[29]/ P2[11]/ P2[10]/ P2[7]/D7 P2[4]/D4...
  • Page 92 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 80. LPC22xx Ball allocation …continued Row Column P0[29]/ P0[30]/ P1[16]/ P0[0]/ P3[19]/ P0[2]/ P3[15]/ P0[4]/ P3[12]/...
  • Page 93 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) Symbol Pin (LQFP) Pin (TFBGA) Type Description P0[0] to P0[31] Port 0: Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block.
  • Page 94 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description P0[10]/RTS1/ RTS1 — Request to Send output for UART1. CAP1[0] CAP1[0] — Capture input for Timer 1, channel 0.
  • Page 95 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description P0[20]/MAT1[3]/ MAT1[3] — Match output for Timer 1, channel 3. SSEL1/EINT3 SSEL1 — Slave Select for SPI1/SSP. Selects the SPI interface as a slave.
  • Page 96 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description P1[1]/OE OE — LOW-active Output Enable signal. P1[16]/ TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with TRACEPKT0 internal pull-up.
  • Page 97 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description P2[1]/D1 D1 — External memory data line 1. P2[2]/D2 D2 — External memory data line 2.
  • Page 98 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description P2[27]/D27/ D27 — External memory data line 27. BOOT1 BOOT1 — While RESET is low, together with BOOT0 controls booting and internal operation.
  • Page 99 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description P3[16]/A16 A16 — External memory address line 16. P3[17]/A17 A17 — External memory address line 17.
  • Page 100 UM10114 NXP Semiconductors Chapter 7: LPC21xx/22xx Pin configuration Table 81. LPC22xx Pin description (144 pin packages) …continued Symbol Pin (LQFP) Pin (TFBGA) Type Description Analog ground: 0 V reference. This should nominally be the same voltage as V , but should be isolated to minimize noise and error.
  • Page 101 UM10114 Chapter 8: LPC21xx/22xx Pin connect block Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The pin connect blocks are identical for all LPC21xx and LPC22xx parts, respectively. The LPC22xx use additional bits in the PINSEL2 register to select the EMC, additional ADC pins, and for boot control (see Table 8–83).
  • Page 102 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block 4. Description The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.
  • Page 103 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block Table 85. Pin connect block register map Name Description Access Reset value Address PINSEL0 Pin function select 0x0000 0000 0xE002 C000 register 0 PINSEL1 Pin function select 0x1540 0000 0xE002 C004...
  • Page 104 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block Table 86. Pin function Select register 0 (PINSEL0 - address 0xE002 C000) bit description ) Symbol Value Function Reset value 13:12 P0.6 GPIO Port 0.6 MOSI0 (SPI0) Capture 0.2 (Timer 0)
  • Page 105 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block 6.2 Pin function Select register 1 (PINSEL1 - 0xE002 C004) The PINSEL1 register controls the functions of the pins using the settings listed in Table 8–87. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin.
  • Page 106 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block Table 87. Pin function Select register 1 (PINSEL1 - address 0xE002 C004) bit description Symbol Value Function Reset value 17:16 P0.24 GPIO Port 0.24 TD2 (CAN2) Reserved Reserved 19:18 P0.25 GPIO Port 0.25...
  • Page 107 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block Table 88. Pin function Select register 2 (PINSEL2 - 0xE002 C014) bit description Symbol Value Function Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 108 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block Table 89. Pin function Select register 2 (PINSEL2 - 0xE002 C014) bit description Symbol Value Function Value after reset CTRLDBP Controls the use of the data bus and strobe pins. At a reset triggered via the BOOT1:0 or RESET pin, these bits are loaded with the content from lines BOOT1:0;...
  • Page 109 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block Table 89. Pin function Select register 2 (PINSEL2 - 0xE002 C014) bit description Symbol Value Function Value after reset 15:14 CTRLP325 Controls the use of pin P3.25: P3.25 is a GPIO pin.
  • Page 110 UM10114 NXP Semiconductors Chapter 8: LPC21xx/22xx Pin connect block 6.5 Boot control for LPC22xx parts The state of the BOOT1:0 pins (P2.26 and P2.27) while RESET is low controls booting and initial operation. Internal pull-up resistors in the receivers ensure high state if a pin is left unconnected.
  • Page 111 UM10114 Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Rev. 03 — 2 April 2008 User manual 1. How to read this chapter For port 0 and port 1 , the GPIO can be selected to be Fast GPIO or legacy GPIO (see Section 9–5).
  • Page 112 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 91. GPIO features Part Legacy I/O ports Fast GPIO ports Register base address Register base address 0xE002 8000 0xE002 8010 0xE002 8020 0xE002 8030 0x3FFF C000 0x3FFF C020...
  • Page 113 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller • Backward compatibility with other earlier devices is maintained with legacy registers appearing at the original addresses on the APB bus. 3. Applications • General purpose I/O • Driving LEDs, or other indicators •...
  • Page 114 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller The "slow", legacy registers are word accessible only. The “fast” GPIO registers are byte, half-word, and word accessible. UM10114_3 © NXP B.V. 2008. All rights reserved. User manual Rev. 03 — 2 April 2008...
  • Page 115 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 93. GPIO register map (legacy APB accessible registers) Generic Description Access Reset PORT0 PORT1 PORT2 PORT3 Name value Address & Address & Address & Address & Name Name...
  • Page 116 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 94. GPIO register map (local bus accessible registers - enhanced GPIO features) Generic Description Access Reset PORT0 PORT1 Name value Address & Name Address & Name FIOPIN Fast Port Pin value register using FIOMASK.
  • Page 117 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 97. GPIO port 2 Direction register (IO2DIR - address 0xE002 8028) bit description Symbol Value Description Reset value 31:0 P2xDIR Slow GPIO Direction control bits. Bit 0 in IO2DIR controls P2.0 ... Bit 31 in 0x0000 0000 IO2DIR controls P2.31.
  • Page 118 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 101. Fast GPIO port 0 Direction control byte and half-word accessible register description Register Register Address Description Reset name length (bits) value & access FIO0DIR3 8 (byte) 0x3FFF C003 Fast GPIO Port 0 Direction control register 3.
  • Page 119 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 104. GPIO port 1 output Set register (IO1SET - address 0xE002 8014) bit description Symbol Description Reset value 31:0 P1xSET Slow GPIO output value Set bits. Bit 0 in IO1SET corresponds to P1.0 ... Bit 31 0x0000 0000 in IO1SET corresponds to P1.31.
  • Page 120 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 110. Fast GPIO port 1 output Set byte and half-word accessible register description Register Register Address Description Reset name length (bits) value & access FIO1SET0 8 (byte) 0x3FFF C038 Fast GPIO Port 1 output Set register 0.
  • Page 121 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 114. GPIO port 3 output Clear register 3 (IO3CLR - address 0xE002 803C) bit description Symbol Description Reset value 31:0 P3xCLR Slow GPIO output value Clear bits. Bit 0 in IO3CLR corresponds to P1.0 ... Bit 0x0000 0000 31 in IO3CLR corresponds to P2.31.
  • Page 122 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 118. Fast GPIO port 1 output Clear byte and half-word accessible register description Register Register Address Description Reset name length (bits) value & access FIO1CLR3 8 (byte) 0x3FFF C03F Fast GPIO Port 1 output Clear register 3. Bit 0 in FIO1CLR3 register 0x00 corresponds to P1.24 ...
  • Page 123 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 121. GPIO port 2 Pin value register (IO2PIN - address 0xE002 8020) bit description Symbol Description Reset value 31:0 P2xVAL Slow GPIO pin value bits. Bit 0 in IO2PIN corresponds to P1.0 ... Bit 31 in IO2PIN corresponds to P2.31.
  • Page 124 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Table 126. Fast GPIO port 1 Pin value byte and half-word accessible register description Register Register Address Description Reset name length (bits) value & access FIO1PIN0 8 (byte) 0x3FFF C034 Fast GPIO Port 1 Pin value register 0.
  • Page 125 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–129 Table 9–130.
  • Page 126 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller IO0CLR = 0x0000 0080 ;P0.7 goes LOW IO0SET = 0x0000 0080 ;P0.7 goes HIGH IO0CLR = 0x0000 0080 ;P0.7 goes LOW pin P0.7 is configured as an output pin (write to IO0DIR register). Then, the P0.7 output pin is set to low (first write to IO0CLR register).
  • Page 127 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller contain 0s in bits corresponding to pins that will be changed, and 1s for all others. Finally, this result has to be logically ORred with the desired content and stored back into the IOPIN register.
  • Page 128 UM10114 NXP Semiconductors Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller Fig 24. Illustration of the fast and slow GPIO access and output showing 3.5 x increase of the pin output frequency UM10114_3 © NXP B.V. 2008. All rights reserved.
  • Page 129 UM10114 Chapter 10: LPC21xx/22xx Universal Asynchronous Receiver/Transmitter 0 (UART0) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The following features on the LPC21xx and LPC22xx are available in parts with enhanced features only: • Fractional baud rate controller •...
  • Page 130 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 131. LPC21xx/22xx part-specific registers Part Baud rate Auto-baud control Software flow control Section 10–4.3 Section Section Section 10–4.5 Section 10–4.6 Section 10–4.12 10–4.4 10–4.11 LPC2212 U0DLL U0DLM U0FDR U0ACR U0IER, bits 9:8...
  • Page 131 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 133. UART0 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...
  • Page 132 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous 4.1 UART0 Receiver Buffer register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.
  • Page 133 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous PCLK UARTn ------------------------------------------------------------------------------- - × × baudrate UnDLM UnDLL Details on how to select the right value for U0DLL and U0DLM if the part includes a fractional divider (see Table 10–131) can be found later on in this chapter.
  • Page 134 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous PCLK UARTn ---------------------------------------------------------------------------------------------------------------------------------- baudrate ⎛ ⎞ DivAddVal × × × ---------------------------- - UnDLM UnDLL ⎝ ⎠ MulVal Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate generator specific parameters.
  • Page 135 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
  • Page 136 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 139. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
  • Page 137 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 140. UART0 Interrupt Enable Register (U0IER - address 0xE000 C004, when DLAB = 0) bit description Symbol Value Description Reset value U0IER[0] enables the Receive Data Available interrupt Interrupt for UART0. It also controls the Character Receive Enable Time-out interrupt.
  • Page 138 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 141: UART0 Interrupt Identification Register (U0IIR - address 0xE000 C008, read only) bit description Symbol Value Description Reset value Interrupt U0IER[3:1] identifies an interrupt corresponding to the Identification UART0 Rx FIFO. All other combinations of U0IER[3:1] not listed above are reserved (000,100,101,111).
  • Page 139 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 142: UART0 interrupt handling U0IIR[3:0] Priority Interrupt Type Interrupt Source Interrupt Reset value 0001 None None 0110 Highest RX Line Status / Error OE or PE or FE or BI U0LSR Read...
  • Page 140 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 143: UART0 FIFO Control Register (U0FCR - address 0xE000 C008) bit description Symbol Value Description Reset value RX FIFO No impact on either of UART0 FIFOs. Reset Writing a logic 1 to U0FCR[1] will clear all bytes in UART0 Rx FIFO and reset the pointer logic.
  • Page 141 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous 4.9 UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only) The U0LSR is a read-only register that provides status information on the UART0 TX and RX blocks. Table 145: UART0 Line Status Register (U0LSR - address 0xE000 C014, read only) bit description...
  • Page 142 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 145: UART0 Line Status Register (U0LSR - address 0xE000 C014, read only) bit description Bit Symbol Value Description Reset value Transmitter TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when Empty either the U0TSR or the U0THR contain valid data.
  • Page 143 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 147: Auto-baud Control Register (U0ACR - 0xE000 C020) bit description Symbol Value Description Reset value ABEOIntClr End of auto-baud interrupt clear bit (write only accessible). Writing a 1 will clear the corresponding interrupt in the U0IIR.
  • Page 144 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous × CLK PCLK ≤ ≤ ratemin ------------------------ - ----------------------------------------------------------------------------------------------------------- - UART0 baudrate ratemax × 16 2 15 databits paritybits stopbits × 4.11.2 Auto-baud modes When the software is expecting an ”AT" command, it configures the UART0 with the expected character format and sets the U0ACR Start bit.
  • Page 145 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UART0 RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
  • Page 146 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous Table 148: UART0 Transmit Enable Register (U0TER - address 0xE000 C030) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 147 UM10114 NXP Semiconductors Chapter 10: LPC21xx/22xx Universal Asynchronous U0TX NTXRDY TXD0 U0THR U0TSR U0BRG U0DLL NBAUDOUT U0DLM RCLK U0RX NRXRDY INTERRUPT RXD0 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 27. UART0 block diagram UM10114_3 ©...
  • Page 148 UM10114 Chapter 11: LPC21xx/22xx Universal Asynchronous Receiver/Transmitter 1 (UART1) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The following features on the LPC21xx and LPC22xx are available in parts with enhanced features only: • Fractional baud rate controller •...
  • Page 149 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 149. LPC21xx/22xx part-specific registers Part Baud rate Auto-baud control Software flow control Section 11–4.3 Section Section Section 11–4.5 Section 11–4.6 Section 11–4.16 11–4.4 11–4.13 LPC2212 U1DLL U1DLM U1FDR U1ACR U1IER, bits 9:8...
  • Page 150 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 150. UART1 pin description Type Description DTR1 Output Data Terminal Ready. Active LOW signal indicates that the UART1 is ready to establish connection with external modem. The complement value of this signal is stored in U1MCR[0].
  • Page 151 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 151. UART1 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...
  • Page 152 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous 4.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface.
  • Page 153 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous PCLK UARTn ------------------------------------------------------------------------------- - × × baudrate UnDLM UnDLL Details on how to select the right value for U1DLL and U1DLM if the part includes a fractional divider (see Table 11–149) can be found later on in this chapter.
  • Page 154 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous PCLK UARTn ---------------------------------------------------------------------------------------------------------------------------------- baudrate ⎛ ⎞ DivAddVal × × × ---------------------------- - UnDLM UnDLL ⎝ ⎠ MulVal Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baudrate generator specific parameters.
  • Page 155 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
  • Page 156 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 157. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
  • Page 157 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 158. UART1 Interrupt Enable Register (U1IER - address 0xE001 0004, when DLAB = 0) bit description Symbol Value Description Reset value U1IER[0] enables the Receive Data Available Interrupt interrupt for UART1. It also controls the Character Enable Receive Time-out interrupt.
  • Page 158 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous 4.6 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only) The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access.
  • Page 159 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below the trigger level.
  • Page 160 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous immediately if the UART1 THR FIFO has held two or more characters at one time and currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
  • Page 161 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 162. UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description Symbol Value Description Reset value Parity Enable Disable parity generation and checking. Enable parity generation and checking. Parity Select Odd parity.
  • Page 162 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 163. UART1 Modem Control Register (U1MCR - address 0xE001 0010) bit description Symbol Value Description Reset value CTSen Auto-CTS control bit. Disable auto-CTS flow control. Enable auto-CTS flow control. 4.9.1 Auto-flow control If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1...
  • Page 163 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous transmitter from sending the following byte, CTS1 must be released before the middle of the last stop bit that is currently being sent. In auto-CTS mode a change of the CTS1 signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set, Delta CTS bit in the U1MSR will be set though.
  • Page 164 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 165. UART1 Line Status Register (U1LSR - address 0xE001 0014, read only) bit description Bit Symbol Value Description Reset value Receiver Data U1LSR[0] is set when the U1RBR holds an unread character and is cleared when Ready the UART1 RBR FIFO is empty.
  • Page 165 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 165. UART1 Line Status Register (U1LSR - address 0xE001 0014, read only) bit description Bit Symbol Value Description Reset value Error in RX U1LSR[7] is set when a character with a RX error such as framing error, parity error FIFO or break interrupt, is loaded into the U1RBR.
  • Page 166 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous 4.13 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020) The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion.
  • Page 167 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin.
  • Page 168 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous 6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the remaining bits of the ”A/a"...
  • Page 169 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous Table 169. UART1 Transmit Enable Register (U1TER - address 0xE001 0030) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 170 UM10114 NXP Semiconductors Chapter 11: LPC21xx/22xx Universal Asynchronous MODEM U1TX NTXRDY TXD1 U1THR U1TSR U1MSR U1BRG U1DLL NBAUDOUT U1MCR U1DLM RCLK U1RX NRXRDY INTERRUPT RXD1 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS...
  • Page 171 UM10114 Chapter 12: LPC21xx/22xx I C interface Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The I C-bus interface is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 172 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface The LPC21xx/22xx I C interface is byte oriented, and have four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode. The I C interface complies with entire I...
  • Page 173 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 6.1 Master Transmitter mode In this mode data is transmitted from master to slave. Before the master transmitter mode can be entered, the I2CONSET register must be initialized as shown in Table 12–171.
  • Page 174 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 6.2 Master Receiver mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition...
  • Page 175 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface I2EN must be set to 1 to enable the I C function. AA bit must be set to 1 to acknowledge its own slave address or the general call address. The STA, STO and SI bits are set to 0.
  • Page 176 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 7. I C Implementation and operation Figure 12–39 shows how the on-chip I2C-bus interface is implemented, and the following text describes the individual blocks. 7.1 Input filters and output stages Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out.
  • Page 177 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface ADDRESS REGISTER I2ADR COMPARATOR INPUT FILTER OUTPUT SHIFT REGISTER STAGE I2DAT BIT COUNTER/ ARBITRATION & SYNC LOGIC PCLK INPUT TIMING & FILTER CONTROL LOGIC interrupt OUTPUT SERIAL CLOCK STAGE GENERATOR I2CONSET CONTROL REGISTER &...
  • Page 178 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 7.2 Address Register, I2ADDR This register may be loaded with the 7-bit slave address (7 most significant bits) to which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (0x00) recognition.
  • Page 179 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface SDA line SCL line high period period Fig 41. Serial clock synchronization A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer.
  • Page 180 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface four modes of the I C block are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software.
  • Page 181 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 174. I C Control Set register (I2CONSET - address 0xE001 C000) bit description Bit Symbol Description Reset value 1:0 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 182 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface SI is the I C Interrupt Flag. This bit is set when the I C state changes. However, entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case.
  • Page 183 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET register. Writing 0 has no effect. I2ENC is the I C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the I2CONSET register.
  • Page 184 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 8.7 I C SCL Low duty cycle register (I2SCLL - 0xE001 C014) Table 180. I C SCL Low Duty Cycle register (I2SCLL - address 0xE001 C014) bit description Symbol Description Reset value...
  • Page 185 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface • Slave Transmitter Data transfers in each mode of operation are shown in Figures to 46. Table 12–182 lists abbreviations used in these figures when describing the I C operating modes.
  • Page 186 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
  • Page 187 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface action to be taken for each of these status codes is detailed in Table 104. The slave receiver mode may also be entered if arbitration is lost while the I C block is in the master mode (see status 0x68 and 0x78).
  • Page 188 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR...
  • Page 189 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
  • Page 190 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
  • Page 191 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface reception of the own Slave address and one or more Data DATA DATA P OR S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted.
  • Page 192 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 186. Master Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
  • Page 193 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 187. Master Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
  • Page 194 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 188. Slave Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
  • Page 195 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 188. Slave Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
  • Page 196 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 189. Slave Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
  • Page 197 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 9.5 Miscellaneous States There are two I2STAT codes that do not correspond to a defined I C hardware state (see Table 12–190). These are discussed below. 9.6 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set.
  • Page 198 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface Table 190. Miscellaneous States Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
  • Page 199 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I C-bus stays busy indefinitely. If the STA flag is set and bus access is not...
  • Page 200 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface time limit STA flag STO flag SDA line SCL line start condition Fig 47. Forced access to a busy I C-bus STA flag SDA line SCL line start condition Fig 48. Recovering from a bus obstruction caused by a low level on SDA 9.14 I...
  • Page 201 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface The I C hardware now begins checking the I C-bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information.
  • Page 202 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 1. Initialize Master data counter. 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit.
  • Page 203 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer.
  • Page 204 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.15 State: 0x38 Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered.
  • Page 205 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 8. Exit 10.20 State: 0x58 Data has been received, NOT ACK has been returned. Data will be read from I2DAT. A Stop condition will be transmitted. 1. Read data byte from I2DAT into Master Receive buffer.
  • Page 206 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 10.25 State: 0x78 Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been received and ACK has been returned. Data will be received and ACK returned. STA is set to restart Master mode after the bus is free again.
  • Page 207 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 10.29 State: 0x98 Previously addressed with general call. Data has been received, NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit.
  • Page 208 UM10114 NXP Semiconductors Chapter 12: LPC21xx/22xx I C interface 1. Load I2DAT from Slave Transmit buffer with data byte. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Increment Slave Transmit buffer pointer.
  • Page 209 UM10114 Chapter 13: LPC21xx/22xx SPI Rev. 03 — 2 April 2008 User manual 1. How to read this chapter All LPC21xx and all LPC22xx have by default two SPI interfaces SPI0 and SPI1. Remark: For enhanced parts only, the SPI1 interface can be selected as an SSP interface using the same pins as SPI1 (see Section 14–1).
  • Page 210 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI 2. Features • Two complete and independent SPI controllers • Compliant with Serial Peripheral Interface (SPI) specification • Synchronous, serial, and full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate •...
  • Page 211 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8...
  • Page 212 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI When a device is a slave, and CPHA is set to 0, the transfer starts when the SSEL signal goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on the last clock edge where data is sampled.
  • Page 213 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI 6. Read the received data from the SPI data register (optional). 7. Go to step 3 if more data is required to transmit. Note: A read or write of the SPI data register is required in order to clear the SPIF status bit.
  • Page 214 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI 3.3.4.3 Mode fault The SSEL signal must always be inactive when the SPI block is a master. If the SSEL signal goes active, when the SPI block is a master, this indicates another master has selected the device to be a slave.
  • Page 215 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI Table 194. SPI register map Name Description Access Reset SPI0 SPI1 value Address & Address & name name SPCR SPI Control Register. This register 0x0000 0xE002 0000 0xE003 0000 controls the operation of the SPI.
  • Page 216 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI Table 195. SPI Control Register (S0SPCR - address 0xE002 0000 and S1SPCR - address 0xE003 0000) bit description Symbol Value Description Reset value MSTR Master mode select. The SPI operates in Slave mode.
  • Page 217 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI Table 196. SPI Status Register (S0SPSR - address 0xE002 0004 and S1SPSR - address 0xE003 0004) bit description Symbol Description Reset value ROVR Read overrun. When 1, this bit indicates that a read overrun has occurred.
  • Page 218 UM10114 NXP Semiconductors Chapter 13: LPC21xx/22xx SPI Table 199. SPI Interrupt Register (S0SPINT - address 0xE002 001C and S1SPINT - address 0xE003 001C) bit description Bit Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 219 UM10114 Chapter 14: LPC21xx/22xx SSP interface Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The SSP interface is available on the following parts: • LPC2109/01, LPC2119/01, LPC2129/01 • LPC2114/01, LPC2124/01 • LPC2194/01 • LPC2210/01, LPC2220 •...
  • Page 220 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface To switch on the fly from SPI1 to SSP and back, first disable the active peripheral’s interrupt(s), both in the peripheral’s and VIC’s registers. Next, clear all pending interrupt flags (if any set). Only then, the currently enabled peripheral can be turned off in the PCONP register.
  • Page 221 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface 4. Bus description 4.1 Texas Instruments synchronous serial frame format Figure 14–51 shows the 4-wire Texas Instruments synchronous serial frame format supported by the SSP module. DX/DR 4 to 16 bits a. Single frame transfer...
  • Page 222 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface 4.2.1 Clock Polarity (CPOL) and Phase (CPHA) Control When the CPOL clock polarity control bit is LOW, it produces a steady state low value on the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is placed on the CLK pin when data is not being transferred.
  • Page 223 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface One half SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SCK master clock pin goes HIGH after one further half SCK period.
  • Page 224 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. 4.2.4 SPI format with CPOL = 1,CPHA = 0...
  • Page 225 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero.
  • Page 226 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface 8 bit control 4 to 16 bits output data Fig 56. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device.
  • Page 227 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface 8 bit control 4 to 16 bits 4 to 16 bits output data output data Fig 57. Microwire frame format (continuos transfers) 4.3.1 Setup and hold time requirements on CS with respect to SK in Microwire...
  • Page 228 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface Table 201. SSP Registers Name Description Access Reset value Address SSPCR0 Control Register 0. Selects the serial clock 0x0000 0xE005 C000 rate, bus type, and data size. SSPCR1 Control Register 1. Selects master/slave...
  • Page 229 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface Table 202: SSP Control Register 0 (SSPCR0 - address 0xE005 C000) bit description Symbol Value Description Reset value CPOL Clock Out Polarity. This bit is only used in SPI mode. SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.
  • Page 230 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface 5.3 SSP Data Register (SSPDR - 0xE005 C008) Software can write data to be transmitted to this register, and read data that has been received. Table 204: SSP Data Register (SSPDR - address 0xE005 C008) bit description...
  • Page 231 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the peripheral clock. The content of the SSPCPSR register is not relevant. In master mode, CPSDVSR = 2 or larger (even numbers only).
  • Page 232 UM10114 NXP Semiconductors Chapter 14: LPC21xx/22xx SSP interface 5.8 SSP Masked Interrupt Register (SSPMIS - 0xE005 C01C) This read-only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPIMSC. When an SSP interrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt.
  • Page 233 UM10114 Chapter 15: LPC21xx/22xx Timer 0/1 Rev. 03 — 2 April 2008 User manual 1. How to read this chapter Remark: External event counting on the capture inputs can be selected for LPC21xx/01, LPC22xx/01, and LPC2220 parts only. External event counting uses the TnCTCTR registers.
  • Page 234 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 – Set high on match. – Toggle on match. – Do nothing on match. 3. Applications • Interval Timer for counting internal events. • Pulse Width Demodulator via Capture inputs. • Free running timer.
  • Page 235 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 212. Timer/Counter pin description Type Description CAP0.3..0 Input Capture Signals- A transition on a capture pin can be configured to CAP1.3..0 load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt.
  • Page 236 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 213. TIMER/COUNTER0 and TIMER/COUNTER1 register map Generic Description Access Reset TIMER/ TIMER/ Name value COUNTER0 COUNTER1 Address & Name Address & Name Interrupt Register. The IR can be written to clear...
  • Page 237 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 213. TIMER/COUNTER0 and TIMER/COUNTER1 register map Generic Description Access Reset TIMER/ TIMER/ Name value COUNTER0 COUNTER1 Address & Name Address & Name Capture Register 3. See CR0 description. 0xE000 4038 0xE000 8038...
  • Page 238 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 215: Timer Control Register (TCR, TIMER0: T0TCR - address 0xE000 4004 and TIMER1: T1TCR - address 0xE000 8004) bit description Symbol Description Reset value Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting.
  • Page 239 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 216: Count Control Register (CTCR, TIMER0: T0CTCR - address 0xE000 4070 and TIMER1: T1TCR - address 0xE000 8070) bit description Symbol Value Description Reset value Count When bits 1:0 in this register are not 00, these bits select...
  • Page 240 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 6.8 Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 and TIMER1: T1MCR - 0xE000 8014) The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown Table 15–217.
  • Page 241 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 6.9 Capture Registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture...
  • Page 242 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 218: Capture Control Register (CCR, TIMER0: T0CCR - address 0xE000 4028 and TIMER1: T1CCR - address 0xE000 8028) bit description Symbol Value Description Reset value CAP3RE 1 Capture on CAPn.3 rising edge: a sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC.
  • Page 243 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 Table 219: External Match Register (EMR, TIMER0: T0EMR - address 0xE000 403C and TIMER1: T1EMR - address0xE000 803C) bit description Symbol Description Reset value EMC2 External Match Control 2. Determines the functionality of External Match 2.
  • Page 244 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 PCLK prescale counter timer counter TCR[0] (counter enable) interrupt Fig 60. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled 8. Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 15–61.
  • Page 245 UM10114 NXP Semiconductors Chapter 15: LPC21xx/22xx Timer 0/1 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0] INTERRUPT CAP[3:0] STOP ON MATCH RESET ON MATCH LOAD[3:0] CAPTURE CONTROL REGISTER...
  • Page 246 UM10114 Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The PWM controller is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 247 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) includes four capture inputs to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. The PWM function is in addition to these features, and is based on match register events.
  • Page 248 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) SHADOW REGISTER 0 MATCH REGISTER 0 LOAD ENABLE MATCH REGISTER 1 SHADOW REGISTER 1 LOAD ENABLE SHADOW REGISTER 2 MATCH REGISTER 2 LOAD ENABLE SHADOW REGISTER 3 MATCH REGISTER 3...
  • Page 249 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) implementation supports up to N-1 single edge PWM outputs or (N-1)/2 double edge PWM outputs, where N is the number of match registers that are implemented. PWM types can be mixed if desired.
  • Page 250 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) 2. Each PWM output will go low when its match value is reached. If no match occurs (i.e. the match value is greater than the PWM rate), the PWM output remains continuously high.
  • Page 251 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 223. Pulse Width Modulator Register Map Name Description Access Reset Address value PWMIR PWM Interrupt Register. The PWMIR can be 0xE001 4000 written to clear interrupts. The PWMIR can be read to identify which of the possible interrupt sources are pending.
  • Page 252 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 223. Pulse Width Modulator Register Map Name Description Access Reset Address value PWMMR3 PWM Match Register 3. PWMMR3 can be enabled 0xE001 4024 through PWMMCR to reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate an interrupt when it matches the PWMTC.
  • Page 253 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 224: PWM Interrupt Register (PWMIR - address 0xE001 4000) bit description Symbol Description Reset value PWMMR3 Interrupt Interrupt flag for PWM match channel 3. Reserved, user software should not write ones to 0000 reserved bits.
  • Page 254 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) 5.3 PWM Timer Counter (PWMTC - 0xE001 4008) The 32-bit PWM Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching its upper limit, the PWMTC will count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
  • Page 255 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 226: Match Control Register (MCR, TIMER0: T0MCR - address 0xE000 4014 and TIMER1: T1MCR - address 0xE000 8014) bit description Symbol Value Description Reset Value PWMMR1I Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC.
  • Page 256 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 226: Match Control Register (MCR, TIMER0: T0MCR - address 0xE000 4014 and TIMER1: T1MCR - address 0xE000 8014) bit description Symbol Value Description Reset Value PWMMR5R Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.
  • Page 257 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 227: PWM Control Register (PWMPCR - address 0xE001 404C) bit description Bit Symbol Valu Description Reset Value PWMENA2 1 The PWM2 output enabled. The PWM2 output disabled. PWMENA3 1 The PWM3 output enabled.
  • Page 258 UM10114 NXP Semiconductors Chapter 16: LPC21xx/22xx Pulse Width Modulator (PWM) Table 228: PWM Latch Enable Register (PWMLER - address 0xE001 4050) bit description Symbol Description Reset value Enable PWM Writing a one to this bit allows the last value written to the...
  • Page 259 UM10114 Chapter 17: LPC21xx/22xx WatchDog Timer (WDT) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The WDT is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 260 UM10114 NXP Semiconductors Chapter 17: LPC21xx/22xx WatchDog Timer (WDT) When the Watchdog counter underflows, the program counter will start from 0x0000 0000 as in the case of external reset. The Watchdog Time-Out Flag (WDTOF) can be examined to determine if the watchdog has caused the reset condition. The WDTOF flag must be cleared by software.
  • Page 261 UM10114 NXP Semiconductors Chapter 17: LPC21xx/22xx WatchDog Timer (WDT) Table 231: Watchdog Mode register (WDMOD - address 0xE000 0000) bit description Symbol Description Reset value WDEN WDEN Watchdog interrupt Enable bit (Set Only). WDRESET WDRESET Watchdog Reset Enable bit (Set Only).
  • Page 262 UM10114 NXP Semiconductors Chapter 17: LPC21xx/22xx WatchDog Timer (WDT) 6. Block diagram The block diagram of the Watchdog is shown below in the Figure 17–64. WDTC feed sequence feed error feed ok WDFEED 32 BIT DOWN underflow PCLK COUNTER enable...
  • Page 263 UM10114 Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The RTC is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 264 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) 4. Architecture PCLK CLK32k REFERENCE CLOCK DIVIDER (PRESCALER) CLOCK GENERATOR strobe CLK1 CCLK ALARM TIME COUNTERS COMPARATORS REGISTERS COUNTER INCREMENT ALARM MASK counter enables INTERRUPT ENABLE REGISTER INTERRUPT GENERATOR Fig 65. RTC block diagram 5.
  • Page 265 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 235. Real Time Clock (RTC) register map Name Size Description Access Reset Address value Seconds Counter 0xE002 4020 Minutes Register 0xE002 4024 HOUR Hours Register 0xE002 4028 Day of Month Register...
  • Page 266 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 236. Miscellaneous registers Name Size Description Access Address Interrupt Location. Reading this location 0xE002 4000 indicates the source of an interrupt. Writing a one to the appropriate bit at this location clears the associated interrupt.
  • Page 267 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) 5.5 Clock Control Register (CCR - 0xE002 4008) The clock register is a 5-bit register that controls the operation of the clock divide circuit. Each bit of the clock register is described in Table 18–239.
  • Page 268 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 241: Alarm Mask Register (AMR - address 0xE002 4010) bit description Symbol Description Reset value AMRSEC When 1, the Second value is not compared for the alarm. AMRMIN When 1, the Minutes value is not compared for the alarm.
  • Page 269 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 243: Consolidated Time register 1 (CTIME1 - address 0xE002 4018) bit description Symbol Description Reset value Day of Month Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
  • Page 270 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 246. Time counter registers Name Size Description Access Address Day of month value in the range of 1 to 28, 29, 30, 0xE002 402C or 31 (depending on the month and whether it is a leap year).
  • Page 271 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) No provision is made in the LPC21xx/LPC22xx to retain RTC status upon power loss, or to maintain time incrementation if the clock source is lost, interrupted, or altered. Loss of chip power will result in complete loss of all RTC register contents. Entry to Power Down mode will cause a lapse in the time update.
  • Page 272 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 250: Prescaler Integer register (PREFRAC - address 0xE002 4084) bit description Symbol Description Reset value 14:0 Prescaler Contains the integer portion of the RTC prescaler value. Fraction Reserved, user software should not write ones to reserved bits.
  • Page 273 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) PCLK to clock tick counter (APB clock) UNDERFLOW 15 BIT FRACTION COUNTER 13 BIT INTEGER COUNTER (DOWN COUNTER) RELOAD COMBINATORIAL LOGIC extend reload 13 BIT RELOAD INTEGER 15 BIT FRACTION REGISTER...
  • Page 274 UM10114 NXP Semiconductors Chapter 18: LPC21xx/22xx Real-Time Clock (RTC) Table 251. Prescaler cases where the Integer Counter reload value is incremented Fraction Counter PREFRAC Bit 14 13 12 11 10 9 --- ---- ---- ---1 --- ---- ---- --10 --- ---- ---- -100...
  • Page 275 UM10114 Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The following chapter only applies to parts with CAN controllers. The register descriptions are given for the full set of CAN controllers. The LPC21xx and LPC22xx have different CAN configurations depending on part number and version.
  • Page 276 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 2. CAN controllers The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high speed networks to low cost multiplex wiring.
  • Page 277 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 254. Memory map of the CAN block Address Range Used for 0xE004 8000 - 0xE004 805F CAN Controller 2 Registers 0xE004 C000 - 0xE004 C05F CAN Controller 3 Registers...
  • Page 278 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 256. CAN1, CAN2, CAN3, CAN4 controller register map Generic Description Access CAN1 CAN2 CAN3 CAN4 Register Address & Address & Address & Address & Name Name Name Name...
  • Page 279 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter while hardware reset sets RM, in this case the setting noted in the “Reset Value” column prevails over that shown in the “RM Set” column, in the few bits where they differ. In both columns, X indicates the bit or field is unchanged.
  • Page 280 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 6.2 Command Register (CMR: CAN1CMR- 0xE004 4004, CAN2CMR - 0xE004 8004, CAN3CMR - 0x004 C004, CAN4CMR - 0x005 0004) Writing to this write-only register initiates an action. Bits not listed should be written as 0.
  • Page 281 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 259. Global Status Register (GSR: CAN1GSR - address 0xE004 0008, CAN2GSR - address 0xE004 8008, CAN3GSR - address 0xE004 C008, CAN4GSR address 0xE005 0008) bit description Symbol Value...
  • Page 282 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 6.4 Interrupt and Capture Register (ICR: CAN1ICR- 0xE004 400C, CAN2ICR - 0xE004 800C, CAN3ICR - 0xE004 C00C, CAN4ICR - 0xE005 000C) Bits in this register indicate information about events on the CAN bus. This register is read-only.
  • Page 283 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 260. Interrupt and Capture register (ICR: CR: CAN1ICR- address 0xE004 400C, CAN2ICR - 0xE004 address 800C, CAN3ICR - address 0xE004 C00C, CAN4ICR - address 0xE005 000C) bit description...
  • Page 284 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 260. Interrupt and Capture register (ICR: CR: CAN1ICR- address 0xE004 400C, CAN2ICR - 0xE004 address 800C, CAN3ICR - address 0xE004 C00C, CAN4ICR - address 0xE005 000C) bit description...
  • Page 285 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 6.6 Bus Timing Register (BTR: CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014, CAN3BTR - 0xE004 C014, CAN4BTR - 0xE005 0014) This register controls how various CAN timings are derived from the VPB clock. It can be read at any time, but can only be written if the RM bit in CANmod is 1.
  • Page 286 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 6.8 Status Register (SR - CAN1SR 0xE004 401C, CAN2SR - 0xE004 801C, CAN3SR - 0xE004 C01C, CAN4SR - 0xE005 001C) This register contains three status bytes, in which the bits not related to transmission are identical to the corresponding bits in the Global Status Register, while those relating to transmission reflect the status of each of the 3 Tx Buffers.
  • Page 287 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 265. Receive Frame Status register (RFS - CAN1RFS - address 0xE004 4020, CAN2RFS - address 0xE004 8020, CAN3RFS - address 0xE004 C020, CAN4RFS - address 0xE005 0020) bit description...
  • Page 288 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 267. Receive Identifier register when FF = 1 Symbol Function Reset Value RM Set 28:0 The 29 bit Identifier field of the current received message. In CAN 2.0B these bits are called ID29-0.
  • Page 289 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 6.13 Transmit Frame Information register (TFI1, 2, 3 - CAN1TF1n - 0xE004 4030, 40, 50; CAN2TFIn - 0xE004 8030, 40, 50; CAN3TFIn - 0xE004 C030, 40, 50; CAN4TFIn - 0xE005 0030, 40, 50) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the format of the next transmit message for that Tx buffer.
  • Page 290 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 271. Transfer Identifier register when FF=0 (TID1, 2, 3: CAN1TIDn - addresses 0xE004 4034, 44, 54; CAN2TIDn - addresses 0xE004 8034, 44, 54; CAN3TIDn - addresses 0xE004 C034, 44, 54; CAN4TIDn - addresses 0xE005 0034, 44, 54) bit...
  • Page 291 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter Table 274. Transmit Data register B (TDB1, 2, 3: CAN1TDBn - addresses 0xE004 403C, 4C, 5C; CAN2TDBn - addresses 0xE004 803C, 4C, 5C; CAN3TDBn - addresses 0xE004 C03C, 4C, 5C; CAN4TDBn - addresses 0xE005 003C, 4C, 5C) bit description...
  • Page 292 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 7.3 Interrupts Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each Receive and Transmit interrupt request from each controller is assigned its own channel in the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine.
  • Page 293 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 8.2 Central Receive Status Register (CANRxSR - 0xE004 0004) Table 276. Central Receive Status register (CANRxSR - address 0xE004 0004) bit description Symbol Description Reset Value RS4:1 1: the CAN controller CAN4:1 is receiving a message (same as RS in CANGSR).
  • Page 294 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter If Standard (11 bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty. If the optional “fullCAN mode” is enabled, the first table contains Standard identifiers for which reception is to be handled in this mode.
  • Page 295 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 29 28 CONTROLLER # IDENTIFIER Fig 69. Entry in either extended identifier table The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table.
  • Page 296 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 10. Acceptance filter registers 10.1 Acceptance Filter Mode Register (AFMR - 0xE003 C000) Table 278. Acceptance Filter Mode Register (AFMR - address 0xE003 C000) bit description Symbol Valu Description...
  • Page 297 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 10.3 Standard Frame Group Start Address Register (SFF_GRP_sa - 0xE003 C008) Table 280. Standard Frame Group Start Address register (SFF_GRP_sa - address 0xE003 C008) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits.
  • Page 298 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 10.6 End of AF Tables register (ENDofTable - 0xE003 C014) Table 283. End of AF Tables register (ENDofTable - address 0xE003 C014) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 299 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 11. Examples of acceptance filter tables and ID index values Suppose that the five Acceptance Filter address registers contain the values shown in the third column below. In this case each table contains the decimal number of words and...
  • Page 300 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter 000 d := 000 h := 0 0000 0000 b SFF_sa look-up table RAM ID index # VPB base + column_lower column_upper address 00d = 00h 04d = 04h...
  • Page 301 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter • The Standard Frame Individual Start Address Register (SFF_sa) must be greater than or equal to the number of IDs for which automatic receive storage is to be done, times two.
  • Page 302 UM10114 NXP Semiconductors Chapter 19: LPC21xx/22xx CAN controller and acceptance filter START read 1st word SEM == 01? this message has not been SEM == 11? received since last check clear SEM, write back 1 st word read 2nd and 3rd words...
  • Page 303 UM10114 Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter Remark: The LPC21xx and LPC22xx contain different ADC features depending on part number and version. The registers and their addresses that are available in select parts only are shown in Table 20–288.
  • Page 304 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) 2. Features • 10 bit successive approximation analog to digital converter • Input multiplexing among 4 pins or 8 pins • Power-down mode • Measurement range 0 V to V 10 bit conversion time ≥ 2.44 μs (400,000 conversions per second) •...
  • Page 305 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) Table 290. ADC registers Name Description Access Reset Address value ADCR ADC Control Register. The ADCR register must be written to select 0x0000 0001 0xE003 4000 the operating mode before ADC conversion can occur.
  • Page 306 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) 5.1 ADC Control Register (ADCR - 0xE003 4000) Table 291. ADC Control Register (ADCR - address 0xE003 4000) bit description Symbol Value Description Reset value Selects which of the ADC pins is (are) to be sampled and converted. Bit 0 selects Pin 0x01 AIN0, and bit 7 selects pin AIN7.
  • Page 307 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) Table 291. ADC Control Register (ADCR - address 0xE003 4000) bit description Symbol Value Description Reset value 26:24 START When the BURST bit is 0, these bits control whether and when an ADC conversion is started: No start (this value should be used when clearing PDN to 0).
  • Page 308 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) 5.3 ADC Status Register (ADSTAT - 0xE003 4004) The ADC Status register allows checking the status of all ADC channels simultaneously. The DONE and OVERRUN flags appearing in the ADDRn register for each ADC channel are mirrored in ADSTAT.
  • Page 309 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) Table 294. ADC Interrupt Enable Register (ADINTEN - address 0xE003 400C) bit description Symbol Value Description Reset value ADINTEN3 Completion of a conversion on ADC channel 3 will not generate an interrupt.
  • Page 310 UM10114 NXP Semiconductors Chapter 20: LPC21xx/22xx Analog-to-Digital Converter (ADC) on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection logic.
  • Page 311 UM10114 Chapter 21: LPC21xx/22xx Flash memory controller Rev. 03 — 2 April 2008 User manual 1. How to read this chapter Read this chapter for LPC21xx and LPC2xx parts with on-chip flash memory. Table 296. LPC21xx and LPC22xx flash memory options Part Flash size no suffix, /00, and /01 parts...
  • Page 312 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 4. Applications The flash boot loader provides both In-System and In-Application programming interfaces for programming the on-chip flash memory. 5. Description The flash boot loader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or the user application code.
  • Page 313 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 0x7FFF FFFF 2.0 GB 8 kB BOOT BLOCK (RE-MAPPED FROM TOP OF FLASH MEMORY) (BOOT BLOCK INTERRUPT VECTORS) 2.0 GB - 8 kB 0x7FFF E000 0x0003 FFFF 8 kB BOOT BLOCK RE-MAPPED TO...
  • Page 314 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller Once the crystal frequency is received the part is initialized and the ISP command handler is invoked. For safety reasons an "Unlock" command is required before executing the commands resulting in flash erase/write operations and the "Go" command. The rest of the commands can be executed without the unlock command.
  • Page 315 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 5.10 Interrupts during IAP The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active.
  • Page 316 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 5.14 Boot process flowchart RESET INITIALIZE ENABLED? ENABLE DEBUG WATCHDOG FLAG SET? BOOT EXTERNAL? CRP3 ENABLED? with external USER CODE memory VALID? ENABLED? EXECUTE INTERNAL EXECUTE EXTERNAL Enter ISP USER CODE...
  • Page 317 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 6. Sector numbers Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicates the correspondence between sector numbers and memory addresses for LPC21xx/LPC22xx devices containing 64 kB, 128 kB, or 256 kB of flash respectively.
  • Page 318 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 7. Flash content protection mechanism The LPC21xx/LPC22xx is equipped with the Error Correction Code (ECC) capable flash memory. The purpose of an error correction module is twofold. Firstly, it decodes data words read from the memory into output data words.
  • Page 319 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller Table 298. Code Read Protection levels Name Pattern Description programmed in 0x000001FC CRP1 0x12345678 Access to chip via the JTAG pins is disabled. This mode allows partial Flash update using the following ISP commands and restrictions: •...
  • Page 320 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller In case a CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED. 8.1 Bootloader options The levels of code read protection implemented depend on the boot loader code version.The following options can be selected by the user in various revisions of the...
  • Page 321 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 9. ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
  • Page 322 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 9.2 Set Baud Rate <baud rate> <stop bit> Table 304. ISP Set Baud Rate command Command Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400 Stop bit: 1 | 2...
  • Page 323 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller ISP command handler compares it with the check-sum of the received bytes. If the check-sum matches, the ISP command handler responds with "OK<CR><LF>" to continue further transmission. If the check-sum does not match, the ISP command handler responds with "RESEND<CR><LF>".
  • Page 324 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 9.6 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. Table 309. ISP Prepare sector(s) for write operation command...
  • Page 325 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 9.8 Go <address> <mode> Table 311. ISP Go command Command Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary.
  • Page 326 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 9.10 Blank check sector(s) <sector number> <end sector number> Table 313. ISP Blank check sector command Command Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number.

  • Page 327: Table Of Contents

    UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 9.13 Compare <address1> <address2> <no of bytes> Table 317. ISP Compare command Command Input Address1 (DST): Starting Flash or RAM address of data bytes to be compared. This address should be a word boundary.
  • Page 328 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller Table 318. ISP Return codes Summary Return Mnemonic Description Code PARAM_ERROR Insufficient number of parameters or invalid parameter. ADDR_ERROR Address is not on word boundary. ADDR_NOT_MAPPED Address is not mapped in the memory map. Count value is taken in to consideration where applicable.
  • Page 329 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller typedef void (*IAP)(unsigned int [],unsigned int[]); IAP iap_entry; Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following statement. iap_entry (command, result); The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS (ARM Developer Suite).
  • Page 330 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller COMMAND CODE command PARAMETER 1 parameter table PARAMETER 2 ARM REGISTER r0 PARAMETER n ARM REGISTER r1 STATUS CODE RESULT 1 command result table RESULT 2 RESULT n Fig 74. IAP parameter passing 10.1 Prepare sector(s) for write operation...

  • Page 331: Src_Addr_Error

    UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 10.2 Copy RAM to Flash Table 321. IAP Copy RAM to Flash command Command Copy RAM to Flash Input Command code: 51 Param0(DST): Destination Flash address where data bytes are to be written. This address should be a 256 byte boundary.
  • Page 332 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 10.4 Blank check sector(s) Table 323. IAP Blank check sector(s) command Command Blank check sector(s) Input Command code: 53 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
  • Page 333 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 10.7 Compare <address1> <address2> <no of bytes> Table 326. IAP Compare command Command Compare Input Command code: 56 Param0(DST): Starting Flash or RAM address of data bytes to be compared. This address should be a word boundary.
  • Page 334 UM10114 NXP Semiconductors Chapter 21: LPC21xx/22xx Flash memory controller 11. JTAG Flash programming interface Debug tools can write parts of the flash image to the RAM and then execute the IAP call "Copy RAM to Flash" repeatedly with proper offset.
  • Page 335 UM10114 Chapter 22: LPC21xx/22xx On-chip serial bootloader for LPC2210/20/90 Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The on-chip serial bootloader controls the boot process for flashless LPC21xx/LPC22xx parts. Read this chapter for flashless parts •...
  • Page 336 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for The boot loader flow-chart is shown in Figure 22–76. 3. Memory map after reset The boot loader resides in an on-chip ROM sector of 8 kB in size. After any reset this entire boot sector is mapped and is also visible in the memory region starting from the address 0x7FFF E000.
  • Page 337 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for frequency (in kHz) at which the part is running. For example if the part is running at 10 MHz a valid response from the host should be "10000<CR><LF>". "OK<CR><LF>" string is sent to the host after receiving the crystal frequency. If synchronization is not verified then the auto-baud routine waits again for a synchronization character.
  • Page 338 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for 8. ISP flow control A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to stop the flow of data.
  • Page 339 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for 15. Boot process flowchart RESET INITIALIZE WATCHDOG FLAG SET? EXECUTE EXTERNAL USER CODE ENTER ISP MODE? (PO.14 LOW?) RUN AUTO-BAUD AUTO-BAUD SUCCESSFUL? RECEIVE CRYSTAL FREQUENCY Fig 76. Boot process flowchart 16.
  • Page 340 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for Table 328. ISP Command Summary ISP Command Usage Described in Unlock U <Unlock Code> Table 22–329 Set Baud Rate B <Baud Rate> <stop bit> Table 22–330 Echo A <setting> Table 22–332 Write to RAM W <start address>...
  • Page 341 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for Table 331. Correlation between possible ISP baudrates and external crystal frequency (in MHz) ISP Baudrate 9600 19200 38400 57600 115200 230400 .vs. external crystal frequency 18.4320 19.6608 24.5760 25.0000 16.3 Echo <setting>...
  • Page 342 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for 16.5 Read Memory <address> <number of bytes> The data stream is followed by the command success return code. The check-sum is sent after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data (before UU-encoding) bytes and is reset after transmitting 20 UUencoded lines.
  • Page 343 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for Table 336. ISP Read Part ID command description Command Return Code CMD_SUCCESS followed by part identification number in ASCII format. Description This command is used to read the part identification number.
  • Page 344 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for Table 339. ISP Compare command description Command Description This command is used to compare the memory contents (on or off-chip) at two locations. Example "M 1073742336 1073741824 4<CR><LF>" compares 4 bytes from the on-chip RAM address 0x4000 0000 to the 4 bytes from the on-chip RAM address 0x4000 0200.
  • Page 345 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for parameter table should be big enough to hold all the results in case if number of results are more than number of parameters. Parameter passing is illustrated in Figure 22–77.
  • Page 346 UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively.

  • Page 347: Src_Addr_Not_Mapped

    UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for 17.2 Read Boot code version Table 343. IAP Read Boot Code version command description Command Read boot code version Input Command Code 55 Parameters: None Status Code CMD_SUCCESS Result Result0: 2 bytes of boot code version number. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>...

  • Page 348: Count_Error

    UM10114 NXP Semiconductors Chapter 22: LPC21xx/22xx On-chip serial bootloader for Table 345. IAP Status Codes Summary Status Mnemonic Description Code COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value. COMPARE_ERROR Source and destination data is not same.
  • Page 349 UM10114 Chapter 23: LPC21xx/22xx Embedded ICE controller Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The Embedded ICE controller is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 350 UM10114 NXP Semiconductors Chapter 23: LPC21xx/22xx Embedded ICE controller does not affect the comparison. Either watchpoint register can be configured as a watchpoint (i.e. on a data access) or a break point (i.e. on an instruction fetch). The watchpoints and breakpoints can be combined such that: •...
  • Page 351 UM10114 NXP Semiconductors Chapter 23: LPC21xx/22xx Embedded ICE controller 6. Reset state of multiplexed pins The pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kΩ depending on the external JTAG circuitry) between V and the P1.26/RTCK pin.
  • Page 352 UM10114 NXP Semiconductors Chapter 23: LPC21xx/22xx Embedded ICE controller JTAG PORT serial parallel EMBEDDED ICE interface INTERFACE EMBEDDED ICE PROTOCOL CONVERTER host running debugger ARM7TDMI-S TARGET BOARD Fig 78. EmbeddedICE debug environment block diagram UM10114_3 © NXP B.V. 2008. All rights reserved.
  • Page 353 UM10114 Chapter 24: LPC21xx/22xx Embedded Trace Module (ETM) Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The ETM is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 354 UM10114 NXP Semiconductors Chapter 24: LPC21xx/22xx Embedded Trace Module (ETM) Table 348. ETM configuration Resource number/type Small Pairs of address comparators Data Comparators 0 (Data tracing is not supported) Memory Map Decoders Counters Sequencer Present External Inputs External Outputs FIFOFULL Present...
  • Page 355 UM10114 NXP Semiconductors Chapter 24: LPC21xx/22xx Embedded Trace Module (ETM) 6. Reset state of multiplexed pins On the LPC21xx/LPC22xx, the ETM pin functions are multiplexed with P1.25-16. To have these pins come as a Trace port, connect a weak bias resistor (4.7 kΩ) between the P1.20/TRACESYNC pin and V...
  • Page 356 UM10114 NXP Semiconductors Chapter 24: LPC21xx/22xx Embedded Trace Module (ETM) Table 350. ETM Registers Name Description Access Register encoding Sequencer State and Control Holds the next state triggering events. 110 00xx External Output 1 to 4 Holds the controlling events for each output.
  • Page 357 UM10114 Chapter 25: LPC21xx/22xx RealMonitor Rev. 03 — 2 April 2008 User manual 1. How to read this chapter The RealMonitor is identical for all LPC21xx and LPC22xx parts. For an overview of how LPC21xx and LPC22xx parts and versions are described in this manual, see Section 1–2 “How to read this manual”.
  • Page 358 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor RealMonitor combines features and mechanisms from both Angel and Multi-ICE to provide the services and functions that are required. In particular, it contains both the Multi-ICE communication mechanisms (the DCC using JTAG), and Angel-like support for processor context saving and restoring.
  • Page 359 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor 4.4 How RealMonitor works In general terms, the RealMonitor operates as a state machine, as shown in Figure 25–81. RealMonitor switches between running and stopped states, in response to packets received by the host, or due to asynchronous events on the target. RMTarget supports the triggering of only one breakpoint, watchpoint, stop, or semihosting SWI at a time.
  • Page 360 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor – Undef exception caused by the undefined instructions in user foreground application. This indicates an error in the application being debugged. RealMonitor stops the user application until a "Go" packet is received from the host.
  • Page 361 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor 5.5 Prefetch Abort mode RealMonitor uses four words on entry to its Prefetch abort interrupt handler. 5.6 Data Abort mode RealMonitor uses four words on entry to its data abort interrupt handler. 5.7 User/System mode RealMonitor makes no use of this stack.
  • Page 362 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor RealMonitor supplied exception vector handlers RM_UNDEF_HANDLER() RESET RM_PREFETCHABORT_HANDLER() RM_DATAABORT_HANDLER() RM_IRQHANDLER() UNDEF sharing IRQs between RealMonitor and user IRQ handler PREFETCH ABORT RM_IRQHANDLER2() DATA ABORT APP_IRQDISPATCH RESERVED APP_IRQHANDLER2() Fig 82. Exception handlers 5.11 RMTarget initialization While the processor is in a privileged mode, and IRQs are disabled, user must include a line of code within the start-up sequence of application to call rm_init_entry().
  • Page 363 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor NOP ; Insert User code valid signature here. LDR pc, [pc, #-0xFF0] ;Load IRQ vector from VIC LDR PC, FIQ_Address Reset_Address DCD __init ;Reset Entry point Undefined_Address DCD rm_undef_handler ;Provided by RealMonitor SWI_Address DCD 0 ;User can put address of SWI handler here...
  • Page 364 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor ; /********************************************************************* ; * Setup Vectored Interrupt controller. DCC Rx and Tx interrupts ; * generate Non Vectored IRQ request. rm_init_entry is aware ; * of the VIC and it enables the DBGCommRX and DBGCommTx interrupts.
  • Page 365 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor ;is not aware of the VIC interrupt priority hardware so trick ;rm_irqhandler2 to return here STMFD sp!, {ip,pc} pc, rm_irqhandler2 ;rm_irqhandler2 returns here cpsr_c, #0x52 ;Disable irq, move to IRQ mode spsr, r12 ;Restore SPSR from r12...
  • Page 366 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor RM_OPT_READBYTES=TRUE RM_OPT_WRITEBYTES=TRUE RM_OPT_READHALFWORDS=TRUE RM_OPT_WRITEHALFWORDS=TRUE RM_OPT_READWORDS=TRUE RM_OPT_WRITEWORDS=TRUE Enables/Disables support for 8/16/32 bit read/write. RM_OPT_EXECUTECODE=FALSE Enables/Disables support for executing code from "execute code" buffer. The code must be downloaded first. RM_OPT_GETPC=TRUE This option enables or disables support for the RealMonitor GetPC packet. Useful in code profiling when real monitor is used in interrupt mode.
  • Page 367 UM10114 NXP Semiconductors Chapter 25: LPC21xx/22xx RealMonitor This option specifies the size, in words, of the data logging FIFO buffer. CHAIN_VECTORS=FALSE This option allows RMTarget to support vector chaining through µHAL (ARM HW abstraction API). UM10114_3 © NXP B.V. 2008. All rights reserved.
  • Page 368 UM10114 Chapter 26: Supplementary information Rev. 03 — 2 April 2008 User manual 1. Abbreviations Table 352. Acronym list Acronym Description Analog-to-Digital Converter AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Controller Area Network CISC Complex Instruction Set Computer FIFO First In, First Out GPIO General Purpose Input/Output...
  • Page 369 Notice: All referenced brands, product names, service names and trademarks information. are the property of their respective owners. Right to make changes — NXP Semiconductors reserves the right to make C-bus — logo is a trademark of NXP B.V. changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice.
  • Page 370 UM10114 NXP Semiconductors Chapter 26: Supplementary information 3. Tables Table 1. LPC21xx and LPC22xx legacy/enhanced parts address 0xFFFF F008) bit description ..46 overview .......4 Table 41.
  • Page 371 UM10114 NXP Semiconductors Chapter 26: Supplementary information Table 73. Power Control register (PCON - address 0xE002 8034) bit description ... . . 119 0xE01F COCO) bit description ... . .76 Table 107.Fast GPIO port 0 output Set register (FIO0SET -...
  • Page 372 UM10114 NXP Semiconductors Chapter 26: Supplementary information address 0xE000 C000, when DLAB = 0, Write Table 162.UART1 Line Control Register (U1LCR - address Only) bit description ....132 0xE001 000C) bit description.
  • Page 373 UM10114 NXP Semiconductors Chapter 26: Supplementary information bit description ......217 Table 225:PWM Timer Control Register (PWMTCR - Table 198.SPI Clock Counter Register (S0SPCCR - address...
  • Page 374 UM10114 NXP Semiconductors Chapter 26: Supplementary information CAN4MOD - address 0x005 0000) bit CAN2TFIn - addresses 0xE004 8030, 40, 50; description ......279 CAN3TFIn - addresses 0xE004 C030, 40, 50;...
  • Page 375 UM10114 NXP Semiconductors Chapter 26: Supplementary information Table 293.ADC Status Register (ADSTAT - address description ......343 0xE003 4004) bit description .
  • Page 376 UM10114 NXP Semiconductors Chapter 26: Supplementary information 4. Figures Fig 1. LPC21xx and LPC22xx block diagram ..11 Fig 40. Arbitration procedure..... 178 Fig 2.
  • Page 377 UM10114 NXP Semiconductors Chapter 26: Supplementary information diagram .......352 Fig 79. ETM debug environment block diagram ..356 Fig 80.
  • Page 378 UM10114 NXP Semiconductors Chapter 26: Supplementary information 5. Contents Chapter 1: Introductory information Introduction ......3 LPC2210/2220 .
  • Page 379 UM10114 NXP Semiconductors Chapter 26: Supplementary information FIQ Status Register (VICFIQStatus - Interrupt sources..... . . 49 0xFFFF F004)......48 Spurious interrupts .
  • Page 380 UM10114 NXP Semiconductors Chapter 26: Supplementary information Chapter 9: LPC21xx/22xx General Purpose I/O (GPIO) controller How to read this chapter ....111 GPIO port Pin value register IOPIN (IO0PIN - 0xE002 8000, IO1PIN - 0xE002 8010, IO2PIN - Features .
  • Page 381 UM10114 NXP Semiconductors Chapter 26: Supplementary information UART1 Modem Control Register (U1MCR - 4.12 UART1 Scratch Pad Register (U1SCR - 0xE001 0010) ......161 0xE001 001C) .
  • Page 382 UM10114 NXP Semiconductors Chapter 26: Supplementary information 10.34 State: 0xB8 ......207 10.36 State: 0xC8 ......208 10.35...
  • Page 383 UM10114 NXP Semiconductors Chapter 26: Supplementary information 6.10 Capture Control Register (CCR, TIMER0: T0CCR 6.11 External Match Register (EMR, TIMER0: T0EMR - 0xE000 4028 and TIMER1: T1CCR - - 0xE000 403C; and TIMER1: T1EMR - 0xE000 8028) ......241 0xE000 803C) .
  • Page 384 UM10114 NXP Semiconductors Chapter 26: Supplementary information Mode Register (MOD: CAN1MOD - 0xE004 4000, 6.14 Transmit Identifier register (TID1, 2, 3 - CAN1TIDn CAN2MOD - 0xE004 8000, CAN3MOD - 0x004 - 0xE004 4034, 44, 54; CAN2TIDn - C000, CAN4MOD - 0x005 0000) ..279 0xE004 8034, 44, 54;...
  • Page 385 UM10114 NXP Semiconductors Chapter 26: Supplementary information ADC Interrupt Enable Register (ADINTEN - Operation ......309 0xE003 400C).
  • Page 386 UM10114 NXP Semiconductors Chapter 26: Supplementary information Chapter 23: LPC21xx/22xx Embedded ICE controller How to read this chapter ....349 Pin description ..... . . 350 Features .

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