NXP Semiconductors LPC11U3x User Manual

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UM10462

LPC11U3x/2x/1x User manual

Rev. 5.5 — 21 December 2016

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LPC11U3x/2x/1x, ARM Cortex-M0, microcontroller, LPC11U12,

LPC11U14, LPC11U13, USB, LPC11U22, LPC11U23, LPC11U24,

LPC11U34, LPC11U35, LPC11U36, LPC11U37, LPC11U37H, I/O Handler

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LPC11U3x/2x/1x User manual

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Page 1 UM10462 LPC11U3x/2x/1x User manual Rev. 5.5 — 21 December 2016 User manual Document information Info Content Keywords LPC11U3x/2x/1x, ARM Cortex-M0, microcontroller, LPC11U12, LPC11U14, LPC11U13, USB, LPC11U22, LPC11U23, LPC11U24, LPC11U34, LPC11U35, LPC11U36, LPC11U37, LPC11U37H, I/O Handler Abstract LPC11U3x/2x/1x User manual...
Page 2 UM10462 NXP Semiconductors LPC11U3x/2x/1x User manual Revision history Date Description 20161221 Modifications: • Updated Table 200 “USBD_API_INIT_PARAM class structure” with: Parameters: a. hUsb = Handle to the USB device stack. Returns: The call back should return ErrorCode_t type to indicate success or error condition.
Page 3 “LPC11U3x/2x/1x Pin configuration”. • Pin description notes relating to open-drain I2C-bus pins updated for clarity. Chapter 8 “LPC11U3x/2x/1x Pin configuration”. • Pin description of the WAKEUP pin updated for clarity. Chapter 8 “LPC11U3x/2x/1x Pin configuration”. 20131220 Modifications: • Reset value of the SYSAHBCLKCTRL register corrected. See Table 5.
Page 4 Bootloader description clarified. See Section 20.2. • Code listings corrected in Chapter 10. • Table 346 “LPC11U3x flash sectors and pages” corrected for LPC11U35 parts. • Editorial updates in Section 20.14 “IAP commands”. • Steps to enter Deep-sleep mode and Power-down mode updated in Section 3.9.4.2 “Programming Deep-sleep mode”...
Page 5 Revision history …continued Date Description • Flash page erase command added for LPC11U3x parts in Chapter 20. • FREQSEL bit values updated in Table 14 “Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description”. • SRAM use by bootloader specified in Section 20.2.
Page 6: Chapter 1: Lpc11U3X/2X/1X Introductory Information
Memory: – Up to 32 kB on-chip flash program memory. – LPC11U3x only: Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase (256 byte) access. – In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
Page 7 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information LPC11U3x: up to 12 kB (8 kB main SRAM0, 2 kB SRAM1, 2 kB USB SRAM). – 16 kB boot ROM. – LPC11U2x/3x only: Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable;...
Page 8: Ordering Information
UM10462 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information – 12 MHz Internal high-frequency RC oscillator (IRC) that can optionally be used as a system clock. – Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output. – PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.
Page 9 UM10462 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information Table 1. Ordering information …continued Type number Package Name Description Version plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm LPC11U22FBD48/301 LQFP48 SOT313-2 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm...
Page 10 UM10462 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information Table 2. Part ordering options …continued Part Number FLASH SRAM SRAM1 Total EEPROM USB I2C/ SSP ADC GPIO (kB) (kB) (kB) SRAM genera (kB) Fast+ Chan (Main (kB) purpose nels SRAM) SRAM...
Page 11: Block Diagram
UM10462 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information 1.4 Block diagram SWD, JTAG XTALIN XTALOUT RESET LPC11U12/13/14 SYSTEM OSCILLATOR CLOCK GENERATION, IRC, WDO TEST/DEBUG POWER CONTROL, CLKOUT INTERFACE SYSTEM FUNCTIONS CORTEX-M0 PLL0 USB PLL FLASH SRAM system bus 16/24/32 kB...
Page 12 UM10462 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information SWD, JTAG XTALIN XTALOUT RESET LPC11U2x SYSTEM OSCILLATOR TEST/DEBUG CLOCK INTERFACE GENERATION, IRC, WDO POWER CONTROL, CLKOUT SYSTEM FUNCTIONS CORTEX-M0 PLL0 USB PLL EEPROM 1/2/4 kB FLASH SRAM system bus 16/24/32 kB...
Page 13 UM10462 NXP Semiconductors Chapter 1: LPC11U3x/2x/1x Introductory information SWD, JTAG XTALIN XTALOUT RESET LPC11U3x SYSTEM OSCILLATOR TEST/DEBUG CLOCK INTERFACE GENERATION, IRC, WDO POWER CONTROL, CLKOUT SYSTEM FUNCTIONS CORTEX-M0 PLL0 USB PLL EEPROM 4 kB FLASH SRAM system bus 40/48/64/96/128 kB...
Page 14: How To Read This Chapter
UM10462 Chapter 2: LPC11U3x/2x/1x Memory mapping Rev. 5.5 — 21 December 2016 User manual 2.1 How to read this chapter Table 3 for the memory configuration of the LPC11U3x/2x/1x parts. Table 3. LPC11U3x/2x/1x memory configuration Part Flash Main SRAM1 at...
Page 15: Memory Map
UM10462 NXP Semiconductors Chapter 2: LPC11U3x/2x/1x Memory mapping 2.2 Memory map The LPC11U3x/2x/1x incorporates several distinct memory regions, shown in the following figures. Figure 4 shows the overall map of the entire address space from the user program viewpoint following reset.
Page 16: Chapter 2: Lpc11U3X/2X/1X Memory Mapping
UM10462 NXP Semiconductors Chapter 2: LPC11U3x/2x/1x Memory mapping LPC11U12/13/14 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved APB peripherals 0x5000 4000 0x4008 0000 GPIO 25 - 31 reserved 0x4006 4000 0x5000 0000 GPIO GROUP1 INT...
Page 17 UM10462 NXP Semiconductors Chapter 2: LPC11U3x/2x/1x Memory mapping LPC11U2x 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved APB peripherals 0x5000 4000 0x4008 0000 GPIO 25 - 31 reserved 0x4006 4000 0x5000 0000 GPIO GROUP1 INT...
Page 18 UM10462 NXP Semiconductors Chapter 2: LPC11U3x/2x/1x Memory mapping LPC11U3x 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved 0x5000 4000 GPIO 0x5000 0000 APB peripherals 0x4008 0000 reserved 0x4008 4000 25 - 31 reserved 0x4006 4000...
Page 19: Chapter 3: Lpc11U3X/2X/1X System Control Block
User manual 3.1 How to read this chapter The system control block is identical for all LPC11U3x/2x/1x parts. The following register bit is available on LPC11U3x/501 and LPC11U37H only and is reserved otherwise: SYSAHBCLKCTRL register bit RAM1 (bit 26) (Table 24).
Page 20: Register Description
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block The main clock, and the clock outputs from the IRC, the system oscillator, and the watchdog oscillator can be observed directly on the CLKOUT pin. CPU, system control, system clock SYSTEM CLOCK...
Page 21 UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block In addition to the system control block registers described in Table 5, the flash access timing register, which can be re-configured as part the system setup, is described in Table 6. This register is not part of the system configuration block.
Page 22: System Memory Remap Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 5. Register overview: system control block (base address 0x4004 8000) …continued Name Access Offset Description Reset value Reset value Reference after boot BODCTRL 0x150 Brown-Out Detect Table 36 SYSTCKCAL 0x154...
Page 23: Peripheral Reset Control Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description Symbol Value Description Reset value System memory remap. Value 0x3 is reserved. Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
Page 24: System Pll Status Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 9. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Symbol Value Description Reset value MSEL Feedback divider value. The division value M is the programmed MSEL value + 1.
Page 25: Usb Pll Status Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 11. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description Symbol Value Description Reset value MSEL Feedback divider value. The division value M is the 0x000 programmed MSEL value + 1.
Page 26: Watchdog Oscillator Control Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3.5.8 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana).
Page 27: Internal Resonant Crystal Control Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3.5.9 Internal resonant crystal control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. Table 15.
Page 28 UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 17. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040) bit description Symbol Value Description Reset value System PLL clock source Crystal Oscillator (SYSOSC) Reserved Reserved 31:2 Reserved UM10462 All information provided in this document is subject to legal disclaimers.
Page 29: System Pll Clock Source Update Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3.5.12 System PLL clock source update register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
Page 30: Main Clock Source Select Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 20. USB PLL clock source update enable register (USBPLLCLKUEN, address 0x4004 804C) bit description Symbol Value Description Reset value Enable USB PLL clock source update No change Update clock source...
Page 31: System Clock Control Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 23. System clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit description Symbol Description Reset value System AHB clock divider values 0: System clock disabled. 1: Divide by 1. 255: Divide by 255.
Page 32 UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 24. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Symbol Value Description Reset value CT16B1 Enables clock for 16-bit counter/timer 1. Disable Enable CT32B0 Enables clock for 32-bit counter/timer 0.
Page 33: Ssp0 Clock Divider Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 24. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Symbol Value Description Reset value GROUP1INT Enables clock to GPIO GROUP1 interrupt register interface. Disable Enable Reserved RAM1 Enables SRAM1 block at address 0x2000 0000.
Page 34: Ssp1 Clock Divider Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3.5.21 SSP1 clock divider register This register configures the SSP1 peripheral clock SSP1_PCLK. The SSP1_PCLK can be shut down by setting the DIV bits to 0x0. Table 27. SPI1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description...
Page 35: Usb Clock Divider Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 29. USB clock source update enable register (USBCLKUEN, address 0x4004 80C4) bit description Symbol Value Description Reset value Enable USB clock source update No change Update clock source 31:1 Reserved 0x00 3.5.24 USB clock divider register...
Page 36: Clkout Clock Divider Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 32. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004 80E4) bit description Symbol Value Description Reset value Enable CLKOUT clock source update No change Update clock source 31:1 Reserved 3.5.27 CLKOUT clock divider register...
Page 37: System Tick Counter Calibration Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Both the BOD interrupt and the BOD reset, depending on the value of bit BODRSTENA in this register, can wake-up the chip from Sleep, Deep-sleep, and Power-down modes. See Section 3.9.
Page 38: Nmi Source Selection Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Setting this parameter to a very low value (e.g. zero) will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter. Requiring the system to always take a larger number of cycles (whether it needs it or not) will reduce the amount of uncertainty but may not necessarily eliminate it.
Page 39: Usb Clock Control Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots # 0 to 7 (see Table 59). To enable each pin interrupt and configure its edge or level sensitivity, use the GPIO pin...
Page 40: Interrupt Wake-Up Enable Register 0
Enabled 31:8 Reserved 3.5.38 Interrupt wake-up enable register 1 This register selects which interrupts will wake the LPC11U3x/2x/1x from deep-sleep and power-down modes. Interrupts selected by a one in these registers must be enabled in the NVIC (Table 59) in order to successfully wake the LPC11U3x/2x/1x from deep-sleep or power-down mode.
Page 41: Deep-Sleep Mode Configuration Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 44. Interrupt wake-up enable register 1 (STARTERP1, address 0x4004 8214) bit description Symbol Value Description Reset value 11:0 Reserved. WWDTINT WWDT interrupt wake-up Disabled Enabled BODINT Brown Out Detect (BOD) interrupt wake-up...
Page 42: Wake-Up Configuration Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 45. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit description …continued Symbol Value Description Reset value WDTOSC_PD Watchdog oscillator power-down control for Deep-sleep and Power-down mode Powered Powered down 31:7 Reserved 3.5.40 Wake-up configuration register...
Page 43: Power Configuration Register
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Table 46. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description …continued Symbol Value Description Reset value Reserved. USBPAD_PD USB transceiver wake-up configuration USB transceiver powered USB transceiver powered down Reserved. Always write this bit as 1.
Page 44: Device Id Register
31:16 Reserved 3.5.42 Device ID register This device ID register is a read-only register and contains the part ID for each LPC11U3x/2x/1x part. This register is also read by the ISP/IAP commands (see Table 376). Table 48. Device ID register (DEVICE_ID, address 0x4004 83F4) bit description...
Page 45: Flash Memory Access
Bits 31:2 must be written back exactly as read. 3.6 Reset Reset has the following sources on the LPC11U3x/2x/1x: the RESET pin, Watchdog Reset, Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is an ARM software reset.
Page 46: Start-Up Behavior
Fig 8. Start-up timing 3.8 Brown-out detection The LPC11U3x/2x/1x includes up to four levels for monitoring the voltage on the V pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC or issues a reset, depending on the value of the BODRSTENA bit in the BOD...
Page 47: Power Management
Chapter 3: LPC11U3x/2x/1x System control block 3.9 Power management The LPC11U3x/2x/1x support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are four special modes of processor power reduction with different peripherals running: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.
Page 48: Active Mode
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3.9.2 Active mode In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock.
Page 49: Wake-Up From Sleep Mode
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction. 3.9.3.3 Wake-up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers.
Page 50: Wake-Up From Deep-Sleep Mode
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 5. Select the power configuration after wake-up in the PDAWAKECFG (Table register. 6. If any of the available wake-up interrupts are needed for wake-up, enable the interrupts in the interrupt wake-up registers...
Page 51: Power Configuration In Power-Down Mode
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block Remark: Do not set the LOCK bit in the WWDT MOD register (Table 337) when the IRC is selected as a clock source for the WWDT. This prevents the part from entering the Power-down mode correctly.
Page 52: Deep Power-Down Mode
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block – Reset from the BOD circuit. In this case, the BOD reset must be enabled in the BODCTRL register (Table 36). • WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register: –...
Page 53: Wake-Up From Deep Power-Down Mode
Remark: The RESET pin has no functionality in Deep power-down mode. 3.10 System PLL/USB PLL functional description The LPC11U3x/2x/1x uses the system PLL to create the clocks for the core and peripherals. An identical PLL is available for the USB.
Page 54: Lock Detector
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block optionally two additional phases. The CCO frequency range is 156 MHz to 320 MHz.These clocks are either divided by 2P by the programmable post divider to create the output clocks, or are sent directly to the outputs. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock.
Page 55: Frequency Selection
UM10462 NXP Semiconductors Chapter 3: LPC11U3x/2x/1x System control block 3.10.4 Frequency selection The PLL frequency equations use the following parameters (also see Figure Table 51. PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys_pllclkin (input clock to the system PLL) from the...
Page 56: Chapter 4: Lpc11U3X/2X/1X Power Management Unit (Pmu)
UM10462 Chapter 4: LPC11U3x/2x/1x Power Management Unit (PMU) Rev. 5.5 — 21 December 2016 User manual 4.1 How to read this chapter The PMU is identical on all LPC11U3x/2x/1x parts. Also refer to Chapter 5 for power control. 4.2 Introduction The PMU controls the Deep power-down mode.
Page 57: General Purpose Registers 0 To 3
UM10462 NXP Semiconductors Chapter 4: LPC11U3x/2x/1x Power Management Unit (PMU) Table 54. Power control register (PCON, address 0x4003 8000) bit description …continued Symbol Value Description Reset value Reserved. Do not write ones to this bit. SLEEPFLAG Sleep mode flag Read: No power-down mode entered. LPC11U3x/2x/1x is in Active mode.
Page 58: Functional Description
UM10462 NXP Semiconductors Chapter 4: LPC11U3x/2x/1x Power Management Unit (PMU) Table 56. General purpose register 4 (GPREG4, address 0x4003 8014) bit description …continued Symbol Value Description Reset value WAKEUPHYS WAKEUP pin hysteresis enable Hysteresis for WAKUP pin disabled. Hysteresis for WAKEUP pin enabled.
Page 59: Chapter 5: Lpc11U3X/2X/1X Power Profiles
UM10462 Chapter 5: LPC11U3x/2x/1x Power profiles Rev. 5.5 — 21 December 2016 User manual 5.1 How to read this chapter The power profiles are available for all LPC11U3x/2x/1x. 5.2 Features • Includes ROM-based application services • Power Management services •...
Page 60 DIVIDER SYS PLL sys_osc_clk sys_pllclkin SYSPLLCLKSEL Fig 11. LPC11U3x/2x/1x clock configuration for power API use UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved. User manual Rev. 5.5 — 21 December 2016...
Page 61: Definitions
UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles 5.5 Definitions The following elements have to be defined in an application that uses the power profiles: typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]); void (*set_power)(unsigned int cmd[], unsigned int resp[]);...
Page 62: Param0: System Pll Input Frequency And Param1: Expected System Clock
UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles #define CPU_FREQ_GTE #define CPU_FREQ_APPROX /* set_pll result0 options */ #define PLL_CMD_SUCCESS #define PLL_INVALID_FREQ #define PLL_INVALID_MODE #define PLL_FREQ_NOT_FOUND #define PLL_NOT_LOCKED For a simplified clock configuration scheme see Figure 11. For more details see Figure 5.6.1.1 Param0: system PLL input frequency and Param1: expected system clock...
Page 63: Code Examples
UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles Remark: The time it takes the PLL to lock depends on the selected PLL input clock source (IRC/system oscillator) and its characteristics. The selected source can experience more or less jitter depending on the operating conditions such as power supply and/or ambient temperature.
Page 64: Value
UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles 5.6.1.4.4 System clock less than or equal to the expected value command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_LTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 25 MHz and no locking time-out.
Page 65 UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles using power profiles and changing system clock current_clock, new_clock , new_mode use power routine call to change mode to DEFAULT use either clocking routine call or custom code to change system clock...
Page 66: Param0: Main Clock
UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles For a simplified clock configuration scheme see Figure 11. For more details see Figure 5.7.1.1 Param0: main clock The main clock is the clock rate the microcontroller uses to source the system’s and the peripherals’...
Page 67 UM10462 NXP Semiconductors Chapter 5: LPC11U3x/2x/1x Power profiles (*rom)->pWRD->set_power(command, result); The above code specifies that an application is running at the main and system clock of 24 MHz with emphasis on efficiency. set_power returns PWR_CMD_SUCCESS in result[0] after configuring the microcontroller’s internal power control features.
Page 68: Chapter 6: Lpc11U3X/2X/1X Nvic
Chapter 6: LPC11U3x/2x/1x NVIC Rev. 5.5 — 21 December 2016 User manual 6.1 How to read this chapter The NVIC is identical for all LPC11U3x/2x/1x parts. See Section 24.5.2 for details. Interrupt 31 (I/O Handler interrupt) is available on part LPC11U37HFBD64/401 only.
Page 69 UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 59. Connection of interrupt sources to the Vectored Interrupt Controller …continued Interrupt Name Description Flags number GINT0 GPIO GROUP0 interrupt GINT1 GPIO GROUP1 interrupt 13 to 10 Reserved SSP1 SSP1 interrupt Tx FIFO half empty...
Page 70: Register Description
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC 6.5 Register description See the ARM Cortex-M0+ technical reference manual. The NVIC registers are located on the ARM private peripheral bus. Table 60. Register overview: NVIC (base address 0xE000 E000) Name Access Address...
Page 71: Interrupt Set Enable Register 0 Register
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 60. Register overview: NVIC (base address 0xE000 E000) …continued Name Access Address Description Reset Reference offset value IPR5 0x414 Interrupt Priority Registers 5. This register allows assigning a priority Table 71 to each interrupt. This register contains the 2-bit priority fields for interrupts 12 to 15.
Page 72: Interrupt Clear Enable Register 0
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 61. Interrupt Set Enable Register 0 register (ISER0, address 0xE000 E100) bit description …continued Symbol Description Reset value ISE_USB_IRQ Interrupt enable. ISE_USB_FIQ Interrupt enable. ISE_ADC Interrupt enable. ISE_WWDT Interrupt enable. ISE_BOD Interrupt enable.
Page 73: Interrupt Set Pending Register 0 Register
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 62. Interrupt clear enable register 0 (ICER0, address 0xE000 E180) …continued Symbol Description Reset value ICE_SSP0 Interrupt disable. ICE_USART0 Interrupt disable. ICE_USB_IRQ Interrupt disable. ICE_USB_FIQ Interrupt disable. ICE_ADC0 Interrupt disable. ICE_WWDT Interrupt disable.
Page 74: Interrupt Clear Pending Register 0 Register
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 63. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit description …continued Symbol Description Reset value ISP_CT16B0 Interrupt pending set. ISP_CT16B1 Interrupt pending set. ISP_CT32B0 Interrupt pending set. ISP_CT32B1 Interrupt pending set.
Page 75: Interrupt Active Bit Register 0
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 64. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit description …continued Symbol Function Reset value Reserved. Reserved. Reserved. ICP_SSP1 Interrupt pending clear. ICP_I2C0 Interrupt pending clear. ICP_CT16B0 Interrupt pending clear.
Page 76: Interrupt Priority Register 0
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC Table 65. Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description Symbol Function Reset value IAB_GINT0 Interrupt active state. IAB_GINT1 Interrupt active state. Reserved. Reserved. Reserved. Reserved. IAB_SSP1 Interrupt active state.
Page 77: Interrupt Priority Register 1
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC 6.5.7 Interrupt Priority Register 1 The IPR1 register controls the priority of four peripheral interrupts. Each interrupt can have one of 4 priorities, where 0 is the highest priority. Table 67. Interrupt Priority Register 1 (IPR1, address 0xE000 E404) bit description...
Page 78: Interrupt Priority Register 4
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC 6.5.10 Interrupt Priority Register 4 The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can have one of 4 priorities, where 0 is the highest priority. Table 70. Interrupt Priority Register 4 (IPR4, address 0xE000 E410) bit description...
Page 79: Interrupt Priority Register 7
UM10462 NXP Semiconductors Chapter 6: LPC11U3x/2x/1x NVIC 6.5.13 Interrupt Priority Register 7 The IPR7 register controls the priority of four peripheral interrupts. Each interrupt can have one of 4 priorities, where 0 is the highest priority. Table 73. Interrupt Priority Register 7 (IPR7, address 0xE000 E41C) bit description...
Page 80: How To Read This Chapter
UM10462 Chapter 7: LPC11U3x/2x/1x I/O configuration Rev. 5.5 — 21 December 2016 User manual 7.1 How to read this chapter The IOCON register map depends on the package type (see Table 74). Registers for pins which are not pinned out are reserved.
Page 81: Chapter 7: Lpc11U3X/2X/1X I/O Configuration
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration open-drain enable strong pin configured output enable pull-up as digital output driver data output strong pull-down weak pull-up pull-up enable weak repeater mode pull-down pin configured enable pull-down enable as digital input...
Page 82: Hysteresis
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration not applicable to the Deep power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven.
Page 83: Reset Pin (Pin Reset_Pio0_0)
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.3.9 RESET pin (pin RESET_PIO0_0) Figure 14 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode.
Page 84: Register Description
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4 Register description The I/O configuration registers control the PIO port pins, the inputs and outputs of all peripherals and functional blocks, the I C-bus pins, and the ADC input pins. Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and electrical characteristics.
Page 85 UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 75. Register overview: I/O configuration (base address 0x4004 4000) …continued Name Access Address Description Reset value Reference offset PIO0_20 0x050 I/O configuration for pin 0x0000 0090 Table 96 PIO0_20/CT16B1_CAP0 PIO0_21 0x054...
Page 86: I/O Configuration Registers
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 75. Register overview: I/O configuration (base address 0x4004 4000) …continued Name Access Address Description Reset value Reference offset PIO1_22 0x0B8 I/O configuration for pin PIO1_22/RI/MOSI1 0x0000 0090 Table 122 PIO1_23 0x0BC...
Page 87: Pio0_1 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 76. RESET_PIO0_0 register (RESET_PIO0_0, address 0x4004 4000) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. Remark: This is not a true open-drain mode. 31:11 Reserved.
Page 88: Pio0_2 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.3 PIO0_2 register Table 78. PIO0_2 register (PIO0_2, address 0x4004 4008) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. PIO0_2. SSEL0. CT16B0_CAP0. IOH_0.
Page 89: Pio0_4 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 79. PIO0_3 register (PIO0_3, address 0x4004 400C) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 90: Pio0_6 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 81. PIO0_5 register (PIO0_5, address 0x4004 4014) bit description …continued Symbol Value Description Reset value Reserved. 10000 I2CMODE Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
Page 91: Pio0_7 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.8 PIO0_7 register Table 83. PIO0_7 register (PIO0_7, address 0x4004 401C) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x3 to 0x7 are reserved. PIO0_7. CTS. IOH_5. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 92: Pio0_9 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 84. PIO0_8 register (PIO0_8, address 0x4004 4020) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 93: Swclk_Pio0_10 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 85. PIO0_9 register (PIO0_9, address 0x4004 4024) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. Remark: This is not a true open-drain mode. 31:11 Reserved.
Page 94: Tdi_Pio0_11 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.12 TDI_PIO0_11 register Table 87. TDI_PIO0_11 register (TDI_PIO0_11, address 0x4004 402C) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. TDI. PIO0_11. AD0. CT32B0_MAT3.
Page 95: Tms_Pio0_12 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.13 TMS_PIO0_12 register Table 88. TMS_PIO0_12 register (TMS_PIO0_12, address 0x4004 4030) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. TMS. PIO0_12. AD1. CT32B1_CAP0.
Page 96: Pio0_13 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.14 PIO0_13 register Table 89. TDO_PIO0_13 register (TDO_PIO0_13, address 0x4004 4034) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. TDO. PIO0_13. AD2. CT32B1_MAT0.
Page 97: Trst_Pio0_14 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.15 TRST_PIO0_14 register Table 90. TRST_PIO0_14 register (TRST_PIO0_14, address 0x4004 4038) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. TRST. PIO0_14. AD3. CT32B1_MAT1.
Page 98: Swdio_Pio0_15 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.16 SWDIO_PIO0_15 register Table 91. SWDIO_PIO0_15 register (SWDIO_PIO0_15, address 0x4004 403C) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. SWDIO. PIO0_15. AD4. CT32B1_MAT2.
Page 99: Pio0_16 Register
Symbol Value Description Reset value FUNC Selects pin function. This pin functions as WAKEUP pin if the LPC11U3x/2x/1x is in Deep power-down mode regardless of the value of FUNC. Values 0x4 to 0x7 are reserved. PIO0_16. AD5. CT32B1_MAT3. IOH_8. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 100: Pio0_17 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.18 PIO0_17 register Table 93. PIO0_17 register (PIO0_17, address 0x4004 4044) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. PIO0_17. RTS. CT32B0_CAP0. SCLK (UART synchronous clock).
Page 101: Pio0_19 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 94. PIO0_18 register (PIO0_18, address 0x4004 4048) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 102: Pio0_20 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 95. PIO0_19 register (PIO0_19, address 0x4004 404C) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. Remark: This is not a true open-drain mode. 31:11 Reserved.
Page 103: Pio0_21 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.22 PIO0_21 register Table 97. PIO0_21 register (PIO0_21, address 0x4004 4054) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x3 to 0x7 are reserved. PIO0_21. CT16B1_MAT0. MOSI1. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 104: Pio0_23 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 98. PIO0_22 register (PIO0_22, address 0x4004 4058) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 105: Pio1_0 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 99. PIO0_23 register (PIO0_23, address 0x4004 405C) bit description …continued Symbol Value Description Reset value Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 106: Pio1_1 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 100. PIO1_0 register (PIO1_0, address 0x4004 4060) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.
Page 107: Pio1_2 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.27 PIO1_2 register Table 102. PIO1_2 register (PIO1_2, address 0x4004 4068) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. PIO1_2. CT32B1_MAT2. IOH_12. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 108: Pio1_4 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 103. PIO1_3 (PIO1_3, address 0x4004406C) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 109: Pio1_5 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 104. I/O configuration PIO1_4 (PIO1_4, address 0x4004 4070) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.
Page 110: Pio1_7 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 106. PIO1_6 register (PIO1_6, address 0x4004 4078) bit description …continued Symbol Value Description Reset value MODE Selects function mode (on-chip pull-up/pull-down resistor control). Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled.
Page 111: Pio1_8 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 107. PIO1_7 register (PIO1_7, address 0x4004 407C) bit description …continued Symbol Value Description Reset value RESERVED Reserved. Open-drain mode. Disable. Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.
Page 112: Pio1_9 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.34 PIO1_9 register Table 109. PIO1_9 register (PIO1_9, address 0x4004 4084) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x1 to 0x7 are reserved. PIO1_9. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 113: Pio1_11 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 110. PIO1_10 register (PIO1_10, address 0x4004 4088) bit description …continued Symbol Value Description Reset value Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 114: Pio1_12 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.37 PIO1_12 register Table 112. PIO1_12 register (PIO1_12, address 0x4004 4090) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x1 to 0x7 are reserved. PIO1_12. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 115: Pio1_14 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 113. PIO1_13 register (PIO1_13, address 0x4004 4094) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 116: Pio1_15 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 114. PIO1_14 register (PIO1_14, address 0x4004 4098) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. Remark: This is not a true open-drain mode. 31:11 Reserved.
Page 117: Pio1_16 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.41 PIO1_16 register Table 116. PIO1_16 register (PIO1_16, address 0x4004 40A0) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x3 to 0x7 are reserved. PIO1_16. CT16B0_CAP0. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 118: Pio1_18 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 117. PIO1_17 register (PIO1_17, address 0x4004 40A4) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 119: Pio1_19 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 118. PIO1_18 register (PIO1_18, address 0x4004 40A8) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD.
Page 120: Pio1_20 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.45 PIO1_20 register Table 120. PIO1_20 register (PIO1_20, address 0x4004 40B0) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x3 to 0x7 are reserved. PIO1_20. DSR. SCK1. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 121: Pio1_22 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 121. PIO1_21 register (PIO1_21, address 0x4004 40B4) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 122: Pio1_23 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 122. PIO1_22 register (PIO1_22, address 0x4004 40B8) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. Remark: This is not a true open-drain mode. 31:11 Reserved.
Page 123: Pio1_24 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.49 PIO1_24 register Table 124. PIO1_24 register (PIO1_24, address 0x4004 40C0) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x2 to 0x7 are reserved. PIO1_24. CT32B0_MAT0. MODE Selects function mode (on-chip pull-up/pull-down resistor control).
Page 124: Pio1_26 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 125. PIO1_25 register (PIO1_25, address 0x4004 40C4) bit description …continued Symbol Value Description Reset value Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 125: Pio1_27 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration 7.4.1.52 PIO1_27 register Table 127. PIO1_27 register (PIO1_27, address 0x4004 40CC) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. PIO1_27. CT32B0_MAT3. TXD. IOH_20.
Page 126: Pio1_29 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 128. PIO1_28 register (PIO1_28, address 0x4004 40D0) bit description …continued Symbol Value Description Reset value Hysteresis. Disable. Enable. Invert input Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0).
Page 127: Pio1_31 Register
UM10462 NXP Semiconductors Chapter 7: LPC11U3x/2x/1x I/O configuration Table 129. PIO1_29 register (PIO1_29, address 0x4004 40D4) bit description …continued Symbol Value Description Reset value Open-drain mode. Disable. Open-drain mode enabled. Remark: This is not a true open-drain mode. 31:11 Reserved.
Page 128: Chapter 8: Lpc11U3X/2X/1X Pin Configuration
Chapter 8: LPC11U3x/2x/1x Pin configuration Rev. 5.5 — 21 December 2016 User manual 8.1 How to read this chapter Table 131 shows the possible pin configuration for the LPC11U3x/2x/1x parts. Table 131. LPC11U3x/2x/1x pin configurations Part Package Pin configuration Pin description...
Page 129: Pin Configuration
UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration 8.2 Pin configuration terminal 1 index area PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 LPC11U1x XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3 LPC11U2x XTALOUT LPC11U3x PIO0_22/AD6/CT16B1_MAT1/MISO1 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_20/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1 33 V PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0 002aaf888_1 Transparent top view Fig 15. Pin configuration (HVQFN33) UM10462 All information provided in this document is subject to legal disclaimers.
Page 130 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration PIO1_25/CT32B0_MAT1 PIO1_13/DTR/CT16B0_MAT0/TXD PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 TDI/PIO0_11/AD0/CT32B0_MAT3 LPC11U1x LPC11U2x XTALIN PIO1_29/SCK0/CT32B0_CAP1 LPC11U3x XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_20/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0 PIO1_26/CT32B0_MAT2/RXD PIO1_21/DCD/MISO1 PIO1_27/CT32B0_MAT3/TXD PIO1_31 002aaf884_1 Fig 16. Pin configuration (LQFP48) UM10462 All information provided in this document is subject to legal disclaimers.
Page 131 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration ball A1 LPC11U1x/3x index area 002aag101_1 Transparent top view Fig 17. Pin configuration (TFBGA48) PIO1_0 PIO1_25 PIO1_13 PIO1_19 TRST/PIO0_14 RESET/PIO0_0 TDO/PIO0_13 PIO0_1 TMS/PIO0_12 PIO1_7 PIO1_11 TDI/PIO0_11 LPC11U2x XTALIN PIO1_29 LPC11U3x XTALOUT PIO0_22...
Page 132: Lpc11U1X Pin Description
UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration 8.2.1 LPC11U1x pin description Table 132 shows all pins and their assigned digital or analog functions ordered by GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and PIO0_5.
Page 133 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 132. LPC11U1x pin description …continued Symbol Reset Type Description state PIO0_4/SCL I; IA PIO0_4 — General purpose digital input/output pin (open-drain). SCL — I C-bus clock input/output (open-drain). High-current sink only if I C Fast-mode Plus is selected in the I/O configuration register.
Page 134 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 132. LPC11U1x pin description …continued Symbol Reset Type Description state TMS/PIO0_12/AD1/ I; PU TMS — Test Mode Select for JTAG interface. CT32B1_CAP0 PIO_12 — General purpose digital input/output pin. AD1 — A/D converter, input 1.
Page 135 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 132. LPC11U1x pin description …continued Symbol Reset Type Description state PIO0_18/RXD/ I; PU PIO0_18 — General purpose digital CT32B0_MAT0 input/output pin. RXD — Receiver input for USART.Used in UART ISP mode.
Page 136 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 132. LPC11U1x pin description …continued Symbol Reset Type Description state PIO1_14/DSR/ I; PU PIO1_14 — General purpose digital CT16B0_MAT1/RXD input/output pin. DSR — Data Set Ready input for USART. CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
Page 137 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 132. LPC11U1x pin description …continued Symbol Reset Type Description state PIO1_24/CT32B0_MAT0 I; PU PIO1_24 — General purpose digital input/output pin. CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_25/CT32B0_MAT1 I; PU PIO1_25 —...
Page 138 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
Page 139: Lpc11U2X Pin Description
UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 133. Multiplexing of peripheral functions …continued Peripheral Function Type Default Available on ports HVQFN33/LQFP48/TFBGA48 LQFP48/TFBGA48 TFBGA48 CT16B1 CT16B1_CAP0 PIO0_20 CT16B1_MAT0 PIO0_21 CT16B1_MAT1 PIO0_22 PIO1_23 CT32B0 CT32B0_CAP0 PIO0_17 PIO1_28 CT32B0_CAP1 PIO1_29 CT32B0_MAT0...
Page 140 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes. The USART, counter/timer, and SSP functions are available on more than one port pin.
Page 141 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 134. LPC11U2x pin description …continued Symbol Reset Type Description state PIO0_6/USB_CONNECT/ I; PU PIO0_6 — General purpose digital input/output pin. SCK0 USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature.
Page 142 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 134. LPC11U2x pin description …continued Symbol Reset Type Description state PIO0_16/AD5/ I; PU PIO0_16 — General purpose digital input/output pin. In CT32B1_MAT3/WAKEUP Deep power-down mode, this pin functions as the WAKEUP pin with 20 ns glitch filter. Pull this pin HIGH externally to enter Deep power-down mode.
Page 143 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 134. LPC11U2x pin description …continued Symbol Reset Type Description state PIO1_4/CT32B1_CAP0 I; PU PIO1_4 — General purpose digital input/output pin. CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. PIO1_5/CT32B1_CAP1 I; PU PIO1_5 —...
Page 144 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 134. LPC11U2x pin description …continued Symbol Reset Type Description state PIO1_21/DCD/MISO1 I; PU PIO1_21 — General purpose digital input/output pin. DCD — Data Carrier Detect input for USART. MISO1 — Master In Slave Out for SSP1.
Page 145: Lpc11U3X Pin Description
UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
Page 146 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 135. LPC11U3x pin description …continued Symbol Reset Type Description state PIO0_3/USB_VBUS/ I; PU PIO0_3 — General purpose digital input/output pin. A IOH_1 LOW level on this pin during reset starts the ISP command handler.
Page 147 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 135. LPC11U3x pin description …continued Symbol Reset Type Description state PIO0_9/MOSI0/ I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1/R/IOH_7 MOSI0 — Master Out Slave In for SSP0. CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
Page 148 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 135. LPC11U3x pin description …continued Symbol Reset Type Description state PIO0_16/AD5/ I; PU PIO0_16 — General purpose digital input/output pin. CT32B1_MAT3/IOH_8/ In Deep power-down mode, this pin functions as the WAKEUP WAKEUP pin with 20 ns glitch filter.
Page 149 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 135. LPC11U3x pin description …continued Symbol Reset Type Description state PIO1_0/CT32B1_MAT0/ I; PU PIO1_0 — General purpose digital input/output pin. IOH_10 CT32B1_MAT0 — Match output 0 for 32-bit timer 1. IOH_10 — I/O Handler input/output 10.
Page 150 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 135. LPC11U3x pin description …continued Symbol Reset Type Description state PIO1_13/DTR/ I; PU PIO1_13 — General purpose digital input/output pin. CT16B0_MAT0/TXD DTR — Data Terminal Ready output for USART. CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
Page 151 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration Table 135. LPC11U3x pin description …continued Symbol Reset Type Description state PIO1_25/CT32B0_MAT1 I; PU PIO1_25 — General purpose digital input/output pin. CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_26/CT32B0_MAT2/ G2 11 I;...
Page 152 UM10462 NXP Semiconductors Chapter 8: LPC11U3x/2x/1x Pin configuration 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant; includes digital input glitch filter.
Page 153: Chapter 9: Lpc11U3X/2X/1X Gpio
UM10462 Chapter 9: LPC11U3x/2x/1x GPIO Rev. 5.5 — 21 December 2016 User manual 9.1 How to read this chapter All GPIO registers refer to 32 pins on each port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO registers are reserved (see Table 136).
Page 154: Gpio Port Features
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO • Two group interrupts are supported to reflect two distinct interrupt patterns. • The GPIO group interrupts can wake up the part from sleep, deep-sleep or power-down modes. 9.3.3 GPIO port features •...
Page 155 UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO The GPIO interrupt registers are listed in Table 137 Section 9.5.1 • The GPIO GROUP0 interrupt block at address 0x4005 C000. Registers in this block allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The...
Page 156 UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 139. Register overview: GPIO GROUP1 interrupt (base address 0x4006 0000) Name Access Address Description Reset Reference offset value CTRL 0x000 GPIO grouped interrupt control Table 151 register PORT_POL0 R/W 0x020 GPIO grouped interrupt port 0 polarity...
Page 157: Gpio Pin Interrupts Register Description
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO 9.5.1 GPIO pin interrupts register description 9.5.1.1 Pin interrupt mode register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 40), one bit in the ISEL register determines whether the interrupt is edge or level sensitive.
Page 158: Pin Interrupt Level (Rising Edge Interrupt) Clear Register
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 143. Pin interrupt level (rising edge) interrupt set register (SIENR, address 0x4004 C008) bit description Symbol Description Reset Access value SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts.
Page 159: Pin Interrupt Active Level (Falling Edge) Interrupt Set Register
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 145. Pin interrupt active level (falling edge) interrupt enable register (IENF, address 0x4004 C010) bit description Symbol Description Reset Access value ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt.
Page 160: Pin Interrupt Rising Edge Register
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 147. Pin interrupt active level (falling edge) interrupt clear register (CIENF, address 0x4004 C018) bit description Symbol Description Reset Access value CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts.
Page 161: Pin Interrupt Status Register
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO 9.5.1.10 Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones to this register clears both rising- and falling-edge detection for the pin. For level-sensitive pins, writing ones inverts the corresponding bit in the Active level register, thus switching the active level on the pin.
Page 162: Gpio Grouped Interrupt Port Enable Registers
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 152. GPIO grouped interrupt port 0 polarity registers (PORT_POL0, addresses 0x4005 C020 (GROUP0 INT) and 0x4006 0020 (GROUP1 INT)) bit description Symbol Description Reset Access value 31:0 POL0 Configure pin polarity of port 0 pins for group interrupt. Bit n corresponds to pin P0_n of port 0.
Page 163: Gpio Port Register Description
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO 9.5.3 GPIO port register description 9.5.3.1 GPIO port byte pin registers Each GPIO pin has a byte register in this address range. Software typically reads and writes bytes to access individual pins, but can read or write halfwords to sense or set the state of two pins, and read or write words to sense or set the state of four pins.
Page 164: Gpio Port Direction Registers
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 159. GPIO port 1 word pin registers (W32 to W63, addresses 0x5000 1080 to 0x5000 10FC) bit description Symbol Description Reset Access value 31:0 PWORD Read 0: pin is LOW. Write 0: clear output bit.
Page 165: Gpio Port Pin Registers
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 163. GPIO mask port 1 register (MASK1, address 0x5000 2084) bit description Symbol Description Reset Access value 31:0 MASKP1 Controls which bits corresponding to P1_n are active in the P1MPORT register (bit 0 = P1_0, bit 1 = P1_1, ..., bit 31 = P1_31).
Page 166: Gpio Port Set Registers
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 167. GPIO masked port 1 pin register (MPIN1, address 0x5000 2184) bit description Symbol Description Reset Access value 31:0 MPORTP1 Masked port register (bit 0 = P1_0, bit 1 = P1_1, ..., bit 31 = P1_31).
Page 167: Functional Description
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 172. GPIO toggle port 0 register (NOT0, address 0x5000 2300) bit description Symbol Description Reset Access value 31:0 NOTP0 Toggle output bits: 0 = no operation. 1 = Toggle output bit. Table 173. GPIO toggle port 1 register (NOT1, address 0x5000 2304) bit description...
Page 168: Masked I/O
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO • Writing to a port’s MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port’s MASK register. • Writing ones to a port’s SET register sets output bits.
Page 169: Group Interrupts
UM10462 NXP Semiconductors Chapter 9: LPC11U3x/2x/1x GPIO Table 174. Pin interrupt registers for edge- and level-sensitive pins Name Edge-sensitive function Level-sensitive function IENR Enables rising-edge interrupts. Enables level interrupts. SIENR Write to enable rising-edge interrupts. Write to enable level interrupts.
Page 170: How To Read This Chapter
Rev. 5.5 — 21 December 2016 User manual 10.1 How to read this chapter The USB on-chip drivers are available on parts LPC11U2x and LPC11U3x only. 10.2 Introduction The boot ROM contains a USB driver to simplify the USB application development. The USB driver implements the Communication Device Class (CDC), the Human Interface Device (HID), and the Mass Storage Device (MSC) device class.
Page 171: Calling The Usb Device Driver
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers – USB descriptors data structure (Table 191 “_USB_CORE_DESCS_T class structure”) – USB device stack initialization parameter data structure (Table 200 “USBD_API_INIT_PARAM class structure”). – USB device stack core API functions structure (Table 203 “USBD_CORE_API...
Page 172: Nxp B.v. 2016. All Rights Reserved
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers const USBD_DFU_API_T* dfu; const USBD_HID_API_T* hid; const USBD_CDC_API_T* cdc; const uint32_t* reserved6; const uint32_t version; } USBD_API_T; Ptr to USB ROM Driver table USB API 0x1FFF 1FF8 USB hardware function table...
Page 173: Descriptor
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 176. _BM_T class structure Member Description Recipient uint8_t _BM_T::Recipient Recipient type. Type uint8_t _BM_T::Type Request type. uint8_t _BM_T::Dir Direction type. 10.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR Table 177. _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR class structure Member Description bFunctionLength...
Page 174: Cdc_Union_1Slave_Descriptor
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 180. _CDC_LINE_CODING class structure Member Description dwDTERate uint32_t _CDC_LINE_CODING::dwDTERate bCharFormat uint8_t _CDC_LINE_CODING::bCharFormat bParityType uint8_t _CDC_LINE_CODING::bParityType bDataBits uint8_t _CDC_LINE_CODING::bDataBits 10.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR Table 181. _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR::sUnion...
Page 175: Hid_Report_T
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 184. _HID_DESCRIPTOR class structure Member Description bLength uint8_t _HID_DESCRIPTOR::bLength Size of the descriptor, in bytes. bDescriptorType uint8_t _HID_DESCRIPTOR::bDescriptorType Type of HID descriptor. bcdHID uint16_t _HID_DESCRIPTOR::bcdHID BCD encoded version that the HID descriptor and device complies to.
Page 176: Msc_Cbw
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers 10.5.13 _MSC_CBW Table 187. _MSC_CBW class structure Member Description dSignature uint32_t _MSC_CBW::dSignature dTag uint32_t _MSC_CBW::dTag dDataLength uint32_t _MSC_CBW::dDataLength bmFlags uint8_t _MSC_CBW::bmFlags bLUN uint8_t _MSC_CBW::bLUN bCBLength uint8_t _MSC_CBW::bCBLength uint8_t _MSC_CBW::CB[16][16] 10.5.14 _MSC_CSW Table 188.
Page 177: Usb_Core_Descs_T
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers 10.5.17 _USB_CORE_DESCS_T USB descriptors data structure. Table 191. _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t * _USB_CORE_DESCS_T::device_desc Pointer to USB device descriptor string_desc uint8_t * _USB_CORE_DESCS_T::string_desc Pointer to array of USB string descriptors...
Page 178: Usb_Interface_Descriptor
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 193. _USB_DFU_FUNC_DESCRIPTOR class structure Member Description bLength uint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength bDescriptorType uint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType bmAttributes uint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes wDetachTimeOut uint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut wTransferSize uint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize bcdDFUVersion uint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion 10.5.20 _USB_INTERFACE_DESCRIPTOR Table 194. _USB_INTERFACE_DESCRIPTOR class structure...
Page 179: Usb_Other_Speed_Configuration 178 _Usb_Setup_Packet
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 195. _USB_OTHER_SPEED_CONFIGURATION class structure Member Description bLength uint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength Size of descriptor bDescriptorType uint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType Other_speed_Configuration Type wTotalLength uint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength Total length of data returned bNumInterfaces uint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces Number of interfaces supported by this speed configuration...
Page 180: Wb_T
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 197. _USB_STRING_DESCRIPTOR class structure Member Description bLength uint8_t _USB_STRING_DESCRIPTOR::bLength Size of this descriptor in bytes bDescriptorType uint8_t _USB_STRING_DESCRIPTOR::bDescriptorType STRING Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR::bString UNICODE encoded string 10.5.24 _WB_T Table 198. _WB_T class structure...
Page 181: Usbd_Api_Init_Param
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 199. USBD_API class structure Member Description const USBD_CDC_API_T* USBD_API::cdc Pointer to function table which exposes functions provided by CDC-ACM function driver module. reserved6 const uint32_t* USBD_API::reserved6 Reserved for future function driver module.
Page 182 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 200. USBD_API_INIT_PARAM class structure Member Description USB_Suspend_Event USB_CB_T USBD_API_INIT_PARAM::USB_Suspend_Event Event for USB suspend. This event fires when the USB host suspends the device by halting its transmission of Start Of Frame pulses to the device. This is generally hooked in order to move the device over to a low power state until the host wakes up the device.
Page 183 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 200. USBD_API_INIT_PARAM class structure Member Description USB_WakeUpCfg USB_PARAM_CB_T USBD_API_INIT_PARAM::USB_WakeUpCfg Event for remote wake-up configuration, when enabled. This event fires when the USB host request the device to configure itself for remote wake-up capability. The USB host sends this request to device which report remote wake-up capable in their device descriptors, before going to low-power state.
Page 184: Usbd_Cdc_Api
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 200. USBD_API_INIT_PARAM class structure Member Description USB_Feature_Event USB_CB_T USBD_API_INIT_PARAM::USB_Feature_Event Event for USB feature changed. This event fires when a the USB host send set/clear feature request. The stack handles this request for USB_FEATURE_REMOTE_WAKEUP, USB_FEATURE_TEST_MODE and USB_FEATURE_ENDPOINT_STALL features only.
Page 185: Usbd_Cdc_Init_Param
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 201. USBD_CDC_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param, USBD_HANDLE_T *phCDC) Function to initialize CDC function driver module. This function is called by application layer to initialize CDC function driver module.
Page 186 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_CDC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller.
Page 187 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) Communication Interface Class specific set request call-back function. This function is provided by the application software. This function gets called when host sends a CIC management element requests.
Page 188 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description CDC_BulkOUT_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkOUT_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Communication Device Class specific BULK OUT endpoint handler. The application software should provide the BULK OUT endpoint handler. Applications should transfer data depending on the communication protocol type set in descriptors.
Page 189 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description GetEncpsResp ErrorCode_t(* USBD_CDC_INIT_PARAM::GetEncpsResp)(USBD_HANDLE_T hCDC, uint8_t **buffer, uint16_t *len) Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request call-back function. This function is provided by the application software. This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request.
Page 190 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description GetCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::GetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t **pBuffer, uint16_t *len) Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request.
Page 191 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description ClrCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature) Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a CLEAR_COMM_FEATURE request.
Page 192 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description SetCtrlLineState ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state) Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function. This function is provided by the application software. This function gets called when host sends a SET_CONTROL_LINE_STATE request.
Page 193 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding) Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. This function is provided by the application software. This function gets called when host sends a SET_LINE_CODING request.
Page 194: Usbd_Core_Api
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 202. USBD_CDC_INIT_PARAM class structure Member Description CDC_Ep0_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user override-able function to replace the default CDC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 195 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 203. USBD_CORE_API class structure Member Description RegisterEpHandler ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void *data) Function to register interrupt/event handler for the requested endpoint with USB device stack. The application layer uses this function to register the custom class's EP0 handler. The stack calls all the registered class handlers on any EP0 event before going through default handling of the event.
Page 196 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 203. USBD_CORE_API class structure Member Description DataOutStage void(*void USBD_CORE_API::DataOutStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in data_out state. This function is called by USB stack and the application layer to set the EP0 state machine in data_out state.
Page 197: Usbd_Dfu_Api
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 203. USBD_CORE_API class structure Member Description StallEp0 void(*void USBD_CORE_API::StallEp0)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in stall state. This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint.
Page 198: Usbd_Dfu_Init_Param
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 204. USBD_DFU_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_DFU_API::GetMemSize)(USBD_DFU_INIT_PARAM_T *param) Function to determine the memory required by the DFU function driver module. This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used by DFU function driver module.
Page 199 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 205. USBD_DFU_INIT_PARAM class structure Member Description wTransferSize uint16_t USBD_DFU_INIT_PARAM::wTransferSize DFU transfer block size in number of bytes. This value should match the value set in DFU descriptor provided as part of the descriptor array (...
Page 200: Usbd_Hid_Api
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 205. USBD_DFU_INIT_PARAM class structure Member Description DFU_Detach void(* USBD_DFU_INIT_PARAM::DFU_Detach)(USBD_HANDLE_T hUsb) DFU detach callback function. This function is provided by the application software. This function gets called after USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH bit in DFU descriptor should define this function.
Page 201: Usbd_Hid_Init_Param
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 206. USBD_HID_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HID_API::GetMemSize)(USBD_HID_INIT_PARAM_T *param) Function to determine the memory required by the HID function driver module. This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used by HID function driver module.
Page 202 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 207. USBD_HID_INIT_PARAM class structure Member Description mem_base uint32_t USBD_HID_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. Also this value should be aligned on 4 byte boundary.
Page 203 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 207. USBD_HID_INIT_PARAM class structure Member Description HID_SetReport ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) HID set report callback function. This function is provided by the application software. This function gets called when host sends a HID_REQUEST_SET_REPORT request.
Page 204 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 207. USBD_HID_INIT_PARAM class structure Member Description HID_SetIdle ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetIdle)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t idleTime) Optional callback function to handle HID_REQUEST_SET_IDLE request. The application software could provide this callback to handle HID_REQUEST_SET_IDLE requests sent by the host.
Page 205 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 207. USBD_HID_INIT_PARAM class structure Member Description HID_EpIn_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpIn_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt IN endpoint event handler. The application software could provide Interrupt IN endpoint event handler. Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member.
Page 206 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 207. USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt OUT endpoint event handler. The application software could provide Interrupt OUT endpoint event handler. Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member.
Page 207: Usbd_Hw_Api
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 207. USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default HID class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 208 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HW_API::GetMemSize)(USBD_API_INIT_PARAM_T *param) Function to determine the memory required by the USB device stack's DCD and core layers. This function is called by application layer before calling pUsbApi->hw->GetMemSize Remark: Some memory areas are not accessible by all bus masters.
Page 209 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description void(*void USBD_HW_API::ISR)(USBD_HANDLE_T hUsb) Function to USB device controller interrupt events. When the user application is active the interrupt handlers are mapped in the user flash space. The user application must provide an interrupt handler for the USB interrupt and call this function in the interrupt handler routine.
Page 210 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description WakeUpCfg void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg) Function to configure USB device controller to walk-up host on remote events. This function is called by application layer to configure the USB device controller to wake up on remote events.
Page 211 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description ConfigEP void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) Function to configure USB Endpoint according to descriptor. This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received by the stack from USB host. All the endpoints associated with the selected configuration are configured.
Page 212 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description EnableEP void(*void USBD_HW_API::EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to enable selected USB endpoint. This function enables interrupts on selected endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
Page 213 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description SetStallEP void(*void USBD_HW_API::SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to STALL selected USB endpoint. Generates STALL signalling for requested endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
Page 214 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description ReadEP uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) Function to read data received on the requested endpoint. This function is called by USB stack and the application layer to read the data received on the requested endpoint.
Page 215: Usbd_Msc_Api
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 208. USBD_HW_API class structure Member Description WriteEP uint32_t(*uint32_t USBD_HW_API::WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt) Function to write data to be sent on the requested endpoint. This function is called by USB stack and the application layer to send data on the requested endpoint.
Page 216: Usbd_Msc_Init_Param
UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 209. USBD_MSC_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_MSC_API::GetMemSize)(USBD_MSC_INIT_PARAM_T *param) Function to determine the memory required by the MSC function driver module. This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used by MSC function driver module.
Page 217 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 210. USBD_MSC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_MSC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller.
Page 218 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 210. USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t offset, uint8_t **dst, uint32_t length) MSC Read callback function. This function is provided by the application software. This function gets called when host sends a read command.
Page 219 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 210. USBD_MSC_INIT_PARAM class structure Member Description MSC_Verify ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Verify)(uint32_t offset, uint8_t buf[], uint32_t length) MSC Verify callback function. This function is provided by the application software. This function gets called when host sends a verify command.
Page 220 UM10462 NXP Semiconductors Chapter 10: LPC11U3x/2x/1x USB on-chip drivers Table 210. USBD_MSC_INIT_PARAM class structure Member Description MSC_Ep0_Hdlr ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default MSC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 221: Chapter 11: Lpc11U3X/2X/1X Usb2.0 Device Controller
(SOF) marker and transactions that transfer data to or from device endpoints. Each device can have a maximum of 16 logical or 32 physical endpoints. The LPC11U3x/2x/1x device controller supports up to 10 physical endpoints. There are four types of transfers defined for the endpoints.
Page 222 Chapter 11: LPC11U3x/2x/1x USB2.0 device controller For more information on the Universal Serial Bus, see the USB Implementers Forum website. The USB device controller on the LPC11U3x/2x/1x enables full-speed (12 Mb/s) data exchange with a USB host controller. Figure 20 shows the block diagram of the USB device controller.
Page 223: Usb Software Interface
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.4.1 USB software interface USB EP List Start Address EP_LIST 0x00 CS = Endpoint Control /Status bits SRAM NBytes ADDR OFFSET 1 NBytes ADDR OFFSET 2 USB Data Buffer Start Address...
Page 224: Interrupts
A device will go into the L2 suspend state if there is no activity on the USB bus for more than 3 ms. A suspended device wakes up, if there is transmission from the host (host-initiated wake up). The USB controller on the LPC11U3x/2x/1x also supports software initiated remote wake-up. To initiate remote wake-up, software on the device must enable all clocks and clear the suspend bit.
Page 225: Clocking
NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.4.7 Clocking The LPC11U3x/2x/1x USB device controller has the following clock connections: • USB main clock: The USB main clock is the 48 MHz +/- 500 ppm clock from the dedicated USB PLL or the main clock (see Table 28).
Page 226: (Devcmdstat)
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 213. Register overview: USB (base address: 0x4008 0000) Name Access Address Description Reset Reference offset value INTSETSTAT 0x028 USB set interrupt status register 0 Table 224 INTROUTING 0x02C USB interrupt routing register...
Page 227 UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 214. USB Device Command/Status register (DEVCMDSTAT, address 0x4008 0000) bit description Symbol Value Description Reset Access value DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect.
Page 228: Usb Info Register (Info)
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 214. USB Device Command/Status register (DEVCMDSTAT, address 0x4008 0000) bit description Symbol Value Description Reset Access value Reserved. VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high.
Page 229: (Databufstart)
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 216. USB EP Command/Status List start address (EPLISTSTART, address 0x4008 0008) bit description Symbol Description Reset Access value Reserved 31:8 EP_LIST Start address of the USB EP Command/Status List. 11.6.4 USB Data buffer start address (DATABUFSTART) This register indicates the page of the AHB address where the endpoint data can be located.
Page 230: Usb Endpoint Skip (Epskip)
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.6.6 USB Endpoint skip (EPSKIP) Table 219. USB Endpoint skip (EPSKIP, address 0x4008 0014) bit description Symbol Description Reset Access value 29:0 SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software.
Page 231: Usb Interrupt Status Register (Intstat)
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.6.9 USB interrupt status register (INTSTAT) Table 222. USB interrupt status register (INTSTAT, address 0x4008 0020) bit description Symbol Description Reset Access value EP0OUT Interrupt status register bit for the Control EP0 OUT direction.
Page 232: Usb Interrupt Enable Register (Inten)
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 222. USB interrupt status register (INTSTAT, address 0x4008 0020) bit description Symbol Description Reset Access value EP3IN Interrupt status register bit for the EP3 IN direction. R/WC This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.
Page 233: Usb Set Interrupt Status Register
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.6.11 USB set interrupt status register (INTSETSTAT) Table 224. USB set interrupt status register (INTSETSTAT, address 0x4008 0028) bit description Symbol Description Reset Access value EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
Page 234: Functional Description
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.7 Functional description 11.7.1 Endpoint command/status list Figure 22 gives an overview on how the Endpoint List is organized in memory. The USB EP Command/Status List start register points to the start of the list that contains all the endpoint information in memory.
Page 235 UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 227. Endpoint commands Symbol Access Description Active The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word.
Page 236 UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Table 227. Endpoint commands Symbol Access Description Endpoint Type 0: Generic endpoint. The endpoint is configured as a bulk or interrupt endpoint 1: Isochronous endpoint NBytes For OUT endpoints this is the number of bytes that can be received in this buffer.
Page 237: Control Endpoint 0
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.7.2 Control endpoint 0 Wait on EP 0Setup /Out interrupt EP0Setup/Out Interrupt = ‘1’ ? If not all IN data transferred , the - Write EP0OUT(Active = ‘1’ host aborts Control Read .
Page 238: Generic Endpoint: Single-Buffering
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Wait on EP 0In interrupt EP0In Interrupt = ‘1’ ? If not all OUT data transferred , the host aborts Control Write . - Write EP0IN( Active = ‘1’ Otherwise it is a normal completion Stall = ‘1’...
Page 239: Generic Endpoint: Double-Buffering
UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller Software must wait until hardware has cleared the Active bit to change some of the command/status bits. This prevents hardware from overwriting a new value programmed by software with some old values that were still cached.
Page 240: Set Configuration
11.7.6 USB wake-up 11.7.6.1 Waking up from Deep-sleep and Power-down modes on USB activity To allow the LPC11U3x/2x/1x to wake up from Deep-sleep or Power-down mode on USB activity, complete the following steps: 1. Set bit AP_CLK in the USBCLKCTRL register...
Page 241 UM10462 NXP Semiconductors Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 5. Wait until the USB leaves the suspend state by polling the DSUS bit in the DSVCMD_STAT register (DSUS =0). 6. Clear the AP_CLK bit (Table 41, bit 0) in the USBCLKCTRL to enable automatic USB clock control.
Page 242: How To Read This Chapter
Chapter 12: LPC11U3x/2x/1x USART Rev. 5.5 — 21 December 2016 User manual 12.1 How to read this chapter The USART controller is available on all LPC11U3x/2x/1x parts. 12.2 Basic configuration The USART is configured as follows: • Pins: The USART pins must be configured in the corresponding IOCON registers (see Section 7.4).
Page 243: Register Description
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 12.5 Register description The USART contains registers organized as shown in Table 229. The Divisor Latch Access Bit (DLAB) is contained in the LCR register bit 7 and enables access to the Divisor Latches.
Page 244: Usart Receiver Buffer Register (When Dlab = 0, Read Only)
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 229. Register overview: USART (base address: 0x4000 8000) Name Access Address Description Reset Reference offset value RS485CTRL 0x04C RS-485/EIA-485 Control. Contains controls to Table 253 configure various aspects of RS-485/EIA-485 modes. RS485ADRMATCH 0x050 RS-485/EIA-485 address match.
Page 245: Usart Divisor Latch Lsb And Msb Registers
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 12.5.3 USART Divisor Latch LSB and MSB Registers (when DLAB = 1) The USART Divisor Latch is part of the USART Baud Rate Generator and holds the value used (optionally with the Fractional Divider) to divide the UART_PCLK clock in order to produce the baud rate clock, which must be the multiple of the desired baud rate that is specified by the Oversampling Register (typically 16X).
Page 246: Usart Interrupt Identification Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 234. USART Interrupt Enable Register when DLAB = 0 (IER - address 0x4000 8004) bit description …continued Symbol Value Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 247 UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Bits IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register.
Page 248: Only)
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 236. USART Interrupt Handling IIR[3:0] Priority Interrupt Interrupt source Interrupt value type reset 1100 Second Character Minimum of one character in the RX FIFO and no Time-out character input or removed during a time period...
Page 249: Usart Line Control Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 237. USART FIFO Control Register Write only (FCR - address 0x4000 8008) bit description Symbol Value Description Reset value FIFOEN FIFO enable USART FIFOs are disabled. Must not be used in the application.
Page 250: Usart Modem Control Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 238. USART Line Control Register (LCR - address 0x4000 800C) bit description Symbol Value Description Reset Value Parity Enable Disable parity generation and checking. Enable parity generation and checking. Parity Select Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
Page 251: Auto-Flow Control
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 239. USART Modem Control Register (MCR - address 0x4000 8010) bit description Symbol Value Description Reset value RTSEN RTS enable Disable auto-rts flow control. Enable auto-rts flow control. CTSEN CTS enable Disable auto-cts flow control.
Page 252: Auto-Cts
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART UART1 Rx start byte N stop start bits0..7 stop start bits0..7 stop RTS1 pin UART1 Rx FIFO read UART1 Rx FIFO level Fig 25. Auto-RTS Functional Timing 12.5.8.1.2 Auto-CTS The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled, the transmitter circuitry checks the CTS input before sending the next data byte.
Page 253: Usart Line Status Register (Read-Only)
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART UART1 TX start bits0..7 stop start bits0..7 stop start bits0..7 stop CTS1 pin Fig 26. Auto-CTS Functional Timing During transmission of the second character the CTS signal is negated. The third character is not sent thereafter. The USART maintains 1 on TXD as long as CTS is negated (high).
Page 254 UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 241. USART Line Status Register Read only (LSR - address 0x4000 8014) bit description …continued Symbol Value Description Reset Value Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs.
Page 255: Usart Modem Status Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 12.5.10 USART Modem Status Register The MSR is a read-only register that provides status information on USART input signals. Bit 0 is cleared when (after) this register is read. Table 242: USART Modem Status Register (MSR - address 0x4000 8018) bit description...
Page 256: Usart Auto-Baud Control Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 12.5.12 USART Auto-baud Control Register The USART Auto-baud Control Register (ACR) controls the process of measuring the incoming clock/data rate for baud rate generation, and can be read and written at the user’s discretion.
Page 257: Auto-Baud Modes
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Two auto-baud measuring modes are available which can be selected by the ACR Mode bit. In Mode 0 the baud rate is measured on two subsequent falling edges of the USART Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the USART Rx pin (the length of the start bit).
Page 258: Irda Control Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 6. The rate counter is loaded into DLM/DLL and the baud rate will be switched to normal operation. After setting the DLM/DLL, the end of auto-baud interrupt IIR ABEOInt will be set, if enabled. The RSR will now continue receiving the remaining bits of the character.
Page 259 UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 245: IrDA Control Register (ICR - 0x4000 8024) bit description Symbol Value Description Reset value IRDAEN IrDA mode enable IrDA mode is disabled. IrDA mode is enabled. IRDAINV Serial input inverter The serial input is not inverted.
Page 260: Usart Fractional Divider Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 12.5.14 USART Fractional Divider Register The USART Fractional Divider Register (FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements.
Page 261: Baud Rate Calculation
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART 12.5.14.1 Baud rate calculation The USART can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values.
Page 262 UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 263: Example 1: Uart_Pclk = 14.7456 Mhz, Br
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 248. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
Page 264: Usart Transmit Enable Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 249. USART Oversampling Register (OSR - address 0x4000 802C) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 265: Uart Half-Duplex Enable Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 250. USART Transmit Enable Register (TER - address 0x4000 8030) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 266: Usart Rs485 Control Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 252. Smart Card Interface Control register (SCICTRL - address 0x4000 8048) bit description Symbol Value Description Reset value SCIEN Smart Card Interface Enable. Smart card interface disabled. Asynchronous half duplex smart card interface is enabled.
Page 267: Usart Rs-485 Address Match Register
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 253. USART RS485 Control register (RS485CTRL - address 0x4000 804C) bit description …continued Symbol Value Description Reset value RXDIS Receiver enable. The receiver is enabled. The receiver is disabled. AADEN AAD enable.
Page 268 UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART Table 255. USART RS-485 Delay value register (RS485DLY - address 0x4000 8054) bit description Symbol Description Reset value Contains the direction control (RTS or DTR) delay value. This 0x00 register works in conjunction with an 8-bit counter.
Page 269 N cycles whenever data is to be sent in either direction. (N being the number of bits/character.) When the LPC11U3x/2x/1x USART is the clock source (CSRC=1), such half-duplex operation can lead to the rather artificial-seeming requirement of writing a dummy character to the Transmitter Holding Register in order to generate 8 clocks so that a character can be received.
Page 270: Usart Synchronous Mode Control Register 268 Functional Description
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART CSCEN=1 and CCCLR=1. After the USART has sent N clock cycles and thus received a character, it clears the CSCEN bit. If more characters need to be received thereafter, software can repeat setting CSCEN and CCCLR.
Page 271: Rs-485/Eia-485 Auto Direction Control
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO.
Page 272: Smart Card Set-Up Procedure
Software must use timers to implement character and block waiting times (no hardware support via trigger signals is provided on the LPC11U3x/2x/1x). GPIO pins can be used to control the smart card reset and power pins. Any power supplied to the card must be externally switched as card power supply requirements often exceed source currents possible on the LPC11U3x/2x/1x.
Page 273: Architecture
UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART • If necessary, program PRESETCTRL (Table 8) so that the USART is not continuously reset. • Program one IOCON register to enable a USART TXD function. • If the smart card requires a clock, program one IOCON register to select the USART SCLK function.
Page 274 UM10462 NXP Semiconductors Chapter 12: LPC11U3x/2x/1x USART MODEM TXD1 NTXRDY DTR/DIR NBAUDOUT RTS/DIR RCLK INTERRUPT RXD1 NRXRDY U1INTR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 31. USART block diagram UM10462 All information provided in this document is subject to legal disclaimers.
Page 275: Chapter 13: Lpc11U3X/2X/1X Ssp/Spi
Rev. 5.5 — 21 December 2016 User manual 13.1 How to read this chapter Two SSP/SPI interfaces are available on all LPC11U3x/2x/1x parts. 13.2 Basic configuration The SSP0/1 are configured using the following registers: 1. Pins: The SSP/SPI pins must be configured in the IOCON register block.
Page 276: Pin Description
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI 13.5 Pin description Table 257. SSP/SPI pin descriptions Interface pin name/function Type Pin description name Microwire SCK0/1 Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave.
Page 277: Ssp/Spi Control Register 0
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI Remark: Register names use the SSP prefix to indicate that the SPI controllers have full SSP capabilities. Table 258. Register overview: SSP/SPI0 (base address 0x4004 0000) Name Access Address Description Reset Reference offset...
Page 278: Ssp/Spi Control Register 1
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI Table 260. SSP/SPI Control Register 0 (CR0 - address 0x4004 0000 (SSP0) and 0x4005 8000 (SSP1)) bit description Symbol Value Description Reset Value Data Size Select. This field controls the number of bits 0000 transferred in each frame.
Page 279: Ssp/Spi Data Register
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI Table 261. SSP/SPI Control Register 1 (CR1 - address 0x4004 0004 (SSP0) and 0x4005 8004 (SSP1)) bit description Symbol Value Description Reset Value Loop Back Mode. During normal operation. Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
Page 280: Ssp/Spi Status Register
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI 13.6.4 SSP/SPI Status Register This read-only register reflects the current status of the SPI controller. Table 263. SSP/SPI Status Register (SR - address 0x4004 000C (SSP0) and 0x4005 800C (SSP1)) bit description Symbol...
Page 281: Ssp/Spi Raw Interrupt Status Register
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI Table 265. SSP/SPI Interrupt Mask Set/Clear register (IMSC - address 0x4004 0014 (SSP0) and 0x4005 8014 (SSP1)) bit description Symbol Description Reset Value RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received.
Page 282: Ssp/Spi Interrupt Clear Register
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI Table 267. SSP/SPI Masked Interrupt Status register (MIS - address 0x4004 001C (SSP0) and 0x4005 801C (SSP1)) bit description Symbol Description Reset value RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
Page 283: Spi Frame Format
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI DX/DR 4 to 16 bits a. Single frame transfer DX/DR 4 to 16 bits 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 32. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two...
Page 284: Spi Format With Cpol=0,Cpha=0
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
Page 285: Spi Format With Cpol=0,Cpha=1
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.
Page 286 UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI SSEL MOSI MISO 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SSEL MOSI MISO 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 35. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: •...
Page 287: Spi Format With Cpol = 1,Cpha = 1
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI 13.7.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 36, which covers both single and continuous transfers.
Page 288 UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI 8-bit control 4 to 16 bits of output data Fig 37. Microwire frame format (single transfer) 8-bit control 4 to 16 bits 4 to 16 bits of output data of output data Fig 38. Microwire frame format (continuous transfers) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique.
Page 289: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode
UM10462 NXP Semiconductors Chapter 13: LPC11U3x/2x/1x SSP/SPI turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO.
Page 290: Chapter 14: Lpc11U3X/2X/1X I2C-Bus Controller
Rev. 5.5 — 21 December 2016 User manual 14.1 How to read this chapter The I C-bus block is identical for all LPC11U3x/2x/1x parts. 14.2 Basic configuration The I C-bus interface is configured using the following registers: 1. Pins: The I2C pin functions and the I2C mode are configured in the IOCON register...
Page 291: I 2 C Fast-Mode Plus
C Fast-mode Plus Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I C-bus products which NXP Semiconductors is now providing. UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
Page 292: Pin Description
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.6 Pin description Table 269. I C-bus pin description Type Description Input/Output C Serial Data Input/Output C Serial Clock The I C-bus pins must be configured through the IOCON_PIO0_4 (Table 80) and...
Page 293: I 2 C Control Set Register (Conset)
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 270. Register overview: I C (base address 0x4000 0000) …continued Name Access Address Description Reset Reference offset value ADR2 0x024 I2C Slave Address Register 2. Contains the 7-bit slave 0x00 Table 280...
Page 294 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 271. I C Control Set register (CONSET - address 0x4000 0000) bit description Symbol Description Reset value START flag. I2EN C interface enable. 31:7 - Reserved. The value read from a reserved bit is not defined.
Page 295: I 2 C Status Register (Stat)
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: 1.
Page 296: I 2 C Slave Address Register 0 (Adr0)
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.7.4 I C Slave Address register 0 (ADR0) This register is readable and writable and are only used when an I C interface is set to slave mode. In master mode, this register has no effect. The LSB of the ADR register is the General Call bit.
Page 297: I 2 C Control Clear Register (Conclr)
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 277. SCLL + SCLH values for selected I C clock values C mode C bit I2C_PCLK (MHz) frequency SCLH + SCLL Standard mode 100 kHz Fast-mode 400 kHz Fast-mode Plus 1 MHz SCLL and SCLH values should not necessarily be the same.
Page 298: I 2 C Monitor Mode Control Register (Mmctrl) 297 Interrupt In Monitor Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 279. I C Monitor mode control register (MMCTRL - 0x4000 001C) bit description Symbol Value Description Reset value MM_ENA Monitor mode enable. Monitor mode disabled. The I C module will enter monitor mode. In this mode the SDA output will be forced high.
Page 299: Loss Of Arbitration In Monitor Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus. 14.7.7.2 Loss of arbitration in Monitor mode In monitor mode, the I C module will not be able to respond to a request for information by the bus master or issue an ACK).
Page 300: I 2 C Mask Registers (Mask[0, 1, 2, 3])
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 281. I C Data buffer register (DATA_BUFFER - 0x4000 002C) bit description Symbol Description Reset value Data This register holds contents of the 8 MSBs of the DAT shift register. 31:8 - Reserved.
Page 301: Input Filters And Output Stages
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller ADDRESS REGISTERS I2CnADDR0 to I2CnADDR3 MATCHALL I2CnMMCTRL[3] MASK REGISTERS MASK and COMPARE I2CnMASK0 to I2CnMASK3 INPUT FILTER I2CnDATABUFFER SHIFT REGISTER OUTPUT I2CnDAT STAGE MONITOR MODE REGISTER I2CnMMCTRL BIT COUNTER/ PCLK ARBITRATION and...
Page 302: Address Registers, Adr0 To Adr3
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.8.2 Address Registers, ADR0 to ADR3 These registers may be loaded with the 7-bit slave address (7 most significant bits) to which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition.
Page 303: Serial Clock Generator
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller SDA line SCL line (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I C master by pulling the SDA line low. Arbitration is lost, and this I C enters Slave Receiver mode.
Page 304: Timing And Control
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller via the I C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.
Page 305: Master Receiver Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the SIC bit in the CONCLR register. THe STA bit should be cleared after writing the slave address.
Page 306: Slave Receiver Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For slave mode, the possible status codes are 0x68, 0x78, or 0xB0.
Page 307: Slave Transmitter Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller mode. After the address and direction bit have been received, the SI bit is set and a valid status code can be read from the Status register (STAT). Refer to Table 291 for the status codes and actions.
Page 308: Master Transmitter Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller • Master Receiver • Slave Receiver • Slave Transmitter Data transfers in each mode of operation are shown in Figure Figure Figure Figure 52, and Figure Table 285 lists abbreviations used in these figures when describing the I C operating modes.
Page 309 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller The master transmitter mode may now be entered by setting the STA bit. The I C logic will now test the I C-bus and generate a START condition as soon as the bus becomes free.
Page 310 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 287. Master Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From DAT To CON (I2CSTAT STA STO SI...
Page 311 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR...
Page 312: Master Receiver Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.10.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 50). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load DAT with the 7-bit slave address and the data direction bit (SLA+R).
Page 313 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 288. Master Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From DAT To CON (STAT) STA STO SI...
Page 314 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
Page 315: Slave Receiver Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.10.3 Slave Receiver mode In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 51). To initiate the slave receiver mode, ADR and CON must be loaded as follows: Table 289.
Page 316 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 291. Slave Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From DAT To CON (STAT) STA STO SI...
Page 317 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 291. Slave Receiver mode …continued Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From DAT To CON (STAT) STA STO SI...
Page 318 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
Page 319: Slave Transmitter Mode
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.10.4 Slave Transmitter mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 52). Data transfer is initialized as in the slave receiver mode. When ADR and...
Page 320 UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller Table 292. Slave Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From DAT To CON (STAT) STA STO SI...
Page 321: Miscellaneous States
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller reception of the own Slave address and one or more Data DATA DATA P OR S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched...
Page 322: Some Special Cases
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller causes the I C block to enter the “not addressed” slave mode (a defined state) and to clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted).
Page 323: Data Transfer After Loss Of Arbitration
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller OTHER MASTER DATA CONTINUES other Master sends retry repeated START earlier Fig 53. Simultaneous Repeated START conditions from two masters 14.10.6.2 Data transfer after loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes (see Figure 42).
Page 324: C-Bus Obstructed By A Low Level On Scl Or Sda
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.10.6.4 I C-bus obstructed by a LOW level on SCL or SDA An I C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on the bus.
Page 325: Initialization
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.10.8 Initialization In the initialization example, the I C block is enabled for both master and slave modes. For each mode, a buffer is used for transmission and reception. The initialization routine performs the following functions: •...
Page 326: Start Master Receive Function
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 2. Set up the Slave Address to which data will be transmitted, and add the Write bit. 3. Write 0x20 to CONSET to set the STA bit. 4. Set up data to be transmitted in Master Transmit buffer.
Page 327: State: 0X10
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 14.11.5.4 State: 0x10 A Repeated START condition has been transmitted. The Slave Address + R/W bit will be transmitted, an ACK bit will be received.
Page 328: State: 0X30
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 6. Write 0x04 to CONSET to set the AA bit. 7. Write 0x08 to CONCLR to clear the SI flag. 8. Increment Master Transmit buffer pointer 9. Exit 14.11.6.4 State: 0x30 Data has been transmitted, NOT ACK received. A STOP condition will be transmitted.
Page 329: State: 0X58
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 4. Exit 5. Write 0x04 to CONSET to set the AA bit. 6. Write 0x08 to CONCLR to clear the SI flag. 7. Increment Master Receive buffer pointer 8. Exit 14.11.7.4 State: 0x58 Data has been received, NOT ACK has been returned.
Page 330: State: 0X78
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 4. Initialize Slave data counter. 5. Exit 14.11.8.4 State: 0x78 Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been received and ACK has been returned. Data will be received and ACK returned. STA is set to restart Master mode after the bus is free again.
Page 331: State: 0X98
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.11.8.8 State: 0x98 Previously addressed with General Call. Data has been received, NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to CONSET to set the AA bit.
Page 332: State: 0Xc0
UM10462 NXP Semiconductors Chapter 14: LPC11U3x/2x/1x I2C-bus controller 2. Write 0x04 to CONSET to set the AA bit. 3. Write 0x08 to CONCLR to clear the SI flag. 4. Increment Slave Transmit buffer pointer. 5. Exit 14.11.9.4 State: 0xC0 Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is entered.
Page 333: Chapter 15: Lpc11U3X/2X/1X 16-Bit Counter/Timers Ct16B0/1
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Rev. 5.5 — 21 December 2016 User manual 15.1 How to read this chapter CT16B0/1 are available on all LPC11U3x/2x/1x parts. The number of capture inputs depends on package size. See Chapter 15.2 Basic configuration The CT16B0/1 counter/timers are configured through the following registers: •...
Page 334: Applications
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 15.4 Applications • Interval timer for counting internal events • Pulse Width Demodulator via capture input • Free running timer • Pulse Width Modulator via match outputs 15.5 General description Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers.
Page 335 UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 295. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000) Name Access Address Description Reset Reference offset value 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR can...
Page 336 UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 296. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000) Name Access Address Description Reset Reference value 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR...
Page 337: Interrupt Register
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Reset value reflects the data stored in used bits only. It does not include reserved bits content. 15.7.1 Interrupt Register The Interrupt Register consists of four bits for the match interrupts and two bits for the capture interrupts.
Page 338: Timer Counter
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 299. Timer Control Register (TCR, address 0x4000 C004 (CT16B0) and 0x4001 0004 (CT16B1)) bit description Symbol Value Description Reset value CRST Counter reset. Do nothing. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK.
Page 339: Match Control Register
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 302: Prescale counter registers (PC, address 0x4000 C010 (CT16B0) and 0x4001 0010 (CT16B1)) bit description Symbol Description Reset value 15:0 Prescale counter value. 31:16 Reserved. 15.7.6 Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter.
Page 340: Match Registers
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 303. Match Control Register (MCR, address 0x4000 C014 (CT16B0) and 0x4001 0014 (CT16B1)) bit description …continued Symbol Value Description Reset value MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
Page 341 UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 305. Capture Control Register (CCR, address 0x4000 C028 (CT16B0)) bit description Symbol Value Description Reset value CAP0RE Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.
Page 342: Capture Registers
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 306. Capture Control Register (CCR, address 0x4001 0028 (CT16B1)) bit description Symbol Value Description Reset value CAP0I Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will generate an interrupt.
Page 343: External Match Register
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 309: Capture register 1 (CR1, address 0x4001 0030 (CT16B1)) bit description Symbol Description Reset value 15:0 Timer counter capture value. 31:16 Reserved. 15.7.10 External Match Register The External Match Register provides both control and status of the external match pins CT16Bn_MAT[1:0].
Page 344: Count Control Register
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 310. External Match Register (EMR, address 0x4000 C03C (CT16B0) and 0x4001 003C (CT16B1)) bit description Symbol Value Description Reset value 7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1.
Page 345 UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input cannot exceed one half of the PCLK clock.
Page 346 UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 312. Count Control Register (CTCR, address 0x4000 C070 (CT16B0)) bit description Symbol Value Description Reset value SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared.
Page 347: Pwm Control Register
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 313. Count Control Register (CTCR, address 0x4001 0070 (CT16B1)) bit description Symbol Value Description Reset value SELCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared.
Page 348: Rules For Single Edge Controlled Pwm Outputs
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 Table 314. PWM Control Register (PWMC, address 0x4000 C074 (CT16B0) and 0x4001 0074 (CT16B1)) bit description Symbol Value Description Reset value PWMEN3 PWM mode enable for channel3. CT16Bn_MAT3 is controlled by EM3.
Page 349: Example Timer Operation
UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 15.8 Example timer operation Figure 57 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset.
Page 350 UM10462 NXP Semiconductors Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[2:0] INTERRUPT CAP[1:0] STOP ON MATCH RESET ON MATCH LOAD[0]...
Page 351: How To Read This Chapter
User manual 16.1 How to read this chapter CT32B0/1 are available on all LPC11U3x/2x/1x parts. The CT32B1_CAP1 input is only available on the TFBGA48 and LQFP64 packages. The CT32B0_CAP1 input is only available on LQFP48, TFBGA48, and LQFP64 packages. For all other packages, the registers controlling the CT32B1_CAP1 and CT32B0_CAP1 inputs are reserved.
Page 352: Applications
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 • For each timer, up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs. 16.4 Applications •...
Page 353 UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 316. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000) Name Access Address Description Reset Reference offset value 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR...
Page 354 UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 317. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000) Name Access Address Description Reset Reference offset value 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR...
Page 355: Interrupt Register
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 16.7.1 Interrupt Register The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be HIGH.
Page 356: Timer Counter Registers
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 320: Timer Control Register (TCR, address 0x4001 4004 (CT32B0) and 0x4001 8004 (CT32B1)) bit description Symbol Value Description Reset value CRST Counter reset. Do nothing. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK.
Page 357: Match Control Register
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 16.7.6 Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown Table 324.
Page 358: Match Registers
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 324: Match Control Register (MCR, address 0x4001 4014 (CT32B0) and 0x4001 8014 (CT32B1)) bit description Symbol Value Description Reset value MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
Page 359 UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 326: Capture Control Register (CCR, address 0x4001 4028 (CT32B0) ) bit description Symbol Value Description Reset value CAP1RE Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.
Page 360: Capture Registers
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 327: Capture Control Register (CCR, address 0x4001 8028 (CT32B1)) bit description Symbol Value Description Reset value CAP1I Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will generate an interrupt.
Page 361 UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 331: External Match Register (EMR, address 0x4001 403C (CT32B0) and 0x4001 803C (CT32B1)) bit description Symbol Value Description Reset value External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin.
Page 362: Count Control Register
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 331: External Match Register (EMR, address 0x4001 403C (CT32B0) and 0x4001 803C (CT32B1)) bit description Symbol Value Description Reset value 11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3.
Page 363 UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Remark: The bit positions for the CAP1 channel count input select (CIS) and edge select bits (SELCC) are different for counter/timers CT16B0 (Table 333) and CT16B1 (Table 334). Table 333: Count Control Register (CTCR, address 0x4001 4070 (CT32B0)) bit description...
Page 364: Pwm Control Register
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Table 334: Count Control Register (CTCR, address 0x4001 8070 (CT32B1)) bit description Symbol Value Description Reset value Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
Page 365: Rules For Single Edge Controlled Pwm Outputs
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 HIGH. The timer is reset by the match register that is configured to set the PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared.
Page 366: Example Timer Operation
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 Note: When the match outputs are selected to perform as PWM outputs, the timer reset (MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to zero except for the match register setting the PWM cycle length.
Page 367: Architecture
UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 PCLK prescale counter timer counter TCR[0] (counter enable) interrupt Fig 62. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled 16.9 Architecture The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in...
Page 368 UM10462 NXP Semiconductors Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0] INTERRUPT CAP[1:0] STOP ON MATCH RESET ON MATCH LOAD[3:0]...
Page 369: Chapter 17: Lpc11U3X/2X/1X Windowed Watchdog Timer (Wwdt)
(WWDT) Rev. 5.5 — 21 December 2016 User manual 17.1 How to read this chapter The WWDT is identical on all LPC11U3x/2x/1x parts. 17.2 Basic configuration The WWDT is configured through the following registers: • Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL...
Page 370: Applications
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) 17.4 Applications The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state. When enabled, a watchdog reset and/or will be generated if the user program fails to “feed”...
Page 371: Clocking And Power Control
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) feed ok enable count wd_clk ÷4 24-bit down counter WDTV FEED WINDOW range feed sequence compare detect and WDINTVAL protection compare compare feed error underflow interrupt compare shadow bit feed ok...
Page 372: Using The Wwdt Lock Features
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) 17.7 Using the WWDT lock features The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times: • Accidental overwrite of the WWDT clock source •...
Page 373: Register Description
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) 17.8 Register description The Watchdog Timer contains the registers shown in Table 336. Table 336. Register overview: Watchdog timer (base address 0x4000 4000) Name Access Address Description Reset Reference offset...
Page 374 UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) Table 337. Watchdog mode register (MOD - 0x4000 4000) bit description Symbol Value Description Reset value WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
Page 375: Watchdog Timer Constant Register
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) Table 338. Watchdog operating modes selection WDEN WDRESET Mode of Operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.
Page 376: Watchdog Timer Value Register
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) Table 340. Watchdog Feed register (FEED - 0x4000 4008) bit description Symbol Description Reset Value FEED Feed value should be 0xAA followed by 0x55. 31:8 Reserved, user software should not write ones to reserved bits.
Page 377: Watchdog Timer Warning Interrupt Register . 376 Watchdog Timer Window Register
UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) Table 343. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit description Symbol Description Reset Value WARNINT Watchdog warning interrupt compare value. 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 378 UM10462 NXP Semiconductors Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT) WDCLK / 4 Watchdog 1201 1200 11FF 11FE 11FD 11FC 2000 1FFF 1FFE 1FFD 1FFC Counter Correct Feed Event Watchdog Reset Conditions : WDWINDOW = 0x1200 WDWARNINT = 0x3FF WDTC = 0x2000 Fig 66.
Page 379: Chapter 18: Lpc11U3X/2X/1X System Tick Timer
UM10462 Chapter 18: LPC11U3x/2x/1x System tick timer Rev. 5.5 — 21 December 2016 User manual 18.1 How to read this chapter The system tick timer (SysTick timer) is part of the ARM Cortex-M0 core and is identical for all LPC11U3x/2x/1x.
Page 380: Register Description
UM10462 NXP Semiconductors Chapter 18: LPC11U3x/2x/1x System tick timer Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by providing a standard timer that is available on Cortex-M0 based devices. The SysTick timer can be used for: •...
Page 381: System Timer Reload Value Register
UM10462 NXP Semiconductors Chapter 18: LPC11U3x/2x/1x System tick timer Table 346. SysTick Timer Control and status register (SYST_CSR - 0xE000 E010) bit description Symbol Description Reset value ENABLE System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
Page 382: System Timer Calibration Value Register
SysTick timer interrupt. The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the LPC11U3x/2x/1x system clock set to 50 MHz. Example (system clock = 50 MHz) The system tick clock = system clock = 50 MHz. Bit CLKSOURCE in the SYST_CSR register set to 1 (system clock).
Page 383: Chapter 19: Lpc11U3X/2X/1X Adc
Rev. 5.5 — 21 December 2016 User manual 19.1 How to read this chapter The ADC block is identical for all LPC11U3x/2x/1x parts. 19.2 Basic configuration The ADC is configured using the following registers: 1. Pins: The ADC pin functions are configured in the IOCON register block (Section 7.4).
Page 384: Register Description
UM10462 NXP Semiconductors Chapter 19: LPC11U3x/2x/1x ADC The ADC function must be selected via the IOCON registers in order to get accurate voltage readings on the monitored pin. For a pin hosting an ADC input, it is not possible to have a have a digital function selected and yet get valid ADC readings.
Page 385: A/D Control Register (Cr - 0X4001 C000)
UM10462 NXP Semiconductors Chapter 19: LPC11U3x/2x/1x ADC 19.5.1 A/D Control Register (CR - 0x4001 C000) The A/D Control Register provides bits to select A/D channels to be converted, A/D timing, A/D modes, and the A/D start trigger. Table 352. A/D Control Register (CR - address 0x4001 C000) bit description...
Page 386: A/D Global Data Register (Gdr - 0X4001 C004)
UM10462 NXP Semiconductors Chapter 19: LPC11U3x/2x/1x ADC Table 352. A/D Control Register (CR - address 0x4001 C000) bit description Symbol Value Description Reset Value 26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: No start (this value should be used when clearing PDN to 0).
Page 387: A/D Interrupt Enable Register (Inten - 0X4001 C00C)
UM10462 NXP Semiconductors Chapter 19: LPC11U3x/2x/1x ADC 19.5.3 A/D Interrupt Enable Register (INTEN - 0x4001 C00C) This register allows control over which A/D channels generate an interrupt when a conversion is complete. For example, it may be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them.
Page 388: A/D Status Register (Stat - 0X4001 C030) . 387 Operation
UM10462 NXP Semiconductors Chapter 19: LPC11U3x/2x/1x ADC Table 356. A/D Status Register (STAT - address 0x4001 C030) bit description Symbol Description Reset Value DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel n.
Page 389: How To Read This Chapter
UM10462 Chapter 20: LPC11U3x/2x/1x Flash programming firmware Rev. 5.5 — 21 December 2016 User manual 20.1 How to read this chapter Table 357 for different flash configurations and functionality. Table 357. LPC11U3x/2x/1x flash configurations Type number Flash in kB Configuration...
Page 390: Chapter 20: Lpc11U3X/2X/1X Flash Programming Firmware
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.2 Bootloader The bootloader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.
Page 391: Memory Map After Any Reset
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware For the LPC11U3x/2x/1x parts, the state of PIO0_3 determines whether the UART or USB interface will be used (see Section 20.1): • If PIO0_3 is sampled HIGH, the bootloader connects the LPC1Uxx as a MSC USB device to a PC host.
Page 392: Criterion For Valid User Code
ISP, the CCLK frequency should be greater than or equal to 10 MHz. In USART ISP mode, the LPC11U3x/2x/1x is clocked by the IRC and the crystal frequency is ignored. Once the crystal frequency is received the part is initialized and the ISP command handler is invoked.
Page 393: Isp/Iap Communication Protocol
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.8 ISP/IAP communication protocol All ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and <LF>...
Page 394: Interrupts During Iap
The entire available user flash is mapped to a file of the size of the LPC11U3x/2x/1x flash in the host’s folder with the default name ‘firmware.bin’. The ‘firmware.bin’ file can be deleted and a new file can be copied into the directory, thereby updating the user code in flash.
Page 395: Usage Note
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 359. CRP levels for USB boot images CRP status Volume label Description No CRP CRP DISABLD The user flash can be read or written. CRP1 CRP1 ENABLD The user flash content cannot be read but can be updated. The flash memory sectors are updated depending on the new firmware image.
Page 396: Boot Process Flowchart
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.10 Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? ENABLE DEBUG WATCHDOG FLAG SET? USER CODE VALID? CRP3/NO_ISP ENABLED? ENTER ISP EXECUTE INTERNAL no (HIGH) MODE? USER CODE (PIN PIO0_1) yes (LOW)
Page 397: Sector Numbers
0x0000 7000 - 0x0000 7FFF 20.11.2 LPC11U3x The LPC11U3x support a page erase command. The following table shows the correspondence between page numbers, sector numbers, and memory addresses. The size of a sector is 4 kB, the size of a page is 256 Byte. One sector contains 16 pages.
Page 398: Code Read Protection (Crp)
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 361. LPC11U3x flash sectors and pages …continued Sector Sector Page Address range number size [kB] number 224 - 239 0x0000 E000 - 0x0000 EFFF no 240 - 255 0x0000 F000 - 0x0000 FFFF...
Page 399 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 362. Code Read Protection (CRP) options Name Pattern Description programmed in 0x0000 02FC NO_ISP 0x4E69 7370 Prevents sampling of pin PIO0_1 for entering ISP mode. PIO0_1 is available for other uses.
Page 400: Isp Entry Protection
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 363. Code Read Protection hardware/software interaction …continued CRP option User Code PIO0_1 pin at SWD enabled LPC11Uxx partial flash Valid reset enters USB or update in ISP UART ISP mode...
Page 401: Isp Commands
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.13 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 402: Set Baud Rate
UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.13.2 Set Baud Rate <Baud Rate> <stop bit> Table 367. ISP Set Baud Rate command Command Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 Stop bit: 1 | 2...

Page 403 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 369. ISP Write to RAM command Command Input Start Address: RAM address where data bytes are to be written. This address should be a word boundary. Number of Bytes: Number of bytes to be written. Count should be a multiple of 4...
Page 404 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 371. ISP Prepare sector(s) for write operation command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS |...
Page 405 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 372. ISP Copy command Command Input Flash Address (DST): Destination flash address where data bytes are to be written. The destination address should be a 256 byte boundary. RAM Address (SRC): Source RAM address from where data bytes are to be read.
Page 406 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware The following ISP commands will send the system reset code loaded into 0x1000 000. U 23130 W 268435456 16 0`4@"20%@_N<,[0#@!`#Z!0`` 1462 G 268435456 T Table 373. ISP Go command Command Input Address: Flash or RAM address from which the code execution is to be started.
Page 407 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.13.10 Blank check sector(s) <sector number> <end sector number> Table 375. ISP Blank check sector command Command Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number.
Page 408 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 377. LPC11U3x/2x/1x device identification numbers …continued Device Hex coding LPC11U34FBD48/311 0x0003 D440 LPC11U34FHN33/421 0x0001 CC40 LPC11U34FBD48/421 0x0001 CC40 LPC11U35FHN33/401 0x0001 BC40 LPC11U35FBD48/401 0x0001 BC40 LPC11U35FBD64/401 0x0001 BC40 LPC11U35FHI33/501 0x0000 BC40...
Page 409 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.13.14 ReadUID Table 380. ReadUID command Command Input None Return Code CMD_SUCCESS followed by four 32-bit words of a unique serial number in ASCII format. The word sent at the lowest address is sent first.
Page 410 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.14 IAP commands Remark: When using the IAP commands, configure the power profiles in Default mode. Section 5.7.1 “set_power”. For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters.
Page 411 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively (see the ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05). Additional parameters are passed on the stack. Up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively.
Page 412 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Command Parameter Array Command code command_param[0] command_param[1] Param 0 Param 1 command_param[2] ARM REGISTER r0 command_param[n] Param n ARM REGISTER r1 Status Result Array status_result[0] Status code Result 0 status_result[1] status_result[2]...
Page 413 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 384. IAP Copy RAM to flash command Command Copy RAM to flash Input Command code: 51 (decimal) Param0(DST): Destination flash address where data bytes are to be written. This address should be a 256 byte boundary.
Page 414 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.14.4 Blank check sector(s) Table 386. IAP Blank check sector(s) command Command Blank check sector(s) Input Command code: 53 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
Page 415 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.14.7 Compare <address1> <address2> <no of bytes> Table 389. IAP Compare command Command Compare Input Command code: 56 (decimal) Param0(DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
Page 416 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.14.10 Erase page Remark: Table 357 for list of parts that implement this command. Table 392. IAP Erase page command Command Erase page Input Command code: 59 (decimal) Param0: Start page number.
Page 417 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.14.13 IAP Status codes Table 395. IAP Status codes summary Status Mnemonic Description code CMD_SUCCESS Command is executed successfully. INVALID_COMMAND Invalid command. SRC_ADDR_ERROR Source address is not on a word boundary.
Page 418 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware 20.16 Register description Table 397. Register overview: FMC (base address 0x4003 C000) Name Access Address Description Reset Reference offset value FLASHCFG 0x010 Flash memory access time Table 401 configuration register FMSSTART...
Page 419 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 399. EEPROM BIST stop address register (EEMSSTOP - address 0x4003 C0A0) bit description Symbol Description Reset Access value 13:0 STOPA BIST stop address: Bit 0 is fixed zero since only even addresses are allowed.
Page 420 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 401. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description Symbol Value Description Reset value FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
Page 421 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 403. Flash module signature stop register (FMSSTOP - 0x4003 C024) bit description Symbol Value Description Reset value 16:0 STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
Page 422 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware Table 408. Flash module status register (FMSTAT - 0x4003 CFE0) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 423 UM10462 NXP Semiconductors Chapter 20: LPC11U3x/2x/1x Flash programming firmware The signature as it is read from the FMSW0 to FMSW3 registers must be equal to the reference signature. The algorithms to derive the reference signature is given in Figure int128 signature = 0...
Page 424 The ARM Cortex-M0 is configured to support up to four breakpoints and two watchpoints. 21.4 Description Debugging with the LPC11U3x/2x/1x uses the Serial Wire Debug mode. Support for boundary scan is available. 21.5 Pin description The tables below indicate the various pin functions related to debug. Some of these functions share pins with other functions which therefore may not be used at the same time.
Page 425 JTAG boundary scan when the RESET pin is LOW. 21.6 Functional description 21.6.1 Debug limitations Important: Due to limitations of the ARM Cortex-M0 integration, the LPC11U3x/2x/1x cannot wake up in the usual manner from Deep-sleep mode. It is recommended not to use this mode during debug.
Page 426 UM10462 NXP Semiconductors Chapter 21: LPC11U3x/2x/1x Serial Wire Debugger (SWD) LPC11Uxx VTREF SWDIO SWDIO SWCLK SWCLK nSRST RESET PIO0_1 ISP entry The VTREF pin on the SWD connector enables the debug connector to match the target voltage. Fig 72. Connecting the SWD pins to a standard SWD connector 21.6.3 Boundary scan...
Page 427 UM10462 Chapter 22: LPC11U3x/2x/1x Integer division routines Rev. 5.5 — 21 December 2016 User manual 22.1 How to read this chapter The ROM-based 32-bit integer division routines are available on LPC11U2x/LPC11U3x. 22.2 Features • Performance-optimized signed/unsigned integer division. • Performance-optimized signed/unsigned integer division with remainder.
Page 428 UM10462 NXP Semiconductors Chapter 22: LPC11U3x/2x/1x Integer division routines The integer division routines perform arithmetic integer division operations and can be called in the application code through simple API calls. The following function prototypes are used: typedef struct { int quot; int rem; } idiv_return;...
Page 429 UM10462 NXP Semiconductors Chapter 22: LPC11U3x/2x/1x Integer division routines result = pDivROM->sidiv(-99, 6); /* result now contains (-16) */ 22.4.3 Unsigned division with remainder The example C-code listing below shows how to perform an unsigned integer division with remainder via the ROM API.
Page 430 UM10462 Chapter 23: LPC11U3x/2x/1x I/O Handler Rev. 5.5 — 21 December 2016 User manual 23.1 How to read this chapter The I/O Handler is only available on part LPC11U37HFBD64/401. 23.2 Features • I/O Handler for hardware emulation of serial interfaces and DMA.
Page 431 UM10462 NXP Semiconductors Chapter 23: LPC11U3x/2x/1x I/O Handler 23.6.1.1 I/O Handler I The I/O Handler software library provides functions to emulate an I S master transmit interface using the I/O Handler hardware block. The emulated I S interface loops over a 1 kB buffer, transmitting the datawords according to the I S protocol.
Page 432 UM10462 Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Rev. 5.5 — 21 December 2016 User manual 24.1 Introduction The following material is using the ARM Cortex-M0 User Guide. Minor changes have been made regarding the specific implementation of the Cortex-M0 for the LPC11U3x/2x/1x.
Page 433 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC: • includes a non-maskable interrupt (NMI). • provides zero jitter interrupt option.
Page 434 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 System timer — The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter. 24.3 Processor 24.3.1 Programmers model This section describes the Cortex-M0 programmers model.
Page 435 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Fig 75. Processor core register set Table 413. Core register set summary Name Type Reset value Description R0-R12 Unknown Section 24–24.3.1.3.1 See description Section 24–24.3.1.3.2 Unknown Section 24–24.3.1.3.2 Unknown Section 24–24.3.1.3.3 See description Section 24–24.3.1.3.4...
Page 436 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 On reset, the processor loads the MSP with the value from address 0x00000000. 24.3.1.3.3 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the LR value is Unknown.
Page 437 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 See the instruction descriptions Section 24–24.4.7.6 Section 24–24.4.7.7 for more information about how to access the program status registers. Application Program Status Register: The APSR contains the current state of the condition flags, from previous instruction executions.
Page 438 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 417. EPSR bit assignments Bits Name Function [31:25] Reserved [24] Thumb state bit [23:0] Reserved Attempts by application software to read the EPSR directly using the MRS instruction always return zero. Attempts to write the EPSR using the MSR instruction are ignored.
Page 439 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 419. CONTROL register bit assignments Bits Name Function [31:2] Reserved Active stack Defines the current stack: pointer 0 = MSP is the current stack pointer 1 = PSP is the current stack pointer.
Page 440 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 For a Cortex-M0 microcontroller system, CMSIS defines: • a common way to: – access peripheral registers – define exception vectors • the names of: – the registers of the core peripherals –...
Page 441 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 For the LPC11U3x/2x/1x specific implementation of the memory map, see Figure Fig 77. Cortex-M0 memory map The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see Section 24–24.2.
Page 442 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Strongly-ordered — The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
Page 443 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 420. Memory access behavior Address Memory Memory Description range region type 0x00000000- Code Normal Executable region for program code. You can also put data here. 0x1FFFFFFF 0x20000000- SRAM Normal Executable region for data. You can also put code here.
Page 444 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Vector table — If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector.
Page 445 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active — An exception that is being serviced by the processor but has not completed.
Page 446 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 421. Properties of different exception types Exception Exception Priority Vector number number type address PendSV Configurable 0x00000038 SysTick Configurable 0x0000003C 16 and above 0 and above Interrupt (IRQ) Configurable 0x00000040 and...
Page 447 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Fig 80. Vector table The vector table is fixed at address 0x00000000. 24.3.3.5 Exception priorities Table 24–421 shows, all exceptions have an associated priority, with: • a lower priority value indicating a higher priority •...
Page 448 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
Page 449 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Sufficient priority means the exception has greater priority than any limit set by the mask register, see Section 24–24.3.1.3.6. An exception with less priority than this is pending but is not handled by the processor.
Page 450 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 not a normal branch operation and, instead, that the exception is complete. Therefore, it starts the exception return sequence. Bits[3:0] of the EXC_RETURN value indicate the required return stack and processor mode, as Table 24–422...
Page 451 24.3.5.1.2 Wait for event Remark: The WFE instruction is not implemented on the LPC11U3x/2x/1x. The Wait For Event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the value of the event register: 0 —...
Page 452 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.3.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler and returns to Thread mode it immediately enters sleep mode.
Page 453 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 • angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands and mnemonic parts • the Operands column is not exhaustive. For more information on the instructions and operands, see the instruction descriptions.
Page 454 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 423. Cortex-M0 instructions Mnemonic Operands Brief description Flags Reference Rt, label Load Register from PC-relative Section 24–24.4.4 address Rt, [Rn, <Rm|#imm>] Load Register with word Section 24–24.4.4 LDRB Rt, [Rn, <Rm|#imm>] Load Register with byte Section 24–24.4.4...
Page 455 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 423. Cortex-M0 instructions Mnemonic Operands Brief description Flags Reference Rt, [Rn, <Rm|#imm>] Store Register as word Section 24–24.4.4 STRB Rt, [Rn, <Rm|#imm>] Store Register as byte Section 24–24.4.4 STRH Rt, [Rn, <Rm|#imm>] Store Register as halfword Section 24–24.4.4...
Page 456 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 424. CMSIS intrinsic functions to generate some Cortex-M0 instructions Instruction CMSIS intrinsic function void __SEV(void) void __WFE(void) void __WFI(void) The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 425.
Page 457 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.3.3 Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed directly by the instructions ASR, LSR, LSL, and ROR and the result is written to a destination register.The permitted shift...
Page 458 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 • If n is 32 or more, then all the bits in the result are cleared to 0. • If n is 33 or more and the carry flag is updated, it is updated to 0.
Page 459 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 • If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.
Page 460 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 On the Cortex-M0 processor, conditional execution is available by using conditional branches. This section describes: • Section 24.4.3.6.1 “The condition flags” • Section 24.4.3.6.2 “Condition code suffixes”. 24.4.3.6.1 The condition flags The APSR contains the following condition flags: N —...
Page 461 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 426. Condition code suffixes Suffix Flags Meaning N = 0 Positive or zero V = 1 Overflow V = 0 No overflow C = 1 and Z = 0 Higher, unsigned...
Page 462 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 ADR facilitates the generation of position-independent code, because the address is PC-relative. If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to 1 for correct execution.
Page 463 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 • imm must be between: – 0 and 1020 and an integer multiple of four for LDR and STR using SP as the base register – 0 and 124 and an integer multiple of four for LDR and STR using R0-R7 as the base register –...
Page 464 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.4.3.3 Restrictions In these instructions: • Rt, Rn, and Rm must only specify R0-R7. • the computed memory address must be divisible by the number of bytes in the load or...
Page 465 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.4.5.1 Syntax LDM Rn{!}, reglist STM Rn!, reglist where: Rn is the register on which the memory addresses are based. ! writeback suffix. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges.
Page 466 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.4.5.5 Examples R0,{R0,R3,R4} ; LDMIA is a synonym for LDM STMIA R1!,{R2-R4,R6} 24.4.4.5.6 Incorrect examples R5!,{R4,R5,R6} ; Value stored for R5 is unpredictable R2,{} ; There must be at least one register in the list 24.4.4.6 PUSH and POP...
Page 467 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.4.6.5 Examples PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack PUSH {R2,LR} ; Push R2 and the link-register onto the stack {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to ;...
Page 468 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 ADD{S} {Rd,} Rn, <Rm|#imm> RSBS {Rd,} Rn, Rm, #0 SBCS {Rd,} Rn, Rm SUB{S} {Rd,} Rn, <Rm|#imm> Where: S causes an ADD or SUB instruction to update flags Rd specifies the result register...
Page 469 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 429. ADC, ADD, RSB, SBC and SUB operand restrictions Instruction Rd Restrictions ADCS R0-R7 R0-R7 R0-R7 Rd and Rn must specify the same register. R0-R15 R0-R15 R0-PC Rd and Rn must specify the same register.
Page 470 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 BICS {Rd,} Rn, Rm where: Rd is the destination register. Rn is the register holding the first operand and is the same as the destination register. Rm second register. 24.4.5.2.2 Operation The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive OR operations on the values in Rn and Rm.
Page 471 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 where: Rd is the destination register. If Rd is omitted, it is assumed to take the same value as Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm.
Page 472 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 where: Rn is the register holding the first operand. Rm is the register to compare with. imm is the immediate value to compare with. 24.4.5.4.2 Operation These instructions compare the value in a register with either the value in another register or an immediate value.
Page 473 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Rm is a register. imm is any value in the range 0-255. 24.4.5.5.2 Operation The MOV instruction copies the value of Rm into Rd. The MOVS instruction performs the same operation as the MOV instruction, but also updates the N and Z flags.
Page 474 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.5.6.2 Operation The MUL instruction multiplies the values in the registers specified by Rn and Rm, and places the least significant 32 bits of the result in Rd. The condition code flags are...
Page 475 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.5.7.4 Condition flags These instructions do not change the flags. 24.4.5.7.5 Examples REV R3, R7 ; Reverse byte order of value in R7 and write it to R3 REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0 REVSH R0, R5 ;...
Page 476 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.5.9.1 Syntax TST Rn, Rm where: Rn is the register holding the first operand. Rm the register to test against. 24.4.5.9.2 Operation This instruction tests the value in a register against another register. It updates the condition flags based on the result, but does not write the result to a register.
Page 477 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 BX Rm BLX Rm where: cond is an optional condition code, see Section 24–24.4.3.6. label is a PC-relative expression. See Section 24–24.4.3.5. Rm is a register providing the address to branch to.
Page 478 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 ; Return from function call BLX R0 ; Branch with link and exchange (Call) to a address stored ; in R0 BEQ labelD ; Conditionally branch to labelD if last flag setting ;...
Page 479 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.7.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
Page 480 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.7.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction. DMB does not affect the ordering of instructions that do not access memory.
Page 481 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.7.5.3 Restrictions There are no restrictions. 24.4.7.5.4 Condition flags This instruction does not change the flags. 24.4.7.5.5 Examples ISB ; Instruction Synchronisation Barrier 24.4.7.6 MRS Move the contents of a special register to a general-purpose register.
Page 482 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 spec_reg is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL. 24.4.7.7.2 Operation MSR updates one of the special registers with the value from the register specified by Rn.
Page 483 ; by locating it via the stacked PC) 24.4.7.11 WFE Wait For Event. Remark: The WFE instruction is not implemented on the LPC11U3x/2x/1x. 24.4.7.11.1 Syntax 24.4.7.11.2 Operation If the event register is 0, WFE suspends execution until one of the following events...
Page 484 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 • an exception, unless masked by the exception mask registers or the current priority level • an exception enters the Pending state, if SEVONPEND in the System Control Register is set •...
Page 485 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.4.7.12.5 Examples WFI ; Wait for interrupt 24.5 Peripherals 24.5.1 About the ARM Cortex-M0 The address map of the Private peripheral bus (PPB) is: Table 433. Core peripheral register regions Address...
Page 486 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.5.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS CMSIS functions enable software portability between different Cortex-M profile processors. To access the NVIC registers when using CMSIS, use the following functions: Table 435. CMISIS acess NVIC functions...
Page 487 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 437. ICER bit assignments Bits Name Function [31:0] CLRENA Interrupt clear-enable bits. Write: 0 = no effect 1 = disable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled.
Page 488 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.5.2.6 Interrupt Priority Registers The IPR0-IPR7 registers provide an 2-bit priority field for each interrupt. These registers are only word-accessible. See the register summary in Table 24–434 for their attributes. Each register holds four priority fields as shown: Fig 86.
Page 489 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
Page 490 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 24.5.2.8.1 NVIC programming hints Software uses the CPSIE i and instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts...
Page 491 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 443. CPUID register bit assignments Bits Name Function [31:24] Implementer Implementer code: 0x41 = ARM [23:20] Variant Variant number, the r value in the rnpn product revision identifier [19:16] Constant...
Page 492 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 444. ICSR bit assignments Bits Name Type Function [31] NMIPENDSET NMI set-pending bit. Write: 0 = no effect 1 = changes NMI exception state to pending. Read: 0 = NMI exception is not pending 1 = NMI exception is pending.
Page 493 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 444. ICSR bit assignments Bits Name Type Function [22] ISRPENDING Interrupt pending flag, excluding NMI and Faults: 0 = interrupt not pending 1 = interrupt pending. [21:18] Reserved. [17:12] VECTPENDING...
Page 494 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 445. AIRCR bit assignments Bits Name Type Function SYSRESETREQ System reset request: 0 = no effect 1 = requests a system level reset. This bit reads as 0. VECTCLRACTIVE Reserved for debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
Page 495 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 447. CCR bit assignments Bits Name Function [31:10] Reserved. STKALIGN Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment.
Page 496 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 450. SHPR3 register bit assignments Bits Name Function [31:24] PRI_15 Priority of system handler 15, SysTick exception [23:16] PRI_14 Priority of system handler 14, PendSV [15:0] Reserved 24.5.3.8 SCB usage hints and tips Ensure software uses aligned 32-bit word size transactions to access all the SCB registers.
Page 497 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 452. SYST_CSR bit assignments Bits Name Function CLKSOURCE Selects the SysTick timer clock source: 0 = external reference clock 1 = processor clock. TICKINT Enables SysTick exception request: 0 = counting down to zero does not assert the SysTick exception request 1 = counting down to zero to asserts the SysTick exception request.
Page 498 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 455. SYST_CALIB register bit assignments Bits Name Function [31] NOREF Reads as one. Indicates that no separate reference clock is provided. [30] SKEW Reads as one. Calibration value for the 10ms inexact timing is not known because TENMS is not known.
Page 499 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 456. Cortex M0- instruction summary Operation Description Assembler Cycles Subtract Lo and Lo SUBS Rd, Rn, Rm 3-bit immediate SUBS Rd, Rn, #<imm> 8-bit immediate SUBS Rd, Rd, #<imm> With carry...
Page 500 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Table 456. Cortex M0- instruction summary Operation Description Assembler Cycles Store Halfword, immediate offset STRH Rd, [Rn, #<imm>] Byte, immediate offset STRB Rd, [Rn, #<imm>] Word, register offset STR Rd, [Rn, Rm]...
Page 501 UM10462 NXP Semiconductors Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0 Executes as NOP. UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved. User manual Rev. 5.5 — 21 December 2016 501 of 523...
Page 502 UART Universal Asynchronous Receiver/Transmitter USART Universal Synchronous Asynchronous Receiver/Transmitter 25.2 References LPC11U1x data sheet: http://www.nxp.com/documents/data_sheet/LPC11U1X.pdf LPC11U2x data sheet: http://www.nxp.com/documents/data_sheet/LPC11U2X.pdf LPC11U3x data sheet: http://www.nxp.com/documents/data_sheet/LPC11U3X.pdf LPC11U1x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U1X.pdf LPC11U2x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U2X.pdf LPC11U3x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U3X.pdf UM10462 All information provided in this document is subject to legal disclaimers.
Page 503 NXP Semiconductors. applications and products. In no event shall NXP Semiconductors be liable for any indirect, incidental, NXP Semiconductors does not accept any liability related to any default, punitive, special or consequential damages (including - without limitation - lost...
Page 504 Part ordering options .....9 address 0x4004 8098) bit description ..33 Table 3. LPC11U3x/2x/1x memory configuration ..14 Table 27. SPI1 clock divider register (SSP1CLKDIV, Table 4.
Page 505 UM10462 NXP Semiconductors Chapter 25: Supplementary information 0x4003 C010) bit description ....45 bit description ......88 Table 50.
Page 506 ......163 Table 135. LPC11U3x pin description ....145 Table 157.
Page 507 UM10462 NXP Semiconductors Chapter 25: Supplementary information Table 160. GPIO direction port 0 register (DIR0, address Table 193. _USB_DFU_FUNC_DESCRIPTOR class 0x5000 2000) bit description ... . .164 structure ......178 Table 161.
Page 508 UM10462 NXP Semiconductors Chapter 25: Supplementary information Table 230. USART Receiver Buffer Register when Table 257. SSP/SPI pin descriptions ....276 DLAB = 0, Read Only (RBR - address Table 258.
Page 509 UM10462 NXP Semiconductors Chapter 25: Supplementary information 0x4000 00[30, 34, 38, 3C]) bit description . . .300 Table 311. External match control....344 Table 283.
Page 510 Table 403. Flash module signature stop register (FMSSTOP Table 361. LPC11U3x flash sectors and pages ..397 - 0x4003 C024) bit description ... . 421 Table 362.
Page 511 UM10462 NXP Semiconductors Chapter 25: Supplementary information Table 409. Flash module status clear register (FMSTATCLR - 0x0x4003 CFE8) bit description ..422 Table 410. Serial Wire Debug pin description ..424 Table 411.
Page 512 Fig 51. Format and states in the Slave Receiver mode 318 Fig 6. LPC11U3x memory map ....18 Fig 52. Format and states in the Slave Transmitter mode .
Page 513: Table Of Contents
Memory map ......15 Chapter 3: LPC11U3x/2x/1x System control block How to read this chapter ....19 3.5.40...
Page 514 UM10462 NXP Semiconductors Chapter 25: Supplementary information Chapter 4: LPC11U3x/2x/1x Power Management Unit (PMU) How to read this chapter ....56 4.3.1 Power control register ....56 4.3.2...
Page 515 Pin configuration ..... . 129 8.2.3 LPC11U3x pin description ....145 Chapter 9: LPC11U3x/2x/1x GPIO How to read this chapter .
Page 516 10.5.15 _REQUEST_TYPE ....176 Chapter 11: LPC11U3x/2x/1x USB2.0 device controller 11.1 How to read this chapter ....221 11.6.7...
Page 517 SK in Microwire mode ..289 13.6.8 SSP/SPI Masked Interrupt Status Register . 281 Chapter 14: LPC11U3x/2x/1x I2C-bus controller 14.1 How to read this chapter ....290 14.7.7...
Page 518 14.11.5 Non mode specific states ....326 Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1 15.1 How to read this chapter ....333 15.7.5...
Page 519 ISP/IAP communication protocol ..393 20.11.2 LPC11U3x ......397 20.8.1 ISP command format .
Page 520 Compare <address1> <address2> <no of bytes> ......415 Chapter 21: LPC11U3x/2x/1x Serial Wire Debugger (SWD) 21.1 How to read this chapter ....424 21.5...
Page 521 UM10462 NXP Semiconductors Chapter 25: Supplementary information 24.3.1 Programmers model ....434 24.4.3.3.1 ASR ....... 457 24.3.1.1...
Page 522 UM10462 NXP Semiconductors Chapter 25: Supplementary information 24.4.5.1.3 Restrictions......468 24.4.7.1 BKPT ......478 24.4.5.1.4 Examples .
Page 523 UM10462 NXP Semiconductors Chapter 25: Supplementary information 24.4.7.10.4 Condition flags ..... . 483 24.5.2.7.1 Hardware and software control of interrupts 489 24.4.7.10.5 Examples .

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NXP Semiconductors LPC11U3x User Manual

Chapter 1: Lpc11U3X/2X/1X Introductory Information

Introduction

Features

Chapter 25 : Supplementary Information

Ordering Information

Block Diagram

How to Read this Chapter

Memory Map

Chapter 2: Lpc11U3X/2X/1X Memory Mapping

Chapter 3: Lpc11U3X/2X/1X System Control Block

How to Read this Chapter

Introduction

Pin Description

Clocking and Power Control

Register Description

Reset

Start-Up Behavior

Brown-Out Detection

Power Management

System PLL/USB PLL Functional Description

Chapter 4: Lpc11U3X/2X/1X Power Management Unit (PMU)

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Introduction

Register Description

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Chapter 5: Lpc11U3X/2X/1X Power Profiles

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Features

Basic Configuration

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Power Routine

Chapter 6: Lpc11U3X/2X/1X NVIC

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Introduction

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Interrupt Sources

Register Description

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Introduction

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Chapter 7: Lpc11U3X/2X/1X I/O Configuration

Register Description

Chapter 8: Lpc11U3X/2X/1X Pin Configuration

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Pin Configuration

Chapter 9: Lpc11U3X/2X/1X GPIO

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Basic Configuration

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Chapter 10 : Lpc11U3X/2X/1X USB On-Chip Drivers

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