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UM10503
LPC43xx ARM Cortex-M4/M0 dual-core microcontroller
Rev. 1.3 — 6 July 2012
Document information
Info
Content
Keywords
LPC4350FET256; LPC4350FET180; LPC4350FBD208; LPC4330FET256;
LPC4330FET180; LPC4330FET100; LPC4330FBD144; LPC4320FET100;
LPC4320FBD144; LPC4310FET100; LPC4310FBD144; LPC4357FET256;
LPC4357FET180; LPC4357FBD208; LPC4353FET256; LPC4353FET180;
LPC4353FBD208; LPC43xx, LPC4350, LPC4330, LPC4320, LPC4310,
LPC4357, LPC4353, LPC4337, LPC4333, LPC43Sxx, ARM Cortex-M4, ARM
Cortex-M0, SPIFI, SCT, USB, Ethernet
Abstract
LPC4300 user manual
User manual
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Related Manuals for NXP Semiconductors LPC43 Series
Summary of Contents for NXP Semiconductors LPC43 Series
- Page 1 UM10503 LPC43xx ARM Cortex-M4/M0 dual-core microcontroller Rev. 1.3 — 6 July 2012 User manual Document information Info Content Keywords LPC4350FET256; LPC4350FET180; LPC4350FBD208; LPC4330FET256; LPC4330FET180; LPC4330FET100; LPC4330FBD144; LPC4320FET100; LPC4320FBD144; LPC4310FET100; LPC4310FBD144; LPC4357FET256; LPC4357FET180; LPC4357FBD208; LPC4353FET256; LPC4353FET180; LPC4353FBD208; LPC43xx, LPC4350, LPC4330, LPC4320, LPC4310, LPC4357, LPC4353, LPC4337, LPC4333, LPC43Sxx, ARM Cortex-M4, ARM Cortex-M0, SPIFI, SCT, USB, Ethernet Abstract...
- Page 2 UM10503 NXP Semiconductors LPC43xx user manual Revision history Date Description 20120706 LPC43xx user manual. • Modifications: Description of USB CDC device class updated in Section 25.5.26 “USBD_API_INIT_PARAM” Section 25.5.27 “USBD_CDC_API”. • Section 24.7.1 “Susp_CTRL module” added for USB1. • Section 23.11 “USB power optimization”...
- Page 3 UM10503 NXP Semiconductors LPC43xx user manual Revision history …continued Date Description 20120510 • Modifications: Reset value of the ETB bit in the ETBCFG register changed to one (see Table 48). • UART1 FIFOLVL register removed. • Chapter 46 “LPC43xx flash programming/ISP and IAP” added.
- Page 4 UM10503 Chapter 1: Introductory information Rev. 1.3 — 6 July 2012 User manual 1.1 Introduction The LPC43xx are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264 kB of SRAM, advanced configurable peripherals such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
- Page 5 UM10503 NXP Semiconductors Chapter 1: Introductory information – Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually. – 64 kB ROM containing boot code and on-chip software drivers. – 32 bit general-purpose One-Time Programmable (OTP) memory.
- Page 6 UM10503 NXP Semiconductors Chapter 1: Introductory information • Digital peripherals – External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. – LCD controller with DMA support and a programmable display resolution of up to 1024H 768V. Supports monochrome and color STN panels and TFT color panels;...
- Page 7 UM10503 NXP Semiconductors Chapter 1: Introductory information – Ultra-low power Real-Time Clock (RTC) crystal oscillator. – Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
- Page 8 UM10503 NXP Semiconductors Chapter 1: Introductory information Table 2. Ordering options Type number Total LCD Ethernet USB0 USB1 GPIO Package SRAM (Host, (Host, channels Device, Device)/ OTG) ULPI interface LPC4350FET256 264 kB yes/yes LBGA256 LPC4350FET180 264 kB yes/yes TFBGA180 LPC4350FBD208 264 kB...
- Page 9 UM10503 NXP Semiconductors Chapter 1: Introductory information Table 4. Ordering options Type number Flash Flash Flash Total Ethernet USB0 USB1 GPIO bank A bank B SRAM (Host, (Host, channels Device, Device)/ OTG) ULPI interface LPC4357FET256 1 MB 512 kB 512 kB...
- Page 10 UM10503 NXP Semiconductors Chapter 1: Introductory information 1.5 Block diagram (flashless parts) LPC4350/30/20/10 TEST/DEBUG INTERFACE TEST/DEBUG INTERFACE HIGH-SPEED PHY CORTEX-M0 CORTEX-M4 ETHERNET HIGH-SPEED HIGH-SPEED 10/100 USB0 USB1 GPDMA HOST/ HOST/DEVICE IEEE 1588 DEVICE/OTG masters slaves AHB MULTILAYER MATRIX slaves 128 kB LOCAL SRAM...
- Page 11 UM10503 NXP Semiconductors Chapter 1: Introductory information 1.6 Block diagram (parts with on-chip flash) LPC4357/53/37/33 TEST/DEBUG INTERFACE TEST/DEBUG INTERFACE HIGH-SPEED PHY CORTEX-M0 CORTEX-M4 ETHERNET HIGH-SPEED HIGH-SPEED 10/100 USB0 USB1 GPDMA HOST/ HOST/DEVICE IEEE 1588 DEVICE/OTG masters slaves AHB MULTILAYER MATRIX...
- Page 12 UM10503 Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process Communication (IPC) Rev. 1.3 — 6 July 2012 User manual 2.1 How to read this chapter The ARM Cortex-M0 co-processor is available on all LPC43xx parts. 2.2 Basic configuration The ARM Cortex-M0 co-processor is configured as follows: •...
- Page 13 UM10503 NXP Semiconductors Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process Interrupt Write Pointer Read HOST_CMD_BUFFER Pointer Cortex M4 Cortex M0 (Master) (Slave) Write Pointer HOST_MSG_BUFFER Read Pointer Interrupt = M0 subsystem = M4 subsystem = shared Fig 3.
- Page 14 UM10503 NXP Semiconductors Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process The basic IPC features are: • The ARM Cortex-M4 initializes the ARM Cortex-M0 system. • The ARM Cortex-M4 communicates with the ARM Cortex-M0 system via a command queue.
- Page 15 UM10503 NXP Semiconductors Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process It is the responsibility of the process writing to a queue making sure that the queue is not filled completely; before loading a new item the process should confirm that the write pointer will not be equal to, or overtake the read pointer and will leave at least one free space.
- Page 16 UM10503 NXP Semiconductors Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process Table 7. Message list Message Bit mask Description MSG_SRV_ID 0xTTTT.SS00 ARM Cortex-M0 request servicing for the task with ID = 0xTTTT. The service type is coded in bytes SS. The meaning of SS is proprietary per task.
- Page 17 UM10503 NXP Semiconductors Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process Table 9. IPC example Command Message Byte values Description CMD_WR 0x1234<rst>1, pointer Command to initialise the task, the pointer informs the ARM Cortex-M0 the location of the register values.
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UM10503 Chapter 3: LPC43xx Memory mapping Rev. 1.3 — 6 July 2012 User manual 3.1 How to read this chapter The available peripherals and their memories vary for different parts. • Ethernet: available only on LPC435x/3x. • USB0: available only on LPC435x/3x/2x. •... - Page 19 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping Table 10. LPC43xx SRAM configuration Part Local SRAM Local SRAM AHB SRAM AHB SRAM AHB SRAM/ SRAM LPC4310 96 kB 40 kB 16 kB 16 kB Figure 4 LPC4357 32 kB 40 kB...
- Page 20 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping Table 11. LPC435x/3x/2x/1x Flash configuration Part Flash bank A Flash bank A Flash bank A Flash bank B Flash bank B Flash bank B 256 kB 128 kB 128 kB 256 kB...
- Page 21 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping 3.4 Memory map (flashless parts) LPC4350/30/20/10 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3 0x7000 0000...
- Page 22 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC4350/30/20/10 0x400F 0000 reserved 0x400E 5000 0xFFFF FFFF APB3 ADC1 0x400E 4000 external memories and peripherals ARM private bus ADC0...
- Page 23 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping 3.5 Memory map (parts with on-chip flash) The memory map shown in Figure 6 Figure 7 is global to both the Cortex-M4 and the Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between both processors.
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UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping LPC4357/53/37/33 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 128 MB SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3 0x7000 0000 256 MB dynamic external memory DYCS2... - Page 25 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC4357/53/37/33 0x400F 0000 0x4006 0000 reserved 0x400E 5000 0xFFFF FFFF reserved 0x4005 4000 APB3 ADC1 0x400E 4000 external memories and...
- Page 26 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping 3.6 AHB Multilayer matrix configuration The multilayer AHB matrix enables all bus masters to access any embedded memory as well as external SPI flash memory connected to the SPIFI interface. When two or more bus masters try to access the same slave, a round robin arbitration scheme is used;...
- Page 27 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping HIGH-SPEED PHY TEST/DEBUG TEST/DEBUG INTERFACE INTERFACE ETHERNET USB0 USB1 masters CORTEX-M4 CORTEX-M0 System code code slaves 64 kB ROM 128 kB LOCAL SRAM 72 kB LOCAL SRAM SPIFI 32 kB AHB SRAM...
- Page 28 UM10503 NXP Semiconductors Chapter 3: LPC43xx Memory mapping HIGH-SPEED PHY TEST/DEBUG TEST/DEBUG INTERFACE INTERFACE ETHERNET USB0 USB1 masters CORTEX-M4 CORTEX-M0 System code code slaves 256/512 kB FLASH A 256/512 kB FLASH B 16 kB EEPROM 64 kB ROM 32 kB LOCAL SRAM...
- Page 29 UM10503 Chapter 4: LPC43xx One-Time Programmable (OTP) memory and API Rev. 1.3 — 6 July 2012 User manual 4.1 How to read this chapter This chapter applies to all LPC43xx parts. AES keys and AES functions are supported for parts LPC43Sxx only. The following bit is reserved for flash-based parts: JTAG_DISABLE in the OTP memory bank 3, word 0 (bit 31).
- Page 30 UM10503 NXP Semiconductors Chapter 4: LPC43xx One-Time Programmable (OTP) memory and API Table 12. OTP memory description (OTP base address 0x4004 5000) Word Access Address Size Description Reference bank offset Pre-programmed; cannot 0x00C 32 bit Reserved be changed by the user.
- Page 31 UM10503 NXP Semiconductors Chapter 4: LPC43xx One-Time Programmable (OTP) memory and API Table 13. OTP memory bank 3, word 0 - Customer control data (address offset 0x030) Symbol Value Description 28:25 BOOT_SRC Boot source selection in OTP. For details, see...
- Page 32 UM10503 NXP Semiconductors Chapter 4: LPC43xx One-Time Programmable (OTP) memory and API Ptr to ROM Driver table 0x1040 0104 Device 0 ROM Driver Table Ptr to Function 0 0x1040 0100 Ptr to Device Table 0 Ptr to Function 1 0x1040 0104...
- Page 33 UM10503 NXP Semiconductors Chapter 4: LPC43xx One-Time Programmable (OTP) memory and API 4.5.1 OTP function allocation Table 17. OTP function allocation Function Offset Description otp_Init 0x00 Initializes OTP controller. Parameter - void Return- unsigned: see the general error codes .
- Page 34 UM10503 Chapter 5: LPC43xx Boot ROM Rev. 1.3 — 6 July 2012 User manual 5.1 How to read this chapter This chapter applies to all LPC4350/30/20/10 parts. AES support is available on LPC43Sxx parts only. Flash-based parts boot from on-chip flash by default (see Chapter 46), but other boot modes described in this chapter are also supported.
- Page 35 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM For flash-based and flashless parts alike, several external sources are available for booting depending on the values of the OTP bits BOOT_SRC (see Section 4.4). If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.
- Page 36 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Table 19. Boot mode when OTP BOOT_SRC bits are zero Boot mode P2_9 P2_8 P1_2 P1_1 Description USB1 HIGH HIGH Boot from USB1. SPI (SSP) HIGH HIGH HIGH Boot from SPI flash connected to the SSP0 interface on P3_3...
- Page 37 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM CPU clock disable LPC 18 xx RESET = IRC IRQ & capable and 12 MHz key > 0 ? load AES enable JTAG CPU clock 96 MHz check BOOT _ SRC = 2 .. 5 , 8 = 6 ..
- Page 38 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM 5.3.2 AES capable parts AES capable parts will normally always boot from a secure (encrypted) image and use CMAC authentication. However a special development mode allows booting from a plain text image. This development mode is active when the AES key has not been programmed.
- Page 39 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Table 21. Boot image header description Address Name Description size [bits] 15:14 AES_CONTROL These 2 bits can be set to a value such that when AES encryption is active, that the AES_ACTIVE field, after AES encryption, is...
- Page 40 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM The first message block is the header. Since the CMAC tag is stored in the header field HASH_VALUE, and this tag is not yet known until after CMAC calculation, a temporary header with a dummy tag value of 0x3456789A is used during CMAC calculation. This dummy value should be replaced by the calculated tag value in the final header field HASH_VALUE.
- Page 41 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Setup Pin Init UART assuming Configuration PCLK =12MHz UART0 P2_1, P2_0 or UART3 P2_3,P2_4 receive character char = 0x3F? transmit prepare “OK” CR image transmit valid “FAILED” image? CR LF transmit “OK” CR see main boot flow Fig 13.
- Page 42 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Setup Pin Configuration Read Image EMC _A[13:0] Header EMC_CS0 Image size > 16384-16 Extend address bus see main boot flow Fig 14. EMC boot process 5.3.5.3 SPI boot mode The boot uses SSP0 in SPI mode. The SPI clock is 18 MHz.
- Page 43 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM If no header is present, it is assumed that the image is located on address 0x8000 0000 and is executed from there. Setup clock Setup Pin SPIFI_SCK= Configuration Detect device 32MHz P3_3..P3_8...
- Page 44 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM Boot source? USB0 USB1 Setup clock Setup clock USB_CLK=480MHz USB_CLK=60MHz Enable HS PHY Setup VBUS pin P2_5 enumerate receive image see main boot flow Fig 17. USB boot process 5.3.6 Boot process timing The following parameters describe the timing of the boot process: Table 22.
- Page 45 UM10503 NXP Semiconductors Chapter 5: LPC43xx Boot ROM IRC12 IRC12 stable starts IRC12 RESET VDDREG valid threshold 22 μs 0.5μs; IRC stability count supply boot time ramp up user code μs μs μs processor status check boot initialise copy image to...
- Page 46 UM10503 Chapter 6: LPC43xx Security API Rev. 1.3 — 6 July 2012 User manual 6.1 How to read this chapter AES encryption and decryption are supported for parts LPC43Sxx only. 6.2 Features • Decryption of external image data. • Encryption of image data. •...
- Page 47 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API Remark: The randomly generated and software defined keys are not retained during Deep power-down and reset and must be reloaded. Remark: To update the Random Number Generator (RNG) and load a new random...
- Page 48 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API Table 23. Security API calls Function Offset relative to Description the API entry point aes_Init 0x00 Initialize AES engine Parameter - void Return - void aes_SetMode 0x04 Defines AES engine operation mode...
- Page 49 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API Table 23. Security API calls Function Offset relative to Description the API entry point aes_Operate 0x1C Performs the AES decryption after the AES mode has been set using aes_Set_Mode and the appropriate keys and init vectors have been loaded.
- Page 50 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API DECRYPTION decrypt header with AES AES key = User Key IV = 0 0x3456 replace MAC by constant 789A encrypt temporary header with AES AES key = User Key IV = 0...
- Page 51 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API 1. Divide message into b-bit blocks M = M || … || M || M * where M , …, M complete blocks. M 2. M 3. Set c = 00...0 (binary).
- Page 52 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API AES plain text - Array of 16 bytes Printe d text Byte Nr RAM address AES key - Array of 16 bytes Printed text Byte Nr RAM address AES cypher text - Array of 16 bytes...
- Page 53 UM10503 NXP Semiconductors Chapter 6: LPC43xx Security API 1. Load the stored random number from the backup register. 2. Load this number in the AES engine using aes_LoadKeySW. UM10503 All information provided in this document is subject to legal disclaimers.
- Page 54 UM10503 Chapter 7: LPC43xx Nested Vectored Interrupt Controller (NVIC) Rev. 1.3 — 6 July 2012 User manual 7.1 How to read this chapter The NVIC interrupt sources vary for different parts. • Ethernet interrupt: available only on LPC435x/3x. • USB0 interrupt: available only on LPC435x/3x/2x. •...
- Page 55 UM10503 NXP Semiconductors Chapter 7: LPC43xx Nested Vectored Interrupt Controller (NVIC) 7.5 Pin description Table 24. NVIC pin description Function Direction Description External Non-Maskable Interrupt (NMI) input 7.6 Interrupt sources Table 25 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller.
- Page 56 UM10503 NXP Semiconductors Chapter 7: LPC43xx Nested Vectored Interrupt Controller (NVIC) Table 25. Connection of interrupt sources to the Cortex-M4 NVIC Interrupt Exception Vector Function Flag(s) Number Offset 0x8C I2C1 0x90 0x94 ADC1 0x98 SSP0 0x9C SSP1 0xA0 USART0 0xA4...
- Page 57 UM10503 NXP Semiconductors Chapter 7: LPC43xx Nested Vectored Interrupt Controller (NVIC) 7.6.2 Interrupt sources for the Cortex-M0 Table 26. Connection of interrupt sources to the Cortex-M0 NVIC Interrupt Exception Vector Function Flag(s) Number Offset 0x40 M0_RTC 0x44 M0_M4CORE Interrupt from the M4 core...
- Page 58 UM10503 NXP Semiconductors Chapter 7: LPC43xx Nested Vectored Interrupt Controller (NVIC) 7.7 Register description The following table summarizes the registers in the NVIC. The Cortex-M4/M0 User Guides provide a functional description of the NVIC registers. Table 27. Register overview: NVIC (base address 0xE000 E000)
- Page 59 UM10503 Chapter 8: LPC43xx Event router Rev. 1.3 — 6 July 2012 User manual 8.1 How to read this chapter The event router sources vary for different parts. • Ethernet: available only on LPC435x/3x. • USB0: available only on LPC435x/3x/2x. •...
- Page 60 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Each event input to the event router can be configured to trigger an output signal on rising or falling edges or on HIGH or LOW levels. The event router combines all events to an output signal which is used as follows: •...
- Page 61 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 29. Event router inputs Event # Source Description Ethernet peripheral Wake-up packet indicator. Not active in Deep-sleep, Power-down, and Deep power-down mode. Use for wake-up from Sleep mode. USB0 peripheral Wake-up request signal. Not active in Deep-sleep, Power-down, and Deep power-down mode.
- Page 62 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router 8.6 Register description Table 31. Register overview: Event router (base address 0x4004 4000) Name Access Address Description Reset Reference offset Value HILO 0x000 Level configuration register 0x000 Table 32 EDGE 0x004 Edge configuration...
- Page 63 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 32. Level configuration register (HILO - address 0x4004 4000) bit description Symbol Value Description Reset value WAKEUP3_L Level detect mode for WAKEUP3 event. Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0.
- Page 64 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 32. Level configuration register (HILO - address 0x4004 4000) bit description Symbol Value Description Reset value USB0_L Level detect mode for USB0 event Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0.
- Page 65 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 32. Level configuration register (HILO - address 0x4004 4000) bit description Symbol Value Description Reset value QEI_L Level detect mode for QEI event. Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0.
- Page 66 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 34. Edge configuration register (EDGE - address 0x4004 4004) bit description Symbol Value Description Reset value WAKEUP0_E Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.
- Page 67 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 34. Edge configuration register (EDGE - address 0x4004 4004) bit description Symbol Value Description Reset value WWDT_E Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.
- Page 68 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 34. Edge configuration register (EDGE - address 0x4004 4004) bit description Symbol Value Description Reset value TIM6_E Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.
- Page 69 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 35. Clear event enable register (CLR_EN - address 0x4004 4FD8) bit description Symbol Description Reset value RTC_CLREN Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register.
- Page 70 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 36. Event set enable register (SET_EN - address 0x4004 4FDC) bit description Symbol Description Reset value RTC_SETEN Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register.
- Page 71 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 37. Event status register (STATUS - address 0x4004 4FE0) bit description Symbol Description Reset value ETH_ST A 1 in this bit shows that the ETHERNET event has been raised. - USB0_ST A 1 in this bit shows that the USB0 event has been raised.
- Page 72 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 38. Event enable register (ENABLE - address 0x4004 4FE4) bit description Symbol Description Reset value BOD_EN A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.
- Page 73 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 39. Clear event status register (CLR_STAT - address 0x4004 4FE8) bit description Symbol Description Reset value WAKEUP0_CLRST Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register.
- Page 74 UM10503 NXP Semiconductors Chapter 8: LPC43xx Event router Table 40. Set event status register (SET_STAT - address 0x4004 4FEC) bit description Symbol Description Reset value WAKEUP0_SETST Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register.
- Page 75 UM10503 Chapter 9: LPC43xx Configuration Registers (CREG) Rev. 1.3 — 6 July 2012 User manual 9.1 How to read this chapter The available peripherals vary for different parts. • Ethernet: available only on LPC435x/3x. • USB0: available only on LPC435x/3x/2x. •...
- Page 76 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) 9.3 Features The following settings are controlled in the configuration register block: • ETB SRAM configuration • BOD trip settings • RTC Oscillator output • DMA-to-peripheral muxing • Ethernet mode •...
- Page 77 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) 9.4 Register description Table 42. Register overview: Configuration registers (base address 0x4004 3000) Name Access Address Description Reset Reset Reset Reference offset value value after value EMC, after UART0/3 USB0/1 boot...
- Page 78 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) Table 42. Register overview: Configuration registers (base address 0x4004 3000) Name Access Address Description Reset Reset Reset Reference offset value value after value EMC, after UART0/3 USB0/1 boot boot M0APPMEMMAP 0x404...
- Page 79 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) Table 43. CREG0 register (CREG0, address 0x4004 3004) bit description …continued Symbol Value Description Reset Access value BODLVL1 BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.
- Page 80 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) 9.4.3 CREG5 control register Use this register to disable the JTAG for the M4 main core and the M0 co-processor. By default the JTAG access is enabled unless an AES key is programmed and the device is a secure device.
- Page 81 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) Table 46. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value DMAMUXPER3 Select DMA to peripheral connection for DMA peripheral 3. Timer 1 match 0...
- Page 82 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) Table 46. DMA mux control register (DMAMUX, address 0x4004 311C) bit description Symbol Value Description Reset Access value 21:20 DMAMUXPER10 Select DMA to peripheral connection for DMA peripheral 10. SSP0 transmit...
- Page 83 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) Changing the FLASHCFG register value causes the flash accelerator to invalidate all of the holding latches, resulting in new reads of flash information as required. This guarantees synchronization of the flash accelerator to CPU operation.
- Page 84 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) Table 48. Flash Accelerator Configuration for flash bank B register (FLASHCFGB - address 0x4004 3124) bit description Symbol Value Description Reset value 11:0 Reserved. Do not change these bits from the reset value.
- Page 85 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) • Bit 4 selects the functionality of the SCT outputs connected to the CTOUT_n pins and selected GIMA inputs: – SCT output ORed with timer match output (default). – SCT output only.
- Page 86 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) 9.4.9 Cortex-M4 TXEV event clear register This register captures the signal TXEV from the ARM Cortex-M4 processor (see Section 2.4.2). Table 51. M4 TXEV clear register (M4TXEVENT, address 0x4004 3130) bit description...
- Page 87 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) 9.4.13 USB0 frame length adjust register Remark: This register is only implemented for parts with on-chip flash. See Section 9.1. The USB frame length adjust register is used to adjust any offset from the clock source that generates the clock that drives the SOF counter.
- Page 88 UM10503 NXP Semiconductors Chapter 9: LPC43xx Configuration Registers (CREG) This register should not be reprogrammed by USB system software unless the default values are incorrect, or the system is restoring the register while returning from a suspended state. For details on using the SOF signal, see Section 23.7.7.1.
- Page 89 UM10503 Chapter 10: LPC43xx Power Management Controller (PMC) Rev. 1.3 — 6 July 2012 User manual 10.1 How to read this chapter The power management controller is identical on all LPC43xx parts. 10.2 General description The PMC implements the control sequences to enable transitioning between different power modes and controls the power state of each peripheral.
- Page 90 UM10503 NXP Semiconductors Chapter 10: LPC43xx Power Management Controller (PMC) 10.2.3 Deep-sleep mode In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power; logic states and SRAM memory are maintained. All analog blocks and the BOD control circuit are powered down.
-
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UM10503 NXP Semiconductors Chapter 10: LPC43xx Power Management Controller (PMC) 10.2.6 Memory retention in Power-down modes Table 57 shows which parts of the SRAM memory are preserved in Sleep mode and the various power-down modes. In addition, all FIFO memory contained in the peripheral blocks (USB0/1, LCD, CAN, Ethernet, USART0/2/3, UART) is retained in Sleep mode and Deep-sleep mode but not in Power-down mode and Deep-power-down mode. -
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UM10503 NXP Semiconductors Chapter 10: LPC43xx Power Management Controller (PMC) 10.3.1 Hardware sleep event enable register PD0_SLEEP0_HW_ENA Table 59. Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address 0x4004 2000) bit description Symbol Description Reset Access value ENA_EVENT0 Writing a 1 enables the Power-down modes for the Cortex-M4 (see the PD0_SLEEP0_MODE register for selecting the mode). -
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UM10503 NXP Semiconductors Chapter 10: LPC43xx Power Management Controller (PMC) Table 61. Typical settings for PMC power modes Power-down Description PD0_SLEEP0_MODE mode register bit settings Deep-sleep CPU, peripherals, analog, USB PHY in retention mode; 0x0030 00AA all SRAM supplies in active mode; BOD in power-down mode. -
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UM10503 Chapter 11: LPC43xx Clock Generation Unit (CGU) Rev. 1.3 — 6 July 2012 User manual 11.1 How to read this chapter Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See Section 1.3. The corresponding clock control registers are reserved. The VADC peripheral is available on <tbd>... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.2.1.1 Changing the BASE_M4_CLK after power-up, reset, or deep power-down mode The following procedure shows how to change the default setting of the core clock (BASE_M4_CLK = 96 MHz; IRC = clock source) to an operating frequency above 110 MHz while also changing the clock source from IRC to crystal oscillator: 1. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) BASE_M4_CLK BASE_M4_CLK clock source = crystal osc PLL1 PLL1 (crystal osc) (crystal osc) 204 MHz 110 MHz 90 MHz 100 μs 12 MHz configure configure configure wake-up from crystal PLL1 < 110 MHz PLL1 <= 204 MHz... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) PLL0 WWDT BASE_SAFE_CLK (USB0) IDIVA OUTCLK1- 6, 9 - 10 branch clocks to core 12 MHz IRC IDIVB CCU1 PLL0 (BASE_xxx_CLK) and peripherals (AUDIO) RTCX1 32 kHz OSC IDIVC branch clocks to... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) – Integer divider A: maximum division factor = 4 (see Table 81). – Integer dividers B, C, D: maximum division factor = 16 (see Table 82). – Integer divider E: maximum division factor = 256 (see Table 83). -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 64. Clock sources for clock generators with selectable inputs Clock generators Clock sources PLL0 PLL0 PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE AUDIO /256 32 kHz oscillator IRC 12 MHz... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 65. Clock sources for output stages Output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) Clock sources PLL1... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.5 Pin description Table 66. CGU pin description Pin function Direction Description XTAL1 Crystal oscillator input XTAL2 Crystal oscillator output RTCX1 RTC 32 kHz oscillator input RTCX2 RTC 32 kHz oscillator output... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 67. Register overview: CGU (base address 0x4005 0000) Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot PLL0AUDIO_STAT... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 67. Register overview: CGU (base address 0x4005 0000) Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot BASE_SPI_CLK... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 67. Register overview: CGU (base address 0x4005 0000) Name Access Address Description Reset Reset Reset Reference offset value value value after after EMC, USB0/1 UART0/ boot 3 boot OUTCLK_21_CTRL... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 68. FREQ_MON register (FREQ_MON, address 0x4005 0014) bit description Symbol Value Description Reset Access value RCNT 9-bit reference clock-counter value 22:9 FCNT 14-bit selected clock-counter value MEAS Measure frequency... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 69. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit description Symbol Value Description Reset Access value BYPASS Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 71. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description …continued Symbol Value Description Reset Access value DIRECTO PLL0 direct output CLKEN PLL0 clock enable Reserved Free running mode Reserved Reserved. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) case 1: x = 0x00018003; case 2: x = 0x00010003; default: for (i = M; i <= M_max; i++) x = (((x ^ (x>>1)) & 1) << 14) | ((x>>1) & 0x3FFF); } MDEC[16:0] = x;... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) default: for (i = N; i <= N_max; i++) x = (((x ^ (x>>2) ^ (x>>3) ^ (x>>4)) & 1) << 7) | ((x>>1) & 0x7F); } NENC[9:0] = x;... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.6.4.2 PLL0AUDIO control register Table 75. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description Symbol Value Description Reset Access value PLL0 power down PLL0 enabled PLL0 powered down BYPASS Input clock bypass control CCO clock sent to post-dividers. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 75. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values 0x01 are reserved. 0x00... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 76. PLL0AUDIO M-divider register (PLL0AUDIO_MDIV, address 0x4005 0034) bit description Symbol Description Reset Access value 16:0 MDEC Decoded M-divider coefficient value. Select values for 0x5B6A the M-divider between 1 and 131071. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.6.4.5 PLL0AUDIO fractional divider register When the fractional divider is active, the sigma-delta modulator block generates divider values M and M+1 in the correct proportion so that an average division ratio of M+K/L is realized where 0<=K<=L and M, K, and L are integer values. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 80. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description …continued Symbol Value Description Reset Access value FBSEL PLL feedback select (see Figure 29 “PLL1 block diagram”). CCO output is used as feedback divider input clock. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 80. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default) 0x02... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 81. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values 0x01 are reserved. 0x00... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 82. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. All other values 0x01 are reserved. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 83. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. All other values are 0x01 reserved. 0x00 32 kHz oscillator... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 85. BASE_USB0_CLK control register (BASE_USB0_CLK, address 0x4005 0060) bit description Symbol Value Description Reset Access value Output stage power down Output stage enabled (default) power-down 10:1 Reserved AUTOBLOCK Block clock automatically during frequency... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 86. BASE_PERIPH_CLK control register (BASE_PERIPH_CLK, address 0x4005 0064) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved. 0x00... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 87. BASE_USB1_CLK control register (BASE_USB1_CLK, address 0x4005 0068) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved. 0x00... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 88. BASE_M4_CLK to BASE_UART3_CLK control registers (BASE_M4_CLK to BASE_UART3_CLK, address 0x4005 006C to 0x4005 00A8) bit description Symbol Value Description Reset Access value 28:24 CLK_SEL Clock source selection. All other values are 0x01 reserved. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 89. BASE_OUT_CLK control register BASE_OUT_CLK, addresses 0x4005 00AC) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default) -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 90. BASE_APLL_CLK control register (BASE_APLL_CLK, addresses 0x4005 00C0) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. 0x01 0x00 32 kHz oscillator 0x01 IRC (default) -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 91. BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK control register (BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK , addresses 0x4005 00C4 to 0x4005 00C8) bit description …continued Symbol Value Description Reset Access value 28:24 CLK_SEL Clock-source selection. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.7.4.1 Features • Input frequency: 14 kHz to 150 MHz. The input from an external crystal is limited to 25 MHz. • CCO frequency: 275 MHz to 550 MHz. •... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Bypass Direct Output CTRL[1] CTRL[3] 32kHz CLKOUT ENET_RX_CLK ENET_TX_CLK GP_CLKIN CRYSTAL P-DIVIDER N-DIVIDER Filter PLL1 CLKIN IDIVA “1” IDIVB IDIVC IDIVD Bandwidth Select P,I,R NP_DIV[6:0] NP_DIV[21:12] IDIVE MDIV[31:17] Direct Input... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) • mode 1a: Normal operating mode without post-divider and without pre-divider • mode 1b: Normal operating mode with post-divider and without pre-divider • mode 1c: Normal operating mode without post-divider and with pre-divider •... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-divider In normal operating mode 1d none of the dividers are bypassed. The operating frequencies are: Fout = Fcco /(2 x P) = M x Fin /(N x P) (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) the fractional part of the PLLFRACT_CTRL register (PLLFRACT[14:0]). Consecutive M and M+1 values are then further encoded into appropriate MENC values before being presented as input to the M-divider. Bypass... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.7.6.2 PLL1 description PSEL<1:0> NSEL<1:0> LOCK FCLKOUT LOCK DETECT BYPASS DIRECT analog section FBSEL MSEL<7:0> Fig 29. PLL1 block diagram The block diagram of this PLL is shown in Figure 29. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) FCLKIN --------------------- - FCCO FCLKOUT Non-integer mode In this mode the post-divider is enabled and the feedback divider is set to run directly on the CCO clock, which gives the following frequency dividers:... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) 11.8 Example CGU configurations 11.8.1 Programming the CGU for Deep-sleep and Power-down modes Before the LPC43xx enters Deep-sleep or Power-down mode, the IRC must be programmed as the clock source in the control registers for all output stages (OUTCLK_0 to OUTCLK_27). -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 94. PLL0 (for USB) settings for 480 MHz output clock Fclkin [MHz] PLL0USB_MDIV PLL0USB_NP_DIV Table 72 Table 73 0x073E 56C9 0x0030 2062 0x073E 2DAD 0x0030 2062 0x0B3E 34B1 0x0030 2062... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 95. PLL0AUDIO divider settings for 12 MHz input Fs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRL Table 77 Table 78 12.288 417.792 0x00001003 0x1a1cac 44.1 11.2896... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 95. PLL0AUDIO divider settings for 12 MHz input Fs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRL Table 77 Table 78 16.384 360.448 0x0000101d 0x16872b 12.288 417.792... -
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UM10503 NXP Semiconductors Chapter 11: LPC43xx Clock Generation Unit (CGU) Table 96. PLL0AUDIO divider setting for 12 MHz with fractional divider bypassed Fout Fcco Error PLL0AUDIO_ PLL0AUDIO_ [KHz] [MHz] [MHz] [Hz] NDEC MDEC PDEC MDIV NP_DIV Table 76 Table 77 18.432... -
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UM10503 Chapter 12: LPC43xx Clock Control Unit (CCU) Rev. 1.3 — 6 July 2012 User manual 12.1 How to read this chapter Remark: The VADC is not available on parts LPC4350/30/20/10. Flash/EEPROM, Ethernet, USB0, USB1, and LCD-related clocks are not available on all packages. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 98. CCU1 branch clocks Base clock Branch clock Description BASE_APB3_CLK CLK_APB3_BUS APB3 bus clock. CLK_APB3_I2C1 Clock to the I2C1 register interface and I2C1 peripheral clock. CLK_APB3_DAC Clock to the DAC register interface. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 98. CCU1 branch clocks Base clock Branch clock Description BASE_M4_CLK CLK_M4_TIMER0 Clock to the timer0 register interface and timer0 peripheral clock. CLK_M4_TIMER1 Clock to the timer1 register interface and timer1 peripheral clock. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) 12.5 Register description Table 100. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset 0x000 CCU1 power mode register 0x0000 0000 Table 102 BASE_STAT... -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 100. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_M4_SPIFI_STAT 0x40C CLK_M4_SPIFI status register 0x0000 0001 Table 108 CLK_M4_GPIO_CFG 0x410 CLK_M4_GPIO configuration register... -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 100. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_M4_WWDT_CFG 0x500 CLK_M4_WWDT configuration register 0x0000 0001 Table 105 CLK_M4_WWDT_STAT 0x504 CLK_M4_WWDT status register... -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 100. Register overview: CCU1 (base address 0x4005 1000) Name Access Address Description Reset value Reference offset CLK_PERIPH_SGPIO_CFG 0x718 CLK_PERIPH_SGPIO configuration 0x0000 0001 Table 105 register CLK_PERIPH_SGPIO_STAT 0x71C CLK_PERIPH_SGPIO status register... -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 101. Register overview: CCU2 (base address 0x4005 2000) Name Access Address Description Reset value Reference offset 0x508 to Reserved 0x5FC CLK_APB2_SSP1_CFG 0x600 CLK_APB2_SSP1 configuration register 0x0000 0001 Table 107... -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 103. CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit description Symbol Description Reset Access value BASE_APB3_ Base clock indicator for BASE_APB3_CLK CLK_IND 0 = All branch clocks switched off. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 104. CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit description …continued Symbol Description Reset Access value BASE_UART0_ Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 105. CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 1100, 0x4005 1104,..., 0x4005 1A00) bit description Symbol Value Description Reset Access value Run enable Clock is disabled. Clock is enabled. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 107. CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 2100, 0x4005 2200,..., 0x4005 2800) bit description Symbol Value Description Reset Access value Run enable Clock is disabled. Clock is enabled. -
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UM10503 NXP Semiconductors Chapter 12: LPC43xx Clock Control Unit (CCU) Table 109. CCU2 branch clock status register (CLK_XXX_STAT, addresses 0x4005 2104, 0x4005 2204,..., 0x4005 2804) bit description Symbol Description Reset Access value Run enable status 0 = clock is disabled... -
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UM10503 Chapter 13: LPC43xx Reset Generation Unit (RGU) Rev. 1.3 — 6 July 2012 User manual 13.1 How to read this chapter Flash/EEPROM, Ethernet, USB0, USB1, and LCD related resets are not available on all packages or parts. See Section 1.3. -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 111. Reset output configuration Reset output Reset Reset source Parts of the device reset when generator output activated CORE_RST external reset, Entire chip including peripherals in the BOD reset,... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 111. Reset output configuration …continued Reset output Reset Reset source Parts of the device reset when generator output activated SCT_RST PERIPH_RST State Configurable Timer reset MOTOCONPWM_RST 38 PERIPH_RST Motor control PWM reset... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) The second level of granularity is monitored by one individual register for each reset output (RESET_EXT_STATUSn) in which the detailed reset cause is indicated, that is whether or not any of the possible inputs to each reset generator are activated. The... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) TRSTn TRSTn_loc ext_rst_an(0) bod_rst_an(4) core_rst_out_n delay=1 wwdt_rst_an(5) pmc_rst_an core_rst_an(1) wwdt_rst_out_n delay=1 no sw creg_rst_out_n delay=1 no sw periph_rst_out_n delay=3 periph_rst_an(2) spi,etc ..delay=0 master_rst_out_n delay=3 master_rst_an(3) m4,usb,lcd,etc... delay=0 Fig 31. RGU Reset structure 13.4 Register overview... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 113. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT7 0x41C Reserved RESET_EXT_STAT8 0x420 Reset external status register 8 for Table 127... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 113. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT35 0x48C Reset external status register 35 for Table 127 TIMER3_RST RESET_EXT_STAT36... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 113. Register overview: RGU (base address: 0x4005 3000) …continued Name Access Address Description Reset value Reference offset RESET_EXT_STAT58 0x4E8 Reset external status register 58 for Table 127 SPI_RST RESET_EXT_STAT59... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 114. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description …continued Symbol Description Reset Access value USB0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 115. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description …continued Symbol Description Reset Access value ADC0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) 13.4.2 RGU reset status register The reset status register shows which source (if any) caused the last reset activation per individual reset output of the RGU. When one (or more) inputs of the RGU caused the... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 116. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Symbol Description Reset Access value 19:18 SCU_RST Status of the SCU_RST reset generator output 00 = No reset activated... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 117. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description …continued Symbol Description Reset Access value SDIO_RST Status of the SDIO_RST reset generator output 00 = No reset activated... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 118. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description Symbol Description Reset Access value TIMER0_RST Status of the TIMER0_RST reset generator output 00 = No reset activated... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 118. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued …continued Symbol Description Reset Access value 17:16 ADC0_RST Status of the ADC0_RST reset generator output 00 = No reset activated... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 119. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description Symbol Description Reset Access value I2C0_RST Status of the I2C0_RST reset generator output 00 = No reset activated... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 119. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description …continued Symbol Description Reset Access value 17:16 M0APP_RST Status of the M0APP_RST reset generator output 00 = No reset activated... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 120. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued Symbol Description Reset Access value CREG_RST Current status of the CREG_RST 0 = Reset asserted 1 = No reset... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 120. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description …continued Symbol Description Reset Access value Reserved Reserved FLASHA_RST Current status of the FLASHA_RST 0 = Reset asserted... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 121. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued Symbol Description Reset Access value MOTOCONPWM_RST Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 121. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description …continued Symbol Description Reset Access value I2S_RST Current status of the I2S_RST 0 = Reset asserted 1 = No reset... -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) 13.4.4.1 Reset external status register 0 for CORE_RST This register shows whether or not any of the inputs to the CORE_RST reset generator has activated the CORE_RST. The CORE_RST can be activated by the external reset pin, a WWDT time-out, a BOD reset or by writing to bit 0 of the RESET_CTRL0 register. -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) 13.4.4.3 Reset external status register 2 for MASTER_RST Table 124. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit description Symbol Description Reset Access value Reserved. Do not modify; read as logic 0. -
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UM10503 NXP Semiconductors Chapter 13: LPC43xx Reset Generation Unit (RGU) Table 127. Reset external status registers x (RESET_EXT_STATx, address 0x4005 34xx) bit description Symbol Description Reset Access value Reserved. Do not modify; read as logic 0. PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. -
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UM10503 Chapter 14: LPC43xx Pin configuration Rev. 1.3 — 6 July 2012 User manual 14.1 How to read this chapter This chapter applies to all parts. 14.2 Pin description On the LPC43xx, digital pins are grouped into 16 pin groups, named P0 to P9 and PA to PF, with up to 20 pins used per group. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description Multiplexed digital pins P0_0 I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_1 I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 19). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_5 I/O GPIO1[8] — General purpose digital input/output pin. CTOUT_10 — SCT output 10. Match output 2 of timer 2. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_8 I/O GPIO1[1] — General purpose digital input/output pin. U1_DTR — Data Terminal Ready output for UART1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_12 I/O GPIO1[5] — General purpose digital input/output pin. U1_DCD — Data Carrier Detect input for UART1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_16 I/O GPIO0[3] — General purpose digital input/output pin. U2_RXD — Receiver input for USART2. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P1_20 K10 100 70 I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_2 121 84 I/O SGPIO6 — General purpose digital input/output pin. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_5 D10 131 91 I/O SGPIO14 — General purpose digital input/output pin. CTIN_2 — SCT input 2. Capture input 2 of timer 0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_8 140 98 I/O SGPIO15 — General purpose digital input/output pin. Boot pin (see Table 19). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P2_12 153 106 I/O GPIO1[12] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 3 of timer 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_1 163 114 I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_4 171 119 I/O GPIO1[14] — General purpose digital input/output pin. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P3_7 176 123 R — Function reserved. I/O SPI_MOSI — Master Out Slave In for SPI. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_1 I/O GPIO2[1] — General purpose digital input/output pin. CTOUT_1 — SCT output 1. Match output 3 of timer 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_4 I/O GPIO2[4] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P4_7 LCD_DCLK — LCD panel clock. GP_CLKIN — General purpose clock input to the CGU. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P5_0 I/O GPIO2[9] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P5_4 I/O GPIO2[13] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_0 105 73 R — Function reserved. I2S0_RX_MCLK — I2S receive master clock. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_3 113 79 I/O GPIO3[2] — General purpose digital input/output pin. USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit);... -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_6 119 83 I/O GPIO0[5] — General purpose digital input/output pin. EMC_BLS1 — LOW active Byte Lane select signal 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P6_10 142 100 I/O GPIO3[6] — General purpose digital input/output pin. MCABORT — Motor control PWM, LOW-active fast abort. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_1 162 113 I/O GPIO3[9] — General purpose digital input/output pin. CTOUT_15 — SCT output 15. Match output 3 of timer 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P7_5 191 133 I/O GPIO3[13] — General purpose digital input/output pin. CTOUT_12 — SCT output 12. Match output 3 of timer 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_0 I/O GPIO4[0] — General purpose digital input/output pin. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition;... -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_4 I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P8_8 R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P9_3 I/O GPIO4[15] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description P9_6 103 72 I/O GPIO4[11] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PA_3 147 - I/O GPIO4[10] — General purpose digital input/output pin. QEI_PHA — Quadrature Encoder Interface PHA input. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PB_2 177 - R — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PB_6 R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_2 I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_6 R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_10 R — Function reserved. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PC_14 R — Function reserved. R — Function reserved. U1_RXD — Receiver input for UART 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_3 R — Function reserved. CTOUT_6 — SCT output 7. Match output 2 of timer 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_7 R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_11 R — Function reserved. R — Function reserved. EMC_CS3 — LOW active Chip Select 3 signal. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PD_15 101 - R — Function reserved. R — Function reserved. I/O EMC_A17 — External memory address line 17. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_2 115 - ADCTRIG0 — ADC trigger input 0. CAN0_RD — CAN receiver input. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_6 124 - R — Function reserved. CTOUT_2 — SCT output 2. Match output 2 of timer 0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_10 154 - R — Function reserved. CTIN_3 — SCT input 3. Capture input 1 of timer 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PE_14 R — Function reserved. R — Function reserved. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_2 168 - R — Function reserved. U3_TXD — Transmitter output for USART3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_6 192 - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description PF_9 203 - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description CLK0 EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description DBGEN JTAG interface control signal. Also used for boundary scan. TCK/SWDCLK I; F Test Clock for JTAG interface (default) or Serial Wire (SW) clock. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description [12] WAKEUP2 I; IA External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description VBAT 184 127 RTC power supply: 3.3 V on this pin supplies power to the RTC. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 129. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. Symbol Description VSSA 196 135 Analog ground. Not connected n.c. x = available; - = not pinned out. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description Pin name Description Multiplexed digital pins P0_0 I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P1_2 I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 19). CTOUT_6 — SCT output 6. Match output 2 of timer 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P1_6 I/O GPIO1[9] — General purpose digital input/output pin. CTIN_5 — SCT input 5. Capture input 2 of timer 2. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P1_10 I/O GPIO1[3] — General purpose digital input/output pin. U1_RI — Ring Indicator input for UART1. CTOUT_14 — SCT output 14. Match output 2 of timer 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P1_14 I/O GPIO1[7] — General purpose digital input/output pin. U1_RXD — Receiver input for UART1. R — Function reserved. I/O EMC_D7 — External memory data line 7. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P1_18 I/O GPIO0[13] — General purpose digital input/output pin. I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. R — Function reserved. ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P2_0 I/O SGPIO4 — General purpose digital input/output pin. U0_TXD — Transmitter output for USART0. See Table 18 for ISP mode. I/O EMC_A13 — External memory address line 13. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P2_3 I/O SGPIO12 — General purpose digital input/output pin. I/O I2C1_SDA — I C1 data input/output (this pin does not use a specialized I C pad). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P2_6 I/O SGPIO7 — General purpose digital input/output pin. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O EMC_A10 — External memory address line 10. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P2_10 I/O GPIO0[14] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U2_TXD — Transmitter output for USART2. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P3_0 I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I S-bus specification. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P3_3 R — Function reserved. I/O SPI_SCK — Serial clock for SPI. I/O SSP0_SCK — Serial clock for SSP0. SPIFI_SCK — Serial clock for SPIFI. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P3_6 I/O GPIO0[6] — General purpose digital input/output pin. I/O SPI_MISO — Master In Slave Out for SPI. I/O SSP0_SSEL — Slave Select for SSP0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P4_1 I/O GPIO2[1] — General purpose digital input/output pin. CTOUT_1 — SCT output 1. Match output 3 of timer 3. LCD_VD0 — LCD data. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P4_4 I/O GPIO2[4] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. LCD_VD1 — LCD data. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P4_8 R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. LCD_VD9 — LCD data. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P5_1 I/O GPIO2[10] — General purpose digital input/output pin. MCI2 — Motor control PWM channel 2, input. I/O EMC_D13 — External memory data line 13. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P5_5 I/O GPIO2[14] — General purpose digital input/output pin. MCOA1 — Motor control PWM channel 1, output A. I/O EMC_D9 — External memory data line 9. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P6_1 I/O GPIO3[0] — General purpose digital input/output pin. EMC_DYCS1 — SDRAM chip select 1. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P6_4 I/O GPIO3[3] — General purpose digital input/output pin. CTIN_6 — SCT input 6. Capture input 1 of timer 3. U0_TXD — Transmitter output for USART0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P6_8 R — Function reserved. I/O EMC_A14 — External memory address line 14. I/O SGPIO7 — General purpose digital input/output pin. USB0_IND0 — USB0 port indicator LED control output 0. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P6_12 I/O GPIO2[8] — General purpose digital input/output pin. CTOUT_7 — SCT output 7. Match output 3 of timer 1. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P7_3 I/O GPIO3[11] — General purpose digital input/output pin. CTIN_3 — SCT input 3. Capture input 1 of timer 1. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P7_7 I/O GPIO3[15] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P8_3 I/O GPIO4[3] — General purpose digital input/output pin. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. R — Function reserved. LCD_VD12 — LCD data. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P8_7 I/O GPIO4[7] — General purpose digital input/output pin. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P9_2 I/O GPIO4[14] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. R — Function reserved. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description P9_6 I/O GPIO4[11] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current condition;... -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PA_3 I/O GPIO4[10] — General purpose digital input/output pin. QEI_PHA — Quadrature Encoder Interface PHA input. R — Function reserved. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PB_2 R — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. LCD_VD21 — LCD data. R — Function reserved. I/O GPIO5[22] — General purpose digital input/output pin. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PB_6 R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. LCD_VD13 — LCD data. R — Function reserved. I/O GPIO5[26] — General purpose digital input/output pin. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PC_3 I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. R — Function reserved. U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART ENET_TXD3 —... -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PC_7 R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved. ENET_RXD3 — Ethernet receive data 3 (MII interface). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PC_11 R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI data line direction. U1_DCD — Data Carrier Detect input for UART 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PD_0 R — Function reserved. CTOUT_15 — SCT output 15. Match output 3 of timer 3. EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PD_4 R — Function reserved. CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PD_8 R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PD_12 R — Function reserved. R — Function reserved. EMC_CS2 — LOW active Chip Select 2 signal. R — Function reserved. I/O GPIO6[26] — General purpose digital input/output pin. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PD_16 R — Function reserved. R — Function reserved. I/O EMC_A16 — External memory address line 16. R — Function reserved. I/O GPIO6[30] — General purpose digital input/output pin. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PE_3 R — Function reserved. CAN0_TD — CAN transmitter output. ADCTRIG1 — ADC trigger input 1. I/O EMC_A21 — External memory address line 21. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PE_7 R — Function reserved. CTOUT_5 — SCT output 5. Match output 3 of timer 3. U1_CTS — Clear to Send input for UART1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PE_11 R — Function reserved. CTOUT_12 — SCT output 12. Match output 3 of timer 3. U1_TXD — Transmitter output for UART 1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PE_15 R — Function reserved. CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O I2C1_SCL — I C1 clock input/output (this pin does not use a specialized I C pad). -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PF_3 R — Function reserved. U3_RXD — Receiver input for USART3. I/O SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PF_6 R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description PF_9 R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. CTOUT_1 — SCT output 1. Match output 3 of timer 3. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description Clock pins CLK0 EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. I/O SD_CLK — SD/MMC card clock. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description TCK/SWDCLK I; F Test Clock for JTAG interface (default) or Serial Wire (SW) clock. TRST I; PU I Test Reset for JTAG interface. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description ADC pins ADC0_0/ I; IA ADC input channel 0. Shared between 10-bit ADC0/1 and DAC. ADC1_0/DAC ADC0_1/ I; IA ADC input channel 1. Shared between 10-bit ADC0/1. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration Table 130. LPC4357/53 Pin description …continued Pin name Description [13] VDDIO I/O power supply. Tie the VDDREG and VDDIO pins to a common E12, H10, power supply to ensure the same ramp-up time for both supply voltages. -
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UM10503 NXP Semiconductors Chapter 14: LPC43xx Pin configuration 5 V tolerant transparent analog pad. = 6.5 F and maximum resistance R For maximum load C = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS = 0.2 V when it is no longer driven. -
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UM10503 Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Rev. 1.3 — 6 July 2012 User manual 15.1 How to read this chapter The following peripherals are not available on all parts, and the corresponding bit values that select those functions in the SFSP registers are reserved: •... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration VDDIO enable output driver data output from core slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration 15.3.3 Input buffer To be able to receive a digital signal, the input buffer must be enabled through bit EZI in the pin configuration registers (see Figure 32). By default, the input buffer is disabled. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration 15.3.10 EMC signal delay control The SCU contains a programmable delay control for all EMC SDRAM clocks (seeTable 144). 15.3.11 Pin multiplexing Multiplexed digital pins are grouped into 16 pin groups, named P0 to P9 and PA to PF, with up to 20 pins used per group. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 132. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name Access Address Description Reset Reset Reset Reference offset value value value after after UART... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 133. Pin configuration registers for normal-drive pins (SFS, address 0x4008 6000 (SPSP0_0) to 0x4008 67AC (SFSPF_11)) bit description Symbol Value Description Reset Access value MODE Select pin function. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration • P8_0 to P8_2 • PA_1 to PA_3 Table 134. Pin configuration registers for high-drive pins (SFS, address 0x4008 60C4 (SFSP1_17) to 0x4008 650C (SFSPA_3) bit description Symbol... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration 15.4.3 Pin configuration registers for high-speed pins Each digital pin and each clock pin on the LPC43xx have an associated pin configuration register which determines the pin’s function and electrical characteristics. The assigned functions for each pin are listed in <tbd>. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 136. Pin configuration for pins USB1_DP/USB1_DM register (SFSUSB, address 0x4008 6C80) bit description Symbol Value Description Reset Access value USB_AIM Differential data input AIP/AIM. Going LOW with full speed edge rate... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration C-bus pins register (SFSI2C0, address 0x4008 Table 137. Pin configuration for open-drain I 6C84) bit description …continued Symbol Value Description Reset Access value SCL_EZI Enable the input receiver for the SCL pin. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 138. Pins controlled by the ENAIO0 register ADC function ENAIO0 register bit P4_3 ADC0_0 P4_1 ADC0_1 PF_8 ADC0_2 P7_5 ADC0_3 P7_4 ADC0_4 PF_10 ADC0_5 PB_6 ADC0_6 By default, all pins are connected to their digital function 0 and only the digital pad is available. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 139. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description Symbol Value Description Reset Access value ADC0_6 Select ADC0_6 Digital function selected on pin PB_6. Analog function ADC0_6 selected on pin PB_6. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 141. ADC1 function select register (ENAIO1, address 0x4008 6C8C) bit description Symbol Value Description Reset Access value ADC1_1 Select ADC1_1 Digital function selected on pin PC_0. Analog function ADC1_1 selected on pin PC_0. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration 1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in input mode. 2. Disable the receiver by setting the EZI bit to zero (see... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 144. EMC clock delay register (EMCDELAYCLK, address 0x4008 6D00) bit description Symbol Description Reset Access value 15:0 CLK_DELAY EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 ... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 145. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description Symbol Value Description Reset value 15:13 PORTSEL1 Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register. -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration To enable each pin interrupt and configure its edge or level sensitivity, use the GPIO pin interrupt registers (see Section 17.4.1). Table 146. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description... -
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UM10503 NXP Semiconductors Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration Table 146. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description Symbol Value Description Reset value 31:29 PORTSEL7 Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register. -
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UM10503 Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Rev. 1.3 — 6 July 2012 User manual 16.1 How to read this chapter Remark: The VADC block is not available on the LPC4350/30/20/10 and LPC4357/53. 16.2 Basic configuration The GIMA is configured as follows: •... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) • I2S0/1 MWS signal • USART0/2/3 RX/TX active signal • USB0/1 SOF signal The following peripheral functions are connected to GIMA outputs: • Timer0/1/2/3 capture inputs • SCT inputs •... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 148. GIMA outputs GIMA GIMA output GIMA inputs Reference output connected to T0 capture channel 0 pin CTIN_0 SGPIO3 pin T0_CAP0 Table 150 T0 capture channel 1 pin CTIN_1... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 148. GIMA outputs GIMA GIMA output GIMA inputs Reference output connected to Event router input 14 SCT output 6 or T1 SGPIO12 T1 match Table 176 match channel 2... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) 16.4 Register description Table 149. Register overview: GIMA (base address: 0x400C 7000) Name Access Address Description Reset Reference offset value CAP0_0_IN 0x000 Timer 0 CAP0_0 capture input multiplexer (GIMA... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 149. Register overview: GIMA (base address: 0x400C 7000) Name Access Address Description Reset Reference offset value CTIN_6_IN 0x058 SCT CTIN_6 capture input multiplexer (GIMA output Table 172 CTIN_7_IN... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) 16.4.2 Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN) Table 151. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit description Symbol Value Description Reset value Invert input Not inverted. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 152. Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN, address 0x400C 7008) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTIN_2... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 154. Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN, address 0x400C 7010) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) 16.4.7 Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN) Table 156. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit description Symbol Value Description Reset value Invert input Not inverted. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 157. Timer 1 CAP1_3 capture input multiplexer (CAP1_3_IN, address 0x400C 701C) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTOUT_3 or T0_MAT3... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 159. Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN, address 0x400C 7024) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) 16.4.12 Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN) Table 161. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit description Symbol Value Description Reset value Invert input Not inverted. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 162. Timer 3 CAP3_0 capture input multiplexer (CAP3_0_IN, address 0x400C 7030) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. 0 CTIN_0 <tbd>... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 164. Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN, address 0x400C 7038) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) 16.4.17 SCT CTIN_0 capture input multiplexer (CTIN_0_IN) Table 166. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit description Symbol Value Description Reset value Invert input Not inverted. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 167. SCT CTIN_1 capture input multiplexer (CTIN_1_IN, address 0x400C 7044) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTIN_1 USART2 TX active... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 169. SCT CTIN_3 capture input multiplexer (CTIN_3_IN, address 0x400C 704C) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) 16.4.22 SCT CTIN_5 capture input multiplexer (CTIN_5_IN) Table 171. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit description Symbol Value Description Reset value Invert input Not inverted. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 172. SCT CTIN_6 capture input multiplexer (CTIN_6_IN, address 0x400C 7058) bit description Symbol Value Description Reset value SELECT Select input. Values 0x4 to 0xF are reserved. CTIN_6 USART3 TX active... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 174. VADC trigger input multiplexer (VADC_TRIGGER_IN, address 0x400C 7060) bit description …continued Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 175. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064) bit description Symbol Value Description Reset value SELECT Select input. Values 0x3 to 0xF are reserved. CTOUT_2 or T0_MAT2... -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 177. Event router input 16multiplexer (EVENTROUTER_16_IN, address 0x400C 706C) bit description Symbol Value Description Reset value SYNCH Enable synchronization Disable synchronization. Enable synchronization. PULSE Enable single pulse generation. -
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UM10503 NXP Semiconductors Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA) Table 179. ADC start1 input multiplexer (ADCSTART1_IN, address 0x400C 7074) bit description Symbol Value Description Reset value EDGE Enable rising edge detection No edge detection. Rising edge detection enabled. -
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UM10503 Chapter 17: LPC43xx GPIO Rev. 1.3 — 6 July 2012 User manual 17.1 How to read this chapter All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO registers are reserved (see Table 180). -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO 17.3 Features 17.3.1 GPIO pin interrupt features • Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO When the designated pattern is detected on the selected input pins, the GPIO grouped interrupt block will generate an interrupt. If the part is in a power-savings mode it will first asynchronously wake the part up prior to asserting the interrupt request. The interrupt request line can be cleared by writing a one to the interrupt status bit in the control register. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO 17.5 Register description The GPIO consists of the following blocks: • The GPIO pin interrupts block at address 0x4008 7000. Registers in this block enable the up to 8 pin interrupts selected in the PINTSELn registers (see... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 183. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000) Name Access Address Description Reset value Reference offset PORT_POL4 R/W 0x030 GPIO grouped interrupt port 4 polarity register 0xFFFF FFFF Table 197... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 185. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 180). Name Access Address Description Reset Width Reference offset value... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 185. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 180). Name Access Address Description Reset Width Reference offset value... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 185. Register overview: GPIO port (base address 0x400F 4000) The highest pin number on each port depends on package size (see Table 180). Name Access Address Description Reset Width Reference offset value... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO 17.5.1.3 Pin interrupt level (rising edge) interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 145 Table 146), one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register: •... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 190. Pin interrupt active level (falling edge) interrupt enable register (IENF, address 0x4008 7010) bit description Symbol Description Reset Access value ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 192. Pin interrupt active level (falling edge) interrupt clear register (CIENF, address 0x4008 7018) bit description Symbol Description Reset Access value CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO 17.5.1.10 Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones to this register clears both rising- and falling-edge detection for the pin. For level-sensitive pins, writing ones inverts the corresponding bit in the Active level register, thus switching the active level on the pin. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 197. GPIO grouped interrupt port polarity registers (PORT_POL, addresses 0x4008 8020 (PORT_POL0) to 0x4008 803C (PORT_POL7) (GROUP0 INT) and 0x4008 9020 (PORT_POL0) to 0x4008 903C (PORT_POL7) (GROUP1 INT)) bit description Symbol Description... -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Table 199. GPIO port byte pin registers (B, addresses 0x400F 4000 (B0) to 0x400F 00FC (B255)) bit description Symbol Description Reset Access value PBYTE Read: state of the pin GPIOn[m], regardless of direction, masking, or alternate function. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO 17.5.3.4 GPIO port mask registers Each GPIO port has one mask register. The mask registers affect writing and reading the MPORT registers. Zeroes in these registers enable reading and writing; ones disable writing and result in zeros in corresponding positions when reading. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO 17.5.3.7 GPIO port set registers Each GPIO port has one port set register. Output bits can be set by writing ones to these registers, regardless of MASK registers. Reading from these register returns the port’s output bits, regardless of pin directions. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO • The state of a single pin can be read in all bits of a byte, halfword, or word from a Word Pin register. • The state of multiple pins in a port can be read as a byte, halfword, or word from a PORT register. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO Applications in which interrupts can result in Masked GPIO operation, or in task switching among tasks that do Masked GPIO operation, must treat code that uses the Mask register as a protected/restricted region. This can be done by interrupt disabling or by using a semaphore. -
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UM10503 NXP Semiconductors Chapter 17: LPC43xx GPIO The raw interrupt request from each of the two group interrupts is sent to the NVIC, which can be programmed to treat it as level- or edge-sensitive (see Table 25). 17.6.5 Recommended practices The following lists some recommended uses for using the GPIO port registers: •... -
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UM10503 Chapter 18: LPC43xx Serial GPIO (SGPIO) Rev. 1.3 — 6 July 2012 User manual 18.1 How to read this chapter The SGPIO is available on all LPC43xx parts. The 12-bit ADC is not available on parts LPC4350/30/20/10. 18.2 Basic configuration The SGPIO is configured as follows: •... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.4 General description Serial GPIO (SGPIO) offer standard GPIO functionality enhanced with features to accelerate serial stream processing. A data stream on a single SGPIO input or output or on a dual, quad, and byte lane data input/output is processed by using so called slices. Up to 16 slices are supported, and all 16 slices have the same basic feature set with some slices offering additional features. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) – Output clock polarity can be inverted. • Interface – The register memory map supports use of ARM Store Multiple and Load Multiple instructions. Slice functions that control the same features are mapped in consecutive registers. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6 Register description Table 211. Register overview: SGPIO (base address 0x4010 1000) Name Access Address offset Description Reset Reference value OUT_MUXCFG0 to 0x0000 to 0x003C Pin multiplexer configuration registers. Table 212... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 211. Register overview: SGPIO (base address 0x4010 1000) Name Access Address offset Description Reset Reference value SET_EN_2 0x0F44 Pattern match interrupt set mask Table 245 ENABLE_2 0x0F48 Pattern match interrupt enable... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 212. Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15, addresses 0x4010 1000 to 0x4010 103C) bit description Symbol Value Description Reset Access value P_OUT_CFG Output control of output SGPIOn. All other values are reserved. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 213. Output pin multiplexing SGPIO Output mode - register OUT_MUX_CFG, bits P_OUT_CFG (see Table 212) 1011 1010 1001 0111 0110 0101 0011 0010 0001 0000 1000 0100 8-bit 8c 8-bit 8b 8-bit 8a 4-bit 4c 4-bit 4b 4-bit 4a 2-bit 2c 2-bit 2b 2-bit 2a 1-bit gpio Table 214. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) dout _doutm1 0000 dout _doutm2 00xx GP IO_RE G 0100 01xx dout dout _doutm4 c lk_out 1000 dout _doutm8 10xx reserved 11xx p_out_cfg OUT_MUX _CFGx p_oe_cfg p_oe_cfg dout_oem1 dout_oem2 dout_oem4 dout_oem8 GP IO _OE RE G Fig 35. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 215. SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15, addresses 0x4010 0040 to 0x4010 007C) bit description …continued Symbol Value Description Reset Access value CLK_SOURCE_PIN Select source clock pin. _MODE SGPIO8... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 216. SGPIO multiplexer slice Slice Din slice Clock Slice Din CONCAT_ENABLE CLK_SOURCE_ SLICE_MODE CONCAT_ORDER Pin 0 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin6 Pin 7 Pin 8... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 217. Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15, addresses 0x4010 1080 to 0x4010 10BC) bit description Symbol Value Description Reset Access value MATCH_MODE Match mode Do not match data. Match data. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 218. Slice data registers (REG0 to 15, addresses 0x4010 10C0 to 0x4010 10FC) bit description Symbol Description Reset Access value 31:0 At each active shift clock the register shifts right;... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.8 Position registers (POS0 to 15) Each position register contains the position counter for one slice: POS0 to POS15 contain the counter for slice A (register 0) to slice P (register 15). -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.12 Slice P mask register (MASK_P) Table 226. Slice P mask register (MASK_P, address 0x4010 120C) bit description Symbol Description Reset Access value 31:0 MASK_P Mask for pattern match function of slice P 0 = No effect. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.16 Slice count enable register (CTRL_ENABLED) Table 230. Slice count enable register (CTRL_ENABLED, address 0x4010 121C) bit description Symbol Description Reset Access value 15:0 CTRL_ENABLED Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.20 Shift clock interrupt enable register (ENABLE_0) This register indicates whether the shift clock interrupt of a slice is enabled. Table 234. Shift clock interrupt enable register (ENABLE_0, address 0x4010 1F08) bit... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 238. Exchange clock interrupt clear mask register (CLR_EN_1, address 0x4010 1F20) bit description Symbol Description Reset Access value 15:0 CLR_EN_CCI 1 = Exchange clock interrupt clear mask of slice n. 0 31:16 - Reserved. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.28 Exchange clock interrupt clear status register (CLR_STATUS_1) Table 242. Exchange clock interrupt clear status register (CLR_STATUS_1, address 0x4010 1F30) bit description Symbol Description Reset Access value 15:0 CLR_STATUS_CCI Exchange clock interrupt clear status of slice n. 0 31:16 - Reserved. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.33 Pattern match interrupt status register (STATUS_2) Table 247. Pattern match interrupt status register (STATUS_2, address 0x4010 1F4C) bit description Symbol Description Reset Access value 15:0 STATUS_PMI Match interrupt status of slice n. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.6.38 Input bit match interrupt enable (ENABLE_3) Table 252. Input interrupt enable register (ENABLE_3, address 0x4010 1F68) bit description Symbol Description Reset Access value 15:0 ENABLE3_INPI Input interrupt enable of slice n. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Interrupt logic int_shift din _pin dout int 0_event (i) int _capt int 1_event (i) din _slice int 2_event (i) int_ input S lice int 3_event (i) qualifier _ pin S lice... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) POS_PRESET qualifier PRESET external clock SGPIO_ 8b POS counter CLOCK 12b COUNTer dout shift_clk in multi-lane modes in multi- lane modes output multiple MSBs input multiple LSBs dout from other slices... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.7.1 Concatenation Slices can be concatenated to increase the buffer size beyond REG_SS. This feature also enables creating PWM streams by implementing reverse catenation. Concatenation is set by register SGPIO_MUX_CFG. The field CONCAT_ENABLE enables this feature. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) (12) (13) (10) (14) (11) (15) Examples: 4 input slices concatenated 2 output slices selfloop E = external data input mode 8 = 8 slices concatenated mode 4 = 4 slices concatenated mode... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Four slices (A, H, I and P) also support masking the pattern; MASK_x must be set for the pattern bits to be compared ('1' is compare). E.g. when looking for pattern 0x1234.xxxx.5678.9ABC, then REG should be set to 0x1234.xxxx.5678.9ABC and MASK... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) c lk _s lic e D c lk _s lic e H c lk _s lic e O c lk_s lic e P c lk _in c lk _pin 8 c lk _pin 9... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 256. Slice I/O multiplexing x = external; cl = clock; q = qualifier SGPIO Pin Input mode Parallel mode 8-bit 4-bit 2-bit 1-bit Clock 18.7.5 Internal connections SGPIO pins 10 and 12 can trigger the 12-bit ADC. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) 18.8.1 Multi-channel I2S 18.8.1.1 I2S slice selection A 5.1 channel I2S output interface in master mode requires 3 data outputs (SD[2:0]), 1 word select output (WS) and 1 clock output (SCK). In slave mode SCK becomes an input. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) word n-1 word n word n+1 right channel left channel right channel Fig 41. I2S configuration 18.8.1.2 I2S slice configuration Using FS = 192 kHz and 32-bit audio samples provides the following parameters: •... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 261. SGPIO setting for I2S 5.1, SLICE_MUX_CFG register SLICE_MUX_CF A,I,E (i=0,8,4) J (i=9) B (i=1) D (i=3) match_mode 0: no 0: no 0: no 0: no clk_gen_mode 0: use COUNTER... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 263. SGPIO setting for I2S 5.1 (master mode, pin 8) PRESETi counter not used counter not used counter not used counter not used COUNTi counter not used counter not used... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) MCK is not phase aligned to the other I2S signals. To toggle the output set REG3 = 0x5555.5555 and REG_SS3 = 0x5555.5555. In slave mode MCK should be divided by 4 to create SCK and the D and WS shift clock, this requires the pattern 11001100…... -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Table 266. SGPIO setting for camera interface (OUT_MUX_CFG registers) OUT_MUX_CFGi A...L Pin 8 M (i=12) G (i=6) P_out_cfg P_oe_cfg GPIO_OUTREG Data is shifted in at PIXCLK (pin 8) using HSYNC (pin 9) as qualifier. -
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UM10503 NXP Semiconductors Chapter 18: LPC43xx Serial GPIO (SGPIO) Data is captured at a falling PIXCLK when HSYNC is low. At a POS interrupt 32 data words are read from REG_SS and written to the data SRAM. Then SGPIO15 is toggled to request a GP-DMA transfer of 32 words from the data SRAM to the final destination. -
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UM10503 Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Rev. 1.3 — 6 July 2012 User manual 19.1 How to read this chapter The GPDMA is available on all LPC43xx parts. Remark: The VADC is not available on parts LPC4350/30/20/10. 19.2 Basic configuration The GPDMA is configured as follows: •... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 270. Peripheral connections to the DMA controller and matching flow control signals Peripheral SREQ BREQ Number muxing option (see Table SPIFI SPIFI SCT match 2 SGPIO14 Timer3 match 1... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 270. Peripheral connections to the DMA controller and matching flow control signals Peripheral SREQ BREQ Number muxing option (see Table SSP0 receive SSP0 receive I2S0 DMA request 1... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller SREQ[15:0] — Single transfer request signals. These cause a single data to be transferred. The DMA controller transfers a single transfer to or from the peripheral. LBREQ[15:0] — Last burst request signals. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 271. Register overview: GPDMA (base address 0x4000 2000) …continued Name Access Address Description Reset value Reference offset SRCADDR0 0x100 DMA Channel 0 Source Address Register 0x0000 0000 Table 286... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 271. Register overview: GPDMA (base address 0x4000 2000) …continued Name Access Address Description Reset value Reference offset CONFIG6 0x1D0 DMA Channel 6 Configuration Register 0x0000 0000 Table 290... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.6.3 DMA Interrupt Terminal Count Request Clear Register The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt requests. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register (IntTCStat) to be cleared. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 276. DMA Interrupt Error Clear Register (INTERRCLR, address 0x4000 2010) bit description Symbol Description Reset Access value INTERRCLR Writing a 1 clears the error interrupt request (IntErrStat) 0x00 for DMA channels. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.6.8 DMA Enabled Channel Register The ENBLDCHNS Register is read-only and indicates which DMA channels are enabled, as indicated by the Enable bit in the CCONFIG Register. A HIGH bit indicates that a DMA channel is enabled. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 281. DMA Software Single Request Register (SOFTSREQ, address 0x4000 2024) bit description Symbol Description Reset Access value 15:0 SOFTSREQ Software single transfer request flags for each of 16 0x00 possible sources. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 283. DMA Software Last Single Request Register (SOFTLSREQ, address 0x4000 202C) bit description Symbol Description Reset Access value 15:0 SOFTLSREQ Software last single transfer request flags for each of 0x00 16 possible sources. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 285. DMA Synchronization Register (SYNC, address 0x4000 2034) bit description Symbol Description Reset Access value 15:0 DMACSYNC Controls the synchronization logic for DMA request 0x00 signals. Each bit represents one set of DMA request... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.6.17 DMA Channel Destination Address registers The eight read/write DESTADDR Registers contain the current destination address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the channel is enabled. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 289. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description Symbol Value Description Reset Access value 11:0 TRANSFERSIZE Transfer size in number of transfers. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 289. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description …continued Symbol Value Description Reset Access value 20:18 SWIDTH Source transfer width. Transfers wider than the AHB master bus width are illegal. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 289. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7)) bit description …continued Symbol Value Description Reset Access value Terminal count interrupt enable bit. The terminal count interrupt is disabled. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 290. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value SRCPERIPHERAL Source peripheral. This value selects the DMA source request peripheral. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 290. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value 10:6 DESTPERIPHERAL Destination peripheral. This value selects the DMA destination request peripheral. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 290. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7)) bit description …continued Symbol Value Description Reset Access value Active: 0 = there is no data in the FIFO of the channel. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.7 Functional description 19.7.1 DMA controller functional description The DMA Controller enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit quantities. This means that when performing mixed-endian activity, where the endianness of the source and destination are different, byte swapping of the data within the 32-bit data bus is observed. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Table 292. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[31:0]... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.7.1.6.3 Error conditions An error during a DMA transfer is flagged directly by the peripheral by asserting an Error response on the AHB bus during the transfer. The DMA Controller automatically disables the DMA stream after the current transfer has completed, and can optionally generate an error interrupt to the CPU. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.8.1.4 Disabling a DMA channel A DMA channel can be disabled in three ways: • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 19.8.2 Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMA Controller where the packet length is programmed by software before the DMA channel is enabled. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 1. Program and enable the DMA channel. 2. Wait for a DMA request. 3. The DMA Controller starts transferring data when: – The DMA request goes active. – The DMA stream has the highest pending priority. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller – The DMA Controller responds with a DMA acknowledge to the destination peripheral. – The terminal count interrupt is generated (this interrupt can be masked). – If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI, and CCONTROL Registers and go to back to step 2. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 4. For a terminal count interrupt, write a 1 to the relevant bit of the INTTCCLR Register. For an error interrupt write a 1 to the relevant bit of the INTERRCLR Register to clear the interrupt request. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller 3. CLLI 4. CCONTROL Note: The CCONFIG DMA channel Configuration Register is not part of the linked list item. 19.8.5.1.1 Programming the DMA controller for scatter/gather DMA To program the DMA Controller for scatter/gather DMA: 1. -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller Linked List Array LLI 1 Source address 0x2000 A200 0x2000 0000 0x2000 A200 Destination address = peripheral 0x2000 0010 Next LLI address Control information = length 3072 3072 bytes of data... -
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UM10503 NXP Semiconductors Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller • Source and destination burst sizes, 16 transfers. • Next LLI address, 0x2000 0020. A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x2000 0000, is programmed into the DMA Controller. -
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UM10503 Chapter 20: LPC43xx SD/MMC interface Rev. 1.3 — 6 July 2012 User manual 20.1 How to read this chapter The SD/MMC card interface is available on all LPC43xx parts. 20.2 Basic configuration Table 294. SDIO clocking and power control Base clock Branch clock Operating frequency... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • Bus Interface Unit (BIU) - Provides AHB and DMA interfaces for register and data read/writes. • Card Interface Unit (CIU) - Handles the card protocols and provides clock management. • Internal MCI DMA controller: AHB bus mastering DMA controller... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 295. SDIO pin description Pin function Direction Description SD_VOLT[2:0] SD/MMC bus voltage select output 2:0. On the LPC43xx, these pins only function as GPIO pins. The SD/MMC controller voltage cannot be changed. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 296. Register overview: SDMMC (base address: 0x4000 4000) Name Access Address Description Reset value Reference offset RST_N 0x078 Hardware Reset Table 322 0x07C Reserved BMOD 0x080 Bus Mode Register 0x00000000 Table 323... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 297. Control Register (CTRL, address 0x4000 4000) bit description Symbol Value Description Reset value INT_ENABLE Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 297. Control Register (CTRL, address 0x4000 4000) bit description Symbol Value Description Reset value SEND_AUTO_STOP_ Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and CCSD send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.2 Power Enable Register (PWREN) Table 298. Power Enable Register (PWREN, address 0x4000 4004) bit description Symbol Description Reset value POWER_ENABLE Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.4 SD Clock Source Register (CLKSRC) Table 300. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description Symbol Description Reset value CLK_SOURCE Clock divider source for SD card. 00 - Clock divider 0... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.7 Card Type Register (CTYPE) Table 303. Card Type Register (CTYPE, address 0x4000 4018) bit description Symbol Description Reset value CARD_WIDTH0 Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 306. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description Symbol Description Reset value TXDR Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.12 Command Register (CMD) Table 308. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value CMD_INDEX Command index RESPONSE_EXPECT Response expect No response expected from card Response expected from card... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 308. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value STOP_ABORT_CMD Stop abort cmd. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 308. Command Register (CMD, address 0x4000 402C) bit description Symbol Value Description Reset value CCS_EXPECTED CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.14 Response Register 1 (RESP1) Table 310. Response Register 1 (RESP1, address 0x4000 4034) bit description Symbol Description Reset value 31:0 RESPONSE1 Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 313. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description Symbol Description Reset value DRTO Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 314. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description Symbol Description Reset value RCRC Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.19 Status Register (STATUS) Table 315. Status Register (STATUS, address 0x4000 4048) bit description Symbol Description Reset value FIFO_RX_ FIFO reached Receive watermark level; not qualified with data transfer. WATERMARK FIFO_TX_ FIFO reached Transmit watermark level; not qualified with data transfer. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.20 FIFO Threshold Watermark Register (FIFOTH) Table 316. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Symbol Value Description Reset value 11:0 TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 316. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description Symbol Value Description Reset value 30:28 DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.22 Write Protect Register (WRTPRT) Table 318. Write Protect Register (WRTPRT, address 0x4000 4054) bit description Symbol Description Reset value WRITE_PROTECT Write protect. 1 represents write protection. 31:1 Reserved 20.6.23 Transferred CIU Card Byte Count Register (TCBCNT) Table 319. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.27 Bus Mode Register (BMOD) Table 323. Bus Mode Register (BMOD, address 0x4000 4080) bit description Symbol Value Description Reset value Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.6.29 Descriptor List Base Address Register (DBADDR) Table 325. Descriptor List Base Address Register (DBADDR, address 0x4000 4088) bit description Symbol Description Reset value 31:0 Start of Descriptor List. Contains the base address of the First Descriptor. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 326. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description Symbol Description Reset value 12:10 EB Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 327. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit description Symbol Description Reset value Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface The card detection signal is debounced based on the number of blocks specified in the Debounce Count Register (DEBNCE). When this signal is connected to the card detect pin of the card slot, then CDETECT register's bit 0 state will be filtered by the number of debounce cycles specified in DEBNCE. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface The condition under which the transfer mode is set to block transfer and byte_count is equal to block size is treated as a single-block data transfer command for both MMC and SD cards. If byte_count = n... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Before issuing a new data transfer command, the software should ensure that the card is not busy due to any previous data transfer command. Before changing the card clock frequency, the software must ensure that there are no data or command transfers in progress. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface One data-transfer requirement between the FIFO and cpu is that the number of transfers should be a multiple of the FIFO data width (F_DATA_WIDTH), which is 32. So if you want to write only 15 bytes to an SD/MMC/CE-ATA card (BYTCNT), the cpu should write 16 bytes to the FIFO or program the DMA to do 16-byte transfers, if DMA mode is enabled. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • Enumerates all connected cards • Sets the RCA for the connected cards • Reads card-specific information • Stores card-specific information locally Enumerate_Card_Stack - Enumerates the card connected on the module. The card can be of the type MMC, CE-ATA, SD, or SDIO. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • CLKDIV @0x08 = 0x0 (bypass of clock divider). • CLKSRC @0x0C = 0x0 • CLKENA @0x10 =0x0 or 0x1. This register enables or disables clock for the card and enables low-power mode, which automatically stops the clock to a card when the card is idle for more than 8 clocks. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface – Check if response_timeout error, response_CRC error, or response error is set. This can be done either by responding to an interrupt raised by these errors or by polling bits 1, 6, and 8 from the RINTSTS register @0x44. If no response error is received, then the response is valid. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface For the data transfer commands, it is important that the same bus width that is programmed in the card should be set in the card type register @0x18. Therefore, in order to change the bus width, you should always use the following supplied APIs as appropriate for the type of card: •... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 5. Software should look for Receive_FIFO_Data_request and/or data starvation by cpu time-out conditions. In both cases, the software should read data from the FIFO and make space in the FIFO for receiving more data. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 3. Program CMDARG register @0x28 with the data address to which data should be written. 4. Write data in the FIFO; it is usually best to start filling data the full depth of the FIFO. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 333. CMD register settings for Single-block or Multiple-block write Name Value Comments User-selectable Wait_prvdata_complete Before sending command on command line, cpu should wait for completion of any data command in process, if any (recommended to... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • Send STOP command - Can be sent on the command line while a data transfer is in progress; this command can be sent at any time during a data transfer. For information on sending this command, refer to "No-Data Command With or Without... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface The following functions can be implemented by programming the appropriate bits in the CCCR register (Function 0) of the SDIO card. To read from or write to the CCCR register, use the CMD52 command. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface If the DF flag is 0, then in case of a read, the Module waits for data. After the data time-out period, it gives a data time-out error. Table 335. Parameters for CMDARG register... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.7.5.2.2 ATA Task File Transfer ATA task file registers are mapped to addresses 0x00h-0x10h in the MMC register space. RW_REG is used to issue the ATA command, and the ATA task file is transmitted in a single RW_REG MMC command sequence. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 337. CMD register settings Name Value Comment start_cmd Css_expect Command Completion Signal is not expected Read_ceata_device 1 – If RW_BLK or RW_REG read update_clock_ registers_only No clock parameters update command card_number Card number in use. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 1. Write the data size in bytes in the BYTCNT register @0x20. 2. Write the block size in bytes in the BLKSIZ register @0x1C. The Module expects a single/multiple block transfer. 3. Program the CMDARG register @0x28 to indicate the Data Unit Count. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • Program the block size (BLKSIZ) register as shown below. Table 342. BLKSIZ register Bits Value Comment 31:16 Reserved bits as zeroes (0) 15:0 512, 1024, 4096 MMC block size can be 512, 1024, or 4096 bytes as negotiated by CPU •... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • IDENTIFY DEVICE - Returns 512-byte data structure to the cpu that describes device-specific information and capabilities. The cpu issues the IDENTIFY DEVICE command only if the MMC block size is set to 512 bytes; any other MMC block size has indeterminate results. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface – Command field of the ATA task file set to E0h – Reserved fields of the task file cleared to 0 • BLKSIZ register bits [15:0] and BYTCNT register - Set to 16 –... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • Generic DMA mode - Simultaneously sets controller_reset, fifo_reset, and dma_reset; clears the RAWINTS register @0x44 by using another write in order to clear any resultant interrupt. If a "graceful" completion of the DMA is required, then it is recommended to poll the status register to see whether the dma request is 0 before resetting the DMA interface control and issuing an additional FIFO reset. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • CRC Error on Command - If a CRC error is detected for a command, the CE-ATA device does not send a response, and a response time-out is expected from the Module. The ATA layer is notified that an MMC transport layer error occurred. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Data Buffer Descriptor A Data Buffer Descriptor B Data Buffer Descriptor C Fig 47. Chain descriptor structure 20.7.6.1 SD/MMC DMA descriptors 20.7.6.1.1 SD/MMC DMA descriptor DESC0 The DES0 descriptor contains control and status information. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 344. SD/MMC DMA DESC0 descriptor Symbol Description 29:6 Reserved Card Error Summary These error bits indicate the status of the transaction to or from the card. These bits are also present in RINTSTS Indicates the logical OR of the following bits: •... -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface Table 347. SD/MMC DMA DESC3 descriptor Symbol Description 31:0 BAP2 Buffer Address Pointer 2/ Next Descriptor Address These bits indicate the physical address of the second buffer when the dual-buffer structure is used. If the Second Address Chained (DES0[4]) bit is set, then this address contains the pointer to the physical memory where the Next Descriptor is present. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 20.7.6.6 Transmission The SD/MMC transmission occurs as follows: 1. The Host sets up the Descriptor (DES0-DES3) for transmission and sets the OWN bit (DES0[31]). The Host also prepares the data buffer. 2. The Host programs the write data command in the CMD register in BIU. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface 7. The SD/MMC DMA engine will now wait for a DMA interface request (dw_dma_req) from BIU. This request will be generated based on the programmed receive threshold value. For the last bytes of data which can’t be accessed using a burst, SINGLE transfers are performed on AHB. -
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UM10503 NXP Semiconductors Chapter 20: LPC43xx SD/MMC interface • In case of a write abort, only the current descriptor during which an abort occurred is closed by the SD/MMC DMA . The remaining unread descriptors are not closed by the IDMAC. -
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UM10503 Chapter 21: LPC43xx External Memory Controller (EMC) Rev. 1.3 — 6 July 2012 User manual 21.1 How to read this chapter The EMC is available on all LPC43xx parts. The memory and address bus widths depend on package size (see Table 349). -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) • Program the SDRAM Delay value for the EMC_CLKn lines in the EMCDELAYCLK register in the SCU block. (See Section 15.4.9.). Add the SDRAM delay for most SDRAM devices running at frequencies above 96 MHz under typical conditions. Add the SDRAM delay at any frequency to compensate for variations over temperature. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) • Read and write buffers to reduce latency and to improve performance. • Separate reset domains allow the for auto-refresh through a chip reset if desired. • Programmable delay elements allow to fine-tune the EMC timing. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) SRAM interface EMC_A[23:0] EMC_WE CLK_M4_EMC/ AHB SLAVE CLK_M4_EMC_DIV MEMORY REGISTER EMC_OE INTERFACE CONTROLLER STATE MACHINE EMC_D[31:0] (write) CLK_M4_EMC/ AHB SLAVE CLK_M4_EMC_DIV EMC_CS[4:0] MEMORY INTERFACE DATAIN EMC_D[31:0] (read) FIFO Fig 49. EMC block diagram (SRAM) 21.5 Memory bank select... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) 21.6 Pin description Table 352. EMC pin description Pin function Direction Description EMC_A[22:0] Address bus EMC_D[31:0] Data bus EMC_BLS[3:0] Byte lane select EMC_CS[3:0] Static RAM memory bank select EMC_OE Output enable... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 353. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot DYNAMICRAS 0x034 Selects the active to precharge Table 361 command period. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 353. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot DYNAMICRASCAS3 0x164 Selects the RAS and CAS latencies for... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 353. Register overview: External memory controller (base address 0x4000 5000) …continued Name Access Address Description Reset Reset Reference offset value value after boot STATICWAITOEN2 0x248 Selects the delay from chip select 2 or... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 354. EMC Control register (CONTROL - address 0x4000 5000) bit description Symbol Value Description Reset value EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 355. EMC Status register (STATUS - address 0x4000 5004) bit description Symbol Value Description Reset value Self-refresh acknowledge. This bit indicates the operating mode of the EMC: Normal mode Self-refresh mode (POR reset value). -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 357. Dynamic Control register (DYNAMICCONTROL - address 0x4000 5020) bit description Symbol Value Description Reset value Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 358. Dynamic Memory Refresh Timer register (DYNAMICREFRESH - address 0x4000 5024) bit description Symbol Description Reset value 10:0 REFRESH Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 359. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG - address 0x4000 5028) bit description Symbol Value Description Reset value Read data strategy. Do not use. POR reset value. Command delayed by 1/2CCLK. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) 21.7.9 Dynamic Memory Self Refresh Exit Time register The DYNAMICTSREX register enables you to program the self-refresh exit time, tSREX. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 364. Dynamic Memory Data In to Active Command Time register (DYNAMICDAL - address 0x4000 5040) bit description Symbol Description Reset value TDAL Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) 21.7.14 Dynamic Memory Auto-refresh Period register The DYNAMICTRFC register enables you to program the auto-refresh period, and auto-refresh to active command period, tRFC. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. Table 369. Dynamic Memory Active Bank A to Active Bank B Time register (DYNAMICRRD -... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency of 50 MHz, the following value must be programmed into this register: (16 x 10... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Address mappings that are not shown in Table 373 are reserved. Table 373. Address mapping 11:9 8:7 Description 16 bit external bus high-performance address mapping (Row, Bank, Column) 16 Mb (2Mx8), 2 banks, row length = 11, column length = 9... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 373. Address mapping 11:9 8:7 Description 64 Mb (8Mx8), 4 banks, row length = 12, column length = 9 64 Mb (4Mx16), 4 banks, row length = 12, column length = 8... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 374. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS[0:3], address 0x4000 5104 (DYNAMICRASCAS0), 0x4000 5124 (DYNAMICRASCAS1), 0x4000 5144 (DYNAMICRASCAS2), 0x4000 5164 (DYNAMICRASCAS3)) bit description Symbol Value Description Reset value RAS latency (active to read/write delay). -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 375. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200 (STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240 (STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description Symbol Value Description Reset value Page mode. In page mode the EMC can burst up to four external accesses. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 375. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200 (STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240 (STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit description Symbol Value Description Reset value Write protect. Writes not protected (POR reset value). -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 377. Static Memory Output Enable delay registers (STATICWAITOEN[0:3], address 0x4000 5208 (STATICWAITOEN0), 0x4000 5228 (STATICWAITOEN1), 0x4000 5248 (STATICWAITOEN2), 0x4000 5268 (STATICWAITOEN3)) bit description Symbol Description Reset value WAITOEN Wait output enable. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 379. Static Memory Page Mode Read Delay registers (STATICWAITPAGE[0:3], address 0x4000 5210 (STATICWAITPAGE0), 0x4000 5230 (STATICWAITPAGE1), 0x4000 5250 (STATICWAITPAGE2), 0x4000 5270 (STATICWAITPAGE3)) bit description Symbol Description Reset value WAITPAGE Asynchronous page mode read after the first read wait states. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 381. Static Memory Turn Round Delay registers (STATICWAITTURN[0:3], address 0x4000 5218 (STATICWAITTURN0), 0x4000 5238 (STATICWAITTURN1), 0x4000 5258 (STATICWAITTURN2), 0x4000 5278 (STATICWAITTURN3)) bit description Symbol Description Reset value WAITTURN Bus turnaround cycles. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) 21.8 Functional description Figure 48 shows a block diagram of the EMC. The functions of the EMC blocks are described in the following sections: • AHB slave register interface. •... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) The EMC dynamic memory interface requires that all EMC_CLK signals are selected on the CLKn pins for 16-bit memory and for 32-bit memory. For static memory larger delays are defined by in steps of one EMC clock cycle by the STATICWAIT registers (see Section 21.7.22... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) • Buffer read requests from memory. Future read requests that hit the buffer read the data from the buffer rather than memory, reducing transaction latency. Convert all read transactions into quadword bursts on the external memory interface. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) Table 382. SDRAM mode register description Address line SDRAM mode Value Description register bit A2:A0 Burst length 1 (M3 = 0) 1 (M3 =1) 2 (M3 = 0) 2 (M3 =1) -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) The read address is calculated as follows: • Determine the mode register content MODE: – For a single 16-bit external SDRAM chip set the burst length to 8. For a single 32-bit SDRAM chip set the burst length to 4. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) 21.8.6 External static memory interface External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding StaticConfig register). If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines. -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) BLS[3] BLS[2] BLS[1] BLS[0] IO[31:0] D[31:0] A[a_m:0] A[a_b:2] c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 50. 32 bit bank external memory interfaces ( bits MW = 10) 21.8.6.2 16-bit wide memory bank connection... -
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UM10503 NXP Semiconductors Chapter 21: LPC43xx External Memory Controller (EMC) 21.8.6.3 8-bit wide memory bank connection IO[7:0] D[7:0] A[a_m:0] A[a_b:0] Fig 52. 8 bit bank external memory interface (bits MW = 00) UM10503 All information provided in this document is subject to legal disclaimers. -
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UM10503 Chapter 22: LPC43xx SPI Flash Interface (SPIFI) Rev. 1.3 — 6 July 2012 User manual 22.1 How to read this chapter The SPIFI is available on all LPC43xx parts. 22.2 Basic configuration The SPIFI is configured as follows: • Table 383 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 22: LPC43xx SPI Flash Interface (SPIFI) Serial flash devices respond to commands sent by software or automatically sent by the SPIFI when software reads either of the two read-only serial flash regions in the memory map (see Table 384). -
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UM10503 NXP Semiconductors Chapter 22: LPC43xx SPI Flash Interface (SPIFI) Table 386. Supported QSPI devices Manufacturer Device name AMIC A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032 Atmel AT25F512B, AT25DF021, AT25DF041A, AT25DF081A, AT25DF161, AT25DQ161, AT25DF321A, AT25DF641 Chingis Pm25LD256, Pm25LD512, Pm25LD010, Pm25LD020, Pm25LD040,... -
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UM10503 Chapter 23: LPC43xx USB0 Host/Device/OTG controller Rev. 1.3 — 6 July 2012 User manual 23.1 How to read this chapter The USB0 Host/Device/OTG controller is available on parts LPC435x, LPC433x, and LPC432x. USB frame length adjustment is available for parts with on-chip flash only. 23.2 Basic configuration The USB0 Host/Device/OTG controller is configured as follows: •... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller • Supports software HNP and SRP for OTG peripherals. • Supports power management • Supports six logical endpoints including one control endpoint for a total of 12 physical endpoints. • This module has its own, integrated DMA engine. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.4.3 USB acronyms and abbreviations Table 388. USB related acronyms Acronym Description Analog Transceiver Device Controller Driver device Endpoint Queue Head device Transfer Descriptor End Of Packet End Point Full Speed... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 389. Fixed endpoint configuration Logical Physical Endpoint type Direction endpoint endpoint Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Interrupt/Bulk/Isochronous Table 390. USB Packet size Endpoint type Speed Packet size (byte) Control Low-speed Full-speed... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 391. USB0 pin description Pin function Direction Description USB0_VBUS VBUS pin (power on USB cable). This pin includes an internal pull-down resistor of 64 kOhm (typical) ± 16 kOhm. For maximum load C = 6.5 uF and maximum... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 393. Register overview: USB0 OTG controller (register base address 0x4000 6000) …continued Name Access Address Description Reset Reset value Reference offset value after USB0 boot HCCPARAMS 0x108 Host controller capability parameters 0x0000... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 393. Register overview: USB0 OTG controller (register base address 0x4000 6000) …continued Name Access Address Description Reset Reset value Reference offset value after USB0 boot 0x188 - 0x1A0 OTGSC 0x1A4... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller The following registers and register bits are used for OTG operations. The values of these register bits are independent of the controller mode and are not affected by a write to the RESET bit in the USBCMD register. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 395. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) …continued Symbol Description Reset Access value 23:20 N_PTT Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 398. DCCPARAMS (address 0x4000 6124) Symbol Description Reset value Access Device Endpoint Number. These bits are reserved and should be set to zero. Device Capable. Host Capable. 31:9 These bits are reserved and should be set to zero. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 399. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description …continued Symbol Value Description Access Reset value SUTW Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 400. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Symbol Value Description Access Reset value Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the host/device controller when the reset process is complete. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 400. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode Symbol Value Description Access Reset value Reserved. ASPE Asynchronous Schedule Park Mode Enable Park mode is disabled. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.4.1 Device mode Table 402. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB interrupt R/WC This bit is cleared by software writing a one to it. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 402. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description Symbol Value Description Reset Access value SOF received R/WC This bit is cleared by software writing a one to it. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.4.2 Host mode Table 403. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description Symbol Value Description Reset Access value USB interrupt (USBINT) R/WC This bit is cleared by software writing a one to it. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 403. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued Symbol Value Description Reset Access value HCHalted The RS bit in USBCMD is set to zero. Set by the host controller. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.5 USB Interrupt register (USBINTR) The software interrupts are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.5.2 Host mode Table 405. USB Interrupt register in host mode (USBINTR_H - address 0x4000 6148) bit description Symbol Description Access Reset value USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.6 Frame index register (FRINDEX) 23.6.6.1 Device mode In Device mode this register is read only, and the device controller updates the FRINDEX[13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX[13:3] will be checked against the SOF marker. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 408. Number of bits used for the frame list index USBCMD USBCMD USBCMD Frame list size bit 15 bit 3 bit 2 32 elements (128 bytes) 16 elements (64 bytes) 8 elements (32 bytes) 23.6.7 Device address (DEVICEADDR - device) and Periodic List Base... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller physical memory pointer is assumed to be 4 kB aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.9.2 Host mode This register contains parameters needed for internal TT operations. This register is used by the host controller only. Writes must be in Dwords. Table 413. USB TT Control register in host mode (TTCTRL - address 0x4000 615C) bit description... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure T remains before the end of the (micro) frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the [micro]frame is <... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 416. USB BINTERVAL register (BINTERVAL - address 0x4000 6174) bit description Symbol Description Reset Access value BINT bInterval value (see Section 23.7.7) 0x00 31:4 Reserved 23.6.13 USB Endpoint NAK register (ENDPTNAK) 23.6.13.1 Device mode... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 418. USB Endpoint NAK Enable register (ENDPTNAKEN - address 0x4000 617C) bit description Symbol Description Reset Access value EPRNE Rx endpoint NAK enable 0x00 Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 419. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Symbol Value Description Reset Access value Reserved Force port resume After the device has been in Suspended state for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 419. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description Symbol Value Description Reset Access value 19:16 PTC3_0 Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.6.15.2 Host mode The host controller uses one port. The register is only reset when power is initially applied or in response to a controller reset. The initial conditions of the port are: •... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 420. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value Port disable/enable change R/WC For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 420. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, Table 421. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 420. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 420. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description Symbol Value Description Reset Access value WKOC Wake on over-current enable (WKOC_E) Disables the port to wake up on over-current events. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller The status inputs are debounced using a 1 msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the status input register or cause an OTG interrupt. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 422. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Symbol Value Description Reset Access value IDIS USB ID interrupt status R/WC This bit is set when a change on the ID input has been detected. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 422. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued Symbol Value Description Reset Access value MS1E 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 423. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 424. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 426. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 61B0) bit description Symbol Description Reset Access value PERB Prime endpoint receive buffer for physical OUT endpoints 5 to 0. R/WS... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 427. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description Symbol Description Reset Access value 15:6 Reserved 21:16 FETB Flush endpoint transmit buffer for physical IN endpoints 5 to 0. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Writing a one will clear the corresponding bit in this register. Table 429. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 61BC) bit description Symbol Description Reset Access value ERCE Endpoint receive complete event for physical OUT endpoints 5 to 0. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 430. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description …continued Symbol Value Description Reset Access value Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 431. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Symbol Value Description Reset Access value Reserved Endpoint type... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 431. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to 0x4000 61D4 (ENDPTCTRL5)) bit description …continued Symbol Value Description Reset Access value Tx data toggle inhibit This bit is only used for test and should always be written as zero. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.7.5 ATX transceiver The USB-OTG has a USB transceiver with UTMI+ interface. It contains the required transceiver OTG functionality; this includes: • VBUS sensing for producing the session-valid and VBUS-valid signals. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller consumption rate, then software can reduce the SOF length using the USB0FLADJ register. The USB bit clock is still running at the normal rate so no bus errors occur. The host only changes when it introduces the next SOF token - earlier or later on a bit-time resolution boundary. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller The hardware assist consists of the following steps: 1. Hardware resets the OTG controller (writes 1 to the RST bit in USBCMD). 2. Hardware selects the device mode (writes 10 to bits CM[1:0] in USBMODE). -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller block in the system, the transaction translator function normally associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The embedded transaction translator function is an extension to EHCI interface but makes use of the standard data structures and operational models that exist in the EHCI specification to support full and low speed devices. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.8.1.4 Data structures The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root Hub with an embedded Transaction Translator. Here it is... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.8.1.6 Split state machines The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simply an internal operation to the embedded Transaction Translator. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller There is no data schedule mechanism for these transactions other than micro-frame pipeline. The embedded TT assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior may result. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller • Software writes a ‘1’ to the port reset bit in the PORTSC1 register to reset the device. • Software writes a ‘0’ to the port reset bit in the PORTSC1 register after 10 ms. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Endpoint Transfer Endpoint Queue Heads Descriptors dTD Endpoint dQH5 - IN Endpoint dQH5 - OUT TRANSFER transfer buffer BUFFER pointer TRANSFER BUFFER transfer buffer Endpoint dQH1 - OUT pointer TRANSFER Control Endpoint dQH0 - IN... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller device Queue Head (dQH) transfer overlay offset ENDPOINT CAPABILITIES/CHARACTERISTICS 0x00 0x04 CURRENT dTD POINTER endpoint transfer descriptor (dTD) 0x08 NEXT dTD POINTER NEXT dTD POINTER 0x0C Total_bytes MulO STATUS Total_bytes MulO... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 434. Endpoint capabilities and characteristics Access Bit Name Description 31:30 MULT Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller After an endpoint is readied, the dTD will be copied into this queue head overlay area by the device controller. Until a transfer is expired, software must not write the queue head overlay area or the associated transfer descriptor. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 438. dTD token Access Name Description reserved 30:16 Total_bytes Total bytes This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 438. dTD token …continued Access Name Description 11:10 MultO Multiplier Override (see Section 23.9.2.1 for an example) This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller In this case three packets are sent: Data2 (8 bytes), Data1 (7 bytes), Data0 (0 bytes). Example 2 MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 2 In this case two packets are sent: Data1 (8 bytes), Data0 (7 bytes). -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup packet. The contents of the first setup packet will require a response in accordance with USB device framework command set (see USB Specification Rev. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller The states powered, attach, default FS/HS, suspend FS/HS are implemented in the device controller and are communicated to the DCD using the following status bits: • DCSuspend - see Table 402. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller • After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSC1 to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and DCD can begin enumeration according to the USB2.0 specification Chapter 9 - Device... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Remark: Before resume signaling can be used, the host must enable it by using the Set Feature command defined in USB Device Framework (chapter 9) of the USB 2.0 Specification. 23.10.5 Managing endpoints The USB 2.0 specification defines an endpoint, also called a device endpoint or an... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 440. Device controller endpoint initialization Field Value 10 - bulk 11 - interrupt Endpoint Stall 23.10.5.2 Stalling There are two occasions where the device controller may need to return to the host a STALL: 1. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.10.5.3.1 Data toggle reset The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a ‘1’ to the data toggle reset bit in the ENDPTCTRLx register. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller fetch the operating context needed to handle a request from the host without the need to follow the linked list, starting at the dQH when the host request is received. After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Table 443. Variable length transfer protocol example (ZLT = 1) Bytes (dTD) Max Packet Length (dQH) Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller length protocol then ACK. SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 23.10.8 Control endpoint operational model 23.10.8.1 Setup phase All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Remark: Leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware behavior. • After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet was received on a particular pipe: a. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.10.8.3 Status phase Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT as described above in the data phase. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for device mode does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller # Packets Occurred > 0 AND # Packets Occurred < MULT. • CRC Error [Transaction Error bit is set] Remark: For ISO, when a dTD is retired, the next dTD is primed for the next frame. For continuous (micro) frame to (micro) frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro) frames. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.10.10 Managing queue heads Endpoint Transfer Endpoint Queue Heads Descriptors dTD transfer buffer TRANSFER pointer BUFFER Endpoint dQH0 - Out transfer buffer pointer TRANSFER Endpoint dQH0 - In BUFFER Endpoint dQH1 - Out... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller • Write the Active bit in the status field to “0”. • Write the Halt bit in the status field to “0”. Remark: The DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD’s. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Head Pointer Tail Pointer current Endpoint next completed dTDs queued dTDs Fig 59. Software link pointers 23.10.11.2 Building a transfer descriptor Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME. Linked list is not empty 1. Add dTD to end of the linked list. 2. Read correct prime bit in ENDPTPRIME – if ‘1’ DONE. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.10.11.5 Flushing an endpoint It is necessary for the DCD to flush one or more endpoints on a USB device reset or during a broken control transfer. There may also be application specific requirements to stop transfers in progress. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.10.12 Servicing interrupts The interrupt service routine must consider different types of interrupts for high-frequency and low-frequency, and error operations and specify the priorities accordingly. 23.10.12.1 High-frequency interrupts High frequency interrupts in particular should be handled in the order below. The most important of these is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 23.11 USB power optimization The USB-HS core is a fully synchronous static design. Applications that transfer more data or use a greater number of packets to be sent will consume a greater amount of power. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller Host directed Autonomous operational 3 ms Low-power idle request resume interrupt received prepare disconnect Suspend SW sets SW sets user-defined Suspend bit Suspend bit wakeup disconnect Suspend Suspend Lock power states... -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller 2. If the host puts resume signaling on the bus, it will clear the Suspend bit and generate a port change interrupt when the resume is finished. Remark: The Suspend interrupt is generated by the USB block whenever it detects that the bus is idle for more than 3 ms. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller external event could clear the suspend bit and start the transceiver clock running again. The software can then initiate a resume by setting the resume bit in the port controller, or force a reconnect by setting the reset bit in the port controller. -
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UM10503 NXP Semiconductors Chapter 23: LPC43xx USB0 Host/Device/OTG controller • a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed). • a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed). The vbusvalid and bvalid signals coming from the transceiver are not filtered in the SUSP_CTRL module. -
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UM10503 Chapter 24: LPC43xx USB1 Host/Device controller Rev. 1.3 — 6 July 2012 User manual 24.1 How to read this chapter The USB1 Host/Device controller is available on parts LPC435x and LPC433x. USB frame length adjustment is available for parts with on-chip flash only. 24.2 Basic configuration The USB1 controller is configured as follows: •... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller • Supports all full-speed USB-compliant peripherals. • Complies with Universal Serial Bus specification 2.0. • Complies with Enhanced Host Controller Interface Specification. • Supports auto USB 2.0 mode discovery. • Supports three logical endpoints plus one control endpoint for a total of 8 physical endpoints. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller LPC43xx SYSTEM ARM Cortex-M4 MEMORY master slave USB1_VBUS TX-BUFFER INTERNAL (DUAL-PORT RAM) USB1_DP FULL-SPEED USB 2.0 USB1_DM Mobile/ RX-BUFFER GROUND (DUAL-PORT RAM) Fig 63. USB1 block diagram with internal full-speed PHY 24.5 Pin description... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 452. USB1 pin description Pin function Direction Description ULPI_STP ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. ULPI_NXT ULPI link NXT signal. Data flow control signal from the PHY. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 454. Register overview: USB1 host/device controller (register base address 0x4000 7000) …continued Name Access Address Description Reset value Reference offset USBINTR_H 0x148 USB interrupt enable (host mode) 0x0000 0000 Table 466... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.1 Device/host capability registers Table 455. CAPLENGTH register (CAPLENGTH - address 0x4000 7100) bit description Symbol Description Reset value Access CAPLENGTH Indicates offset to add to the register base 0x40 address at the beginning of the Operational... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 457. HCCPARAMS register (HCCPARAMS - address 0x4000 7108) bit description Symbol Description Reset value Access 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. Programmable Frame List Flag. If set to one, then... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.2.1 Device mode Table 460. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description Symbol Value Description Reset Access value Run/Stop Writing a 0 to this bit will cause a detach event. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 460. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value Not used in device mode. 23:16 Interrupt threshold control. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 461. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value This bit controls whether the host controller skips processing the periodic schedule. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 461. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued Symbol Value Description Reset Access value Bit 2 of the Frame List Size bits. See Table 462. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.3.1 Device mode Table 463. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB interrupt R/WC This bit is cleared by software writing a one to it. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 463. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description Symbol Value Description Reset Access value SOF received R/WC This bit is cleared by software writing a one to it. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.3.2 Host mode Table 464. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description Symbol Value Description Reset Access value USB interrupt (USBINT) R/WC This bit is cleared by software writing a one to it. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 464. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued Symbol Value Description Reset Access value HCHalted The RS bit in USBCMD is set to zero. Set by the host controller. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.4 USB Interrupt register (USBINTR) The software interrupts are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.4.2 Host mode Table 466. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description Symbol Description Access Reset value USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.5 Frame index register (FRINDEX) 24.6.5.1 Device mode In Device mode this register is read only, and the device controller updates the FRINDEX[13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX[13:3] will be checked against the SOF marker. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 469. Number of bits used for the frame list index USBCMD USBCMD USBCMD Frame list size Size of bit 15 bit 3 bit 2 FRINDEX12_3 bit field 32 elements (128 bytes) -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller physical memory pointer is assumed to be 4 kB aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.8.2 Host mode This register contains parameters needed for internal TT operations. This register is used by the host controller only. Writes must be in Dwords. Table 474. USB TT Control register in host mode (TTCTRL - address 0x4000 715C) bit description... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure T remains before the end of the (micro) frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the [micro]frame is <... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Remark: Writes to the ULPI through the viewport can substantially harm standard USB operations. Currently no usage model has been defined where software should need to execute writes directly to the ULPI – see exception regarding optional features below. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 477. USB ULPI viewport register (ULPIVIEWPORT - address 0x4000 7170) bit description …continued Symbol Value Description Access Reset value ULPIRW ULPI Read/Write control. This bit selects between running a read or write operation. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 479. USB endpoint NAK register in device mode (ENDPTNAK - address 0x4000 7178) bit description Symbol Description Reset Access value EPRN Rx endpoint NAK 0x00 R/WC Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 480. USB Endpoint NAK Enable register in device mode (ENDPTNAKEN - address 0x4000 717C) bit description Symbol Description Reset Access value EPRNE Rx endpoint NAK enable 0x00 Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 481. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value Port enable/disable change This bit is always 0. The device port is always enabled. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 481. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description Symbol Value Description Reset Access value 19:16 PTC3_0 Port test control 0000 Any value other than 0000 indicates that the port is operating in test mode. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller 24.6.15.2 Host mode The host controller uses one port. The register is only reset when power is initially applied or in response to a controller reset. The initial conditions of the port are: •... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 482. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value Port disable/enable change R/WC For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 482. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, Table 483 “Port states as described by the PE and SUSP bits in the... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 482. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 482. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description …continued Symbol Value Description Reset Access value WKDC Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 483. Port states as described by the PE and SUSP bits in the PORTSC1 register PE bit SUSP bit Port state 0 or 1 disabled enabled suspend 24.6.16 USB Mode register (USBMODE) The USBMODE register sets the USB mode for the USB controller. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 484. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 485. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description …continued Symbol Value Description Reset Access value SDIS Stream disable mode Remark: The use of this feature substantially limits the overall USB performance that can be achieved. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 487. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 71B0) bit description Symbol Description Reset Access value PERB Prime endpoint receive buffer for physical OUT endpoints. R/WS For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 488. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description Symbol Description Reset Access value 15:4 Reserved 19:16 FETB Flush endpoint transmit buffer for physical IN endpoints. R/WC Writing a one to a bit(s) will clear any primed buffers. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Writing a one will clear the corresponding bit in this register. Table 490. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 71BC) bit description Symbol Description Reset Access value ERCE Endpoint receive complete event for physical OUT endpoints. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 491. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description …continued Symbol Value Description Reset Access value Tx endpoint stall Endpoint ok. Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 492. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Symbol Value Description Reset Access value Reserved Endpoint type... -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller Table 492. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to 0x4000 71CC (ENDPTCTRL3)) bit description …continued Symbol Value Description Reset Access value Tx data toggle inhibit This bit is only used for test and should always be written as zero. -
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UM10503 NXP Semiconductors Chapter 24: LPC43xx USB1 Host/Device controller raw pin status register hence LOW level detection should be configured for this pin to detect when to turn the PLL off. Simillarly, to detect resume signaling to leave low power state, software should configure this pin to detect a HIGH level in the event router. -
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UM10503 Chapter 25: LPC43xx USB API Rev. 1.3 — 6 July 2012 User manual 25.1 How to read this chapter THe USB ROM API is available on parts LPC4350/30/20. 25.2 Introduction The boot ROM contains a USB driver to simplify the USB application development. The USB driver implements the Communication Device Class (CDC), the Human Interface Device (HID), and the Mass Storage Device (MSC) device class. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API – USB descriptors data structure (Table 509 “_USB_CORE_DESCS_T class structure”) – USB device stack initialization parameter data structure (Table 518 “USBD_API_INIT_PARAM class structure”). – USB device stack core API functions structure (Table 521 “USBD_CORE_API class structure”). -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API const USBD_DFU_API_T* dfu; const USBD_HID_API_T* hid; const USBD_CDC_API_T* cdc; const uint32_t* reserved6; const uint32_t version; } USBD_API_T; Ptr to USB ROM Driver table Device 1 0x1040 011C Ptr to Function 0 Ptr to Function 1 Ptr to Function 2 …... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 494. _BM_T class structure Member Description Recipient uint8_tuint8_t _BM_T::Recipient Recipient type. Type uint8_tuint8_t _BM_T::Type Request type. uint8_tuint8_t _BM_T::Dir Direction type. 25.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR Table 495. _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR class structure Member Description bFunctionLength uint8_tuint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bFunctionLength... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 498. _CDC_LINE_CODING class structure Member Description dwDTERate uint32_tuint32_t _CDC_LINE_CODING::dwDTERate bCharFormat uint8_tuint8_t _CDC_LINE_CODING::bCharFormat bParityType uint8_tuint8_t _CDC_LINE_CODING::bParityType bDataBits uint8_tuint8_t _CDC_LINE_CODING::bDataBits 25.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR Table 499. _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR::sUnion bSlaveInterfaces uint8_tuint8_t _CDC_UNION_1SLAVE_DESCRIPTOR::bSlaveInterfaces[1][1] 25.5.8 _CDC_UNION_DESCRIPTOR... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 502. _HID_DESCRIPTOR class structure Member Description bLength uint8_tuint8_t _HID_DESCRIPTOR::bLength Size of the descriptor, in bytes. bDescriptorType uint8_tuint8_t _HID_DESCRIPTOR::bDescriptorType Type of HID descriptor. bcdHID uint16_tuint16_t _HID_DESCRIPTOR::bcdHID BCD encoded version that the HID descriptor and device complies to. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 505. _MSC_CBW class structure Member Description dSignature uint32_tuint32_t _MSC_CBW::dSignature dTag uint32_tuint32_t _MSC_CBW::dTag dDataLength uint32_tuint32_t _MSC_CBW::dDataLength bmFlags uint8_tuint8_t _MSC_CBW::bmFlags bLUN uint8_tuint8_t _MSC_CBW::bLUN bCBLength uint8_tuint8_t _MSC_CBW::bCBLength uint8_tuint8_t _MSC_CBW::CB[16][16] 25.5.14 _MSC_CSW Table 506. _MSC_CSW class structure... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 509. _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t *uint8_t* _USB_CORE_DESCS_T::device_desc Pointer to USB device descriptor string_desc uint8_t *uint8_t* _USB_CORE_DESCS_T::string_desc Pointer to array of USB string descriptors full_speed_desc uint8_t *uint8_t* _USB_CORE_DESCS_T::full_speed_desc Pointer to USB device configuration descriptor when device is operating in full speed mode. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 511. _USB_DFU_FUNC_DESCRIPTOR class structure Member Description bLength uint8_tuint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength bDescriptorType uint8_tuint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType bmAttributes uint8_tuint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes wDetachTimeOut uint16_tuint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut wTransferSize uint16_tuint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize bcdDFUVersion uint16_tuint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion 25.5.20 _USB_INTERFACE_DESCRIPTOR Table 512. _USB_INTERFACE_DESCRIPTOR class structure... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 513. _USB_OTHER_SPEED_CONFIGURATION class structure Member Description bLength uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength Size of descriptor bDescriptorType uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType Other_speed_Configuration Type wTotalLength uint16_tuint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength Total length of data returned bNumInterfaces uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces Number of interfaces supported by this speed configuration... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 515. _USB_STRING_DESCRIPTOR class structure Member Description bLength uint8_tuint8_t _USB_STRING_DESCRIPTOR::bLength Size of this descriptor in bytes bDescriptorType uint8_tuint8_t _USB_STRING_DESCRIPTOR::bDescriptorType STRING Descriptor Type bString uint16_tuint16_t _USB_STRING_DESCRIPTOR::bString UNICODE encoded string 25.5.24 _WB_T Table 516. _WB_T class structure... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 517. USBD_API class structure Member Description const USBD_CDC_API_T *const USBD_CDC_API_T* USBD_API::cdc Pointer to function table which exposes functions provided by CDC-ACM function driver module. reserved6 const uint32_t *const uint32_t* USBD_API::reserved6 Reserved for future function driver module. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 518. USBD_API_INIT_PARAM class structure Member Description USB_Resume_Event USB_CB_TUSB_CB_T USBD_API_INIT_PARAM::USB_Resume_Event Event for USB wake up or resume. This event fires when a the USB device interface is suspended and the host wakes up the device by supplying Start Of Frame pulses. This is generally hooked to pull the user application out of a low power state and back into normal operating mode. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 518. USBD_API_INIT_PARAM class structure Member Description USB_Configure_Event USB_CB_TUSB_CB_T USBD_API_INIT_PARAM::USB_Configure_Event Event for USB configuration number changed. This event fires when a the USB host changes the selected configuration number. On receiving configuration change request from host, the stack enables/configures the endpoints needed by the new configuration before calling this callback function. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 519. USBD_CDC_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param, USBD_HANDLE_T *phCDC) Function to initialize CDC function driver module. This function is called by application layer to initialize CDC function driver module. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description mem_base uint32_tuint32_t USBD_CDC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length))(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) Communication Interface Class specific set request call-back function. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description CDC_BulkIN_Hdlr ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkIN_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Communication Device Class specific BULK IN endpoint handler. The application software should provide the BULK IN endpoint handler. Applications should transfer data depending on the communication protocol type set in descriptors. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description SendEncpsCmd ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::SendEncpsCmd)(USBD_HANDLE_T hCDC, uint8_t *buffer, uint16_t len))(USBD_HANDLE_T hCDC, uint8_t *buffer, uint16_t len) Abstract control model(ACM) subclass specific SEND_ENCAPSULATED_COMMAND request call-back function. This function is provided by the application software. This function gets called when host sends a SEND_ENCAPSULATED_COMMAND set request. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description SetCommFeature ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t *buffer, uint16_t len))(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t *buffer, uint16_t len) Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back function. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description ClrCommFeature ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature))(USBD_HANDLE_T hCDC, uint16_t feature) Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a CLEAR_COMM_FEATURE request. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description SetCtrlLineState ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state))(USBD_HANDLE_T hCDC, uint16_t state) Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function. This function is provided by the application software. This function gets called when host sends a SET_CONTROL_LINE_STATE request. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding))(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding) Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. This function is provided by the application software. This function gets called when host sends a SET_LINE_CODING request. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 520. USBD_CDC_INIT_PARAM class structure Member Description CDC_Ep0_Hdlr ErrorCode_t(*ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user override-able function to replace the default CDC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 521. USBD_CORE_API class structure Member Description RegisterEpHandler ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void *data) Function to register interrupt/event handler for the requested endpoint with USB device stack. The application layer uses this function to register the custom class's EP0 handler. The stack calls all the registered class handlers on any EP0 event before going through default handling of the event. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 521. USBD_CORE_API class structure Member Description DataOutStage void(*void USBD_CORE_API::DataOutStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in data_out state. This function is called by USB stack and the application layer to set the EP0 state machine in data_out state. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 521. USBD_CORE_API class structure Member Description StallEp0 void(*void USBD_CORE_API::StallEp0)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in stall state. This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 522. USBD_DFU_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_DFU_API::GetMemSize)(USBD_DFU_INIT_PARAM_T *param) Function to determine the memory required by the DFU function driver module. This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used by DFU function driver module. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 523. USBD_DFU_INIT_PARAM class structure Member Description mem_base uint32_tuint32_t USBD_DFU_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. Also this value should be aligned on 4 byte boundary. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 523. USBD_DFU_INIT_PARAM class structure Member Description DFU_Done void(*void(* USBD_DFU_INIT_PARAM::DFU_Done)(void))(void) DFU done callback function. This function is provided by the application software. This function gets called after download is finished. Nothing. Returns: Nothing. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 524. USBD_HID_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HID_API::GetMemSize)(USBD_HID_INIT_PARAM_T *param) Function to determine the memory required by the HID function driver module. This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used by HID function driver module. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 525. USBD_HID_INIT_PARAM class structure Member Description mem_base uint32_tuint32_t USBD_HID_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. Also this value should be aligned on 4 byte boundary. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 525. USBD_HID_INIT_PARAM class structure Member Description HID_SetReport ErrorCode_t(*ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length))(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) HID set report callback function. This function is provided by the application software. This function gets called when host sends a HID_REQUEST_SET_REPORT request. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 525. USBD_HID_INIT_PARAM class structure Member Description HID_SetIdle ErrorCode_t(*ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetIdle)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t idleTime))(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t idleTime) Optional callback function to handle HID_REQUEST_SET_IDLE request. The application software could provide this callback to handle HID_REQUEST_SET_IDLE requests sent by the host. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 525. USBD_HID_INIT_PARAM class structure Member Description HID_EpIn_Hdlr ErrorCode_t(*ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpIn_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt IN endpoint event handler. The application software could provide Interrupt IN endpoint event handler. Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 525. USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t(*ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt OUT endpoint event handler. The application software could provide Interrupt OUT endpoint event handler. Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 525. USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hdlr ErrorCode_t(*ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user over-ridable function to replace the default HID class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_HW_API::GetMemSize)(USBD_API_INIT_PARAM_T *param) Function to determine the memory required by the USB device stack's DCD and core layers. This function is called by application layer before calling pUsbApi->hw->... -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description void(*void USBD_HW_API::ISR)(USBD_HANDLE_T hUsb) Function to USB device controller interrupt events. When the user application is active the interrupt handlers are mapped in the user flash space. The user application must provide an interrupt handler for the USB interrupt and call this function in the interrupt handler routine. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description WakeUpCfg void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg) Function to configure USB device controller to wake-up host on remote events. This function is called by application layer to configure the USB device controller to wake-up on remote events. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description ConfigEP void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) Function to configure USB Endpoint according to descriptor. This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received by the stack from USB host. All the endpoints associated with the selected configuration are configured. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description EnableEP void(*void USBD_HW_API::EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to enable selected USB endpoint. This function enables interrupts on selected endpoint. Parameters: 1. hUsb = Handle to the USB device stack. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description SetStallEP void(*void USBD_HW_API::SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to STALL selected USB endpoint. Generates STALL signalling for requested endpoint. hUsbHandle to the USB device stack. EPNumEndpoint number as per USB specification. ie. An EP1_IN is represented by 0x81 number. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description ReadEP uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) Function to read data received on the requested endpoint. This function is called by USB stack and the application layer to read the data received on the requested endpoint. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 526. USBD_HW_API class structure Member Description WriteEP uint32_t(*uint32_t USBD_HW_API::WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt) Function to write data to be sent on the requested endpoint. This function is called by USB stack and the application layer to send data on the requested endpoint. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 527. USBD_MSC_API class structure Member Description GetMemSize uint32_t(*uint32_t USBD_MSC_API::GetMemSize)(USBD_MSC_INIT_PARAM_T *param) Function to determine the memory required by the MSC function driver module. This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used by MSC function driver module. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 528. USBD_MSC_INIT_PARAM class structure Member Description mem_base uint32_tuint32_t USBD_MSC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers. Remark: The memory address set in this field should be accessible by USB DMA controller. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 528. USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t offset, uint8_t **dst, uint32_t length) MSC Read callback function. This function is provided by the application software. This function gets called when host sends a read command. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 528. USBD_MSC_INIT_PARAM class structure Member Description MSC_Verify ErrorCode_t(*ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Verify)(uint32_t offset, uint8_t buf[], uint32_t length))(uint32_t offset, uint8_t buf[], uint32_t length) MSC Verify callback function. This function is provided by the application software. This function gets called when host sends a verify command. -
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UM10503 NXP Semiconductors Chapter 25: LPC43xx USB API Table 528. USBD_MSC_INIT_PARAM class structure Member Description MSC_Ep0_Hdlr ErrorCode_t(*ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default MSC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure. -
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UM10503 Chapter 26: LPC43xx Ethernet Rev. 1.3 — 6 July 2012 User manual 26.1 How to read this chapter The Ethernet controller is available on parts LPC435x and LPC433x. 26.2 Basic configuration The Ethernet controller is configured as follows: • Table 529 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.4 General description The Ethernet block enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2005 standard. The Ethernet interface contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.5 Pin description Table 530. Ethernet pin description Pin function Direction Description MIIM interface ENET_MDIO Ethernet MIIM Data Input and Output. ENET_MDC Ethernet MIIM Clock. RMII interface ENET_RXD[1:0] Ethernet Receive Data. ENET_TXD[1:0] Ethernet Transmit Data. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.6 Register description Table 531. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address Description Reset value Reference offset MAC_CONFIG 0x0000 MAC configuration register 0x0000 8000 Table 532 MAC_FRAME_FILTER... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 531. Register overview: Ethernet MAC and DMA (base address 0x4001 0000) Name Access Address Description Reset value Reference offset DMA_TRANS_POLL_DEMAND 0x1004 Transmit poll demand 0x0000 0000 Table 562 register DMA_REC_POLL_DEMAND 0x1008 Receive poll demand... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 532. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 532. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 532. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued Symbol Description Reset Access value Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 533. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description …continued Symbol Description Reset Access value Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet If the Hash Table register is configured to be double-synchronized to the MII clock domain, the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0] (in Big-Endian mode) of the Hash Table High/Low registers are written to. Please note that consecutive writes to these register should be performed only after at least 4 clock cycles in the destination clock domain when double synchronization is enabled. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 536. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description Symbol Description Reset Access value MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 537. CSR clock range values Bits 5:2 CLK_M4_ETHERNET MDC clock 1010 CLK_M4_ETHERNET/16 1011 CLK_M4_ETHERNET/26 1100 CLK_M4_ETHERNET/102 1101 CLK_M4_ETHERNET/124 1110 CLK_M4_ETHERNET/42 1111 CLK_M4_ETHERNET/62 26.6.6 MAC MII Data register The MII Data register stores Write data to be written to the PHY register located at the address specified in the MAC_MII_ADDR register. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 539. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description Symbol Description Reset Access value Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 539. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description …continued Symbol Description Reset Access value DZPQ Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Remark: Reset values in this register are valid only if the clocks to the Ethernet block are present during the reset operation. Table 541. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.6.10 MAC Remote wake-up frame filter register This is the address through which the remote Wake-up Frame Filter registers (WKUPFMFILTER) are written/read by the Application. WKUPFMFILTER is actually a pointer to eight (not transparent) such WKUPFMFILTER registers. Eight sequential Writes to this address (0x028) will write all WKUPFMFILTER registers. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 543. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description Symbol Description Reset Access value Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 544. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description Symbol Description Reset Access value Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: •... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet If the MAC address registers are configured to be double-synchronized to the MII clock domains, then the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0] (in Big-Endian mode) of the MAC Address Low Register are written to. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 548. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Symbol Description Reset Access value TSENA Time Stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 548. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description Symbol Description Reset Access value TSIPENA Enable Time Stamp Snapshot for PTP over Ethernet frames When set, the time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet In Coarse Update mode (TSCFUPDT bit in Table 548), the value in this register is added to the system time every clock cycle. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 552. System time nanoseconds register (NANOSECONDS, address 0x4001 070C) bit description Symbol Description Reset Access value 30:0 TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 554. System time nanoseconds update register (NANOSECONDSUPDATE, address 0x4001 0714) bit description Symbol Description Reset Access value 30:0 TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.6.24 Target time nanoseconds register This register contains the higher 32 bits of time to be compared with the system time for interrupt event generation. Table 557. Target time nanoseconds register (TARGETNANOSECONDS, address 0x4001... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 559. Time stamp status register (TIMESTAMPSTAT, address 0x4001 0728) bit description Symbol Description Reset Access value TSSOVF Time stamp seconds overflow When set, indicates that the seconds value of the time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 560. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Symbol Description Reset Access value 13:8 Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 560. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued Symbol Description Reset Access value Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.6.29 DMA Receive poll demand register The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is given to wake up the RxDMA from SUSPEND state. The RxDMA can go into SUSPEND state only due to the unavailability of descriptors owned by it. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 565. DMA Transmit descriptor list address register (DMA_TRANS_DES_ADDR, address 0x4001 1010) bit description Symbol Description Reset Access value 31:0 Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 566. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 566. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued Symbol Description Reset Access value Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 567. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description Symbol Description Reset Access value Reserved Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 567. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued Symbol Description Reset Access value Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 567. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued Symbol Description Reset Access value Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 568. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued Symbol Description Reset Access value Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet AN D sbd _intr_o AN D Fig 66. Interrupt generation 26.6.35 DMA Missed frame and buffer overflow counter register The DMA maintains two counters to track the number of missed frames during reception. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 569. DMA Missed frame and buffer overflow counter register (DMA_MFRM_BUFOF, address 0x4001 1020) bit description Symbol Description Reset Access value 15:0 Number of frames missed This register field can be read by the application (Read),... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 570. DMA Receive interrupt watchdog timer register (DMA_REC_INT_WDT, address 0x4001 1024) bit description Symbol Description Reset Access value RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 573. DMA Current host transmit buffer address register (DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit description Symbol Description Reset Access value 31:0 Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Filter 0 Byte Mask WKUPFMFILTER0 Filter 1 Byte Mask WKUPFMFILTER1 Filter 2 Byte Mask WKUPFMFILTER2 Filter 3 Byte Mask WKUPFMFILTER3 Filter 3 Filter 2 Filter 1 Filter 0 WKUPFMFILTER4 RSVD RSVD RSVD RSVD... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet PMT supports four programmable filters that allow support of different receive frame patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter CRC-16 matches the incoming examined pattern, then the wake-up frame is received. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.1.4 System considerations during power-down MAC neither gates nor stops clocks when Power-down mode is enabled. Power saving by clock gating must be done outside the core by the application. The receive data path must be clocked with ENET_RX_CLK during Power-down mode because it is involved in magic packet/wake-on-LAN frame detection. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 575. Priority scheme for transmit and receive DMA Bit 27 Bit 15 Bit 14 Bit 1 Priority scheme Rx has priority over Tx in the ratio 4:1. Tx always has priority over Rx. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Fig 68. Networked time synchronization As shown in Figure 68, the PTP uses the following process: 1. The master broadcasts the PTP Sync messages to all its nodes. The Sync message contains the master.s reference time information. The time at which this message leaves the master.s system is t1. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Most of the PTP implementation is done in the software above the UDP layer. However, the hardware support is required to capture the exact time when specific PTP packets enter or leave the Ethernet port at the MII. This timing information must be captured and returned to the software for the proper implementation of PTP with high accuracy. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet addend_val[31:0] addend_updt Addend register Accumulator register Constant value incr_sub_sec_reg Sub-second register incr_sec_reg Second register Fig 69. System update using fine method The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns accuracy. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This value is as follows: FreqCompensationValue0 = 232 / FreqDivisionRatio If MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages, the algorithm described below must be applied. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.3.4 Receive path functions The MAC captures the timestamp of all frames received on the MII. The MAC does not process the received frames to identify the PTP frames in the default mode, that is, when the Advanced Timestamp feature is not selected. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet The minimum PTP clock frequency depends on the time required between two consecutive SFD bytes. Because the MII clock frequency is fixed by IEEE specification, the minimum PTP clock frequency required for proper operation depends upon the operating mode and operating speed of the MAC as shown in Table 4-1. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet P2P TC A P2P TC B Delay Delay Requester Responder Time Time Timestamps known by Delay Requester Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up: Fig 70. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction As shown in... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.4.2 Clock types The Ethernet controller supports the following clock types defined in the IEEE 1588-2008 standard: • Ordinary clock • Boundary clock • End-to-end transparent clock • Peer-to-peer transparent clock 26.7.4.2.1 Ordinary clock The ordinary clock in a domain supports a single copy of the protocol. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet The residence time of a SYNC packet inside the end-to-end transparent clock is updated in the correction field of the associated Follow_Up PTP packet before it is transmitted. Similarly, the residence time of a Delay_Req packet inside the end-to-end transparent clock is updated in the correction field of the associated Delay_Resp PTP packet before it is transmitted. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 580. Message format defined in IEEE 1588-2008 Bits OCTETS OFFSET sequenceId controlField ( logMessageInterva Field is used in version 1. In version 2, messageType field is used for detecting different message types. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 581. IPv4-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Position Matched Value Description PTP Control Field 0x00/0x01/0x02/ 0x00 – SYNC, (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 – Follow_Up 0x03 –... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 582. IPv6-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Position Matched Value Description PTP Control Field 93 ( 0x00/0x01/0x02/ 0x00 – SYNC (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 –... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet The address match of destination addresses (DA) programmed in MAC address 1 to 31 is used if the control bit 18 (TSENMACADDR: Enable MAC address for PTP frame filtering) of the Timestamp Control register is set. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.4.6 Receive path functions When you select the advanced timestamp feature, the MAC processes the received frames to identify valid PTP frames. You can control the snapshot of the time, to be sent to... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet in Ethernet. The controller can be programmed to interrupt the Host CPU for situations such as Frame Transmit and Receive transfer completion, and other normal/error conditions. The DMA and the Host driver communicate through two data structures: •... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Ring Structure Chain Structure Buffer 1 Buffer 1 Descriptor 0 Descriptor 0 Buffer 2 Buffer 1 Descriptor 1 Buffer 2 Buffer 1 Descriptor 1 Buffer 1 Descriptor 2 Buffer 2 Buffer 1 Descriptor 2... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet The Transmit and Receive engines enter the Running state and attempt to acquire descriptors from the respective descriptor lists. The Receive and Transmit engines then begin processing Receive and Transmit operations. The Transmit and Receive processes are independent of each other and can be started or stopped separately. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Example: Buffer write If the Receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of a received frame need to be transferred, then the DMA writes 3 full words from address 0x00000FF0. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.5.2 Transmission 26.7.5.2.1 TxDMA operation: Default (non-OSF) mode The transmit DMA engine in default mode proceeds as follows: 1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit (TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame data. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll demand error? TxDMA suspended bit set? Transfer data from buffer(s) (AHB) error? Frame xfer complete? Close intermediate Wait for Tx status descriptor Write time stamp to... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet immediately polls the Transmit Descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. In OSF mode, the Run state Transmit DMA operates in the following sequence: 1. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll error? demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) (AHB) Time stamp error? present? Frame xfer Second Write time stamp to... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.5.2.3 Transmit frame processing The Transmit DMA expects that the data buffers contain complete Ethernet frames, excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or PAD insertion, the buffer must have complete Ethernet frames (excluding preamble), including the CRC bytes. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet The driver must explicitly issue a Transmit Poll Demand command after rectifying the suspension cause. 26.7.5.2.5 Reception The Receive DMA engine’s reception sequence is shown in Figure 74 and proceeds as follows: 1. The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit (RDES0[31]). -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Start RxDMA Start Stop RxDMA (Re-)Fetch next Poll demand / descriptor new frame available (AHB) RxDMA suspended error? Frame transfer Own bit set? complete? Frame data Flush disabled ? available ? Flush the... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet If software has enabled time stamping through CSR, when a valid time stamp value is not available for the frame (for example, because the receive FIFO was full before the time stamp could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise (that is, if time stamping is not enabled), the RDES2 and RDES3 remain unchanged. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet descriptor is still owned by the host, by default, the DMA discards the current frame at the top of the MTL Rx FIFO and increments the missed frame counter. If more than one frame is stored in the MTL Rx FIFO, the process repeats. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet 26.7.5.2.10 Error response to DMA For any data transfer initiated by a DMA channel, if the slave replies with an error response, that DMA stops all operations and updates the error bits and the Fatal Bus... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Ctrl Ctrl Status [16:0] TDES0 [30:26] [23:20] Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES1 Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES3... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet SLOT Ctrl Ctrl Reserved for Reserved for Number TDES0 [30:26] [23:20] Status [17:7] Status [3:0] [6:3] Buffer 2 Byte Count [28:16] Buffer 1 Byte Count [12:0] TDES1 Buffer 1 Address [31:0] TDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] TDES3 Fig 76. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 584. Transmit descriptor word 0 (TDES0) Symbol Description Excessive Collision When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the DR (Disable Retry) bit in the MAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 584. Transmit descriptor word 0 (TDES0) Symbol Description Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care”... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 586. Transmit descriptor word 2 (TDES2) Symbol Description 31:0 B1ADD Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment. See Section 26.7.5.1.2... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Status [30:0] RDES0 Buffer 2 Byte Count CTRL Buffer 1 Byte Count CTRL RDES1 [30:29] [28:16] [15:14] [12:0] Buffer 1 Address [31:0] RDES2 Buffer 2 Address [31:0] or Next Descriptor Address [31:0] RDES3... -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 590. Receive descriptor fields 0 (RDES0) Symbol Description Extended Status Available/Rx MAC Address When Advanced Timestamp is present, this bit, when set, indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when the Last Descriptor bit (RDES0[8]) is set. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 590. Receive descriptor fields 0 (RDES0) Symbol Description Length Error When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 591. Receive descriptor fields 1 (RDES1) Symbol Description 12:0 RBS1 Receive Buffer 1 Size Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16, depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address pointer) is not aligned. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet The extended status written is as shown in Table 594. The extended status is written only when there is status related to IPC or timestamp available. The availability of extended status is indicated by bit-0 of RDES0. This status is available only when Advance Timestamp or IPC Full Offload feature is selected. -
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UM10503 NXP Semiconductors Chapter 26: LPC43xx Ethernet Table 596. Receive descriptor fields 7 (RDES7) Symbol Description 31:0 RTSH Receive Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]). -
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UM10503 Chapter 27: LPC43xx LCD Rev. 1.3 — 6 July 2012 User manual 27.1 How to read this chapter The LCD controller is available on part LPC4350. 27.2 Basic configuration The LCD controller is configured as follows: • Table 597 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 27.4 General description The LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single or dual panel monochrome and color LCDs. Packets of pixel coded data are fed using the AHB interface, to two independent, programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD LCD control signals Timing slave controller interface LCD panel clock Panel clock Upper generator panel LCDCLKIN FIFO Upper Upper Input Upper Pixel panel master FIFO palette panel serializer output interface control (128x32) formatter... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD • Display type: STN monochrome, STN color, or TFT • STN 4 or 8-bit interface mode • STN dual or single panel mode • Little-endian, big-endian, or Windows CE mode • Interrupt generation event 27.4.2 Hardware cursor support... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD • 16 bpp, direct 5:5:5 RGB, with 1 bpp not normally used. This pixel is still output, and can be used as a brightness bit to connect to the Least Significant Bit (LSB) of RGB components of a 6:6:6 TFT panel. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 598. LCD controller pins Pin function Type Function LCDLP Output Line synchronization pulse (STN). Horizontal synchronization pulse (TFT) LCDVD[23:0] Output LCD panel data. Bits used depend on the panel configuration. GP_CLKIN Input General purpose CGU input clock. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 600. Pins used for dual panel STN displays Pin name 4-bit Monochrome 8-bit Monochrome Color (14 pins) (22 pins) (22 pins) LCDVD[11:8] LD[3:0] LD[3:0] LD[3:0] LCDVD[15:12] LD[7:4] LD[7:4] LCDVD[23:16] 27.5.1.3 Signals used for TFT displays... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 602. Register overview: LCD controller (base address: 0x4000 8000) …continued Name Access Address offset Description Reset Reference value 0x00C Line End Control register Table 606 UPBASE 0x010 Upper Panel Frame Base Address register... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 603. Horizontal Timing register (TIMH, address 0x4000 8000) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD • PCD = 5 (LCDCLK / 7) If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10, data does not corrupt for PCD = 4, the minimum value. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 605. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description Symbol Description Reset value PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 605. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description Symbol Description Reset value Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 606. Line End Control register (LE, address 0x4000 800C) bit description Symbol Description Reset value Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 608. Lower Panel Frame Base register (LPBASE, address 0x4000 8014) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 609. LCD Control register (CTRL, address 0x4000 8018) bit description …continued Symbol Description Reset value LCDDUAL Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 27.6.8 Interrupt Mask register The INTMSK register controls whether various LCD interrupts occur.Setting bits in this register enables the corresponding raw interrupt INTRAW status bit values to be passed to the INTSTAT register for processing as interrupts. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 611. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description Symbol Description Reset value VCOMPRIS Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 613. Interrupt Clear register (INTCLR, address 0x4000 8028) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Each word location contains two palette entries. This means that 128 word locations are used for the palette. When configured for little-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. When configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 617. Cursor Image registers (CRSR_IMG, address 0x4000 8800 (CRSR_IMG0) to 0x4000 8BFC (CRSR_IMG1)) bit description Symbol Description Reset value 31:0 CRSR_IMG Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 619. Cursor Configuration register (CRSR_CFG, address 0x4000 8C04) bit description Symbol Description Reset value CrsrSize Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 621. Cursor Palette register 1 (CRSR_PAL1, address 0x4000 8C0C) bit description Symbol Description Reset value Red color component 15:8 GREEN Green color component 23:16 BLUE Blue color component. 31:24 Reserved, user software should not write ones to reserved bits. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 623. Cursor Clip Position register (CRSR_CLIP, address 0x4000 8C14) bit description Symbol Description Reset value CRSRCLIPX Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 27.6.24 Cursor Raw Interrupt Status register The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt controller. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 27.7.1.2 AMBA AHB master interface The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configured to obtain data from any on-chip SRAM on AHB, various types of off-chip static memory, or off-chip SDRAM. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 628 through Table 630 show the structure of the data in each DMA FIFO word corresponding to the endianness and bpp combinations. For each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 629. FIFO bits for Big-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp UM10503 All information provided in this document is subject to legal disclaimers. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 630. FIFO bits for Little-endian Byte, Big-endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp Table 631 shows the structure of the data in each DMA FIFO word in RGB mode. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 631. RGB mode data formats FIFO data 24-bit RGB 16-bit (1:5:5:5 RGB) 16-bit (5:6:5 RGB) 16-bit (4:4:4 RGB) p1 intensity bit p1, Blue 4 p1, Blue 4 p1, Blue 3 p1, Blue 3... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Pixel data values can be written and verified through the AHB slave interface. For information on the supported colors, refer to the section on the related panel type earlier in this chapter. The palette RAM is a dual port RAM with independent controls and addresses for each port. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 633. Palette data storage for STN color modes. Bit(s) Name Description Name Description (RGB format) (RGB format) (BGR format) (BGR format) G[0] Unused G[0] Unused R[4:1] Red palette data B[4:1] Blue palette data... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD When the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. When the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD With FrameSync inactive, the cursor responds immediately to any change in the programmed CRSR_XY value. Some transient smearing effects may be visible if the cursor is moved across the LCD scan line. With FrameSync active, the cursor only updates its position after a vertical synchronization has occurred. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 27.7.5.6 Cursor image format The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 637 shows the buffer to pixel mapping for Cursor 0. Table 637. Buffer to pixel mapping for 32 x 32 pixel cursor format Offset into cursor memory Data bits (8 * y) -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 638. Buffer to pixel mapping for 64 x 64 pixel cursor format Offset into cursor memory Data bits (16 * y) (16 * y) +4 (16 * y) + 8 (16 * y) + 12... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 640. Color display driven with 2 2/3 pixel data Byte CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] CLD[0] P2[Green] P2[Red] P1[Blue] P1[Green] P1[Red] P0[Blue] P0[Green] P0[Red] P5[Red] P4q[Blue] P4[Green] P4[Red] P3[Blue] P3[Green]... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD • Next base address update interrupt. • FIFO underflow interrupt. Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the INT_MSK register. These interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 1. When power is applied, the following signals are held LOW: • LCDLP • LCDDCLK • LCDFP • LCDENAB/ LCDM • LCDVD[23:0] • LCDLE 2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This enables the following signals into their active states: •... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD LCD on sequence LCD off sequence Minimum 0 ms Minimum 0 ms LCD Power Minimum 0 ms Minimum 0 ms LCDLP, LCDCP, LCDFP, LCDAC, LCDLE Contrast Voltage LCDPWR, LCD[23:0] Display specific delay Display specific delay Fig 82. -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD 27.8 LCD timing diagrams one horizontal line pixel clock (internal) LCD_TIMH (HSW) LCDLP (line synch pulse) suppressed during LCDLP LCDDCLK (panel clock) 16 LCD_TIMH(PPL) 1 LCD_TIMH (HFP) LCD_TIMH (HBP) horizontal back porch... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD one frame LCDDCLK panel data clock active (panel clock) LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch all horizontal lines for one frame front porch (defined in line clocks) -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD one frame LCDDCLK panel data clock active (panel clock) LCDENA data enable (data enable) LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch all horizontal lines for one frame... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 641. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC43xx pin LCD function LPC43xx pin LCD function... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 642. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC43xx pin LCD function LPC43xx pin LCD function... -
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UM10503 NXP Semiconductors Chapter 27: LPC43xx LCD Table 643. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC43xx LPC43xx LPC43xx pin LPC43xx pin used... -
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UM10503 Chapter 28: LPC43xx State Configurable Timer (SCT) Rev. 1.3 — 6 July 2012 User manual 28.1 How to read this chapter The SCT is available on all LPC43xx parts. 28.2 Basic configuration The SCT is configured as follows: • Table 644 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) – 32 states 28.4 General description The State Configurable Timer (SCT) allows a wide variety of timing, counting, output modulation, and input capture operations. The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) SCT clock CLK_M4_SCT prescaler H counter Unified counter prescaler L counter Fig 88. SCT counter and select logic 28.5 Pin description The SCT inputs can originate from the external pins or from several internal sources. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 645. SCT inputs and outputs …continued Description Pin function Internal signal Default (see CTOUTCTRL GIMA, bit (see Table 148) Table SCT input 3 CTIN_3 USART0 TX active I2S1_RX_MWS I2S1_TX_MWS... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 645. SCT inputs and outputs …continued Description Pin function Internal signal Default (see CTOUTCTRL GIMA, bit (see Table 148) Table SCT output 8 ORed with Timer2 match output 0... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 2. The REGMODEn bits in the REGMODE register determine whether each set of Match/Capture registers uses the match or capture functionality: – REGMODEn = 1: Registers operate as match and reload registers. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 646. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset EVEN 0x0F0 SCT event enable register 0x0000 0000 Table 662... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 646. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset MATCHREL0_H to 0x202 to SCT match reload value register 0 to 15; high... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 646. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset EVSTATEMSK8 0x340 SCT event state register 8 0x0000 0000 Table 670... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 646. Register overview: State Configurable Timer (base address 0x4000 0000) …continued Name Access Address Description Reset value Reference offset OUTPUTSET12 0x560 SCT output 12 set register 0x0000 0000 Table 672... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 647. SCT configuration register (CONFIG - address 0x4000 0000) bit description …continued Symbol Value Description Reset value CLKSEL SCT clock select 0000 Rising edges on input 0. Falling edges on input 0. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 648. SCT control register (CTRL - address 0x4000 0004) bit description Symbol Value Description Reset value DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) If UNIFY = 0 in the CONFIG register, this register can be written to as two registers LIMIT_L (address 0x4000 4008) and LIMIT_H (address 0x4000 400A). Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 651. SCT stop condition register (STOP - address 0x4000 0010) bit description Symbol Description Reset value 15:0 STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.6.8 SCT state register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers STATE_L (address 0x4000 4044) and STATE_H (address 0x4000 4046). -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 655. SCT input register (INPUT - address 0x4000 0048) bit description Symbol Description Reset value AIN0 Real-time status of input 0. AIN1 Real-time status of input 1. AIN2 Real-time status of input 2. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 656. SCT match/capture registers mode register (REGMODE - address 0x4000 004C) bit description Symbol Description Reset value 15:0 REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 658. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Valu Description Reset value SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 658. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description Symbol Valu Description Reset value SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 659. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O2RES Effect of simultaneous set and clear on output 2. No change. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 659. SCT conflict resolution register (RES - address 0x4000 0058) bit description Symbol Value Description Reset value O10RES Effect of simultaneous set and clear on output 10. No change. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 660. SCT DMA 0 request register (DMAREQ0 - address 0x4000 005C) bit description Symbol Description Reset value 15:0 DEV_0 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.6.17 SCT conflict enable register This register enables the “no change conflict” events specified in the SCT conflict resolution register to request an IRQ. Table 664. SCT conflict enable register (CONEN - address 0x4000 00F8) bit description... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) There is no “write-through” from Reload registers to Match registers. Before starting a counter, software can write one value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1) If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CAPCTRLn_L (address 0x4000 4100 to 0x4000 413C) and CAPCTRLn_H (address 0x4000 4102 to 0x4000 413E). -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) When the UNIFY bit is 0, each event is associated with a particular counter by the HEVENT bit in its event control register. An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 671. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C (EVCTRL15)) bit description Symbol Value Description Reset value STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.7 Functional description 28.7.1 Match logic Counter H Match Match Reload Match i H Reg i H UNIFY Match Match Reload Match i L Reg i L Counter L Fig 89. Match logic 28.7.2 Capture logic... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) H matches select L matches MATCHSELi inputs event i select outputs IOSELi OUTSELi IOCONDi COMBMODEi select STATEMASKi H STATE L STATE HEVENTi Fig 91. Event selection 28.7.4 Output generation Figure 92 shows one output slice of the SCT. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.7.6 Clearing the prescaler When enabled by a non-zero PRE field in the Control register, the prescaler acts as a clock divider for the counter, like a fractional part of the counter value. The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons: •... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.7.8 DMA operation A DMA controller can be used to write one or more Reload registers, or read one or more Capture registers, typically at the start of a counter cycle. DMA access to more than one Reload or Capture register requires that they be consecutive registers. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 675. Alternate address map for DMA halfword access Match register Capture register Standard offset DMA halfword offset MATCHREL1_L CAPCTRL1_L 0x204 0x282 MATCHREL1_H CAPCTRL1_H 0x206 0x2C2 UM10503 All information provided in this document is subject to legal disclaimers. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.7.10 SCT operation In its simplest, single-state configuration, the SCT operates as an event controlled one- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.7.10.1.3 Configure events and event responses 1. Define when each event can occur in the following way in the EVCTRL registers (up to 16, one register per event): – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) 28.7.10.1.4 Configure multiple states 1. In the EVSTATEMASK register for each event (up to 16 events, one register per event), select the state or states (up to 31) in which this event is allowed to occur. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) – When the counters are stopped, both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again. – When the counter are halted, only a software write to clear the HALT bit can start the counter again. -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) input transition events input 0 match events counter output 0 STATE 0 STATE 1 STATE 0 Fig 94. SCT configuration example This application of the SCT uses the following configuration (all register values not listed... -
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UM10503 NXP Semiconductors Chapter 28: LPC43xx State Configurable Timer (SCT) Table 676. SCT configuration example Configuration Registers Setting • Define when event 4 EVCTRL4 Set COMBMODE = 0x1. Event 4 uses match condition only. occurs • Set MATCHSEL = 0x3. Select match value of match register 4. -
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UM10503 Chapter 29: LPC43xx Timer0/1/2/3 Rev. 1.3 — 6 July 2012 User manual 29.1 How to read this chapter The timers are available on all LPC43xx parts. 29.2 Basic configuration The Timers are configured as follows: • Table 677 for clocking and power control. •... -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: –... -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0] INTERRUPT CAP[3:0] STOP ON MATCH RESET ON MATCH LOAD[3:0] CAPTURE CONTROL REGISTER... -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 29.5 Pin description Input signals to each timer capture channel can originate from the external pins or from several other internal sources. The GIMA (see Table 148) and (for capture channel 3 of each timer) the CTOUTCTRL bit of CREG6 determine which signal is captured by the timer. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 679. Timer0 inputs and outputs …continued Input/output From/to From/to internal signal Default (see CTOUTCTRL multiplexed pin GIMA, bit (see function Table 148) Table MAT2 T0_MAT2 CTOUT_2 if match ORed with SCT output... -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 681. Timer2 inputs and outputs Input/output From/to From/to internal signal Default (see CTOUTCTRL multiplexed pin GIMA, bit (see function Table 148) Table Timer2 inputs CAP0 CTIN_0 SGPIO12_DIV T2_CAP0 CAP1 CTIN_1 T2_CAP1 USART2 TX active... -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 682. Timer3 inputs and outputs …continued Input/output From/to From/to internal signal Default (see CTOUTCTRL multiplexed pin GIMA, bit (see function Table 148) Table CAP1 CTIN_6 T3_CAP1 USART3 TX active I2S0_TX_MWS CAP2 CTIN_7... -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 683. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) Name Access Address Description Reset Reference offset value 0x000 Interrupt Register. The IR can be written to clear interrupts. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 29.6.1 Timer interrupt registers The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 686. Timer counter registers (TC - addresses 0x4008 4008 (TIMER0), 0x4008 5008 (TIMER1), 0x400C 3008 (TIMER2), 0x400C 4008 (TIMER3)) bit description Symbol Description Reset value 31:0 Timer counter value. 29.6.4 Timer prescale registers The 32-bit Timer prescale register specifies the maximum value for the Prescale Counter. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 689. Timer match control registers (MCR - addresses 0x4008 4014 (TIMER0), 0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit description …continued Symbol Value Description Reset value MR0S Stop on MR0 TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 29.6.7 Timer match registers (MR0 - MR3) The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 691. Timer capture control registers (CCR - addresses 0x4008 4028 (TIMER0), 0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit description …continued Symbol Value Description Reset value CAP1I Interrupt on CAPn.1 event A CR1 load due to a CAPn.1 event will generate an interrupt. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 29.6.10 Timer external match registers The External Match Register provides both control and status of the external match pins. In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a Match number, 0 through 3. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Table 693. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0), 0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit description Symbol Value Description Reset value EMC2 External Match Control 2. Determines the functionality of External Match 2. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one quarter of the PCLK clock. -
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UM10503 NXP Semiconductors Chapter 29: LPC43xx Timer0/1/2/3 Figure 97 shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and the match register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt indicating that a match occurred is generated. -
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UM10503 Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Rev. 1.3 — 6 July 2012 User manual 30.1 How to read this chapter The Motor control PWM is available on all LPC43xx parts. 30.2 Basic configuration The PWM is configured as follows: •... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can control something off-chip, like one set of coils in a motor. Each channel includes a Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by an input pin (counter mode). -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) 30.5.1 Block Diagram PCLK MCI0-2 Clock Event Clock Event Clock Event selection selection selection selection selection selection MCCNTCON MCCAPCON cntl cntl cntl MAT0 MAT1 MAT2 ACMODE ACMODE (write) (write) (write) -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 697. MOTOCON PWM pin description Pin function Type Description MCOA0/1/2 Output A for channels 0, 1, 2 MCOB0/1/2 Output B for channels 0, 1, 2 MCABORT Low-active Fast Abort... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 698. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000) Name Access Address Description Reset value Reference offset CNTCON_SET 0x060 Count Control set address Table 716... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 699. MCPWM Control read address (CON - 0x400A 0000) bit description Symbol Value Description Reset value POLA1 Selects polarity of the MCOA1 and MCOB1 pins. Passive state is LOW, active state is HIGH. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 699. MCPWM Control read address (CON - 0x400A 0000) bit description Symbol Value Description Reset value DCMODE 3-phase DC mode select (see Section 30.8.6). 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 701. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description Symbol Description Reset value DISUP0_CLR Writing a one clears the corresponding bit in the CON register. - Writing a one clears the corresponding bit in the CON register. - RUN1_CLR Writing a one clears the corresponding bit in the CON register. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 702. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description Symbol Description Reset value CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 703. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit description Symbol Description Reset value CAP2MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. CAP2MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 704. MCPWM Capture control clear register (CAPCON_CLR - address 0x400A 0014) bit description Symbol Description Reset value CAP1MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, the match between TC and LIM switches the channel’s A output from “active” to “passive” state. If the channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A output switches from “passive”... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) 30.7.7 MCPWM Communication Pattern register This register is used in DC mode only. The internal MCOA0 signal is routed to any or all of the six output pins under the control of the bits in this register. Like the Match and Limit registers, this register has “write”... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 711. Motor Control PWM interrupts Symbol Description ILIM0/1/2 Limit interrupts for channels 0, 1, 2. IMAT0/1/2 Match interrupts for channels 0, 1, 2. ICAP0/1/2 Capture interrupts for channels 0, 1, 2. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 712. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description Symbol Value Description Reset value ICAP2 Capture interrupt for channel 2. Interrupt disabled. Interrupt enabled. 14:11 Reserved. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 714. PWM interrupt enable clear register (INTEN_CLR - address 0x400A 0058) bit description Symbol Description Reset value ILIM0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 715. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description Symbol Value Description Reset value TC0MCI0_FE Counter 0 falling edge mode, channel 0. A falling edge on MCI0 does not affect counter 0. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 715. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description Symbol Value Description Reset value TC2MCI1_RE Counter 2 rising edge mode, channel 1. A rising edge on MCI1 does not affect counter 2. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 716. MCPWM Count Control set address (CNTCON_SET - 0x400A 0060) bit description Symbol Description Reset value TC1MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. TC1MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 717. MCPWM Count Control clear address (CNTCON_CLR - 0x400A 0064) bit description Symbol Description Reset value TC0MCI2_RE Writing a one clears the corresponding bit in the CNTCON register. TC0MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 718. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description Symbol Value Description Reset value ILIM0_F Limit interrupt flag for channel 0. This interrupt source is not contributing to the MCPWM interrupt request. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) Table 718. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description Symbol Value Description Reset value ICAP2_F Capture interrupt flag for channel 2. This interrupt source is not contributing to the MCPWM interrupt request. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) 30.7.11.3 MCPWM Interrupt Flags clear address Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus clearing the corresponding interrupt request(s). This is typically done in interrupt service routines. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) 30.8 Functional description 30.8.1 Pulse-width modulation Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors to switch a controlled point between two power rails. Most of the time the two outputs have opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to delay both signals’... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) active active passive passive MCOB passive active passive active MCOA POLA = 0 Fig 100. Center-aligned PWM waveform without dead time, POLA = 0 Dead-time counter When the a channel’s DTE bit is set in CON, the dead-time counter delays the passive-to-active transitions of both MCO outputs. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) active active passive passive MCOB active active passive passive POLA = 0 MCOA Fig 102. Center-aligned waveform with dead time, POLA = 0 30.8.2 Shadow registers and simultaneous updates The Limit, Match, and Communication Pattern registers (LIM, MAT, and CP) are implemented as register pairs, each consisting of a write register and an operational register. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) A capture event on a channel causes the following: • The current value of the TC is stored in the Capture register (CAP). • If the channel’s capture event interrupt is enabled (see... -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) MCOB2 CCPB2 = 1, on-state CCPA2 = 1, on-state MCOA2 MCOB1 CCPB1 = 0, off-state MCOA1 CCPA1 = 1, on-state MCOB0 CCPB0 = 0, off-state CCPA0 = 1, on-state MCOA0 POLA0 = 0, INVBDC = 0 Fig 103. -
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UM10503 NXP Semiconductors Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM) MCOB2 POLA2 = 0 MCOA2 MAT2 MAT2 MCOB1 POLA1 = 0 MCOA1 MAT1 MAT1 MCOB0 POLA0 = 0 MCOA0 MAT0 LIM0 LIM0 timer reset timer reset Fig 104. Three-phase AC mode sample waveforms, edge aligned PWM mode 30.8.8 Interrupts... -
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UM10503 Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) Rev. 1.3 — 6 July 2012 User manual 31.1 How to read this chapter The QEI is available on all LPC435x/3x parts. 31.2 Basic configuration The QEI is configured as follows: • Table 722 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.4 Introduction A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and velocity. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) tim _int Velocity Timer Velocity Reload gating velc _int Velocity Compare Digital Filter Velocity Capture Quad Decoder err _int Velocity Counter inx _int dir _int enclk _int Windowing max _pos _int... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.5 Pin description Table 723. QEI pin description Description function QEI_A Used as the Phase A (PhA) input to the Quadrature Encoder Interface. QEI_B Used as the Phase B (PhB) input to the Quadrature Encoder Interface. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) Table 724. Register overview: QEI (base address 0x400C 6000) Name Access Address Description Reset value Reference offset INTSTAT 0xFE0 Interrupt status register Table 748 0xFE4 Interrupt enable register Table 749... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.1 Control registers 31.6.1.1 QEI Control register This register contains bits which control the operation of the position and velocity counters of the QEI module. Table 725: QEI Control register (CON - address 0x400C 6000) bit description... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) Table 727: QEI Configuration register (CONF - address 0x400C 6008) bit description Symbol Description Reset value DIRINV Direction invert. When = 1, complements the DIR bit. SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.2 Position, index and timer registers 31.6.2.1 QEI Position register This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.2.6 QEI Index Count register This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. Table 733. QEI Index Count register (INXCNT- address 0x400C 6020) bit description... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.2.11 QEI Velocity Capture register This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.2.16 QEI Index acceptance window register This register contains the width of the index acceptance window, when the index and the phase / clock edges fall nearly together. If the activating phase / clock edge falls before the Index, but within the window, the (re)calibration will be activated on that clock/phase edge. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.3 Interrupt registers 31.6.3.1 QEI Interrupt Enable Clear register Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable register (QEIIE). Table 746: QEI Interrupt Enable Clear register (IEC - address 0x400C 6FD8) bit description... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) Table 747: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description Symbol Description Reset value POS2_INT Indicates that the position 2 compare value is equal to the current position. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.6.3.4 QEI Interrupt Enable register This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a 0 bit disables the corresponding interrupt. Table 749: QEI Interrupt Enable register (IE - address 0x400C 6FE4) bit description... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) Table 750: QEI Interrupt Status Clear register (CLR - 0x400C 6FE8) bit description Symbol Description Reset value POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set and the REV0_INT is set. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) 31.7 Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel. -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) Table 754. Encoder direction DIR bit DIRINV bit direction forward reverse reverse forward Figure 106 shows how quadrature encoder signals equate to direction and count. direction position -1 -1 -1 -1... -
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UM10503 NXP Semiconductors Chapter 31: LPC43xx Quadrature Encoder Interface (QEI) is then cleared. The velocity timer is loaded with the contents of the velocity reload register (LOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The number of edges counted in a given time period is directly proportional to the velocity of the encoder. -
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UM10503 Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT) Rev. 1.3 — 6 July 2012 User manual 32.1 How to read this chapter The RIT is available on all LPC43xx parts. 32.2 Basic configuration The RIT is configured as follows: • Table 755 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT) RESET CNT_ENA PBUS RESET 32-bit COUNTER ENABLE_TIMER PBUS ENABLE_BREAK BREAK PBUS ENABLE_CLK PBUS RESET SET_INT COMPARATOR INTR PBUS PBUS write '1' to clear RESET RESET CTRL PBUS PBUS register COMPARE REGISTER... -
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UM10503 NXP Semiconductors Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT) 32.5.2 RI Mask register Table 758. RI Mask register (MASK - address 0x400C 0004) bit description Symbol Description Reset value 31:0 RIMASK Mask register. This register holds the 32-bit mask value. A one written... -
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UM10503 NXP Semiconductors Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT) 32.6 RI timer operation Following reset, the counter begins counting up from 0x0000 0000. Whenever the counter value equals the value programmed into the COMPVAL register the interrupt flag will be set. -
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UM10503 Chapter 33: LPC43xx Alarm timer Rev. 1.3 — 6 July 2012 User manual 33.1 How to read this chapter The Alarm timer is available on all LPC43xx parts. 33.2 Basic configuration The Alarm timer is configured as follows: • Table 761 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 33: LPC43xx Alarm timer 33.4 Register description Table 762. Register overview: Alarm timer (base address 0x4004 0000) Name Access Address Description Reset Reference offset value DOWNCOUNTER 0x000 Downcounter register 0x000 Table 763 PRESET 0x004 Preset value register... -
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UM10503 NXP Semiconductors Chapter 33: LPC43xx Alarm timer 33.4.4 Interrupt set enable register Table 766. Interrupt set enable register (SET_EN - 0x4004 0FDC) bit description Symbol Description Reset value SET_EN Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register. -
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UM10503 Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) Rev. 1.3 — 6 July 2012 User manual 34.1 How to read this chapter The WWDT is available on all LPC43xx parts. 34.2 Basic configuration The WWDT is configured as follows: • Table 771 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) • Flag to indicate Watchdog reset. • The WWDT uses the IRC as a fixed clock source. 34.4 Applications The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) 34.5.2 WWDT behavior in the power-down modes The WWDT is running in Sleep mode. A watchdog triggered reset in Sleep mode resets and wakes up the chip. Likewise, a watchdog triggered interrupt wakes up the chip from Sleep mode if the interrupt is enabled in the NVIC. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) Table 773. Watchdog Mode register (MOD - 0x4008 0000) bit description Symbol Value Description Reset value WDEN Watchdog enable bit. This bit is Set Only. The watchdog timer is stopped. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) Table 774. Watchdog operating modes selection WDEN WDRESET Mode of Operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) Table 776. Watchdog Feed register (FEED - 0x4008 0008) bit description Symbol Description Reset value Feed Feed value should be 0xAA followed by 0x55. 34.7.4 Watchdog timer value register The WDTV register is used to read the current value of Watchdog timer counter. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) Table 779. Watchdog Timer Window register (WINDOW - 0x4008 0018) bit description Symbol Description Reset value 23:0 WDWINDOW Watchdog window value. 0xFF FFFF 31:24 Reserved, user software should not write ones to reserved bits. -
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UM10503 NXP Semiconductors Chapter 34: LPC43xx Windowed Watchdog timer (WWDT) WDCLK / 4 Watchdog 125A 1259 1258 1257 Counter Early Feed Event Watchdog Reset Conditions : WINDOW = 0x1200 WARNINT = 0x3FF = 0x2000 Fig 109. Early Watchdog Feed with Windowed Mode Enabled... -
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UM10503 Chapter 35: LPC43xx Real-Time Clock (RTC) Rev. 1.3 — 6 July 2012 User manual 35.1 How to read this chapter The RTC is available on all LPC43xx parts. 35.2 Basic configuration The RTC is configured as follows: • Table 780 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) 35.4 General description The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially in reduced power modes. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) 35.6 Register description Table 782. Register overview: RTC (base address 0x4004 6000) Name Access Address Description Reset Reference offset value 0x000 Interrupt Location Register Table 784 0x004 Reserved 0x00 0x008 Clock Control Register... -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) 35.6.1 Interrupt Location Register The Interrupt Location Register is a 2-bit register that specifies which blocks are generating an interrupt. Writing a one to the appropriate bit clears the corresponding interrupt. Writing a zero has no effect. This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) 35.6.3 Counter Increment Interrupt Register The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt every time a counter is incremented. This interrupt remains valid until cleared by writing a 1 to bit 0 of the Interrupt Location Register (ILR[0]). -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) 35.6.5 Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The... -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) 35.6.5.3 Consolidated Time Register 2 The Consolidate Time Register 2 contains just the Day of Year value. Table 790. Consolidated Time register 2 (CTIME2 - address 0x4004 601C) bit description Symbol... -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) Table 793. Seconds register (SEC - address 0x4004 6020) bit description Symbol Description Reset value SECONDS Seconds value in the range of 0 to 59 31:6 Reserved, user software should not write ones to reserved bits. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) Table 798. Day of year register (DOY - address 0x4004 6034) bit description Symbol Description Reset value Day of year value in the range of 1 to 365 (366 for leap years). -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) Table 801. Calibration register (CALIBRATION - address 0x4004 6040) bit description Symbol Value Description Reset value CALDIR Calibration direction Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) Table 805. Alarm Hours register (AHRS - address 0x4004 6068) bit description Symbol Description Reset value HOURS Hours value in the range of 0 to 23 31:5 Reserved, user software should not write ones to reserved bits. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) Table 810. Alarm Year register (AYRS - address 0x4004 607C) bit description Symbol Description Reset value 11:0 YEAR Year value in the range of 0 to 4095. 31:12 Reserved, user software should not write ones to reserved bits. -
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UM10503 NXP Semiconductors Chapter 35: LPC43xx Real-Time Clock (RTC) • When the calibration counter reaches CALVAL, a calibration match occurs and all RTC timers will be stopped for one clock cycle so that the timers will not increment in the next cycle. -
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UM10503 Chapter 36: LPC43xx Event monitor/recorder Rev. 1.3 — 6 July 2012 User manual 36.1 How to read this chapter The event monitor/recorder is available on parts with on-chip flash only. 36.2 Basic configuration The event monitor/recorder is configured together with the RTC: •... -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder 36.5 General description The Event Monitor/Recorder relies on VBAT to be present at all times. A loss or dip of VBAT voltage causes the Real-Time Clock power fail detector to reset the event recordings. -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder Timestamp value doy:h:m:s ERFIRSTSTAMP0 ERCONTROL ERLASTSTAMP 0 WAKEUP0 ERFIRSTSTAMP1 Control WAKEUP1 Block ERLASTSTAMP 1 WAKEUP2 ERFIRSTSTAMP2 ERSTATUS ERLASTSTAMP 2 To wakeup/interrupt Fig 113. Event Monitor/Recorder block diagram The CPU may at any time check the ERSTATUS register for events. If, for instance the EV0 bit is set, the corresponding ERFIRSTSTAMP0 and ERLASTSTAMP0 registers contain valid timestamps. -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder 36.6 Pin description Table 812. Event Monitor/Recorder pin description Name Type Description WAKEUP0 Input Event input for event monitor/recorder channel 0. WAKEUP1 Input Event input for event monitor/recorder channel 1. WAKEUP2 Input Event input for event monitor/recorder channel 2. -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder 36.7.1 Event Monitor/Recorder Control Register The Event Monitor/Recorder Control Register allows setup of the Event Monitor/Recorder and individual control over aspects of each channel’s operation. Table 814. Event Monitor/Recorder Control Register (ERCONTROL - address 0x4004 6084) bit description... -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder Table 814. Event Monitor/Recorder Control Register (ERCONTROL - address 0x4004 6084) bit description Symbol Value Description Reset value GPCLEAR_EN2 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2. -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder 36.7.2 Event Monitor/Recorder Status Register The Event Monitor/Recorder Status Register contains flags for the 3 event channels, general purpose register clear flag, and the interrupt/wakeup flag. Table 815. Event Monitor/Recorder Status Register (ERSTATUS - address 0x4004 6080) bit description... -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder 36.7.3 Event Monitor/Recorder Counters Register The Event Monitor/Recorder Counters Register is a read-only register that allows reading counters that record the number of events on each Event Monitor/Recorder channel. Table 816. Event Monitor/Recorder Counters Register (ERCOUNTERS - address 0x4004 6088) bit description... -
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UM10503 NXP Semiconductors Chapter 36: LPC43xx Event monitor/recorder Note that after a first event on any channel, the contents of the corresponding ERFIRSTSTAMP and ERLASTSTAMP registers will be the same (the first event and the most recent event being the same). The values will diverge if a second event occurs on the same channel Table 818. -
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UM10503 Chapter 37: LPC43xx USART0_2_3 Rev. 1.3 — 6 July 2012 User manual 37.1 How to read this chapter The USART0/2/3 controllers are available on all LPC43xx parts. 37.2 Basic configuration The USART0/2/3 are configured as follows: • Table 819 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 • Smart Card interface. 37.4 General description The architecture of the USART is shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the USART. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Transmitter Transmitter Transmitter Transmitter Holding Shift FIFO Register Register Transmitter Interface TX_DMA_REQ TX_DMA_CLR CSRC UCLK UCLK Baud Rate/Clock Generator Fractional Main PCLK UCLK Rate Divider Divider (DLM, DLL) interrupt FIFO Control & Status... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 37.5 Pin description Table 820. USART0/2/3 pin description Pin function Direction Description USART0 U0_RXD Serial Input. Serial receive data. U0_TXD Serial Output. Serial transmit data. U0_DIR RS-485/EIA-485 output enable/direction control. U0_UCLK Serial clock input/output for USART0 in synchronous mode. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 821. Register overview: USART0/2/3 (base address: 0x4008 1000, 0x400C 1000, 0x400C 2000) Name Access Address Description Reset Reference offset value 0x004 Interrupt Enable Register. Contains individual interrupt 0x00 Table 826 enable bits for the 7 potential USART interrupts (DLAB = 0). -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 37.6.1 USART Receiver Buffer Register The RBR is the top byte of the USART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest”... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 824. USART Divisor Latch LSB Register when DLAB = 1 (DLL - addresses 0x4008 1000 (USART0), 0x400C 1000 (USART2), 0x400C 2000 (USART3)) bit description Symbol Description Reset value DLLSB Divisor latch LSB. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 826. USART Interrupt Enable Register when DLAB = 0 (IER - addresses 0x4008 1004 (USART0), 0x400C 1004 (USART2), 0x400C 2004 (USART3)) bit description Symbol Value Description Reset value ABTOINTEN Enables the auto-baud time-out interrupt. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 828. USART Interrupt Handling IIR[3:0] Priority Interrupt Interrupt source Interrupt value type reset 0100 Second RX Data Rx data available or trigger level reached in Available FIFO (FCR0=1) Read USART FIFO drops... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 829. USART FIFO Control Register Write Only (FCR - addresses 0x4008 1008 (USART0), 0x400C 1008 (USART2), 0x400C 2008 (USART3)) bit description Symbol Value Description Reset value FIFOEN FIFO Enable. USART FIFOs are disabled. Must not be used in the application. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 37.6.7 USART Line Control Register The LCR determines the format of the data character that is to be transmitted or received. Table 830. USART Line Control Register (LCR - addresses 0x4008 100C (USART0), 0x400C... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 831. USART Line Status Register Read Only (LSR - addresses 0x4008 1014 (USART0), 0x400C 1014 (USART2), 0x400C 2014 (USART3)) bit description Bit Symbol Value Description Reset Value Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 831. USART Line Status Register Read Only (LSR - addresses 0x4008 1014 (USART0), 0x400C 1014 (USART2), 0x400C 2014 (USART3)) bit description …continued Bit Symbol Value Description Reset Value THRE Transmitter Holding Register Empty. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 833. Autobaud Control Register (ACR - addresses 0x4008 1020 (USART0), 0x400C 1020 (USART2), 0x400C 2020 (USART3)) bit description Symbol Value Description Reset value START Start bit. This bit is automatically cleared after auto-baud completion. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 834. IrDA Control Register (ICR - address 0x4000 8024) bit description Symbol Value Description Reset value IRDAINV Serial input direction. The serial input is not inverted. The serial input is inverted. This has no effect on the serial output. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 836. USART Fractional Divider Register (FDR - addresses 0x4008 1028 (USART0), 0x400C 1028 (USART2), 0x400C 2028 (USART3)) bit description Function Description Reset value DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 837. USART Oversampling Register (OSR - addresses 0x4008 102C (USART0), 0x400C 102C (USART2), 0x400C 20402C (USART3)) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 838. USART Half duplex enable register (HDEN - addresses 0x4008 1040 (USART0), 0x400C 1040 (USART2), 0x400C 2040 (USART3)) bit description Symbol Value Description Reset value HDEN Half-duplex mode enable Disable half-duplex mode. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 The NACKDIS bit is used to inhibit a nack response during T=0 (the I/O line is not pulled low during the guard time to indicate an erroneous reception). The received character will be stored in the RX FIFO but a parity error will be generated. It is up to the software to handle the incorrect received character. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 840. USART RS485 Control register (RS485CTRL - addresses 0x4008 104C (USART0), 0x400C 104C (USART2), 0x400C 204C (USART3)) bit description …continued Symbol Value Description Reset value Reserved. DCTRL Direction control for DIR pin. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 37.6.18 USART RS485 Delay value register The user may program the 8-bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de-assertion of the DIR pin. This delay time is in periods of the baud clock. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 843. USART Synchronous mode control registers (SYNCCTRL - address addresses 0x4008 1058 (USART0), 0x400C 1058 (USART2), 0x400C 2058 (USART3)) bit description Symbol Value Description Reset value SSSDIS Start/stop bits Send start and stop bits as in other modes. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 37.6.20 USART Transmit Enable Register In addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), TER enables implementation of software flow control. When TxEn = 1, USART transmitter will keep sending data as long as they are available. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud. Also, when auto-baud is used, any write to DLM and DLL registers should be done before ACR register write. The minimum and the maximum baud rates supported by USART are function of USART_PCLK, number of data bits, stop bits and parity bits. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Table 845. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778... -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 The USART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. Each USART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the direction control pin. RS485/EIA-485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of the DIR pin. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 start bit is aligned with a clock edge (the clock may not have been running before). In this case, the edge on the serial input data due to the start bit (logic 1 to 0) is used to determine the start of the character. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 During synchronous master mode, when start and stop bits are transmitted, the user can enable the external clock continuously using cscen bit of the Synchronous Mode Control register. This allows the connected slave to transmit data even when no data is transmitted by the master itself. -
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UM10503 NXP Semiconductors Chapter 37: LPC43xx USART0_2_3 Clock Next transfer or Asynchronous transfer First retry start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity NACK start bit0 extra extra extra guard1 guard2 guard1 guard2 guardn Fig 118. Smart card T = 0 waveform The smart card must be set up with the following considerations: 1. -
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UM10503 Chapter 38: LPC43xx UART1 Rev. 1.3 — 6 July 2012 User manual 38.1 How to read this chapter The UART1 controller is available on all LPC43xx parts. 38.2 Basic configuration The UART1 is configured as follows: • Table 846 for clocking and power control. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 The UART1 receiver block, RX, monitors the serial input line, RXD, for valid input. The UART1 RX Shift Register (RSR) accepts valid characters via RXD. After a valid character is assembled in the RSR, it is passed to the UART1 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Transmitter Transmitter Transmitter U1_TXD Transmitter Holding Shift FIFO Register Register Transmitter Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main PCLK Rate Divider Divider (DLM, DLL) UART1 interrupt FIFO Control & Status U1_CTS Interrupt... -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 38.5 Pin description Table 847: UART1 Pin description Direction Description function U1_RXD Input Serial Input. Serial receive data. U1_TXD Output Serial Output. Serial transmit data. U1_CTS Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD from the UART1. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 38.6 Register description UART1 contains registers organized as shown in Table 848. The Divisor Latch Access Bit (DLAB) is contained in LCR[7] and enables access to the Divisor Latches. Reset value reflects the data stored in used bits only. It does not include the content of reserved bits. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 38.6.1 UART1 Receiver Buffer Register (when DLAB = 0) The RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest”... -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 851: UART1 Divisor Latch LSB Register when DLAB = 1 (DLL - address 0x4008 2000) bit description Symbol Description Reset value DLLSB Divisor Latch LSB. 0x01 The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 853: UART1 Interrupt Enable Register when DLAB = 0 (IER - address 0x4008 2004) bit description Symbol Value Description Reset value CTSIE CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 854: UART1 Interrupt Identification Register (IIR - address 0x4008 2008) bit description Symbol Value Description Reset value ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 855: UART1 Interrupt Handling IIR[3:0] Priority Interrupt Interrupt Source Interrupt Reset value Type 1100 Second Character Minimum of one character in the RX FIFO and no RBR Read Time-out character input or removed during a time period depending... -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 856: UART1 FIFO Control Register (FCR - address 0x4008 2008) bit description Symbol Value Description Reset value RXFIFORES RX FIFO Reset. No impact on either of UART1 FIFOs. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 857: UART1 Line Control Register (LCR - address 0x4008 200C) bit description Symbol Value Description Reset value Word Length Select. 5-bit character length. 6-bit character length. 7-bit character length. 8-bit character length. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 858: UART1 Modem Control Register (MCR - address 0x4008 2010) bit description Symbol Value Description Reset value Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 859: UART1 Line Status Register (LSR - address 0x4008 2014) bit description Symbol Value Description Reset value Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 38.6.10 UART1 Modem Status Register The MSR is a read-only register that provides status information on the modem input signals. MSR[3:0] is cleared on MSR read. Note that modem signals have no direct effect on UART1 operation, they facilitate software implementation of modem signal operations. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 862: Autobaud Control Register (ACR - address 0x4008 2020) bit description Symbol Value Description Reset value START Auto-baud start bit. This bit is automatically cleared after auto-baud completion. Auto-baud stop (auto-baud is not running). -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 UART1 baud rate can be calculated as (n = 1): PCLK UART1 ------------------------------------------------------------------------------------------------------------------ baudrate DivAddVal ---------------------------- - MulVal Where PCLK is the peripheral clock, DLM and DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator specific parameters. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Table 864: UART1 Transmit Enable Register (TER - address 0x4008 2030) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 38.6.16 UART1 RS-485 Address Match register The RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 866. UART1 RS485 Address Match register (RS485ADRMATCH - address 0x4008 2050) bit description Symbol Description... -
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UM10503 NXP Semiconductors Chapter 38: LPC43xx UART1 Example: Suppose the UART1 operating in ‘550 mode has trigger level in FCR set to 0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the receive FIFO contains 8 bytes (Table 856 on page 990).
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