Download
Share
Print this page
NXP Semiconductors LPC11E Series User Manual
  1. Manuals
  2. Brands
  3. NXP Semiconductors Manuals
  4. Microcontrollers
  5. LPC11E Series
  6. User manual
NXP Semiconductors LPC11E Series User Manual

NXP Semiconductors LPC11E Series User Manual

Hide thumbs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424

Advertisement

Quick Links

Download this manual
UM10518
LPC11Exx User manual
Rev. 3.5 — 21 December 2016
Document information
Info
Content
Keywords
LPC11Exx, ARM Cortex-M0, microcontroller, LPC11E11, LPC11E12,
LPC11E14, LPC11E13, LPC11E3x, LPC11E37H, LPC11E35, I/O Handler.
Abstract
LPC11Exx User manual.
User manual

Advertisement

loading
Need help?

Need help?

Do you have a question about the LPC11E Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for NXP Semiconductors LPC11E Series

Summary of Contents for NXP Semiconductors LPC11E Series

  • Page 1 UM10518 LPC11Exx User manual Rev. 3.5 — 21 December 2016 User manual Document information Info Content Keywords LPC11Exx, ARM Cortex-M0, microcontroller, LPC11E11, LPC11E12, LPC11E14, LPC11E13, LPC11E3x, LPC11E37H, LPC11E35, I/O Handler. Abstract LPC11Exx User manual.
  • Page 2 Reserved function added to IOCON pin configuration registers PIO0_8 and PIO0_9. See Table 61 and Table 62. 20131125 LPC11Exx User manual UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 2 of 424...
  • Page 3 Chapter 7 “LPC11Exx I/O configuration”. • Parts LPC11E3x added. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 3 of 424...
  • Page 4 For sales office addresses, please send an email to: salesaddresses@nxp.com UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 4 of 424...

  • Page 5: Chapter 1: Lpc11Exx Introductory Information

    – Standard JTAG test interface for BSDL. – Serial Wire Debug. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 5 of 424...
  • Page 6 – Processor wake-up from Deep power-down mode using one special function pin. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 7 Available as LQFP64, LQFP48, HVQFN33 (7x7), and HVQFN33 (5x5) packages. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 7 of 424...

  • Page 8: Ordering Information

    This part includes I/O Handler; additional 2 kB of SRAM1 available for I/O Handler library only; see Table 3 “LPC11Exx memory configuration”. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 8 of 424...

  • Page 9: Block Diagram

    (2) CT16B0/1_CAP1, CT32B1_CAP1 available on the LQFP64 package only. CT32B0_CAP1 available on the LQFP64 and LQFP48 packages only. Fig 1. Block diagram UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 9 of 424...
  • Page 10 CT32B1_CAP1 available in LQFP64 packages only. (3) LPC11E37HFBD64/401 only. Fig 2. Block diagram UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 10 of 424...

  • Page 11: Table Of Contents

    Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 11 of 424...

  • Page 12: Chapter 2: Lpc11Exx Memory Mapping

    0x0000 0000 0 GB Fig 3. LPC11E1x memory map UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 12 of 424...
  • Page 13 0x0000 0000 0 GB 002aah405 Fig 4. LPC11E3x memory map UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 13 of 424...

  • Page 14: Chapter 3: Lpc11Exx System Control Block

    USART and SSP have individual clock dividers to derive peripheral clocks from the main clock. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 14 of 424...

  • Page 15: Register Description

    Table 6 are reserved and should not be written. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 15 of 424...
  • Page 16 0010 0010 NMISRC 0x174 NMI Source Control Table 32 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 16 of 424...

  • Page 17: System Memory Remap Register

    ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map (addresses 0x0000 0000 to 0x0000 0200). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 17 of 424...

  • Page 18: Peripheral Reset Control Register

    CPU. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 19: System Pll Status Register

    15 - 25 MHz frequency range 31:2 Reserved 0x00 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 19 of 424...

  • Page 20: Watchdog Oscillator Control Register

    4.2 MHz 4.4 MHz 4.6 MHz 31:9 Reserved 0x00 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 20 of 424...

  • Page 21: Internal Resonant Crystal Control Register

    3.5.10) must be toggled from LOW to HIGH for the update to take effect. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 22: System Pll Clock Source Update Register

    0 of this register, then write a one. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 23: System Clock Divider Register

    Enables clock for the main SRAM0 block at address range 0x1000 0000 to 0x1000 2000. Disable Enable UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 23 of 424...
  • Page 24 Enable Reserved WWDT Enables clock for WWDT. Disable Enable UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 24 of 424...

  • Page 25: Ssp0 Clock Divider Register

    This register configures the SSP0 peripheral clock SPI0_PCLK. SPI0_PCLK can be shut down by setting the DIV field to zero. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 25 of 424...

  • Page 26: Usart Clock Divider Register

    3.5.19) must be toggled from 0 to 1 for the update to take effect. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 26 of 424...

  • Page 27: Clkout Clock Source Update Enable Register

    GPIO pin. This register is a read-only status register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 28: Por Captured Pio Status Register 1

    Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 28 of 424...

  • Page 29: System Tick Counter Calibration Register

    50. For a description of the NMI functionality, see Section 23.3.3.2. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 29 of 424...

  • Page 30: Pin Interrupt Select Registers

    Reset value PINT0 Pin interrupt 0 wake-up Disabled Enabled UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 30 of 424...

  • Page 31: Interrupt Wake-Up Enable Register 1

    11:0 Reserved. WWDTINT WWDT interrupt wake-up Disabled Enabled UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 31 of 424...

  • Page 32: Deep-Sleep Mode Configuration Register

    This register controls the power configuration of the device when waking up from Deep-sleep or Power-down mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 32 of 424...

  • Page 33: Power Configuration Register

    Therefore, for the IRC a delay is possible before the power-down state takes effect. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 33 of 424...

  • Page 34: Device Id Register

    For LPC11E3x parts, see the ISP/IAP Read Part Id command (Table 311 “LPC11Exx device identification numbers”). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 34 of 424...

  • Page 35: Flash Memory Access

    1. The IRC starts up. After the IRC-start-up time (maximum of 6 s on power-up), the IRC provides a stable clock output. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 35 of 424...

  • Page 36: Start-Up Behavior

    NVIC or issues a reset, depending on the value of the BODRSTENA bit in the BOD control register (Table 29). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 36 of 424...

  • Page 37: Power Management

    Alternatively, the IRC may be selected and locked in WWDT MOD register, which forces the IRC on during Deep-sleep mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 37 of 424...

  • Page 38: Active Mode

    Analog and digital peripherals are selected as in Active mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 38 of 424...

  • Page 39: Programming Sleep Mode

    2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 39 of 424...

  • Page 40: Wake-Up From Deep-Sleep Mode

    Power-down mode in the PDSLEEPCFG UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 41: Power Configuration In Power-Down Mode

    BOD signal, if the BOD is enabled in the PDSLEEPCFG register: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 41 of 424...

  • Page 42: Deep Power-Down Mode

    5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. 6. Use the ARM WFI instruction. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 42 of 424...

  • Page 43: Wake-Up From Deep Power-Down Mode

    These clocks are either divided by 2´P by the programmable post divider to create the UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 44: Lock Detector

    The PLL frequency equations use the following parameters (also see Figure UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 44 of 424...

  • Page 45: Normal Mode

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 46: Chapter 4: Lpc11Exx Power Management Unit (Pmu)

    Deep power-down mode is blocked. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 46 of 424...

  • Page 47: General Purpose Registers 0 To 3

    Reserved. Do not write ones to this bit. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 47 of 424...

  • Page 48: Functional Description

    For details of entering and exiting reduced power modes, see Section 3.9. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 48 of 424...

  • Page 49: Chapter 5: Lpc11Exx Power Profiles

    Power Profiles API. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 49 of 424...

  • Page 50: Definitions

    The following elements have to be defined in an application that uses the power profiles: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 51: Clocking Routine

    #define CPU_FREQ_APPROX /* set_pll result0 options */ #define PLL_CMD_SUCCESS UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 51 of 424...

  • Page 52: Param0: System Pll Input Frequency And Param1: Expected System Clock

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 53: Code Examples

    PLL_FREQ_NOT_FOUND in result[0] and 12000 in result[1] without changing the PLL settings. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 53 of 424...

  • Page 54: Value

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 54 of 424...
  • Page 55 /* set_power result0 options */ #define PWR_CMD_SUCCESS #define PWR_INVALID_FREQ #define PWR_INVALID_MODE UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 55 of 424...

  • Page 56: Pwr_Default

    = 24; command[1] = PWR_CPU_EFFICIENCY; command[2] = 24; UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 56 of 424...
  • Page 57 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 57 of 424...

  • Page 58: Chapter 6: Lpc11Exx Nvic

    GPIO pin interrupt 6 PIN_INT7 GPIO pin interrupt 7 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 58 of 424...
  • Page 59 Reserved Reserved Reserved IOH interrupt I/O Handler interrupt UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 59 of 424...

  • Page 60: Register Description

    This register contains the 2-bit priority fields for interrupts 12 to 15. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 60 of 424...

  • Page 61: Interrupt Set Enable Register 0 Register

    ISE_CT32B1 Interrupt enable. ISE_SSP0 Interrupt enable. ISE_USART0 Interrupt enable. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 61 of 424...

  • Page 62: Interrupt Clear Enable Register 0

    ICE_CT16B1 Interrupt disable. ICE_CT32B0 Interrupt disable. ICE_CT32B1 Interrupt disable. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 62 of 424...

  • Page 63: Interrupt Set Pending Register 0 Register

    Reserved. ISP_SSP1 Interrupt pending set. ISP_I2C0 Interrupt pending set. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 63 of 424...

  • Page 64: Interrupt Clear Pending Register 0 Register

    ICP_GINT0 Interrupt pending clear. ICP_GINT1 Interrupt pending clear. Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 64 of 424...

  • Page 65: Interrupt Active Bit Register 0

    Interrupt active state. IAB_PININT6 Interrupt active state. IAB_PININT7 Interrupt active state. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 65 of 424...

  • Page 66: Interrupt Priority Register 0

    Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 66 of 424...

  • Page 67: Interrupt Priority Register 1

    Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 67 of 424...

  • Page 68: Interrupt Priority Register 4

    Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 68 of 424...

  • Page 69: Interrupt Priority Register 7

    Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 69 of 424...

  • Page 70: Chapter 7: Lpc11Exx I/O Configuration

    The IOCON registers control the function (GPIO or peripheral function) and the electrical characteristics of the port pins (see Figure 11). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 70 of 424...

  • Page 71: Pin Function

    The state retention is UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 72: Hysteresis

    GPIO pin. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 72 of 424...

  • Page 73: Reset Pin (Pin Reset_Pio0_0)

    Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 74: Register Description

    I/O configuration for pin 0x0000 0090 Table 87 PIO0_20/CT16B1_CAP0 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 74 of 424...
  • Page 75 I/O configuration for pin PIO1_22/RI/MOSI1 0x0000 0090 Table 113 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 75 of 424...

  • Page 76: I/O Configuration Registers

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 76 of 424...

  • Page 77: Pio0_1 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 77 of 424...

  • Page 78: Pio0_2 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 78 of 424...

  • Page 79: Pio0_4 Register

    Selects pin function. Values 0x3 to 0x7 are reserved. PIO0_5 (open-drain pin). I2C SDA (open-drain pin). IOH_3. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 79 of 424...

  • Page 80: Pio0_6 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 80 of 424...

  • Page 81: Pio0_7 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 81 of 424...

  • Page 82: Pio0_9 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 82 of 424...

  • Page 83: Swclk_Pio0_10 Register

    Remark: This is not a true open-drain mode. 31:11 - Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 83 of 424...

  • Page 84: Tdi_Pio0_11 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 84 of 424...

  • Page 85: Tms_Pio0_12 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 85 of 424...

  • Page 86: Pio0_13 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 86 of 424...

  • Page 87: Trst_Pio0_14 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 87 of 424...

  • Page 88: Swdio_Pio0_15 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 88 of 424...

  • Page 89: Pio0_16 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 89 of 424...

  • Page 90: Pio0_17 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 90 of 424...

  • Page 91: Pio0_19 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 91 of 424...

  • Page 92: Pio0_20 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 92 of 424...

  • Page 93: Pio0_21 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 93 of 424...

  • Page 94: Pio0_23 Register

    Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. Hysteresis. Disable. Enable. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 94 of 424...

  • Page 95: Pio1_0 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as RESERVED Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 95 of 424...

  • Page 96: Pio1_1 Register

    Input cannot be pulled up above VDD. 31:11 RESERVED Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 96 of 424...

  • Page 97: Pio1_2 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 97 of 424...

  • Page 98: Pio1_4 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as RESERVED Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 98 of 424...

  • Page 99: Pio1_5 Register

    Selects pin function. Values 0x2 to 0x7 are reserved. PIO1_6. IOH_16. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 99 of 424...

  • Page 100: Pio1_7 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 101: Pio1_8 Register

    Input cannot be pulled up above VDD. 31:11 RESERVED Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 101 of 424...

  • Page 102: Pio1_9 Register

    Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. Hysteresis. Disable. Enable. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 102 of 424...

  • Page 103: Pio1_11 Register

    Input cannot be pulled up above VDD. 31:11 RESERVED Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 103 of 424...

  • Page 104: Pio1_12 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 104 of 424...

  • Page 105: Pio1_14 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 105 of 424...

  • Page 106: Pio1_15 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 106 of 424...

  • Page 107: Pio1_16 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 107 of 424...

  • Page 108: Pio1_18 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as RESERVED Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 108 of 424...

  • Page 109: Pio1_19 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 109 of 424...

  • Page 110: Pio1_20 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 110 of 424...

  • Page 111: Pio1_22 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 111 of 424...

  • Page 112: Pio1_23 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 112 of 424...

  • Page 113: Pio1_24 Register

    Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. Hysteresis. Disable. Enable. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 113 of 424...

  • Page 114: Pio1_26 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 114 of 424...

  • Page 115: Pio1_27 Register

    Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 115 of 424...

  • Page 116: Pio1_29 Register

    Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 116 of 424...

  • Page 117: Pio1_31 Register

    Remark: This is not a true open-drain mode. 31:11 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 117 of 424...

  • Page 118: Chapter 8: Lpc11Exx Pin Configuration

    Transparent top view Fig 13. Pin configuration (HVQFN33, 7x7) UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 118 of 424...
  • Page 119 Transparent top view Fig 14. Pin configuration (HVQFN33, 5x5) UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 119 of 424...

  • Page 120: Lpc11E12Fbd48/201

    PIO1_26/CT32B0_MAT2/RXD PIO1_21/DCD/MISO1 PIO1_27/CT32B0_MAT3/TXD PIO1_31 Fig 15. Pin configuration (LQFP48) UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 120 of 424...

  • Page 121: See Table

    IOCON registers. All other functions must be programmed in the IOCON block before they can be used. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 121 of 424...
  • Page 122 I/O configuration register. IOH_3 — I/O Handler input/output 3. LPC11E37HFBD64/401 only. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 122 of 424...
  • Page 123 CT32B1_MAT0 — Match output 0 for 32-bit timer 1. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 123 of 424...
  • Page 124 CT16B1_MAT0 — Match output 0 for 16-bit timer 1. MOSI1 — Master Out Slave In for SSP1. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 124 of 424...
  • Page 125 PIO1_7 — General purpose digital input/output pin. IOH_17 — I/O Handler input/output 17. (LPC11E37HFBD64/401 only.) UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 125 of 424...
  • Page 126 DCD — Data Carrier Detect input for USART. MISO1 — Master In Slave Out for SSP1. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 126 of 424...
  • Page 127 Input voltage must not exceed 1.8 V. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 127 of 424...
  • Page 128 (grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 128 of 424...

  • Page 129: Chapter 9: Lpc11Exx Gpio

    Enabled interrupts can be logically combined through an OR or AND operation. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 130: Gpio Port Features

    33) and configure the level and edge sensitivity for each selected pin interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 131 GPIO grouped interrupt port 1 enable Table 142 register UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 131 of 424...
  • Page 132 “ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn may depend on an external source. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 132 of 424...

  • Page 133: Gpio Pin Interrupts Register Description

    If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 134: Pin Interrupt Level (Rising Edge Interrupt) Clear Register

    If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level interrupt (HIGH or LOW) is configured. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 134 of 424...

  • Page 135: Pin Interrupt Active Level (Falling Edge) Interrupt Set Register

    If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is selected. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 135 of 424...

  • Page 136: Pin Interrupt Rising Edge Register

    Write 1: clear falling edge detection for this pin. 31:8 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 136 of 424...

  • Page 137: Pin Interrupt Status Register

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 138: Gpio Grouped Interrupt Port Enable Registers

    1 = the port 1 pin is enabled and contributes to the grouped interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 138 of 424...

  • Page 139: Gpio Port Register Description

    0 will set the output bit. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 139 of 424...

  • Page 140: Gpio Port Direction Registers

    1 = Read MPORT: 0; write MPORT: output bit not affected. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 140 of 424...

  • Page 141: Gpio Port Pin Registers

    MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 141 of 424...

  • Page 142: Gpio Port Set Registers

    Output bits can be toggled/inverted/complemented by writing ones to these write-only registers, regardless of MASK registers. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 142 of 424...

  • Page 143: Functional Description

    Writing to a port’s PORT register loads the output bits of all the pins written to. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 144: Masked I/O

    The other pin interrupt registers play different roles for edge-sensitive and level-sensitive pins, as described in Table 161. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 144 of 424...

  • Page 145: Group Interrupts

    To make a decision based on multiple pins, read and mask a PORT register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 146: How To Read This Chapter

    Ring Indicator. (Not available on HVQFN33-pin packages). SCLK I/O Serial Clock. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 146 of 424...

  • Page 147: Register Description

    Smart Card Interface Control register. Enables and Table 186 configures the Smart Card Interface feature. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 147 of 424...
  • Page 148 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 149: Usart Receiver Buffer Register (When Dlab = 0, Read Only)

    DLL and DLM can be found in Section 10.5.14. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 149 of 424...

  • Page 150: Usart Interrupt Enable Register

    Disable end of auto-baud Interrupt. Enable end of auto-baud Interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 150 of 424...

  • Page 151: Only)

    Table 170. Given the status of IIR[3:0], an UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 151 of 424...
  • Page 152 Modem CTS, DSR, RI, or DCD. MSR Read Status UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 152 of 424...
  • Page 153 The value read from a reserved bit is not defined. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 153 of 424...

  • Page 154: Usart Fifo Control Register (Write Only) . 153 Usart Line Control Register

    Disable access to Divisor Latches. Enable access to Divisor Latches. 31:8 - Reserved UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 154 of 424...

  • Page 155: Usart Modem Control Register

    RTS until after it has begun sending the UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 156: Auto-Cts

    Delta DSR (MSR[3:1]) interrupt interrupt (IER[7]) (IER[3]) UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 156 of 424...

  • Page 157: Usart Line Status Register (Read-Only)

    Parity error status is inactive. Parity error status is active. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 157 of 424...
  • Page 158 TXRETRY field. 31:9 - Reserved UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 158 of 424...

  • Page 159: Usart Modem Status Register

    Reset Value A readable, writable byte. 0x00 31:8 - Reserved UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 159 of 424...

  • Page 160: Usart Auto-Baud Control Register

    ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 160 of 424...

  • Page 161: Auto-Baud Modes

    Mode = 1, the rate counter will stop on the next rising edge of the USART Rx pin. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 162: Irda Control Register

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 162 of 424...
  • Page 163 PCLK 128  T PCLK 256  T PCLK UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 163 of 424...

  • Page 164: Usart Fractional Divider Register

    If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 164 of 424...

  • Page 165: Baud Rate Calculation

    1.1% from the desired one. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 166 DLL = DL [7:0] Fig 20. Algorithm for setting USART dividers UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 166 of 424...

  • Page 167: Example 2: Uart_Pclk = 12.0 Mhz, Br = 115200

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 167 of 424...

  • Page 168: Usart Transmit Enable Register

    TXEn bit in order to achieve software flow control. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 169: Uart Half-Duplex Enable Register

    This register allows the USART to be used in asynchronous smart card applications. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 170: Usart Rs485 Control Register

    USART to set the parity error and generate an interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 170 of 424...

  • Page 171: Usart Rs-485 Address Match Register

    Any delay time from 0 to 255 bit times may be programmed. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 172 Send start and stop bits as in other modes. Do not send start/stop bits. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 172 of 424...
  • Page 173 SYNCCTRL register with CSCEN=1 and UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 174: Usart Synchronous Mode Control Register 172 Functional Description

    The receiver will also generate an Rx Data Ready Interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 175: Rs-485/Eia-485 Auto Direction Control

    Figure 21 shows a typical asynchronous smart card application. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 175 of 424...

  • Page 176: Smart Card Set-Up Procedure

    The smart card must be set up with the following considerations: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 176 of 424...

  • Page 177: Architecture

    Status information from the TX and RX is stored in the LSR. Control information for the TX and RX is stored in the LCR. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 177 of 424...
  • Page 178 PD[7:0] DDIS INTERFACE PCLK Fig 23. USART block diagram UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 178 of 424...

  • Page 179: Chapter 11: Lpc11Exx Ssp/Spi

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 180: Pin Description

    The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 180 of 424...

  • Page 181: Ssp/Spi Control Register 0

    This register controls the basic operation of the SSP/SPI controller. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 181 of 424...

  • Page 182: Ssp/Spi Control Register 1

    This register controls certain aspects of the operation of the SSP/SPI controller. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 183: Ssp/Spi Data Register

    0s. 31:16 - Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 183 of 424...

  • Page 184: Ssp/Spi Status Register

    This register controls whether each of the four possible interrupt conditions in the SPI controller are enabled. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 184 of 424...

  • Page 185: Ssp/Spi Raw Interrupt Status Register

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 186: Ssp/Spi Interrupt Clear Register

    4-wire Texas Instruments synchronous serial frame format supported by the SPI module. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 186 of 424...

  • Page 187: Spi Frame Format

    CLK pin when data is not being transferred. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 187 of 424...

  • Page 188: Spi Format With Cpol=0,Cpha=0

    The data is captured on the rising and propagated on the falling edges of the SCK signal. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 189: Spi Format With Cpol=0,Cpha=1

    Single and continuous transmission signal sequences for SPI format with CPOL=1, CPHA=0 are shown in Figure UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 189 of 424...
  • Page 190 SSEL pin is returned to its idle state one SCK period after the last bit has been captured. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 190 of 424...

  • Page 191: Spi Format With Cpol = 1,Cpha = 1

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 191 of 424...
  • Page 192 SSP/SPI. Each bit is driven onto SI line on the falling edge of SK. The SSP/SPI in UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 193: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode

    Fig 31. Microwire frame format setup and hold details UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 193 of 424...

  • Page 194: Chapter 12: Lpc11Exx I2C-Bus Controller

    (R/W), two types of data transfers are possible on the I C-bus: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 194 of 424...

  • Page 195: I 2 C Fast-Mode Plus

    Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I C-bus products which NXP Semiconductors is now providing. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 195 of 424...

  • Page 196: Pin Description

    General Call address. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 196 of 424...

  • Page 197: C Control Set Register (Conset)

    Assert acknowledge flag. C interrupt flag. STOP flag. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 197 of 424...
  • Page 198 SI must be reset by software, by writing a 1 to the SIC bit in the CONCLR register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 199: I 2 C Status Register (Stat)

    Reserved. The value read from a reserved bit is not defined. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 199 of 424...

  • Page 200: I 2 C Slave Address Register 0 (Adr0)

    C-bus rates based on I2C_PCLK frequency and SCLL and SCLH values. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 200 of 424...

  • Page 201: I 2 C Control Clear Register (Conclr)

    C bus without actually participating in traffic or interfering with the I C bus. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 201 of 424...

  • Page 202: Interrupt In Monitor Mode

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 202 of 424...

  • Page 203: Loss Of Arbitration In Monitor Mode

    ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of operation. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 203 of 424...

  • Page 204: C Mask Registers (Mask[0, 1, 2, 3])

    C-bus interface is implemented, and the following text describes the individual blocks. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 204 of 424...

  • Page 205: Input Filters And Output Stages

    C is a special pad designed to conform to the I C specification. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 205 of 424...

  • Page 206: Address Registers, Adr0 To Adr3

    C block generates no further clock pulses. Figure 34 shows the arbitration procedure. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 206 of 424...

  • Page 207: Serial Clock Generator

    C output clock frequency and duty cycle is programmable UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 207 of 424...

  • Page 208: Timing And Control

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 209: Master Receiver Mode

    (R/W) should be 1 to indicate a read. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 209 of 424...

  • Page 210: Slave Receiver Mode

    (W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 211: Slave Transmitter Mode

    C operating modes The four operating modes are: • Master Transmitter UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 211 of 424...

  • Page 212: Master Transmitter Mode

    STA, STO, and SI must be reset. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 212 of 424...
  • Page 213 C block may switch to the master receiver mode by loading DAT with SLA+R). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 213 of 424...
  • Page 214 A START condition will be transmitted when the bus becomes free. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 214 of 424...
  • Page 215 Fig 41. Format and states in the Master Transmitter mode UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 215 of 424...

  • Page 216: Master Receiver Mode

    C block may switch to the master transmitter mode by loading DAT with SLA+W. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 216 of 424...
  • Page 217 STO flag will be reset. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 217 of 424...
  • Page 218 Fig 42. Format and states in the Master Receiver mode UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 218 of 424...

  • Page 219: Slave Receiver Mode

    AA bit may be used to temporarily isolate the I C block from the I C-bus. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 219 of 424...
  • Page 220 Data byte will be received and ACK will received; ACK has be returned. been returned. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 220 of 424...
  • Page 221 ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 221 of 424...
  • Page 222 Fig 43. Format and states in the Slave Receiver mode UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 222 of 424...

  • Page 223: Slave Transmitter Mode

    I C block from the I C-bus. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 223 of 424...
  • Page 224 ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 224 of 424...

  • Page 225: Miscellaneous States

    To recover from a bus error, the STO flag must be set and SI must be cleared. This UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 226: Some Special Cases

    START condition (state 0x08), and a retry of the total serial data transfer can commence. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 226 of 424...

  • Page 227: Data Transfer After Loss Of Arbitration

    Fig 46. Forced access to a busy I C-bus UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 227 of 424...

  • Page 228: C-Bus Obstructed By A Low Level On Scl Or Sda

    The 26 state service routines providing support for all four I C operating modes. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 228 of 424...

  • Page 229: Initialization

    Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then initiating a START. 1. Initialize Master data counter. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 229 of 424...

  • Page 230: Start Master Receive Function

    3. Write 0x08 to CONCLR to clear the SI flag. 4. Set up Master Transmit mode data buffer. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 230 of 424...

  • Page 231: State: 0X10

    5. Load DAT with next data byte from Master Transmit buffer. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 231 of 424...

  • Page 232: State: 0X30

    3. Write 0x0C to CONCLR to clear the SI flag and the AA bit. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 233: State: 0X58

    2. Write 0x08 to CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 233 of 424...

  • Page 234: State: 0X78

    2. Write 0x0C to CONCLR to clear the SI flag and the AA bit. 3. Exit UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 234 of 424...

  • Page 235: State: 0X98

    1. Load DAT from Slave Transmit buffer with data byte. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 235 of 424...

  • Page 236: State: 0Xc0

    2. Write 0x08 to CONCLR to clear the SI flag. 3. Exit UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 236 of 424...

  • Page 237: How To Read This Chapter

    PWM outputs. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 237 of 424...

  • Page 238: Applications

    Table 230. More detailed descriptions follow. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 238 of 424...
  • Page 239 Reset value reflects the data stored in used bits only. It does not include reserved bits content. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 240 Table 248 the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 240 of 424...

  • Page 241: Interrupt Register

    The Timer Counter and Prescale Counter are enabled for counting. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 241 of 424...

  • Page 242: Timer Counter

    This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, ... UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 242 of 424...

  • Page 243: Match Control Register

    Reset on MR2: the TC will be reset if MR2 matches it. Enabled Disabled UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 243 of 424...

  • Page 244: Match Registers

    CT16B0 (bits 8:6, Table 239) and CT16B1 (bits 5:3, Table 240). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 244 of 424...
  • Page 245 CR0 to be loaded with the contents of TC. Enabled. Disabled. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 245 of 424...

  • Page 246: Capture Registers

    Reset value 15:0 Timer counter capture value. 31:16 Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 246 of 424...

  • Page 247: External Match Register

    Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 247 of 424...

  • Page 248: Count Control Register

    1:0 in the CTCR register, will the Timer Counter register be incremented. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 249 7:5 occurs. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 249 of 424...
  • Page 250 7:5 occurs. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 250 of 424...

  • Page 251: Pwm Control Register

    CT16Bn_MAT2 is controlled by EM2. PWM mode is enabled for CT16Bn_MAT2. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 251 of 424...

  • Page 252: Rules For Single Edge Controlled Pwm Outputs

    MAT2:0 enabled as PWM outputs by the PWMC register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 252 of 424...

  • Page 253: Example Timer Operation

    The block diagram for counter/timer0 and counter/timer1 is shown in Figure UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 253 of 424...
  • Page 254 TIMER CONTROL REGISTER PRESCALE REGISTER Fig 51. 16-bit counter/timer block diagram UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 254 of 424...

  • Page 255: How To Read This Chapter

    – Toggle on match. – Do nothing on match. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 255 of 424...

  • Page 256: Applications

    Table 251. More detailed descriptions follow. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 256 of 424...
  • Page 257 Reset value reflects the data stored in used bits only. It does not include reserved bits content. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 258 Reset value reflects the data stored in used bits only. It does not include reserved bits content. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 259: Interrupt Register

    The Timer Counter and Prescale Counter are enabled for counting. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 259 of 424...

  • Page 260: Timer Counter Registers

    (CT32B1)) bit description Symbol Description Reset value 31:0 Prescale counter value. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 260 of 424...

  • Page 261: Match Control Register

    Reset on MR3: the TC will be reset if MR3 matches it. Enabled Disabled UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 261 of 424...

  • Page 262: Match Registers

    Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt. Enabled. Disabled. Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 262 of 424...
  • Page 263 CR1 to be loaded with the contents of TC. Enabled. Disabled. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 263 of 424...

  • Page 264: Capture Registers

    (Section 14.7.13 “Rules for single edge controlled PWM outputs” on page 269). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 264 of 424...
  • Page 265 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 265 of 424...

  • Page 266: Count Control Register

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 266 of 424...
  • Page 267 The value read from a reserved bit is not defined. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 267 of 424...

  • Page 268: Pwm Control Register

    When a match occurs in any of the other match registers, the PWM output is set to UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 269: Rules For Single Edge Controlled Pwm Outputs

    HIGH continuously. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 269 of 424...

  • Page 270: Example Timer Operation

    Fig 53. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 271: Architecture

    The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in Figure UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 271 of 424...
  • Page 272 TIMER CONTROL REGISTER PRESCALE REGISTER Fig 55. 32-bit counter/timer block diagram UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 272 of 424...

  • Page 273: Chapter 15: Lpc11Exx Windowed Watchdog Timer (Wwdt)

    • Debug mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 273 of 424...

  • Page 274: Applications

    (PCLK - WDCLK) is not shown in the block diagram. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 274 of 424...

  • Page 275: Clocking And Power Control

    MOD register. The length of the delay depends on the selected watchdog clock WDCLK. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 275 of 424...

  • Page 276: Using The Wwdt Lock Features

    The reload overwrite lock mechanism can only be disabled by a reset of any type. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 277: Register Description

    Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 277 of 424...
  • Page 278 WWDT interrupt must be enabled in the STARTERP1 register in addition to the NVIC. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 279: Watchdog Timer Constant Register

    WDT before control is returned to the interrupted task. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 279 of 424...

  • Page 280: Watchdog Timer Value Register

    0, the interrupt will occur at the same time as the watchdog event. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 281: Watchdog Timer Warning Interrupt Register . 280 Watchdog Timer Window Register

    Fig 57. Early Watchdog Feed with Windowed Mode Enabled UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 281 of 424...
  • Page 282 = 0x3FF = 0x2000 Fig 59. Watchdog Warning Interrupt UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 282 of 424...

  • Page 283: Chapter 16: Lpc11Exx System Tick Timer

    10 millisecond interrupt for use by an operating system or other system management software. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 283 of 424...

  • Page 284: Register Description

    This register determines the clock source for the system tick timer. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 284 of 424...

  • Page 285: System Timer Reload Value Register

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 285 of 424...

  • Page 286: System Timer Calibration Value Register

    RELOAD = (system tick clock frequency  10 ms) 1 = (50 MHz  10 ms) 1 = 5000001 = 499999 = 0x0007A11F. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 286 of 424...

  • Page 287: How To Read This Chapter

    Input ; Reference voltage. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 287 of 424...

  • Page 288: Register Description

    Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 289: A/D Control Register (Cr - 0X4001 C000)

    Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 289 of 424...

  • Page 290: A/D Global Data Register (Gdr - 0X4001 C004)

    ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 290 of 424...

  • Page 291: A/D Interrupt Enable Register

    ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found in ADSTAT. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 291 of 424...

  • Page 292: A/D Status Register (Stat - 0X4001 C030) . 291 Operation

    (see also Section 7.3.7). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 292 of 424...

  • Page 293: Top 64 Byte Are Reserved For 4 Kb Eeprom

    The entire EEPROM is writable for smaller EEPROM sizes. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 293 of 424...

  • Page 294: Register Description

    18.5 Register description The EEPROM has no user-programmable register interface. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 294 of 424...

  • Page 295: How To Read This Chapter

    UART serial port. This can be done when the part resides in the end-user board. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 296: General Description

    A byte of ECC corresponds to every consecutive 128 bits of the user UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 297: Criterion For Valid User Code

    ISP session. The Unlock command is explained in Section 19.12 “ISP commands” on page 305. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 297 of 424...

  • Page 298: Isp/Iap Communication Protocol

    The boot block interrupt vectors located in the boot block of the flash are active after any reset. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 298 of 424...

  • Page 299: Interrupts During Iap

    128 bytes and grows downwards. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 300: Boot Process Flowchart

    (2) For details on available ISP commands based on the CRP settings, see Section 19.11. Fig 61. Boot process flowchart UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 300 of 424...

  • Page 301: Sector Numbers

    0x0000 F000 - 0x0000 FFFF 256-271 0x0001 0000 - 0x0001 0FFF no UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 301 of 424...

  • Page 302: Code Read Protection (Crp)

    Important: any CRP change becomes effective only after the device has gone through a power cycle. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 302 of 424...
  • Page 303 None None High None CRP1 High CRP1 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 303 of 424...

  • Page 304: Isp Entry Protection

    NO_ISP mode but disabled in CRP3 mode. The NO_ISP mode does not offer any code protection. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 304 of 424...

  • Page 305: Isp Commands

    "U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 305 of 424...

  • Page 306: Set Baud Rate

    "RESEND<CR><LF>". In response the host should retransmit the bytes. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 306 of 424...

  • Page 307: Read Memory

    This command makes flash write/erase operation a two step process. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 307 of 424...

  • Page 308: Copy Ram To Flash

    (assuming that those pages have been erased previously). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 308 of 424...

  • Page 309: Go

    This snippet will issue a system reset request to the core. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 309 of 424...

  • Page 310: Sector Number

    "E 2 3<CR><LF>" erases the flash sectors 2 and 3. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 310 of 424...

  • Page 311: Lpc11E11Fhn33/101

    LPC11E37FBD48/501 0x0000 7C41 LPC11E37HFBD64/401 0x0000 7C45 LPC11E37FBD64/501 0x0000 7C41 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 311 of 424...

  • Page 312: Return Code Cmd_Success

    This command is used to read the unique ID. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 312 of 424...

  • Page 313: Code_Read_Protection_Enabled

    The parameter table should be big enough to hold all the results in case the number of UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 314 The suggested parameter passing scheme reduces such risk. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 314 of 424...

  • Page 315: Prepare Sector(S) For Write Operation

    This command makes flash write/erase operation a two step process. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 315 of 424...

  • Page 316: Invalid_Sector

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 316 of 424...

  • Page 317: Erase Sector(S)

    This command is used to read the part identification number. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 317 of 424...

  • Page 318: Compare_Error

    PIO0_1 pin is not accessible to force the ISP mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 319: Readuid

    The entire EEPROM is writable for smaller EEPROM sizes. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 320: Invalid Command

    ARM Cortex-M0 vector table, which is the bottom of the boot ROM, the internal SRAM, or the flash memory respectively. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 320 of 424...

  • Page 321: Serial Wire Debug (Swd) Flash Programming Interface

    Bit 0 is fixed zero since only even addresses are allowed. 31:14 Reserved UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 321 of 424...

  • Page 322: Eeprom Bist Stop Address Register

    PARITY_SIG BIST 16-bit signature calculated from only the parity bits of the data bytes UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 322 of 424...

  • Page 323: Flash Controller Registers

    Setting the SIG_START bit is typically combined with the signature stop address in a single write. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 323 of 424...

  • Page 324: Signature Generation Result Registers

    Word 2 of 128-bit signature (bits 95 to 64). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 324 of 424...

  • Page 325: Flash Module Status Register

    A safe estimation for the duration of the signature generation is: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 326: Content Verification

    Fig 63. Algorithm for generating a 128-bit signature UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 326 of 424...

  • Page 327: How To Read This Chapter

    LPC11E1x. This pin is pulled up internally. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 327 of 424...

  • Page 328: Functional Description

    GPIO, but it should not be held LOW on power-up or reset. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 329: Boundary Scan

    Test-Logic Reset state. The first TCK clock while RESET = HIGH places the test TAP in Run-Test Idle mode. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 329 of 424...

  • Page 330: How To Read This Chapter

    Ptr to Device Table n Fig 65. Power profiles pointer structure UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 330 of 424...

  • Page 331: Examples

    The example C-code listing below shows how to perform a signed integer division via the ROM API. /* Divide (-99) by (+6) */ UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 331 of 424...

  • Page 332: Unsigned Division With Remainder

    /* result.quot contains (+24) */ /* result.rem contains (+3) */ UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 332 of 424...

  • Page 333: How To Read This Chapter

    All library examples make use of the I/O Handler hardware to extend the functionality of the part through software library calls (see http://www.LPCware.com). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 333 of 424...

  • Page 334: I/O Handler I S

    DMA transfers can be triggered by the source/target peripheral, software, counter/timer module CT16B1, or I/O Handler pin PIO1_6/IOH_16. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 334 of 424...

  • Page 335: Chapter 23: Lpc11Exx Appendix Arm Cortex-M0

    32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 335 of 424...

  • Page 336: System-Level Interface

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 336 of 424...

  • Page 337: Processor

    23.3.1.3 Core registers The processor core registers are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 337 of 424...

  • Page 338: General-Purpose Registers

    0 = Main Stack Pointer (MSP). This is the reset value. • 1 = Process Stack Pointer (PSP). UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 338 of 424...

  • Page 339: Link Register

    Reads of the EPSR bits return zero, and the processor ignores writes to the these bits UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...
  • Page 340 Table 23–347 for the EPSR attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 340 of 424...

  • Page 341: Exception Mask Register

    Table 23–347 for its attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 341 of 424...

  • Page 342: Exceptions And Interrupts

    Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device driver library. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 342 of 424...

  • Page 343: Memory Model

    The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 343 of 424...

  • Page 344: Memory Regions, Types And Attributes

    Device — The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 344 of 424...

  • Page 345: Memory System Ordering Of Memory Accesses

    The behavior of accesses to each region in the memory map is: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 346: Software Ordering Of Memory Accesses

    The following are examples of using memory barrier instructions: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 346 of 424...

  • Page 347: Memory Endianness

    Pending — The exception is waiting to be serviced by the processor. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 348: Exception Types

    HardFault 0x0000000C 4-10 Reserved SVCall Configurable 0x0000002C 12-13 Reserved UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 348 of 424...

  • Page 349: Exception Handlers

    Thumb code. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 349 of 424...

  • Page 350: Exception Priorities

    NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 350 of 424...

  • Page 351: Exception Entry And Return

    When one exception preempts another, the exceptions are nested. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 351 of 424...

  • Page 352: Exception Return

    PC it detects that the operation is a UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 353: Fault Handling

    NMI occurs and the current lockup is in the HardFault handler. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 354: Power Management

    SEV instruction, see Section 23–23.4.7.9. Software cannot access this register directly. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 354 of 424...

  • Page 355: Sleep-On-Exit

    Table 357 lists the supported instructions. Remark: In Table 357 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 355 of 424...
  • Page 356 Rn{!}, reglist Load Multiple registers, Section 23–23.4.4 increment after UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 356 of 424...
  • Page 357 Rn!, reglist Store Multiple registers, Section 23–23.4.4 increment after UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 357 of 424...

  • Page 358: Intrinsic Functions

    __REV16(uint32_t int value) REVSH uint32_t __REVSH(uint32_t int value) UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 358 of 424...

  • Page 359: About The Instruction Descriptions

    BL or BLX instruction writes the value of bit[0] into the LR it is automatically assigned the value 1. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 359 of 424...

  • Page 360: Shift Operations

    When the instruction is LSRS, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm. Remark: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 360 of 424...

  • Page 361: Lsl

    When the instruction is RORS the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm. Remark: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 361 of 424...

  • Page 362: Address Alignment

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 363: The Condition Flags

    C = 0 Lower, unsigned N = 1 Negative UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 363 of 424...

  • Page 364: Memory Access Instructions

    ADR generates an address by adding an immediate value to the PC, and writes the result to the destination register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 364 of 424...

  • Page 365: Restrictions

    In these instructions: • Rt and Rn must only specify R0-R7. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 365 of 424...

  • Page 366: Condition Flags

    The memory address to load from or store to is the sum of the values in the registers specified by Rn and Rm. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 366 of 424...

  • Page 367: Restrictions

    23.4.4.5 LDM and STM Load and Store Multiple registers. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 367 of 424...

  • Page 368: Syntax

    23.4.4.5.4 Condition flags These instructions do not change the flags. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 368 of 424...

  • Page 369: Examples

    23.4.4.6.4 Condition flags These instructions do not change the flags. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 369 of 424...

  • Page 370: Examples

    Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract. 23.4.5.1.1 Syntax ADCS {Rd,} Rn, Rm UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 370 of 424...

  • Page 371: Operation

    UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 371 of 424...

  • Page 372: Examples

    ANDS {Rd,} Rn, Rm ORRS {Rd,} Rn, Rm EORS {Rd,} Rn, Rm UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 372 of 424...

  • Page 373: Operation

    LSRS {Rd,} Rm, Rs LSRS {Rd,} Rm, #imm RORS {Rd,} Rm, Rs UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 373 of 424...

  • Page 374: Operation

    CMN Rn, Rm CMP Rn, #imm CMP Rn, Rm UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 374 of 424...

  • Page 375: Operation

    Section 23–23.4.3.6. Rd is the destination register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 375 of 424...

  • Page 376: Operation

    Rn, Rm are registers holding the values to be multiplied. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 376 of 424...

  • Page 377: Operation

    In these instructions, Rd, and Rn must only specify R0-R7. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 377 of 424...

  • Page 378: Condition Flags

    ; extend it, and write the result to R3 23.4.5.9 TST Test bits. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 378 of 424...

  • Page 379: Syntax

    23.4.6.1 B, BL, BX, and BLX Branch instructions. 23.4.6.1.1 Syntax B{cond} label BL label UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 379 of 424...

  • Page 380: Operation

    ; Branch with link (Call) to function funC, return address ; stored in LR UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 380 of 424...

  • Page 381: Miscellaneous Instructions

    0-255. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 381 of 424...

  • Page 382: Operation

    CPSIE i ; Enable interrupts (clear PRIMASK) 23.4.7.3 DMB Data Memory Barrier. 23.4.7.3.1 Syntax UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 382 of 424...

  • Page 383: Operation

    ISB are fetched from cache or memory again, after the ISB instruction has been completed. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 383 of 424...

  • Page 384: Restrictions

    MSR spec_reg, Rn where: Rn is the general-purpose source register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 384 of 424...

  • Page 385: Operation

    Section 23–23.3.5. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 385 of 424...

  • Page 386: Restrictions

    If the event register is 0, WFE suspends execution until one of the following events occurs: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 386 of 424...

  • Page 387: Restrictions

    23.4.7.12.4 Condition flags This instruction does not change the flags. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 387 of 424...

  • Page 388: Examples

    Section 23–23.5.2.5 0xE000E280 0x00000000 IPR0-7 Section 23–23.5.2.6 0xE000E400-0x 0x00000000 E000E41C UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 388 of 424...

  • Page 389: Accessing The Cortex-M0 Nvic Registers Using Cmsis

    Table 23–368 for the register attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 389 of 424...

  • Page 390: Interrupt Set-Pending Register

    Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 390 of 424...

  • Page 391: Interrupt Priority Registers

    A pulse interrupt is an interrupt signal sampled synchronously on the UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 392: Hardware And Software Control Of Interrupts 392 23.5.2.8 Nvic Usage Hints And Tips

    An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 392 of 424...

  • Page 393: Nvic Programming Hints

    See the register summary in for its attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016...

  • Page 394: Interrupt Control And State Register

    Table 23–376 for the ICSR attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 394 of 424...
  • Page 395 This bit is WO. On a register read its value is Unknown. [24:23] Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 395 of 424...

  • Page 396: Application Interrupt And Reset Control Register

    Data endianness implemented: 0 = Little-endian 1 = Big-endian. [14:3] Reserved UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 396 of 424...

  • Page 397: System Control Register

    Table 23–376 for the CCR attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 397 of 424...

  • Page 398: System Handler Priority Registers

    23.5.3.7.2 System Handler Priority Register 3 The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 398 of 424...

  • Page 399: Scb Usage Hints And Tips

    Returns 1 if timer counted to 0 since the last read of this register. [15:3] Reserved. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 399 of 424...

  • Page 400: Systick Reload Value Register

    Table 23–385 for its attributes. The bit assignments are: UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 400 of 424...

  • Page 401: Systick Usage Hints And Tips

    2. Clear current value. 3. Program Control and Status register. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 401 of 424...

  • Page 402: Cortex-M0 Instruction Summary

    Rotate Rotate right by register RORS Rd, Rd, Rs UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 402 of 424...
  • Page 403 MRS Rd, <specreg> Write special register MSR <specreg>, Rn UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 403 of 424...
  • Page 404 Excludes time spend waiting for an interrupt or event. Executes as NOP. UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 19 December 2016 404 of 424...

  • Page 405: Abbreviations

    LPC11E1x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11E1X.pdf LPC11E3x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11E3X.pdf UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 405 of 424...

  • Page 406: Legal Information

    NXP Semiconductors. applications and products. In no event shall NXP Semiconductors be liable for any indirect, incidental, NXP Semiconductors does not accept any liability related to any default, punitive, special or consequential damages (including - without limitation - lost...

  • Page 407: Tables

    Table 53. Interrupt clear enable register 0 (ICER0, address UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 407 of 424...
  • Page 408 40B0) bit description ....110 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 409 0x4005 C000 (GROUP0 INT) and Table 161. Pin interrupt registers for edge- and UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 409 of 424...
  • Page 410 Table 214. I C Slave Address registers (ADR[1, 2, 3]- UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 410 of 424...
  • Page 411 Table 243. Capture register 1 (CR1, address 0x4001 0030 Table 268. Count Control Register (CTCR, address UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 411 of 424...
  • Page 412 40C8) bit description ....325 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 413 Table 391. Abbreviations ......405 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...

  • Page 414: Figures

    C-bus... .227 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...

  • Page 415: Contents

    Power configuration register ....33 continued >> UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 415 of 424...
  • Page 416 SWDIO_PIO0_15 register ....88 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 417 Basic configuration ....146 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 418 12.7.9 C Data buffer register (DATA_BUFFER) . . 203 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 418 of 424...
  • Page 419 Applications......256 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 420 Flash content protection mechanism ..296 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 420 of 424...
  • Page 421 Description ......333 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 422 23.3.5.3 Power management programming hints..355 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016 422 of 424...
  • Page 423 23.4.7.9.2 Operation ......385 UM10518 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 3.5 — 21 December 2016...
  • Page 424 Disclaimers ......406 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com...

This manual is also suitable for:

Lpc11e35fhi33/501Lpc11e11fhn33/101Lpc11e12fbd48/201Lpc11e13fbd48/301Lpc11e14fhn33/401Lpc11e14fbd48/401 ... Show all