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NXP Semiconductors LPC29 Series User Manual

NXP Semiconductors LPC29 Series User Manual

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UM10316

LPC29xx User manual

Rev. 3 — 19 October 2010

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Keywords

LPC2917/01; LPC2919/01; LPC2926; LPC2927; LPC2929; LPC2921;

LPC2923; LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN,

USB

Abstract

This document extends the LPC29xx data sheets with additional details to

support both hardware and software development. It focuses on functional

description and typical application use.

User manual

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Summary of Contents for NXP Semiconductors LPC29 Series

Page 1 UM10316 LPC29xx User manual Rev. 3 — 19 October 2010 User manual Document information Info Content Keywords LPC2917/01; LPC2919/01; LPC2926; LPC2927; LPC2929; LPC2921; LPC2923; LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN, Abstract This document extends the LPC29xx data sheets with additional details to support both hardware and software development.
Page 2 UM10316 NXP Semiconductors LPC29xx User manual Revision history Date Description 20101019 • Modifications: Editorial updates to CGU, PMU, VIC, USB OTG, and Flash/EEPROM chapters. • Table 103 “LPC2930 boot configuration” added. • Part LPC2926 added. • Editorial updates. • Description of USBCmdCode register updated.
Page 3: Chapter 1: Lpc29Xx Introductory Information
UM10316 Chapter 1: LPC29xx Introductory information Rev. 3 — 19 October 2010 User manual 1. Introduction The LPC29xx combine an 125 MHz ARM968E-S CPU core, Full Speed USB 2.0 OTG and device, CAN and LIN, up to 56 kB SRAM, up to 768 kB flash memory, external memory interface, two or three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication.
Page 4 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information – Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO. – Two I C-bus interfaces. • Other peripherals: – Up to three ADCs: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range and one, 8-channel 10-bit ADC with 5.0 V measurement range provide a...
Page 5: Ordering Information
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information – CPU operating voltage: 1.8 V ± 5 %. – I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V. • Available in 100-pin,144-pin, and 208-pin LQFP packages.
Page 6: Ordering Options
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 4.1 Ordering options Table 2. LPC29xx part overview Part Flash SRAM LIN/ Pins UART I2C-bus Clkout number...
Page 7: Lpc29Xx Usb Options
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information 4.3 LPC29xx USB options Table 4. LPC29xx USB options Part On-chip controller Ports On-chip PHY Device Host LPC2917/01 LPC2919/01 LPC2921 Full-speed Device LPC2923 Full-speed Device LPC2925 Full-speed Device LPC2926 Full-speed Full-speed Device...
Page 8: Block Diagram
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information 5. Block diagram JTAG interface TEST/DEBUG LPC2917/01 INTERFACE LPC2919/01 ITCM DTCM 8 kB SRAM 16 kB 16 kB ARM968E-S 1 × master 2 × slave master slave VECTORED AHB TO DTL INTERRUPT...
Page 9 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2921/2923/2925 INTERFACE ITCM DTCM 8 kB SRAM 16 kB 16 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 10 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2926/27/2929 INTERFACE ITCM DTCM 8 kB SRAM 32 kB 32 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 11 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2930 INTERFACE ITCM DTCM 8 kB SRAM 32 kB 32 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 12 UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information JTAG interface TEST/DEBUG LPC2939 INTERFACE ITCM DTCM 8 kB SRAM 32 kB 32 kB ARM968E-S 1 master 2 slaves master GPDMA CONTROLLER master slave VECTORED slave AHB TO DTL INTERRUPT GPDMA REGISTERS...
Page 13: Functional Blocks
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information 6. Functional blocks This chapter gives an overview of the functional blocks, clock domains, and power modes. Table 1–2 for availability of peripherals and blocks for specific LPC29xx parts. The functional blocks are explained in detail in the following chapters. Several blocks are gathered into subsystems and one or more of these blocks and/or subsystems are put into a clock domain.
Page 14: Architectural Overview
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information Table 5. Functional blocks and clock domains …continued Short Description Comment Timer Dedicated Sampling and Control Timer Quadrature encoder interface Clock domain networking subsystem Gateway Includes acceptance filter Master controller LIN master controller...
Page 15: On-Chip Flash Memory System
UM10316 NXP Semiconductors Chapter 1: LPC29xx Introductory information Amongst the most compelling features of the ARM968E-S are: • Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces • Write buffers for the AHB and TCM buses Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed- •...
Page 16: Chapter 2: Lpc29Xx Memory Mapping
UM10316 Chapter 2: LPC29xx memory mapping Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The memory configuration varies for the different LPC29xx parts (see Table 2–6). In addition to the memory blocks, peripheral register blocks in memory region 7 are available only if the peripheral is implemented.
Page 17: Memory-Map Regions
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping 3. Memory-map regions The ARM9 processor has a 4 GB of address space. The LPC29xx has divided this memory space into eight regions of 512 MB each. Each region is used for a dedicated purpose.
Page 18 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC29xx 4 GB 0xFFFF FFFF 0xE00A 0000 PCR/VIC control 0xFFFF 8000 0xFFFF FFFF reserved 0xE008 B000 reserved 0xFFFF F000...
Page 19: Region 0: Tcm/Shadow Area
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping 3.1 Region 0: TCM/shadow area The ARM968E-S processor has its exception vectors located at address logic 0. Since flash is the only non-volatile memory available in the LPC29xx, the exception vectors in the flash must be located at address logic 0 at reset (AHB_RST).
Page 20: Region 1: Embedded Flash Area
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping After reset, the region 1 embedded flash area is always available at the shadow area. After booting, any other region of the AHB system memory map (e.g. internal SRAM) can be re-mapped to region 0 by means of the shadow memory mapping register. For more...
Page 21: Regions 5 And 6
UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping Region 4 is reserved for internal SRAM. The LPC29xx has two internal SRAM instances. Instance #0 is 32 kB, instance #1 is 16 kB. See Section 7–1. 3.6 Regions 5 and 6 Regions 5 and 6 are not used.
Page 22 UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping Note that the ARM stores the pre-fetch abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents the accidental aborts that could be caused by pre-fetches occurring when code is executed very near to a memory boundary.
Page 23 UM10316 NXP Semiconductors Chapter 2: LPC29xx memory mapping Table 10. Peripherals base-address overview …continued Base address Base name AHB peripherals 0xE004 A000 GPIO RegBase General-Purpose I/O 0 0xE004 B000 GPIO RegBase General-Purpose I/O 1 0xE004 C000 GPIO RegBase General-Purpose I/O 2...
Page 24: Chapter 3: Lpc29Xx Clock Generation Unit (Cgu)
UM10316 Chapter 3: LPC29xx Clock Generation Unit (CGU) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter This chapter describes the base clock generation for all LPC29xx parts. CGU0 is identical for all parts. CGU1 is configuration dependent. Table 11.
Page 25: Cgu0 Functional Description
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) BASE_ICLK0_CLK BASE_SYS_CLK BASE_USB_CLK BASE_ICLK1_CLK BASE_USB_I2C_CLK AHB MULTILAYER MATRIX BASE_OUT_CLK CLOCK AHB TO APB BRIDGES CGU1 BASE_IVNSS_CLK networking subsystem GPDMA branch CAN0/1 clocks FLASH/SRAM/SMC GLOBAL ACCEPTANCE USB REGISTERS FILTER branch clocks...
Page 26 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) • OSC1M (LP_OSC) – 1 MHz crystal oscillator • XO50M – up to 25 MHz oscillator • PL160M – PLL • FDIV0..6 – 7 Frequency Dividers • Output control The following clock output branches are generated (Table 3–12):...
Page 27 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) CLOCK GENERATION UNIT (CGU0) OUT 0 BASE_SAFE_CLK SAFE_CLK_CONF FDIV0 BASE_SYS_CLK OUT 1 400 kHz LP_OSC FDIV_CONF0 clkout SYS_CLK_ clkout120 EXTERNAL CONF OUT 2 BASE_PCR_CLK FDIV1 OSCLLLATOR clkout240 PLL_CONTROL PCR_CLK_CONF FDIV_CONF1...
Page 28: Controlling The Xo50M Oscillator (External Oscillator)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) OSC1M FDIV0..6 XO50M PLL160M clkout / clkout120 / clkout240 Output Control Clock outputs Fig 11. Structure of the clock generation scheme 3.1 Controlling the XO50M oscillator (external oscillator) The XO50M oscillator can be disabled using the ENABLE field in the oscillator control register.
Page 29 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) PSEL P23EN clkout120 / clkout240 Input clock / 2PDIV clkout Bypass Direct / MDIV MSEL Fig 12. PL160M PLL control mechanisms The PLL reference input clock is provided by the external oscillator (XO50M). The PLLs accept an input clock frequency in the range of 10 MHz to 25 MHz only.
Page 30: Controlling The Frequency Dividers
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 3.3 Controlling the frequency dividers The seven frequency dividers are controlled by the FDIV0..6 registers. The frequency divider divides the incoming clock by (L/D), where L and D are both 12-bit values, and attempts to produce a 50% duty-cycle.
Page 31: Clock Detection
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 3.7 Clock detection All of the clock sources have a clock detector, the status of which can be read in a CGU register. This register indicates which sources have been detected.
Page 32: Register Overview
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) CLOCK GENERATION UNIT (CGU1) OUT 0 BASE_USB_CLK clkout USB_CLK_CONF BASE_ICLK0_CLK clkout120 FDIV0 clkout240 BASE_ICLK1_CLK OUT 1 BASE_USB_I2C_CLK FDIV_CONF0 PLL_CONTROL USB_I2C_CLK_CONF OUT 2 BASE_OUT_CLK OUT_CLK_CONF CLOCK DETECTION FREQUENCY MONITOR AHB TO DTL BRIDGE...
Page 33 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 14. Register overview: CGU0 (CGU0 base address: 0xFFFF 8000) …continued Name Access Address Description Reset value Reference offset XTAL_OSC_STATUS 0x01C Crystal-oscillator status register 0x0000 0001 see Table 3–18 XTAL_OSC_CONTROL R/W...
Page 34 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 14. Register overview: CGU0 (CGU0 base address: 0xFFFF 8000) …continued Name Access Address Description Reset value Reference offset UART_CLK_CONF 0x098 Output-clock configuration register for 0x0000 0000 see Table 3–27...
Page 35: Frequency Monitor Register
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 15. Register overview: CGU1 (CGU1 base address: 0xFFFF B000) …continued Name Access Address Description Reset value Reference offset RDET 0x018 Clock detection register 0x0000 0FE3 see Table 3–17 PLL_STATUS...
Page 36: Clock Detection Register
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Remark: The clock selection in this register depends on whether the register is used for CGU0 or CGU1. In the CGU0, the low-power oscillator (LP_OSC) or the external crystal oscillator can be selected as input. In the CGU1, the two CGU0 base clocks BASE_ICLK0_CLK and BASE_ICLK1_CLK, can be selected instead.
Page 37 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 17. RDET register bit description (RDET, address 0xFFFF 8018 (CGU0) or 0xFFFF B018 (CGU1)) * = reset value Symbol Access Value Description 31 to 12 reserved Reserved FDIV6_PRESENT Activity-detection register for FDIV 6 (CGU0...
Page 38: Crystal-Oscillator Status Register (Cgu0)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 17. RDET register bit description (RDET, address 0xFFFF 8018 (CGU0) or 0xFFFF B018 (CGU1)) …continued * = reset value Symbol Access Value Description XTAL_PRESENT Activity-detection register for crystal (CGU0) or...
Page 39: Pll Status Register (Cgu0 And Cgu1)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 19. XTAL_OSC_CONTROL register bit description (XTAL_OSC_CONTROL, …continued address 0xFFFF 8020) * = reset value Symbol Access Value Description Oscillator HF pin Oscillator high-frequency mode (crystal or external clock source 15 to 25 MHz)
Page 40: Frequency Selection, Mode 1 (Normal Mode)
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) The feedback-divider division ratio is controlled by MSEL[4:0] in the PLL_CONTROL register. The division ratio between the PLL output clock and the input clock is the decimal value on MSEL[4:0] plus one.
Page 41 UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 21. PLL_CONTROL register bit description (PLL_CONTROL, address 0xFFFF 8028 (CGU0) and 0xFFFF B028 (CGU1)) …continued * = reset value Symbol Access Value Description 23 to 16 MSEL[4:0] Feedback-divider division ratio (M)
Page 42: Frequency Divider Status Register
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 5.7 Frequency divider status register There is one status register FDIV_STATUS_n for each frequency divider (n = 0..6 for CGU0). Note that there is only one frequency divider in the CGU1. The status bits reflect the inputs to the FDIV as driven from the control register Table 22.
Page 43: Output-Clock Status Register For Base_Safe_Clk And Base_Pcr_Clk
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 23. FDIV_CONF_n register bit description (FDIV_CONF_n, address 0xFFFF 8030/38/40/48/50/58/60 (CGU0) and FDIV_CONF_0, address 0xFFFF B028 (CGU1)) * = reset value Symbol Access Value Description 31 to 24 CLK_SEL Selected source clock for FDIV n...
Page 44: Output-Clock Status Register For Cgu0 Clocks
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 25. SAFE_CLK_CONF (address 0xFFFF 8068), PCR_CLK_CONF (address 0xFFFF 8078) register bit description * = reset value Symbol Access Value Description 31 to 24 CLK_SEL Selected source clock 0x0* LP_OSC...
Page 45: Output-Clock Status Register For Cgu1 Clocks
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 27. XX_CLK_CONF register bit description (XX = SYS (address 0xFFFF 8070), IVNSS (address 0xFFFF 8080), MSCSS (address 0xFFFF 8088), UART (address 0xFFFF 8098), SPI (address 0xFFFF 80A0), TMR (address 0xFFFF 80A8), ADC (address...
Page 46: Output-Clock Configuration Register For Cgu1 Clocks
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) 5.14 Output-clock configuration register for CGU1 clocks There is one configuration register for each CGU1 output clock generated. All output generators have the same register bits. The CGU1 output clock can be generated directly from the two CGU0 base clocks BASE_ICLK0_CLK and BASE_ICLK1_CLK or from the CGU1 PLL.
Page 47: Cgu0 Interrupt Bit Description
UM10316 NXP Semiconductors Chapter 3: LPC29xx Clock Generation Unit (CGU) Table 30. BUS_DISABLE register bit description (BUS_DISABLE, address 0xFFFF 8FF4 (CGU0) and 0xFFFF BFF4 (CGU1)) * = reset value Symbol Access Value Description 31 to 1 reserved Reserved; do not modify. Read as logic 0, write...
Page 48: How To Read This Chapter
UM10316 Chapter 4: LPC29xx Reset Generation Unit (RGU) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. The USB reset is not available on the LPC2917/19/01 parts. 2.
Page 49: Reset Hierarchy
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 32. Reset output configuration …continued Reset output Reset source Parts of the device reset when activated QEI_RST WARM_RST Quadrature encoder DMA_RST WARM_RST GPDMA controller USB_RST WARM_RST USB controller VIC_RST...
Page 50: Register Overview
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 33. Reset priority Priority Reset OSC1M GPIO Flash CFID Memory all other controller controllers peripherals (SRAM,SMC) RESET Cold Warm 4. Register overview Table 34. Register overview: RGU (base address: 0xFFFF 9000)
Page 51: Rgu Reset Control Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 34. Register overview: RGU (base address: 0xFFFF 9000) …continued Name Access Address Description Reset value Reference offset IVNSS_A2V_RST_SRC 0x4B8 Source register for IVNSS AHB2APB 0x0000 0040 see Table 4–47...
Page 52: Rgu Reset Status Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 36. RESET_CONTROL1 register bit description (RESET_CONTROL1, 0xFFFF 9104) …continued Symbol Access Value Description 27 to 25 reserved Reserved; do not modify. Write as logic 0 Activate USB_RST DMA_RST_CTRL Activate DMA_RST...
Page 53 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 37. RESET_STATUS0 register bit description (RESET_STATUS0, address 0xFFFF 9110) * = reset value Symbol Access Value Description 31 to 10 reserved Reserved; do not modify. Read as logic 0,...
Page 54 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 39. RESET_STATUS2 register bit description (RESET_STATUS2, address 0xFFFF 9118) * = reset value Symbol Access Value Description 31 and 30 IVNSS_CAN_RST_STAT Reset IVNSS CAN status No reset activated since RGU last...
Page 55 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 39. RESET_STATUS2 register bit description (RESET_STATUS2, address 0xFFFF 9118) …continued * = reset value Symbol Access Value Description 19 and 18 PESS_A2V_RST_STAT Reset PeSS AHB2APB status No reset activated since RGU last...
Page 56 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 39. RESET_STATUS2 register bit description (RESET_STATUS2, address 0xFFFF 9118) …continued * = reset value Symbol Access Value Description 1 and 0 SCU_RST_STAT Reset SCU status No reset activated since RGU last...
Page 57 UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 40. RESET_STATUS3 register bit description (RESET_STATUS3, address 0xFFFF 911C) …continued * = reset value Symbol Access Value Description 13 and 12 MSCSS_QEI_STAT Reset MSCSS QEI status No reset activated since RGU last...
Page 58: Rgu Reset Active Status Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 40. RESET_STATUS3 register bit description (RESET_STATUS3, address 0xFFFF 911C) …continued * = reset value Symbol Access Value Description 1 and 0 IVNSS_LIN_RST_STAT Reset IVNSS LIN status No reset activated since RGU last...
Page 59: Rgu Reset Source Registers
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 42. RST_ACTIVE_STATUS1 register bit description (RST_ACTIVE_STATUS1, address 0xFFFF 9154) …continued * = reset value Symbol Access Value Description SPI_RST_STAT Current state of SPI_RST TMR_RST_STAT Current state of TMR_RST UART_RST_STAT...
Page 60: Cold Reset
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) Table 44. PCR_RST_SRC register bit description (PCR_RST_SRC, address 0xFFFF 9408) * = reset value Symbol Access Value Description 31 to 4 reserved Reserved; do not modify. Read as logic 0...
Page 61: Rgu Bus-Disable Register
UM10316 NXP Semiconductors Chapter 4: LPC29xx Reset Generation Unit (RGU) 4.5 RGU bus-disable register The BUS_DISABLE register prevents any register in the CGU from being written to. Table 48. BUS_DISABLE register bit description (BUS_DISABLE, address 0xFFFF 9FF4) * = reset value...
Page 62: Chapter 5: Lpc29Xx Power Management Unit (Pmu)
UM10316 Chapter 5: LPC29xx Power Management Unit (PMU) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The implementation of some branch clocks for power control depends on the peripheral and memory configuration of each LPC29xx part, see Table 5–49.
Page 63 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. Branch clock overview …continued Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’...
Page 64: Pmu Clock-Branch Run Mode
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 50. Branch clock overview …continued Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’...
Page 65: Pmu Clock Branch Overview
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Clocks that have been programmed to enter sleep mode follow the chosen setting of the PD field in register PM. This means that with a single write-action all of these domains can be set either to sleep or to wake up.
Page 66 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 51. Register overview: PMU (base address: 0xFFFF A000) …continued Name Access Address Reset value Description Reference offset CLK_CFG_SMC 0x230 0x0000 0001 AHB clock to Static Memory Controller Table 5–54...
Page 67 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 51. Register overview: PMU (base address: 0xFFFF A000) …continued Name Access Address Reset value Description Reference offset CLK_STAT_GPIO5 0x28C 0x0000 0001 APB clock to General-Purpose I/O 5 Table 5–55...
Page 68 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 51. Register overview: PMU (base address: 0xFFFF A000) …continued Name Access Address Reset value Description Reference offset CLK_STAT_MSCSS_APB 0x504 0x0000 0001 APB clock to MSCSS module-status Table 5–55 register...
Page 69 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 51. Register overview: PMU (base address: 0xFFFF A000) …continued Name Access Address Reset value Description Reference offset CLK_CFG_UART0 0x700 0x0000 0001 IP clock to UART-0 configuration Table 5–54 register...
Page 70: Power Mode Register (Pm)
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 51. Register overview: PMU (base address: 0xFFFF A000) …continued Name Access Address Reset value Description Reference offset CLK_STAT_USB_CLK 0xD04 0x0000 0001 IP clock to USB CLK status register Table 5–55...
Page 71: Pmu Clock Configuration Register For Output Branches
UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) 4.3 PMU clock configuration register for output branches Each generated output clock from the PMU has a configuration register. Table 54. CLK_CFG_XXX register bit description (CLK_CFG_SAFE to CLK_CFG_USB_CLK, addresses 0xFFFF A100 to 0xFFFF AD00)
Page 72 UM10316 NXP Semiconductors Chapter 5: LPC29xx Power Management Unit (PMU) Table 55. CLK_STAT_XXX register bit description (CLK_STAT_SAFE to CLK_STAT_USB_CLK, addresses 0xFFFF A104 to 0xFFFF AD04) * = reset value Symbol Access Value Description 31 to 10 reserved Reserved; do not modify. Read as logic 0...
Page 73: Chapter 6: Lpc29Xx System Control Unit (Scu)
UM10316 Chapter 6: LPC29xx System Control Unit (SCU) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. See Table 6–56 for available GPIO pins for the port selection registers and for registers that are part specific. Table 56.
Page 74: Scu Port Function Select Registers
UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 57. Register overview: SCU (base address: 0xE000 1000) …continued Name Access Address Description Reset value Reference offset SFSP5_BASE R/W 0x500 Function-select port 5 base 0x0000 0000 Table 6–58 address...
Page 75 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 58. SCU port function select register overview (base address: 0xE000 1000 (port 0), 0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4), 0xE000 1500 (port 5)) Ports not pinned out are reserved;...
Page 76 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 58. SCU port function select register overview (base address: 0xE000 1000 (port 0), 0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4), 0xE000 1500 (port 5)) …continued...
Page 77 UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 59. SFSPn_m register bit description (base address: 0xE000 1000 (port 0), 0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4), 0xE000 1500 (port 5)) …continued...
Page 78: Functional Description
UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) Table 61. SFSP5_18 function select register bit description (SFSP_5_18, address 0xE000 1548) * = reset value Symbol Access Value Description 31:5 reserved VBUS USB mode port 1 in host or device...
Page 79: Jtag Security Registers
UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) SFSPx_y PAD_TYPE RESERVED FUNC_SEL Function 0 Function 1 Function 2 Function 3 Fig 15. Schematic representation of an I/O pin 3.2 JTAG security registers Table 62. Security disable register bit description (SEC_DIS, address 0xE000 1B00)
Page 80: Ahb Master Priority Registers
UM10316 NXP Semiconductors Chapter 6: LPC29xx System Control Unit (SCU) The SSMM0 register defines the memory mapping seen by the ARM CPU master, the SSMM1 and SSMM2 register defines the memory mapping for the DMA0 and DMA1 masters, and the SSMM3 register for the USB master.
Page 81: Chapter 7: Lpc29Xx Chip Feature Id (Cfid)
UM10316 Chapter 7: LPC29xx Chip Feature ID (CFID) Rev. 3 — 19 October 2010 User manual 1. Introduction The CFID module contains registers that show the functionality of the chip. It contains an ID to identify the silicon and four registers containing information about the features enabled or disabled for each part in the LPC29xx series.
Page 82 UM10316 NXP Semiconductors Chapter 7: LPC29xx Chip Feature ID (CFID) Table 68. FEAT3 register bit description (FEAT3, address 0xE000 010C) Symbol Access Value Description JTAGSEC The setting of this bit is determined by the setting of the JTAG security in the flash index sector (see Section 28–2.6.3).
Page 83: Chapter 8: Lpc29Xx Event Router
UM10316 Chapter 8: LPC29xx event router Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Not all event sources are connected to pins. Table 8–69 shows the event router connections for each LPC29xx part.
Page 84: Event Router Pin Connections
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Input events are processed in event slices; one for each event signal. Each of these slices generates one event signal and is visible in the RSR (Raw Status Register). These events are then AND-ed with enables from the MASK register to give PEND (PENDing register) event status.
Page 85: Register Overview
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 70. Event-router pin connections …continued Symbol Direction Bit position Description Default polarity UART1 RXD UART1 receive data input USB_I2C_SCL IN USB I C serial clock CAN interrupt (internal) VIC FIQ (internal)
Page 86: Event-Status Clear Register
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 72. PEND register bit description (address 0xE000 2C00) * = reset value Symbol Access Value Description PEND[0] An event has occurred on a corresponding pin or logic 1 is written to bit 0 in the INT_SET...
Page 87: Event-Enable Clear Register
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 75. MASK register bit description (address 0xE000 2C60) * = reset value Symbol Access Value Description 31 to 27 reserved Reserved; do not modify. Read as logic 0 MASK[26] Event enable...
Page 88: Activation Polarity Register
UM10316 NXP Semiconductors Chapter 8: LPC29xx event router 3.7 Activation polarity register The APR is used to configure which level is the active state for the event source. Table 8–78 shows the bit assignment of the APR register. Table 78.
Page 89 UM10316 NXP Semiconductors Chapter 8: LPC29xx event router Table 80. RSR register bit description (address 0xE000 2D20) Symbol Access Value Description 31 to 27 reserved Reserved; do not modify. Read as logic 0 RSR[26] Corresponding event has occurred Corresponding event has not occurred...
Page 90: Chapter 9: Lpc29Xx Vectored Interrupt Controller (Vic)
UM10316 Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. See Table 9–81 for interrupt requests that are configuration dependent. All other interrupt requests are available in all LPC29xx parts (see Table 9–88).
Page 91 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) • The IRQ exception has a lower priority than FIQ and is masked out when an FIQ exception occurs. IRQ service routines should take care of saving and/or restoring the used registers themselves.
Page 92: Non-Nested Interrupt Service Routine
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) If the level-sensitive interrupt request line of the VIC is enabled (depending on the polarity setting), the request is forwarded to the interrupt selection. The interrupt selection part selects the interrupt request line with the highest priority, based on the target and priority of the interrupt request and priority masks.
Page 93: Register Overview
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) 4. Register overview Table 82. Register overview: Vectored Interrupt Controller (base address: 0xFFFF F000) Name Access Address Description Reset value Reference INT_PRIORITYMASK_0 0x000 Target 0 priority-mask register Table 9–83 INT_PRIORITYMASK_1...
Page 94 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 82. Register overview: Vectored Interrupt Controller (base address: 0xFFFF F000) …continued Name Access Address Description Reset value Reference INT_REQUEST_16 0x440 Interrupt Request 16 control register Table 9–89 INT_REQUEST_17 0x444 Interrupt Request 17 control register Table 9–89...
Page 95: Interrupt Priority Mask Register
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 82. Register overview: Vectored Interrupt Controller (base address: 0xFFFF F000) …continued Name Access Address Description Reset value Reference INT_REQUEST_39 0x49C Interrupt Request 39 control register Table 9–89 INT_REQUEST_40 0x4A0 Interrupt Request 40 control register Table 9–89...
Page 96: Interrupt Vector Register
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 83. INT_PRIORITYMASK_n registers bit description (INT_PRIORITYMASK_0/1, addresses 0xFFFF F000 and 0xFFFF F004) Symbol Access Reset Description value 31 to 4 reserved Reserved; do not modify. Read as logic 3 to 0 PRIORITY_LIMITER[3:0] Priority limiter.
Page 97: Interrupt-Pending Register 1
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Interrupt service routine 2 Entry point Interrupt service routine 1 Index Priority limiter 2 010h Vector 2 Entry point Pointer 00Ch Priority limiter 1 008h Vector 1 "no interrupt" handler...
Page 98: Interrupt-Pending Register 2
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) The INT_PENDING_1_31 register is read-only. Table 9–85 shows the bit assignment of the INT_PENDING_1_31 register. Table 85. INT_PENDING_1_31 register bit description (INT_PENDING_1_31, address 0xFFFF F200) Symbol Access Value Description PENDING[31]...
Page 99: Interrupt Request Register
UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 87. INT_FEATURES register bit description (INT_FEATURES, address 0xFFFF F300) * = reset value Symbol Access Value Description 0Fh* 7 to 0 Number of interrupt requests 3Fh* 4.6 Interrupt request register...
Page 100 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 88. Interrupt source and request reference …continued Interrupt Interrupt source Description request I2C1 C interrupt from I C1 (SI state change) GPDMA GPDMA DMA err GPDMA DMA tc all CAN controllers...
Page 101 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 89. INT_REQUESTn register bit description (INT_REQUEST1 to 56, addresses 0xFFFF F404 to 0xFFFF F4E0). * = reset value Symbol Access Value Description PENDING Pending interrupt request. This reflects the state of the interrupt source channel.
Page 102 UM10316 NXP Semiconductors Chapter 9: LPC29xx Vectored Interrupt Controller (VIC) Table 89. INT_REQUESTn register bit description (INT_REQUEST1 to 56, addresses 0xFFFF F404 to 0xFFFF F4E0). * = reset value Symbol Access Value Description ACTIVE_LOW Active-LOW interrupt line. This selects the polarity of the interrupt request line.
Page 103: Chapter 10: Lpc29Xx General System Control
UM10316 Chapter 10: LPC29xx general system control Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction This chapter contains power control, interrupt, and wake-up features that pertain to various functions and peripherals on the LPC29xx.
Page 104: Reset And Power-Up Behavior
UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control Setting the power mode and configuring the clock domains is handled by the CGU, see Section 3–3. Configuration of wake-up events is handled by the Event Router, see Section 8–2. 4. Reset and power-up behavior The LPC29xx contains external reset input and internal power-up reset circuits.
Page 105: Interrupt Device Architecture
UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control UART Interrupt Requests Fig 22. Interrupt (UART) causing an IRQ Event Router Events Interrupt Requests Fig 23. Event causing an IRQ 6. Interrupt device architecture In the LPC29xx a general approach is taken to generate interrupt requests towards the CPU.
Page 106: Interrupt Registers
UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control Interrupt Request >1 & STATUS ENABLE >1 Event CLEAR CLEAR STATUS STATUS ENABLE ENABLE Control Interface Fig 24. Interrupt device architecture A set of software-accessible variables is provided for each interrupt source to control and observe interrupt request generation.
Page 107: Interrupt Clear-Enable Register
UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control 6.1.1 Interrupt clear-enable register Write ‘1’ actions to this register set one or more ENABLE variables in the INT_ENABLE register. INT_SET_ENABLE is write-only. Writing a 0 has no effect. Table 91.
Page 108: Interrupt Set-Status Register
UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control Table 95. INT_CLR_STATUS register bit description Variable Name Access Value Description CLR_STATUS[i] Clears STATUS[i] variable in INT_STATUS register (set to 0) 6.1.6 Interrupt set-status register Write ‘1’ actions to this register set one or more STATUS variables in the INT_STATUS register.
Page 109: Wake-Up
UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control – Initialization of the interrupt functionality (outside the scope of this driver) – Installation of the event-dispatcher interrupt function – Initialization of the ESR driver • Installation of the ESR: – Configure the signal specifications for external interrupts With this API the edge/level sensitivity can be programmed –...
Page 110 UM10316 NXP Semiconductors Chapter 10: LPC29xx general system control wake-up Event UART Router Events Interrupt Requests Fig 26. Event causing a wake-up UM10316 © NXP B.V. 2010. All rights reserved. User manual Rev. 3 — 19 October 2010 110 of 566...
Page 111: How To Read This Chapter
UM10316 Chapter 11: LPC29xx pin configuration Rev. 3 — 19 October 2010 User manual 1. How to read this chapter Table 11–97 for pin configurations of all LPC29xx parts. Table 97. Feature overview Part Pins Pin configuration Pin assignment LPC2917/19/01 Figure 11–27 Table 11–98 LPC2921/23/25...
Page 112 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 98. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P0[26]/TXD1/ GPIO 0, pin 26 UART1 TXD SPI2 SDI SDI2 P0[27]/RXD1/ GPIO 0, pin 27...
Page 113 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 98. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P2[27]/CAP0[3]/ GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7 MAT0[3]/EI7 P1[27]/CAP1[2]/ GPIO 1, pin 27...
Page 114 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 98. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P1[14]/CAP2[0]/ GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0 SCS0[3]/D0 P1[13]/SCL1/ GPIO 1, pin 13...
Page 115 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 98. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 1.8 V supply for oscillator DD(OSC) ground for PLL SS(PLL) [1][4] P2[7]/MAT1[3]/ GPIO 2, pin 7...
Page 116 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 98. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P2[13]/ GPIO 2, pin 13 PWM0 MAT5 SPI0 SDO PMAT0[5]/ SDO0 P0[4]/PMAT0[2]/ GPIO 0, pin 4...
Page 117 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 98. LPC2917/19/01 LQFP144 pin assignment …continued Pin name Description Default function Function 1 Function 2 Function 3 P0[17]/IN2[1]/ GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23 RXD0/A23 1.8 V power supply for digital core...
Page 118: Lpc2921/23/25 Pin Configuration
UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration 3. LPC2921/23/25 pin configuration LPC2921FBD100 LPC2923FBD100 LPC2925FBD100 002aae242 Fig 28. Pin configuration for SOT407-1 (LQFP100) The LPC2921/23/25 uses three ports: port 1 with 32 pins, port 1 with 28 pins, and port 5 with 2 pins.
Page 119 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 99. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 P1[27]/CAP1[2]/ GPIO 1, pin 27 TIMER1 CAP2, PWM TRAP2 PWM3 MAT3 TRAP2/PMAT3[3] ADC2 EXT START...
Page 120 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 99. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 P1[8]/SCS1[0]/ GPIO 1, pin 8 SPI1 SCS0 TXDL1/CS0 P1[7]/SCS1[3]/RXD1 GPIO 1, pin 7...
Page 121 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 99. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 VREFN LOW reference for ADC P0[8]/IN1[0] GPIO 0, pin 8 ADC1 IN0 P0[9]/IN1[1]...
Page 122: Lpc2927/29 Pin Configuration
UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 99. LPC2921/23/25 LQFP100 pin assignment …continued Pin name Description Function 0 (default) Function 1 Function 2 Function 3 P0[23]/IN2[7]/ GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 PMAT2[5]/A19 IEEE 1149.1 data in, pulled up internally Bidirectional Pad;...
Page 123 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LQFP144 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P0[29]/CAP0[1]/ GPIO 0, pin 29 TIMER0 CAP1 TIMER0 MAT1 MAT0[1] 3.3 V power supply for I/O...
Page 124 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LQFP144 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P1[24]/PMAT0[0]/ GPIO 1, pin 24 PWM0 MAT0 USB_CONNECT PWM3 MAT0 USB_CONNECT/ PMAT3[0] P1[23]/RXD0/ GPIO 1, pin 23...
Page 125 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LQFP144 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P1[11]/SCK1/ GPIO 1, pin 11 SPI1 SCK I2C0 SCL EXTBUS CS3 SCL0/CS3 P1[10]/SDI1/ GPIO 1, pin 10...
Page 126 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LQFP144 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P2[8]/CLK_OUT/ GPIO 2, pin 8 CLK_OUT PWM0 MAT0 SPI0 SCS2 PMAT0[0]/SCS0[2] P2[9]/ GPIO 2, pin 9...
Page 127 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LQFP144 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P0[7]/IN0[3]/ GPIO 0, pin 7 ADC0 IN3 PWM0 MAT5 EXTBUS D31 PMAT0[5]/D31 3.3 V power supply for ADC...
Page 128 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 100. LQFP144 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P2[17]/RXD1/ GPIO 2, pin 17 UART1 RXD PWM1 CAP0 EXTBUS BLS3 PCAP1[0]/BLS3 3.3 V power supply for I/O...
Page 129: Lpc2930/30 Pin Configuration
UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration 5. LPC2930/30 pin configuration LPC2939FBD208 002aae253 Fig 30. Pin configuration for LQFP208 package The LPC2930/29 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each, port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins.
Page 130 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P0[31]/CAP0[3]/ GPIO 0, pin 31 TIMER0 CAP3 TIMER0 MAT3 MAT0[3] P2[24]/SCS1[1]/ GPIO 2, pin 24...
Page 131 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P1[26]/PMAT2[0]/ GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2 TRAP3/PMAT3[2] P4[20]/...
Page 132 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P3[10]/SDI2/ GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 USB_PWRD1 PMAT1[4]/ USB_PWRD1 ground for core SS(CORE) 1.8 V power supply for digital core...
Page 133 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) ground for I/O SS(IO) P1[8]/SCS1[0]/ GPIO 1, pin 8 SPI1 SCS0 LIN1 TXD/ UART TXD EXTBUS CS0...
Page 134 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P2[11]/USB_RST1/ GPIO 2, pin 11 USB_RST1 PWM0 MAT3 SPI0 SCK PMAT0[3]/SCK0 P0[0]/PHB0/ GPIO 0, pin 0...
Page 135 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) 3.3 V power supply for I/O DD(IO) P0[6]/IN0[2]/ GPIO 0, pin 6 ADC0 IN2...
Page 136 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) P5[11]/D23/DCD0 GPIO 5, pin 11 EXTBUS D23 UART0 DCD P0[15]/IN1[7]/ GPIO 0, pin 15...
Page 137: Lpc2930 Boot Control
UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 101. LPC2930/39 LQFP208 pin assignment …continued Pin name Description Function 0 Function 1 Function 2 Function 3 (default) ground for I/O SS(IO) P0[23]/IN2[7]/ GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5...
Page 138 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration For booting from external memory, connect the pins as shown in Table 11–103 to the external memory device. Table 103. LPC2930 boot configuration LPC2930 connections External memory connections Port Function 8-bit 16-bit...
Page 139 UM10316 NXP Semiconductors Chapter 11: LPC29xx pin configuration Table 103. LPC2930 boot configuration LPC2930 connections External memory connections Port Function 8-bit 16-bit 32- bit P1[21] P5[0] P5[1] P5[2] P5[3] P2[4] P2[5] P2[6] P2[7] P5[4] P5[5] P5[6 P5[7] P5[8] P5[9] P5[10]...
Page 140: Chapter 12: Lpc29Xx External Static Memory Controller (Smc)
UM10316 Chapter 12: LPC29xx external Static Memory Controller (SMC) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to parts LPC2917/19/01, LPC2926/27/29, LPC2930, and LPC2939. The LPC2921/23/25 do not have an external static memory controller. The flashless LPC2930 uses the external SMC for booting (see Section 11–6).
Page 141: External Memory Interface
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) 3. External memory interface The external memory interface depends on the bank width: 32, 16 or 8 bits selected via MW bits in the corresponding SMBCR register. Choice of memory chips requires an adequate set-up of the RBLE bit in the same register.
Page 142 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CS0 .. CS n OE_N WE_N BLS3 BLS1 BLS2 BLS0 D[31:16] D[15:0] IO[15:0] IO[15:0] A[x:0] A[x:0] A[x+2:2] 32-bit bank using 16-bit devices Fig 33. External memory interface: 32-bit banks with 16-bit devices CS0 ..
Page 143 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CS0 .. CS n OE_N BLS1 BLS0 D[15:8] D[7:0] IO[7:0] IO[7:0] A[x:0] A[x:0] A[x+1:1] 16-bit bank using 8-bit devices Fig 35. External memory interface: 16-bit banks with 8-bit devices CS0 ..
Page 144 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CS0 .. CS n OE_N BLS0 D[7:0] IO[7:0] A[x:0] A[x:0] 8-bit bank using 8-bit device Fig 37. External memory interface: 8-bit banks with 8-bit devices Memory is available in various speeds, so the numbers of wait-states for both read and write access must be set up.
Page 145 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CLK(SYS) WE/BLS WST2 WSTWEN 002aae705 WSTWEN=3, WST2=7 (1) BLS has the same timing as WE in configurations that use the byte lane enable signals to connect to write enable (8 bit devices).
Page 146: Register Overview
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) CLK(SYS) WST1 WST2 WSTWEN IDCY WSTOEN 002aae706 WSTOEN=2, WSTWEN=4, WST1=6, WST2=4, IDCY=5 Fig 40. Reading/writing external memory Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed to the correct function.
Page 147 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 105. Register overview: external SMC (base address 0x6000 0000) …continued Symbol Access Offset Description Reset Reference Address value SMBWSTOENR1 0x028 Output-enable assertion delay control register for Table 12–109...
Page 148: Bank Idle-Cycle Control Registers
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 105. Register overview: external SMC (base address 0x6000 0000) …continued Symbol Access Offset Description Reset Reference Address value SMBWSTWENR5 0x09C Write-enable assertion delay control register for Table 12–110...
Page 149: Bank Wait-State 1 Control Registers
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 106. SMBIDCYRn register bit description (SMBIDCYR0 to 7, addresses 0x6000 0000, 0x6000 001C, 0x6000 0038, 0x6000 0054, 0x6000 0070, 0x6000 008C, 0x6000 00A8, 0x6000 00C4) * = reset value...
Page 150: Bank Output Enable Assertion-Delay Control Register
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Sequential-access burst-reads from burst-flash devices of the same type as for burst ROM are supported. Due to sharing of the SMBWST2R register between write and burst- read transfers it is only possible to have one setting at a time for burst flash; either write delay or the burst-read delay.
Page 151: Bank Write-Enable Assertion-Delay Control Register 151 Bank Configuration Register
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) Table 109. SMBWSTOENRn register bit description (SMBWSTOENR0 to SMBWSTOENR7, addresses 0x6000 000C, 0x6000 0028, 0x6000 0044, 0x6000 0060, 0x6000 007C, 0x6000 0098, 0x6000 00B4, 0x6000 00D0) * = reset value...
Page 152 UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) A data transfer can be initiated to the external memory greater than the width of the external-memory data bus. In this case the external transfer is automatically split up into several separate transfers.
Page 153: Bank Status Register
UM10316 NXP Semiconductors Chapter 12: LPC29xx external Static Memory Controller (SMC) 4.7 Bank status register The bank status register reflects the status flags of each memory bank. Table 12–112 shows the bit assignment of the SMBSR0 to SMBSR7 registers. Table 112. SMBSRn register bit description (SMBSR0 toSMBSR7, addresses 0x6000 0018,...
Page 154: Chapter 13: Lpc29Xx Usb Device
UM10316 Chapter 13: LPC29xx USB device Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The USB device controller is used in parts LPC2921/23/25, LPC2926/27/29, LPC2930, and LPC2939. The LPC2917/19/01 do not have an USB controller (see also Table 1–4).
Page 155: Features
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 113. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description Random Access Memory Start-Of-Frame Serial Interface Engine SRAM Synchronous RAM UDCA USB Device Communication Area Universal Serial Bus 3.
Page 156: Functional Description
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 114. Fixed endpoint configuration Logical Physical Endpoint type Direction Packet size (bytes) Double buffer endpoint endpoint Isochronous 1 to 1023 Interrupt 1 to 64 Interrupt 1 to 64 Bulk 8, 16, 32, 64...
Page 157: Analog Transceiver
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 5.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional D+ and D- signals of the USB bus. 5.2 Serial Interface Engine (SIE) The SIE implements the full USB protocol layer.
Page 158: Goodlink
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 5.8 GoodLink Good USB connection indication is provided through GoodLink technology. When the device is successfully enumerated and configured, the LED indicator will be permanently ON. During suspend, the LED will be OFF.
Page 159: Clocking And Power Management
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 8. Clocking and power management This section describes the clocking and power management features of the USB Device Controller. 8.1 Power requirements The USB protocol insists on power management by the device. This becomes very critical if the device draws power from the bus (bus-powered device).
Page 160: Remote Wake-Up
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is set. When the device controller is not in use, all of the device controller clocks may be disabled by clearing PCUSB.
Page 161 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 117. Register overview: USB device register map (base address 0xE010 0000) Name Access Address Description Reset value USBEpIntPri 0x240 USB Endpoint Priority 0x0000 0000 Endpoint realization registers USBReEp 0x244 USB Realize Endpoint...
Page 162: Clock Control Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.1 Clock control registers 9.1.1 USB Clock Control register (USBClkCtrl - 0xE010 0FF4) This register controls the clocking of the USB Device Controller. Whenever software wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN must be set.
Page 163: Device Interrupt Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 119. USB Clock Status register (USBClkSt - address 0xE010 0FF8) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 164: Usb Device Interrupt Enable Register (Usbdevinten - 0Xe010 0204)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 121. USB Device Interrupt Status register (USBDevIntSt - address 0xE010 0200) bit description Symbol Description Reset value EP_SLOW Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.
Page 165: Usb Device Interrupt Set Register (Usbdevintset - 0Xe010 020C)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Symbol Symbol ERR_INT EP_RLZED Symbol TxENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME ENDPKT Table 125. USB Device Interrupt Clear register (USBDevIntClr - address 0xE010 0208) bit description Symbol Value Description Reset value 31:0 No effect.
Page 166: Endpoint Interrupt Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 128. USB Device Interrupt Priority register (USBDevIntPri - address 0xE010 022C) bit description Symbol Value Description Reset value 31:2 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 167: Usb Endpoint Interrupt Enable Register (Usbepinten - 0Xe010 0234)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 130. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE010 0230) bit description Symbol Description Reset value EP3RX Endpoint 3, Isochronous endpoint. EP3TX Endpoint 3, Isochronous endpoint. EP4RX Endpoint 4, Data Received Interrupt bit.
Page 168: Usb Endpoint Interrupt Clear Register (Usbepintclr - 0Xe010 0238)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 132. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xE010 0234) bit description Symbol Value Description Reset value 31:0 The corresponding bit in USBDMARSt is set when an interrupt occurs for USBEpIntEn this endpoint.
Page 169: Usb Endpoint Interrupt Set Register (Usbepintset - 0Xe010 023C)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 134. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xE010 0238) bit description Symbol Value Description Reset value 31:0 No effect. USBEpIntClr Clears the corresponding bit in USBEpIntSt, by executing the SIE Select bit allocation Endpoint/Clear Interrupt command for this endpoint.
Page 170: Endpoint Realization Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 138. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xE010 0240) bit description Symbol Value Description Reset value 31:0 The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 0...
Page 171 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 139. USB Realize Endpoint register (USBReEp - address 0xE010 0244) bit allocation Reset value: 0x0000 0003 Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24 Symbol EP23 EP22 EP21 EP20 EP19...
Page 172: Usb Endpoint Index Register (Usbepin - 0Xe010 0248)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device The device will not respond to any transactions to unrealized endpoints. The SIE Configure Device command will only cause realized and enabled endpoints to respond to transactions. For details see Table 13–171.
Page 173: Usb Receive Data Register (Usbrxdata - 0Xe010 0218)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.5.1 USB Receive Data register (USBRxData - 0xE010 0218) For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately.
Page 174: Usb Transmit Packet Length Register (Usbtxplen - 0Xe010 0224)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 145. USB Transmit Data register (USBTxData - address 0xE010 021C) bit description Symbol Description Reset value 31:0 TX_DATA Transmit Data. 0x0000 0000 9.5.4 USB Transmit Packet Length register (USBTxPLen - 0xE010 0224) This register contains the number of bytes transferred from the CPU to the selected endpoint buffer.
Page 175: Sie Command Code Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 147. USB Control register (USBCtrl - address 0xE010 0228) bit description Symbol Value Description Reset value RD_EN Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register.
Page 176: Dma Registers
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 149. USB Command Data register (USBCmdData - address 0xE010 0214) bit description Symbol Description Reset value 31:8 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 177: Usb Dma Request Set Register (Usbdmarset - 0Xe010 0258)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device This register is intended for initialization prior to enabling the DMA for an endpoint. When the DMA is enabled for an endpoint, hardware clears the corresponding bit in USBDMARSt on completion of a packet transfer. Therefore, software should not clear the bit using this register while the endpoint is enabled for DMA operation.
Page 178: Usb Udca Head Register (Usbudcah - 0Xe010 0280)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.7.4 USB UDCA Head register (USBUDCAH - 0xE010 0280) The UDCA (USB Device Communication Area) Head register maintains the address where the UDCA is located in on-chip RAM. Refer to Section 13–14.2 “USB device communication area”...
Page 179: Usb Ep Dma Disable Register (Usbepdmadis - 0Xe010 028C)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.7.7 USB EP DMA Disable register (USBEpDMADis - 0xE010 028C) Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register clears the internal DMA_PROCEED flag.
Page 180: Usb End Of Transfer Interrupt Status Register (Usbeotintst - 0Xe010 02A0)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 159. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xE010 0294) bit description Symbol Value Description Reset value 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 181: Usb End Of Transfer Interrupt Set Register (Usbeotintset - 0Xe010 02A8)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 9.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0xE010 02A8) Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntSet is a write only register.
Page 182: Usb System Error Interrupt Status Register (Usbsyserrintst - 0Xe010 02B8)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 165. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0xE010 02B4) bit description Symbol Value Description Reset value Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0...
Page 183: Interrupt Handling
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 10. Interrupt handling This section describes how an interrupt event on any of the endpoints is routed to the Nested Vectored Interrupt Controller (NVIC). For a diagram showing interrupt event handling, see Figure 13–43.
Page 184 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request interrupts and system error interrupt events are routed to the NDDR and ERR bits respectively in the USBDMAStInt register.
Page 185 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device interrupt event on Slave mode from other Endpoints USBEpIntSt USBDevIntSt FRAME EP_FAST EP_SLOW USBDevIntPri[0] USBEpIntEn[n] USBEpIntPri[n] USBDevIntPri[1] ERR_INT USBDMARSt to VIC to DMA engine USBEoTIntST DMA Mode USBNDDRIntSt USBDMAIntSt NDDR USBSysErrIntSt For simplicity, USBDevIntEn and USBDMAIntEn are not shown.
Page 186: Serial Interface Engine Command Description
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11. Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action).
Page 187: Set Address (Command: 0Xd0, Data: Write 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 169. SIE command code table Command name Recipient Code (Hex) Data phase Device commands Set Address Device Write 1 byte Configure Device Device Write 1 byte Set Mode Device Write 1 byte...
Page 188: Set Mode (Command: 0Xf3, Data: Write 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 171. Configure Device Register bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. CONF_DEVICE Device is configured.
Page 189: Read Current Frame Number (Command: 0Xf5, 14.6.3 Data: Read 1 Or 2 Bytes)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number returns least significant byte first. In case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read.
Page 190 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 173. Set Device Status Register bit description Bit Symbol Value Description Reset value SUS_CH Suspend (SUS) bit change indicator. The SUS bit can toggle because: • The device goes into the suspended state.
Page 191: Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11.7 Get Device Status (Command: 0xFE, Data: read 1 byte) The Get Device Status command returns the Device Status Register. Reading the device status returns 1 byte of data. The bit field definition is same as the Set Device Status...
Page 192: Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 175. Read Error Status Register bit description Symbol Description Reset value TGL_ERR Wrong toggle bit in data PID, ignored data. BTSTF Bit stuff error. B_OVRN Buffer Overrun. End of packet error.
Page 193: Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 176. Select Endpoint Register bit description Bit Symbol Value Description Reset value SETUP bit: the value of this bit is updated after each successfully received packet (i.e. an ACKed package on that particular physical endpoint).
Page 194: Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 177. Set Endpoint Status Register bit description Bit Symbol Value Description Reset value CND_ST Conditional Stall bit. Unstalls both control endpoints. Stall both control endpoints, unless the STP bit is set in the Select Endpoint register.
Page 195: Validate Buffer (Command: 0Xfa, Data: None)
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 178. Clear Buffer Register bit description Symbol Value Description Reset value 7:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 196: Slave Mode Operation
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device – Set the priority of each enabled interrupt using USBEpIntPri. – Configure the desired interrupt mode using the SIE Set Mode command. – Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW, and possibly EP_FAST).
Page 197: Data Transfer For Out Endpoints
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 13.2 Data transfer for OUT endpoints When the software wants to read the data from an endpoint buffer it should set the RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the USBCtrl register.
Page 198: Usb Device Communication Area
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers to these simply as transfers. Within this section they are referred to as USB transfers to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Page 199: Triggering The Dma Engine
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.3 Triggering the DMA engine An endpoint raises a DMA request when Slave mode is disabled by setting the corresponding bit in the USBEpIntEn register to 0 (Section 13–9.3.2) and an endpoint interrupt occurs (see Section 13–9.7.1 “USB DMA Request Status register (USBDMARSt...
Page 200: Next_Dd_Pointer
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Table 179. DMA descriptor Word Access Access Description position (H/W) (S/W) position DMA_mode (00 -Normal; 01 - ATLE) Next_DD_valid (1 - valid; 0 - invalid) Reserved Isochronous_endpoint (1 - isochronous; 0 - non-isochronous)
Page 201: Isochronous_Endpoint
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.4.4 Isochronous_endpoint When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence 5 words have to be read when fetching it. 14.4.5 Max_packet_size The maximum packet size of the endpoint. This parameter is used while transferring the data for IN endpoints from the memory.
Page 202: Packet_Valid
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.4.10 Packet_valid This bit is used for isochronous endpoints. It indicates whether the last packet transferred to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was received without errors.
Page 203: Finding Dma Descriptor
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints). 14.5.2 Finding DMA Descriptor When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first determine whether a new descriptor has to the fetched or not.
Page 204: Packet Dd
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device A DD can have the following types of completion: Normal completion - If the current packet is fully transferred and the Present_DMA_count field equals the DMA_buffer_length, the DD has completed normally. The DD will be written back to memory with DD_retired set and DD_status set to NormalCompletion.
Page 205: Transferring The Data
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.6.3 Transferring the Data The data is transferred to or from the memory location DMA_buffer_start_addr. After the end of the packet transfer the Present_DMA_count value is incremented by 1. The isochronous packet size is stored in memory as shown in Figure 13–45.
Page 206: Auto Length Transfer Extraction (Atle) Mode Operation
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device Next_DD_Pointer NULL DMA_buffer_length Max_packet_size Isochronous_endpoint Next_DD_Valid DMA_mode 0x000A DMA_buffer_start_addr 0x80000000 Present_DMA_Count ATLE settings Packet_Valid DD_Status DD_Retired Isocronous_packetsize_memory_address 0x60000000 after 4 packets 0x000A0010 FULL 0x80000035 frame_ number Packet_Valid Packet_Length EMPTY 0x60000010 data memory packet size memory Fig 45.
Page 207: Out Transfers In Atle Mode
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device OUT transfers in ATLE mode data to be sent data in packets data to be stored in USB by host driver as seen on USB RAM by DMA engine DMA_buffer_start_addr 160 bytes...
Page 208: In Transfers In Atle Mode
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer.
Page 209: Ending The Packet Transfer
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 14.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be generated.
Page 210 UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2.
Page 211: Isochronous Endpoints
UM10316 NXP Semiconductors Chapter 13: LPC29xx USB device 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For...
Page 212: Chapter 14: Lpc29Xx Usb Host Controller
UM10316 Chapter 14: LPC29xx USB Host controller Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The USB host controller is available on LPC2930 and LPC2939 only (see also Table 1–4). 2. Introduction This section describes the host portion of the USB 2.0 OTG dual role core which integrates the host controller (OHCI compliant), device controller and I2C.
Page 213: Architecture
UM10316 NXP Semiconductors Chapter 14: LPC29xx USB Host controller 2.2 Architecture The architecture of the USB host controller is shown below in Figure 14–47. register interface (AHB slave) REGISTER INTERFACE port port 1 HOST CONTROL port 2 CONTROLLER LOGIC/ DMA interface...
Page 214: Usb Host Usage Note
UM10316 NXP Semiconductors Chapter 14: LPC29xx USB Host controller Table 181. USB OTG port pins Pin name Direction Description Pin category U2PWRD2 Port power status Host power switch USB_OVRCR2 Over-current status Host power switch USB_HSTEN2 Host enabled status Control 3.1.1 USB host usage note Both ports can be configured as USB hosts.
Page 215: Usb Host Register Definitions
UM10316 NXP Semiconductors Chapter 14: LPC29xx USB Host controller Table 182. Register overview: USB Host (base address 0xE010 0000) …continued Name Address Description Reset value offset HcBulkCurrentED 0x2C Contains the physical address of the current endpoint descriptor of the bulk list.
Page 216: Chapter 15: Lpc29Xx Usb Otg Interface
UM10316 Chapter 15: LPC29xx USB OTG interface Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The USB OTG controller is available in LPC2926/27/29, LPC2930, and LPC2939 only. Note that the host controller is not implemented on the LPC2926/27 and LPC2929 (see also Table 1–4).
Page 217: Pin Configuration
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface support an OTG connection. The communication between the register interface and an external OTG transceiver is handled through an I C interface and through the external OTG transceiver interrupt signal. For USB connections that use the device or host controller only (not OTG), the ports use an embedded USB Analog Transceiver (ATX).
Page 218 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 184. USB OTG port pins Pin name Direction Description Interfacing USB_SSPND1 Bus suspend status External OTG transceiver USB_PWRD1 Port power status USB host USB_PPWR1 Port power enable USB host USB_OVRCR1...
Page 219: Suggested Usb Interface Solutions
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 5.1 Suggested USB interface solutions DD(IO) VBUS USB_RST1 RESET_N ADR/PSW 33 Ω OE_N/INT_N DD(IO) Mini-AB SPEED 33 Ω connector ISP1302 SUSPEND SS(IO), USB_SCL1 SS(CORE) USB_SDA1 USB_INT1 INT_N USB_D+1 USB_D−1 DD(IO) USB_UP_LED1...
Page 220 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface DD(IO) USB_UP_LED1 SS(IO), SS(CORE) 33 Ω USB_D+1 33 Ω USB_D−1 D− USB-A connector 15 kΩ 15 kΩ DD(IO) USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA OUTA DD(IO) LM3526-L OUTB LPC293X USB_PPWR2 FLAGB USB_OVRCR2 USB_PWRD2 33 Ω...
Page 221: Register Overview
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface DD(IO) USB_UP_LED1 SS(IO), SS(CORE) 33 Ω USB_D+1 33 Ω USB_D−1 D− USB-A connector 15 kΩ 15 kΩ DD(IO) USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA OUTA LM3526-L LPC293X USB_UP_LED2 DD(IO) USB_CONNECT2 SS(IO), SS(CORE) 33 Ω...
Page 222: 0Xe01F 0100)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 185. Register overview: USB OTG and I C registers (base address 0xE010 0000) Name Access Address Description offset C registers I2C_RX 0x300 I2C Receive I2C_TX 0x300 I2C Transmit I2C_STS 0x304...
Page 223: Otg Interrupt Clear Register (Otgintclr - 0Xe010 010C)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 6.4 OTG Interrupt Clear Register (OTGIntClr - 0xE010 010C) Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in OTGIntSt.
Page 224: Otg Timer Register (Otgtmr - 0Xe010 0114)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 187. OTG Status Control register (OTGStCtrl - address 0xE010 0110) bit description Symbol Description Reset Value TMR_MODE Timer mode selection. 0: monoshot 1: free running TMR_SCALE Timer scale selection. This field determines the duration of each timer count.
Page 225: Otg Clock Status Register (Otgclkst - 0Xe010 0Ff8)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 189. OTG_clock_control register (OTG_clock_control - address 0xE010 0FF4) bit description Symbol Value Description Reset Value DEV_CLK_EN Device clock enable Disable the Device clock. Enable the Device clock. HOST_CLK_EN Host clock enable Disable the Host clock.
Page 226: I2C Transmit Register (I2C_Tx - 0Xe010 0300)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 191. I2C Receive register (I2C_RX - address 0xE010 0300) bit description Symbol Description Reset Value RX Data Receive data. 6.10 I2C Transmit Register (I2C_TX - 0xE010 0300) This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.
Page 227 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 193. I2C status register (I2C_STS - address 0xE010 0304) bit description Symbol Value Description Reset Value Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.
Page 228 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 193. I2C status register (I2C_STS - address 0xE010 0304) bit description Symbol Value Description Reset Value Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I C has lost the arbitration to another device on the bus.
Page 229: I2C Control Register (I2C_Ctl - 0Xe010 0308) . 228 I2C Clock High Register (I2C_Clkhi - 0Xe010 030C)
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Table 194. I2C Control register (I2C_CTL - address 0xE010 0308) bit description Symbol Value Description Reset Value DRSIE Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.
Page 230: Interrupt Handling
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 6.15 Interrupt handling The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All OTG related interrupts are routed separately to the VIC. I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL, to the USB_I2C_INT bit.
Page 231: B-Device: Peripheral To Host Switching
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface The OTG software stack is responsible for implementing the HNP state machines as described in the On-The-Go Supplement to the USB 2.0 Specification. The OTG controller hardware provides support for some of the state transitions in the HNP state machines as described in the following subsections.
Page 232 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface idle B_HNP_TRACK = 0 B_HNP_TRACK = 1 ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED bus suspended ? disconnect device controller from U1 PU_REMOVED set? set REMOVE_PU PU_REMOVED set? reconnect port U1 to the...
Page 233: Remove D+ Pull-Up
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK REMOVE_PU set? remove D+ pull-up, set PU_REMOVED go to go to b_wait_acon b_peripheral HNP_FAILURE set? add D+ pull-up HNP_SUCCESS set? go to b_host Fig 55.
Page 234: Add D+ Pull-Up
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x006;...
Page 235 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface idle A_HNP_TRACK = 0 A_HNP_TRACK = 1 ? set HNP_FAILURE, clear A_HNP_TRACK disconnect host controller from U1 bus suspended ? resume detected ? connnect host controller back to U1 bus reset detected?
Page 236 UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend TMR set? HNP_SUCCESS set?
Page 237: Set Bdis_Acon_En In External Otg Transceiver
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210;...
Page 238: Load And Enable Otg Timer
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0)
Page 239: Clocking And Power Management
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface 8. Clocking and power management The OTG controller clocking is shown in Figure 15–58. Note that the host controller is not implemented on the LPC2927 and LPC2929. ahb_slave_clk REGISTER BASE_SYS_CLK INTERFACE...
Page 240: Device Clock Request Signals
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface When software wishes to access registers in one of the controllers, it should first ensure that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Page 241: Usb Otg Controller Initialization
UM10316 NXP Semiconductors Chapter 15: LPC29xx USB OTG interface necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be de-asserted, the status of USB_NEED_CLK can be polled in the USBIntSt register to determine when they have all been de-asserted.
Page 242: Chapter 16: Lpc29Xx General Purpose Input/Output (Gpio)
UM10316 Chapter 16: LPC29xx General Purpose Input/Output (GPIO) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Available ports depend on the pin configuration for each part. Table 197.
Page 243: Register Overview
UM10316 NXP Semiconductors Chapter 16: LPC29xx General Purpose Input/Output (GPIO) The signal line is normally pulled up to a HIGH voltage level (logic 1) by an external resistor. Each of the devices connected to the signal line can either drive the signal line to a LOW voltage level (logic 0) or stay at high impedance (open-drain).
Page 244: Gpio Port Output Register
UM10316 NXP Semiconductors Chapter 16: LPC29xx General Purpose Input/Output (GPIO) 3.2 GPIO port output register The port output register is used to define the output level on each I/O pin individually if this pin has been configured as an output by the port direction register. If the port input register is written to the port output register is written to as well.
Page 245: Chapter 17: Lpc29Xx Timer 0/1/2/3
UM10316 Chapter 17: LPC29xx timer 0/1/2/3 Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Note that capture pins CAP0 and CAP1 on timer 1 are not pinned out for LPC2926/27/29 and LPC2921/23/25. 2.
Page 246: Timer Counter And Interrupt Timing
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 3. Timer counter and interrupt timing Each timer consists of a prescale counter (PR register) and a timer counter (TC register). The prescale counter is incremented at every cycle of the system clock. As soon as the prescale counter matches the prescale value contained in the PV register it is reset to 0 and the timer counter is incremented.
Page 247: Timer Match Functionality
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 CLK(SYS) Prescale Counter (PC) Timer Counter (TC) Timer Counter (TC) reached Timer Interrupt Match Value (MRx=6) (active low) PR=2, MRx=6 Fig 62. Stop-on-match timing 4. Timer match functionality The timer block contains four match circuits, each of which can be programmed with an individual match value and a specific action-on-match.
Page 248: Register Overview
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 5. Register overview Table 202. Timer register overview (base address: 0xE004 1000 (timer 0), 0xE004 2000 (timer 1), 0xE004 3000 (timer 2), 0xE004 4000 (timer 3), 0xE00C 0000 (MSCSS timer 0, 0xE00C1000 (MSCSS timer 1))
Page 249: Timer Counter
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 203. TCR register description (addresses: 0xE004 1000 (timer 0), 0xE004 2000 (timer 1), 0xE004 3000 (timer 2), 0xE004 4000 (timer 3), 0xE00C 0000 (MSCSS timer 0), 0xE00C 1000 (MSCSS timer 1))
Page 250: Timer Match-Control Register
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 205. PR register bit description (addresses: 0xE004 1008 (timer 0), 0xE004 2008 (timer 1), 0xE004 3008 (timer 2), 0xE004 4008 (timer 3), 0xE00C 0008 (MSCSS timer 0), 0xE00C 1008 (MSCSS timer 1))
Page 251: Timer External-Match Register
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 206. MCR register bit description (addresses: 0xE004 100C (timer 0), 0xE004 200C (timer 1), 0xE004 300C (timer 2), 0xE004 400C (timer 3), 0xE00C 000C (MSCSS timer 0), 0xE00C 100C (MSCSS timer 1)) …continued...
Page 252: Timer Match Register
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 207. EMR register bit description (addresses: 0xE004 1010 (timer 0), 0xE004 2010 (timer 1), 0xE004 3010 (timer 2), 0xE004 4010 (timer 3), 0xE00C 0010 (MSCSS timer 0), 0xE00C 1010 (MSCSS timer 1)) …continued...
Page 253: Timer Capture Register
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 209. CCR register bit description (addresses: 0xE004 1024 (timer 0), 0xE004 2024 (timer 1), 0xE004 3024 (timer 2), 0xE004 4024 (timer 3), 0xE00C 0024 (MSCSS timer 0), 0xE00C 1024 (MSCSS timer 1))
Page 254: Timer Interrupt Bit Description
UM10316 NXP Semiconductors Chapter 17: LPC29xx timer 0/1/2/3 Table 210. CR0-3 register bit description (addresses: 0xE004 1028-34 (timer 0), 0xE004 2028-34 (timer 1), 0xE004 3028-34 (timer 2), 0xE004 4028-34 (timer 3), 0xE00C 0028-34 (MSCSS timer 0), 0xE00C 1028-34 (MSCSS timer 1))
Page 255: Chapter 18: Lpc29Xx Spi0/1/2
UM10316 Chapter 18: LPC29xx SPI0/1/2 Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The LPC29xx contains three Serial Peripheral Interface (SPI) modules to enable synchronous serial communication with slave or master peripherals that have either Motorola SPI or Texas Instruments synchronous serial interfaces.
Page 256 UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 In normal transmission mode software programs the settings of the SPI module, writes data to the transmit FIFO and then enables the SPI module. The SPI module transmits until all data has been sent, or until it gets disabled with data still unsent. When data needs to be transmitted to another slave software has to re-program the settings of the SPI module, write new data and enable the SPI module again.
Page 257: Slave Mode
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Transmit FIFO Slave 1 Slave 2 Slave 3 Slave 4 Fig 63. Sequential-slave mode: example It is possible to temporarily suspend or skip one or more of the slaves in a transfer. To do...
Page 258: Register Overview
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 3. Register overview Table 212. Register overview: SPI (base address: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) Name Access Address Description Reset value Reference offset SPI_CONFIG 0x000 Configuration register 0x0001 0000 Table 18–213...
Page 259 UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 213. SPI_CONFIG register bit description (SPI_CONFIG0/1/2, addresses: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) …continued * = reset value Symbol Access Value Description UPDATE_ENABLE Update enable bit This must be set by software when the SLV_ENABLE register has been programmed.
Page 260: Spi Slave-Enable Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 213. SPI_CONFIG register bit description (SPI_CONFIG0/1/2, addresses: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) …continued * = reset value Symbol Access Value Description TRANSMIT_MODE Transmit mode Sequential-slave mode Normal mode...
Page 261: Spi Transmit-Fifo Flush Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 214. SLV_ENABLE register bit description (SLV_ENABLE0/1/2, addresses: 0xE004 7004 (SPI0), 0xE004 8004 (SPI1), 0xE004 9004 (SPI2)) * = reset value Symbol Access Value Description 4 and 5 SLV_ENABLE_2 Slave enable slave 2...
Page 262: Spi Receive Fifo Pop Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 216. FIFO_DATA register bit description (FIFO_DATA0/1/2: addresses 0xE004 700C (SPI0), 0xE004 800C (SPI1), 0xE004 900C (SPI2)) * = reset value Symbol Access Value Description 31 to reserved Reserved; do not modify. Read as logic 0...
Page 263: Spi Dma Settings Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 218. RX_FIFO_READMODE register bit description (RX_FIFO_READMODE0/1/2: addresses 0xE004 7014 (SPI0), 0xE004 8014 (SPI1), 0xE004 9014 (SPI2)) * = reset value Symbol Access Value Description 31 to 1 reserved Reserved; do not modify. Read as logic 0...
Page 264: Spi Status Register (Status)
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 219. DMA_SETTINGS register bit description (DMA_SETTINGS0/1/2: addresses 0xE004 7018 (SPI0), 0xE004 8018 (SPI1), 0xE004 9018 (SPI2)) …continued * = reset value Symbol Access Value Description RX_DMA_BURST 000* - Defines when the SPI will request a Rx burst DMA transfer.
Page 265: Spi Slave-Settings 1 Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 220. SPI status-register bit description (STATUS0/1/2, addresses: 0xE004 701C (SPI0), 0xE004 801C (SPI1), 0xE004 901C (SPI2)) …continued * = reset value Symbol Access Value Description TX_FIFO_FULL Transmit FIFO full bit Transmit FIFO full...
Page 266: Spi Slave-Settings 2 Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 3.10 SPI slave-settings 2 register The SPI second slave-settings register configures several other parameters for each slave of the SPI module. Remark: Some bits in this register are only relevant in master mode, and each individual slave has its own register with parameters.
Page 267: Spi Fifo Interrupt Threshold Register
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 222. SLVn_SETTINGS2 register bit description (SLV0/1/2_SETTINGS2, addresses: 0xE004 7028/30/38/40 (SPI0), 0xE004 8028/30/38/40 (SPI1), 0xE004 9028/30/38/40 (SPI2)) …continued * = reset value Symbol Access Value Description Serial clock phase (only used if Motorola SPI mode is selected).
Page 268: Spi Interrupt Bit Description
UM10316 NXP Semiconductors Chapter 18: LPC29xx SPI0/1/2 Table 223. INT_THRESHOLD register bit description (INT_THRESHOLD, addresses: 0xE004 7FD4 (SPI0), 0xE004 8FD4 (SPI1), 0xE004 9FD4 (SPI2)) * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0...
Page 269: Chapter 19: Lpc29Xx Universal Asynchronous Receiver/Transmitter (Uart)
UM10316 Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter (UART) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. The modem control features are pinned out on the LPC2939/30 only. 2.
Page 270 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 225. UART0/1 Pin description Type Description UART0/1 DCD Input Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UART and data may be exchanged. In normal operation of the modem interface (MCR[4]=0), the complement value of this signal is stored in MSR[7].
Page 271: Register Overview
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 4. Register overview Table 226. Register overview: UART0/1 (base address 0xE004 5000 (UART0) and 0xE004 6000 (UART1)) Name Access Address Description Reset Remark offset value 0x00 Receiver Buffer Register DLAB=0 0x00...
Page 272: Uartn Transmit Holding Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 227. UARTn Receiver Buffer Register (U0RBR - address 0xE004 5000, U1RBR - 0xE004 6000 when DLAB = 0, Read Only) bit description Symbol Description Reset Value 31:8 - Reserved The UARTn Receiver Buffer Register contains the oldest Undefined received byte in the UARTn Rx FIFO.
Page 273: Uartn Interrupt Enable Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 4.4 UARTn Interrupt Enable Register The UnIER is used to enable the three UARTn interrupt sources. Table 231. UARTn Interrupt Enable Register (U0IER - address 0xE004 5004, U1IER - 0xE004 6004 when DLAB = 0) bit description...
Page 274 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 232. UARTn Interrupt Identification Register (U0IIR - address 0xE004 5008, U1IIR - 0xE004 6008, Read Only) bit description Symbol Value Description Reset Value Reserved, user software should not write ones to reserved bits.
Page 275: Uartn Fifo Control Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 233. UARTn Interrupt Handling U0IIR[3:0] Priority Interrupt Type Interrupt Source Interrupt Reset value 0001 None None 0110 Highest RX Line Status or PE or FE or BI UnLSR Read / Error...
Page 276: Uartn Line Control Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 234. UARTn FIFO Control Register (U0FCR - address 0xE004 5008, U1FCR - 0xE004 6008, Write Only) bit description Symbol Value Description Reset Value 31:8 - Reserved RX Trigger These two bits determine how many receiver...
Page 277: Uart0/1 Modem Control Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 235. UARTn Line Control Register (U0LCR - address 0xE004 500C, U1LCR - 0xE004 600C) bit description Bit Symbol Value Description Reset Value Break Control Disable break transmission. Enable break transmission. Output pin UART0 TXD is forced to logic 0 when UnLCR[6] is active high.
Page 278: Auto-Flow Control
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 236: UART0/1 Modem Control Register (U0MCR - address 0xE004 5010, U1MCR - 0xE004 6010) bit description Symbol Value Description Reset value LoopEn The modem loopback mode provides a mechanism to perform diagnostic loopback testing.
Page 279: Auto-Cts
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter If Auto-RTS mode is disabled, the RTSen bit controls the RTS output of the UART. If Auto-RTS mode is enabled, hardware controls the RTS output, and the actual value of RTS will be copied in the RTS Control bit of the UART. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software.
Page 280: Uartn Line Status Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter UART1 TX start bits0..7 stop start bits0..7 stop start bits0..7 stop CTS1 pin Fig 65. Auto-CTS Functional Timing While starting transmission of the initial character the CTS1 signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS1 is deasserted (high).
Page 281: Uart0/1 Modem Status Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 238. UARTn Line Status Register (U0LSR - address 0xE004 5014, U1LSR - 0xE004 6014, Read Only) bit description Bit Symbol Value Description Reset Value Framing Error When the stop bit of a received character is a logic 0, a (FE) framing error occurs.
Page 282: Uartn Scratch Pad Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 239: UARTn Modem Status Register (U0MSR - address 0xE004 5018, U1MSR - 0xE004 6018, Read Only) bit description Bit Symbol Value Description Reset Value Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.
Page 283: Auto-Baud
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 241. UARTn Auto-baud Control Register (U0ACR - 0xE004 5020, U1ACR - 0xE004 6020) bit description Symbol Value Description Reset value 31:10 - Reserved, user software should not write ones to reserved bits.
Page 284: Auto-Baud Modes
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter • The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn is set and the auto-baud rate measurement counter overflows). • The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn is set and the auto-baud has completed successfully).
Page 285: Uartn Fractional Divider Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
Page 286: Baudrate Calculation
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 242. UARTn Fractional Divider Register (U0FDR - address 0xE004 5028, U1FDR - 0xE004 6028) bit description Function Value Description Reset value 31:8 Reserved, user software should not write ones to reserved bits.
Page 287 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 288: Example 1: Base_Uart_Clk = 14.7456 Mhz, Br = 9600
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 243. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538...
Page 289: Uartn Rs485 Control Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter Table 19–244 describes how to use TXEn bit in order to achieve software flow control. Table 244. UARTn Transmit Enable Register (U0TER - address 0xE004 5030, U1TER - 0xE004 6030) bit description...
Page 290: Uartn Rs485 Address Match Register
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter 4.16 UARTn RS485 Address Match register Table 246. UARTn RS485 Address Match register (U0RS485ADRMATCH - address 0xE004 5050, U1RS485ADRMATCH - address 0xE004 6050) bit description Symbol Description Reset value 31:8 Reserved ADRMATCH Contains the address match value.
Page 291: Auto Address Detection (Aad) Mode 290 Rs-485/Eia-485 Auto Direction Control
UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter When a matching address character is detected it will be pushed onto the RXFIFO along with the partiy bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware).
Page 292 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter The UARTn transmitter block, UnTX, accepts data written by the CPU or host and buffers the data in the UARTn TX Holding Register FIFO (UnTHR). The UARTn TX Shift Register (UnTSR) reads the data stored in the UnTHR and assembles the data to transmit via the serial output pin, TXDn.
Page 293 UM10316 NXP Semiconductors Chapter 19: LPC29xx Universal Asynchronous Receiver/Transmitter UnTX NTXRDY TXDn UnTHR UnTSR UnBRG UnDLL NBAUDOUT UnDLM RCLK UnRX NRXRDY INTERRUPT RXDn UnRBR UnRSR UnIER UnINTR UnIIR UnFCR UnLSR UnSCR UnLCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE UART_CLK Fig 68.
Page 294: Chapter 20: Lpc29Xx Watchdog Timer (Wdt)
UM10316 Chapter 20: LPC29xx WatchDog Timer (WDT) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The purpose of the Watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state.
Page 295: Register Overview
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 248. Watchdog programming steps Step Normal mode Debug mode Write 0x251D8951 (key exor Write time-out value (e.g.0x0000 FFFF) counter_enable) to the Watchdog Timer to the Watchdog time-out register. Control register. The timer is now started This indicates time-out reset at 65,536 clock cycles.
Page 296: Watchdog Timer Counter
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 250. WTCR register bit description (WTCR, address: 0xE004 0000) * = reset value Variable name Access Value Description 31 to 3 WD_KEY 0x0000 Protection key, see above. Writes to the...
Page 297: Watchdog Timer Key Register
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 252. PR register bit descritpion (PR, address: 0xE004 0008) * = reset value Variable name Access Value Description 31 to 0 PR[31:0] 0x0000 Prescale register. This specifies the maximum 0000* value for the prescale counter.
Page 298: Watchdog Interrupt Bit Description
UM10316 NXP Semiconductors Chapter 20: LPC29xx WatchDog Timer (WDT) Table 255. WD_DEBUG register bit description (WD_DEBUG, address: 0xE004 0040) * = reset value Variable name Access Value Description 31 to 1 WD_KEY 0x0000 Protection key, see above. Writes to the...
Page 299: Chapter 21: Lpc29Xx Can 0/1
UM10316 Chapter 21: LPC29xx CAN 0/1 Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. CAN functional description Figure 21–69 gives a brief overview of the main blocks in the CAN gateway controller. This consists of two identical CAN controllers working as independent CAN nodes.
Page 300: Can Bus Timing
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 4. CAN bus timing 4.1 Baud-rate prescaler The period of the CAN system clock, t , is programmable and determines individual bit timing. The CAN system clock is calculated using the following equation:...
Page 301: Can Transmit Buffers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 clk(sys) Baud rate prescaler clk(sys) CAN: SYNCSEG TSEG1 TSEG2 nominal bit time TSEG1 Sync. TSEG1 TSEG2 Sync. Seg. Seg . e.g. BRP = 00000001b TSEG1 = 0101b TSEG2 = 010b Fig 70. General structure of a bit-period 5.
Page 302: Automatic Transmit-Priority Protection
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 5.2 Automatic transmit-priority protection To allow uninterrupted streams of transmit messages, the CAN controller provides automatic transmit-priority detection for all transmit buffers. Depending on the selected transmit priority mode (TPM) in the mode register, internal prioritization is based on the CAN identifier or a user-defined local priority.
Page 303: Can Controller Self-Test
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 7. CAN controller self-test The CAN controller supports two options for self-tests: • Global self-test: setting the self-reception request bit in normal operating mode • Local self-test: setting the self-reception request bit in self-test mode Both self-tests use the self-reception feature of the CAN controller.
Page 304: Can Global Acceptance Filter
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 TX Buffer TX Buffer TX Buffer Transceiver RX Buffer Fig 72. Local self-test (example for high-speed CAN bus) A message transmission is initiated by setting the self-reception request bit SRR in conjunction with the selected message buffer(s) STB3, STB2 and STB1.
Page 305: Standard Frame-Format Fullcan Identifier Section
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11-BIT index 0 11-BIT index 1 11-BIT index 2 11-BIT index 3 standard frame h entries format FullCAN identifier section 11-BIT index (h−2) 11-BIT index (h−1) CASFESA 11-BIT index (h) 11-BIT index (h+1)
Page 306 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 258. Standard frame-format FullCAN identifier section …continued Symbol Description 15 to 13 SCC Odd index: CAN controller number Odd index: message disable bit. Logic 0 is message enabled and logic 1 is message disabled...
Page 307: Standard Frame-Format Explicit Identifier Section
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 The semaphore operates in the following manner: • SEM[1:0] = 01: Acceptance filter is in the process of updating the buffer • SEM[1:0] = 11: Acceptance Filter has finished updating the buffer •...
Page 308: Standard Frame-Format Group Identifier Section
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 260. Standard frame-format explicit identifier section …continued Symbol Description Odd index: message disable bit. Logic 0 is message enabled and logic 1 is message disabled Not used 10 to 0 ID[28:18] Odd index: 11-bit CAN 2.0 B identifier...
Page 309: Extended Frame-Format Group Identifier Section
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 262. Extended frame-format explicit identifier section Symbol Description EFF_GRP_ start address 31 to 29 SCC CAN controller number 28 to 0 ID[28:0] 29-bit CAN 2.0 B identifier 8.5 Extended frame-format group identifier section...
Page 310: Section Start-Registers Of The Id Look-Up Table Memory
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Use the ID ready interrupt IDI and the receive interrupt RI. In this mode all CAN messages are accepted and stored in the receive buffers of active CAN Controllers. With the activated FullCAN Mode, received FullCAN messages are automatically stored by the acceptance filter in the FullCAN message-object section (see also Section 21–13...
Page 311: Can Acceptance-Filter Search Algorithm
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Each CAN identifier is linked to an ID Index number (see also Figure 21–75 Figure 21–85). For a CAN identifier match, the matching ID index is stored in the identifier index IDI of the message info register CCRXBMI for the appropriate CAN controller (see Section 21–6.1...
Page 312: Can Central Status Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 It is possible to disable the 5Ah identifier in the FullCAN section. Then, the screening process would be finished with the match in the explicit identifier section. The first group in the group identifier section has been defined so that incoming CAN messages with identifiers of 5Ah up to 5Fh are accepted on SCC 0.
Page 313 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 264. Register overview: CAN controller (base address 0xE008 0000 (CAN0) , 0xE008 1000 (CAN1)) …continued Name Access Address Description Reset value Reference offset CCTXB2ID 0x44 CAN controller transmit- buffer 2 identifier 0x0000 0000 see Table 21–282...
Page 314: Can Controller Mode Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 267. Register overview: CANCS central status (base address: 0xE008 8000) Name Access Address Description Reset Reference offset value CCCTS CAN controllers central transmit-status register 0x030303 Table 21–296 CCCRS CAN controllers central receive-status register 0x03 Table 21–297...
Page 315: Can Controller Command Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 268. CCMODE register bit description (CCMODE, address 0xE008 0000 (CAN0) and 0xE008 1000 (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value Description...
Page 316 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 269. CAN controller command register bit description (CCCMD, address 0xE008 0004 (CAN0) and 0xE008 1004 (CAN1)) …continued Symbol Access Value Description [1][2][3] Self-reception request A message is transmitted from the selected transmit buffer and received simultaneously.
Page 317: Can Controller Global Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 The AT bit is used when the CPU requires suspension of the previously requested transmission; e.g. to transmit a more urgent message first. A transmission already in progress is not stopped. To see if the original message has been either transmitted successfully or aborted, the transmission-complete status bit should be checked.
Page 318 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 270. CCGS register bit description (CCGS, address 0xE008 0008 (CAN0) and 0xE008 1008 (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value Description...
Page 319: Can Controller Interrupt And Capture Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 After reading all messages and releasing their memory space with the command 'release receive buffer' this bit is cleared. 9.4 CAN controller interrupt and capture register The CAN controller interrupt and capture register allows the identification of an interrupt source.
Page 320 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 271. CAN controller interrupt and capture register bit description (CCIC, address 0xE008 000C (CAN0) and 0xE008 100C (CAN1)) * = reset value; **both reset value and soft reset mode value Symbol...
Page 321 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 271. CAN controller interrupt and capture register bit description (CCIC, address 0xE008 000C (CAN0) and 0xE008 100C (CAN1)) …continued * = reset value; **both reset value and soft reset mode value...
Page 322 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 The RI bit is not cleared on a read-access to the interrupt register. Giving the command ‘Release receive buffer will clear RI temporarily. If there is another message available within the receive buffer after the release command, RI is set again: otherwise RI stays cleared.
Page 323: Can Controller Interrupt-Enable Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 9.5 CAN controller interrupt-enable register The CAN controller interrupt-enable register CCIE enables the different types of CAN controller interrupts. Table 21–273 shows the bit assignment of the CCIE register. Table 273. CAN controller interrupt-enable register bit descriptioN (CCIE, address 0xE008...
Page 324: Can Controller Bus Timing Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 273. CAN controller interrupt-enable register bit descriptioN (CCIE, address 0xE008 0010 (CAN0) and 0xE008 1010 (CAN1)) …continued * = reset value Symbol Access Value Description EWIE Error warning interrupt-enable An interrupt is generated if either the error...
Page 325: Can Controller Error-Warning Limit Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 274. CAN controller bust timing register bit description (CCBT, address 0xE008 0014 (CAN0) and 0xE008 1014 (CAN1)) …continued * = reset value Symbol Access Value Description 13 to 10 reserved Reserved; do not modify. Read as logic 0...
Page 326: Can Controller Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 9.8 CAN controller status register The CAN controller status register CCSTAT reflects the transmit status of all three transmit buffers, and also the global status of the CAN controller itself. The register is read-only.
Page 327 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 276. CAN controller status register bit description (CCSTAT, address 0xE008 001C (CAN0) and 0xE008 101C (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value...
Page 328: Can Controller Receive-Buffer Message Info Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 276. CAN controller status register bit description (CCSTAT, address 0xE008 001C (CAN0) and 0xE008 101C (CAN1)) …continued * = reset value; **both reset value and soft reset mode value Symbol Access Value...
Page 329: Can Controller Receive Buffer Identifier Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 277. CAN controller receive-buffer message info register bit description (CCRXBMI, address 0xE008 0020 (CAN0) and 0xE008 1020 (CAN1)) * = reset value Symbol Access Value Description Frame format An extended frame-format message has been...
Page 330: Can Controller Receive Buffer Data A Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 278. CAN controller receive buffer identifier register bit description (CCRXBID, address 0xE008 0024 (CAN0) and 0xE008 1024 (CAN1)) * = reset value Symbol Access Value Description 31 to 29 reserved Reserved; do not modify. Read as logic 0...
Page 331: Can Controller Transmit-Buffer Message Info Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 280. CAN controller receive-buffer data B register bit description (CCRXBDB, address 0xE008 002C (CAN0) and 0xE008 102C (CAN1)) * = reset value Symbol Access Value Description 31 to 24 DB8[7:0] Data byte 8. If the data-length code value is...
Page 332: Can Controller Transmit-Buffer Identifier Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 281. CAN controller transmit-buffer message info register bit description (CCTXB1/2/3MI, addresses 0xE008 0030, 0xE008 0040, 0xE008 0050 (CAN0), and 0xE008 1030, 0xE008 1040, 0xE008 1050 (CAN1)) …continued * = reset value...
Page 333: Can Controller Transmit-Buffer Data B Registers
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 21–283 shows the bit assignment of the CCTXB1DA, CCTXB2DA and CCTXB3DA registers. Table 283. CAN controller transmit-buffer data A registers register bit description (CCTXB1/2/3DA, addresses 0xE008 0038, 0xE008 0048, 0xE008 0058 (CAN0), and...
Page 334: Can Acceptance-Filter Register Overview
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 284. CAN controller transmit-buffer data B register bit description (CCTX1/2/3DB, addresses 0xE008 003C, 0xE008 004C, 0xE008 005C (CAN0), and 0xE008 103C, 0xE008 104C, 0xE008 105C (CAN1)) …continued * = reset value...
Page 335: Can Acceptance-Filter Standard-Frame Explicit Start-Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 10.2 CAN acceptance-filter standard-frame explicit start-address register The CAN acceptance filter standard-frame explicit start-address register CASFESA defines the start address of the section of explicit standard identifiers in the acceptance-filter look-up table. It also indicates the size of the section of standard identifiers which the acceptance filter will search.
Page 336: Can Acceptance-Filter Extended-Frame Explicit Start-Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 287. CAN acceptance-filter standard-frame group start-address register bit description (CASFGSA, address 0xE008 7008) * = reset value Symbol Access Value Description 31 to 12 reserved Reserved; do not modify. Read as logic 0...
Page 337: Can Acceptance-Filter Extended-Frame Group Start-Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 288. CAEFESA register bit description (CAEFESA, address 0xE008 700C) …continued * = reset value Symbol Access Value Description 11 to 2 EFESA[9:0] Extended-frame explicit start address. This register defines the start address of the section of explicit extended identifiers in acceptance-filter look-up table.
Page 338: Can Acceptance-Filter End Of Look-Up Table Address Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 10.6 CAN acceptance-filter end of look-up table address register The CAN acceptance filter end of look-up table address register CAEOTA contains the end-address of the acceptance-filter look-up table. Table 21–290 shows the bit assignment of the CAEOTA register.
Page 339: Can Acceptance-Filter Look-Up Table Error Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 291. CAN acceptance-filter look-up table error address register bit description (CALUTEA, address 0xE008 7018) * = reset value Symbol Access Value Description 31 to 11 reserved Reserved; do not modify. Read as logic 0...
Page 340: Can Controller Central Transmit-Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 294. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0xE008 7024) bit description Symbol Description Reset Value IntPnd0 FullCan Interrupt Pending bit 0. IntPndx (0<x<31) FullCan Interrupt Pending bit x.
Page 341: Can Controller Central Receive-Status Register
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 10.12 CAN controller central receive-status register The CAN controller central receive-status register CCCRS provides bundled access to the reception status of all CAN controllers. The status flags are the same as those in the status register of the corresponding CAN controller.
Page 342: Fullcan Mode
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 298. CAN controller central miscellaneous-status register bit description * = reset value Symbol Access Value Description 31 to 10 reserved Reserved; do not modify. Read as logic 0 CAN controller 1 bus status...
Page 343: Fullcan Message Layout
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 • The Standard Frame Individual Start Address Register (SFF_sa) must be greater than or equal to the number of IDs for which automatic receive storage is to be done, times two. SFF_sa must be rounded up to a multiple of 4 if necessary.
Page 344 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 300. FullCAN semaphore operation SEM1 SEM0 activity Acceptance Filter is updating the content Acceptance Filter has finished updating the content CPU is in process of reading from the Acceptance Filter Prior to writing the first data byte into a message object, the Acceptance Filter will write the FrameInfo byte into the according buffer location with SEM[1:0] = 01.
Page 345 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 START read 1st word SEM == 01? this message has not been SEM == 11? received since last check clear SEM, write back 1 st word read 2nd and 3rd words read 1st word...
Page 346: Fullcan Interrupts
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only.
Page 347: Message Lost Bit And Can Channel Number
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Message Message disable bit disable bit Index 0, 1 11-bit CAN ID 11-bit CAN ID FullCAN Explicit Index 2, 3 11-bit CAN ID 11-bit CAN ID Standard Frame Index 4, 5 11-bit CAN ID...
Page 348: Setting The Interrupt Pending Bits (Intpnd 63 To 0)
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set).
Page 349: Scenario 2: Message Lost
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx Write write write write read clear read read read look-up ID, SEM table access MsgLostx message processor handler access access Fig 79. Normal case, no messages lost 11.3.2 Scenario 2: Message lost...
Page 350: Scenario 3: Message Gets Overwritten Indicated By Semaphore Bits
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 11.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler.
Page 351: Scenario 3.2: Message Gets Overwritten Indicated By Message Lost
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx write write clear write write write read clear write write write read read read read read read look-up table access 1st Object 2nd Object write write 2nd Object 1st Object read...
Page 352: Scenario 4: Clearing Message Lost Bit
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx look-up write write write write write write read write write write clear read read read write write write table access 1st Object 2nd Object 3rd Object write write write...
Page 353: Can Configuration Example 1
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 semaphore bits IntPndx write write write write write write write write write read clear read read write write write read look-up table access 1st Object 2nd Object 3rd Object write write write...
Page 354: Group Of Standard Frame-Format Identifier Section (11-Bit Can Id)
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 12.2 Group of standard frame-format identifier section (11-bit CAN ID) The start address of the group of the standard frame-format section is defined in the CASFGSA register with a value of 10h. The end of this section is defined in the CAEFESA register.
Page 355: Can Configuration Example 2
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Message Message disable bit disable bit Index CASFESA ID28 ID28 ID18 ID18 = 00h Explicit Standard ID28 ID18 ID18 ID28 Frame Format ID28 ID28 ID18 ID18 Identifier Section Disabled, 7 ID28 ID28...
Page 356: Fullcan Explicit Standard Frame-Format Section (11-Bit Can Id)
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Table 302. Used ID look-up table sections of example 2 ID-look-up table section Usage Group of standard frame format Not Activated Explicit extended frame format Not Activated Group of extended frame format Not Activated 13.1 FullCAN explicit standard frame-format section (11-bit CAN ID)
Page 357: Can Look-Up Table Programming Guidelines
UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 Message Message disable bit disable bit Index FullCAN Disabled, 1 ID28 ID28 ID18 ID18 Explicit Standard ID28 ID18 ID18 ID28 Frame Format ID28 ID28 ID18 ID18 Identifier Section ID28 ID28 ID18 ID18...
Page 358 UM10316 NXP Semiconductors Chapter 21: LPC29xx CAN 0/1 • To disable a group of identifiers the message-disable bit must be set for both the upper and lower bounds. UM10316 © NXP B.V. 2010. All rights reserved. User manual Rev. 3 — 19 October 2010...
Page 359: How To Read This Chapter
UM10316 Chapter 22: LPC29xx LIN/UART 0/1 Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The LIN/UART block is identical for all LPC29xx parts. 2. Introduction The LPC29xx LIN controller can function as UART or LIN interface and consists of two independent sub controllers for UART and LIN functions and a fractional baud rate generator for both.
Page 360: Uart Features
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 • One interrupt per LIN message • Slave response time-out detection • Programmable sync-break length • Automatic sync-field and sync-break generation • Programmable inter-byte space • Hardware or software parity generation •...
Page 361: Lin Master
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 5.1 LIN master The LIN master controller can send complete message frames without interrupting the CPU. Generation of a new message frame is always initiated by a transmission-request command. This LIN master command forces the LIN master to send the LIN header field including synch break, synch field and a user-specified ID field.
Page 362: Registers And Mapping
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 5.1.2 Registers and mapping The complete register layout of the LIN master controller is shown in Ref. 31–6. Refer to this for resolving register, register-slice and bit names. 5.1.3 Error detection The LIN master Controller contains error-detection logic which can detect the following wake-up or error conditions: •...
Page 363: Wake-Up Interrupt Handling
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 To safely distinguish between a bit error and a line clamped error, the LIN master should send a second message as soon as a bit error is detected. With the second message the LIN master will be able to distinguish clearly between bit errors and line-clamped errors.
Page 364: Common Lin/Uart Registers
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 305. Register overview: LIN/UART0/1 (base address: 0xE008 9000 (LIN/UART0), 0xE008 A000 (LIN/UART1)) Name Access Address Description Reset value Reference offset LFBRG 0x0C LIN/UART master-controller fractional baud-rate 0x0 0001 Table 22–309 generator register...
Page 365: Lin Master-Controller Configuration Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 306. LIN master-controller mode register bit description (LIN0_LMODE, address 0xE008 9000, LIN1_LMODE, address 0xE008 A000) * = reset value Symbol Access Value Description UART mode mode 31 to 8 reserved Reserved; do not modify. Read as logic 0...
Page 366: Lin Master-Controller Command Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 307. LIN master-controller configuration register bit description (LIN0_LCFG, address 0xE008 9004, LIN1_LCFG, address 0xE008 A004) …continued * = reset value Symbol Access Value Description UART mode mode 4 and 3 IBS[1:0] Inter-byte space length.
Page 367: Lin Master-Controller Fractional Baud Rate Generator Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 7.1.4 LIN master-controller fractional baud rate generator register The LIN master-controller fractional baud rate generator register LFBRG stores the divisor in 16-bit binary format and the fraction in 4-bit binary format for the programmable baud- rate generator.
Page 368 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Figure 22–90 shows the status-flag handling in terms of transmitting and receiving header and response fields. The LSTAT register is read-only. Table 22–310 shows its bit assignment. Header fields Response fields Case 1:...
Page 369 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 310. LIN master-controller status register bit description (LIN0_STAT, address 0xE008 9010, LIN1_LSTAT, address 0xE008 A010) …continued * = reset value Symbol Access Value Description RXD line level. The current RXD line level is dominant...
Page 370: Lin Master-Controller Interrupt And Capture Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 7.2.2 LIN master-controller interrupt and capture register The LIN master-controller interrupt and capture register LIC determines when the LIN master controller gives an interrupt request if the corresponding interrupt-enable has been set. Reading the interrupt register clears the interrupt source. A detailed bus-error capture is reported.
Page 371: Lin Master-Controller Interrupt Enable Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 311. LIN master-controller interrupt and capture register bit description (LIN0_LIC, address 0xE008 9014, LIN1_LIC, address 0xE008 A014) …continued * = reset value Symbol Access Value Description Checksum-error interrupt The received checksum field does not match...
Page 372: Lin Master-Controller Checksum Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 312. LIN master-controller interrupt enable register bit description (LIN0_LIE, address 0xE008 9018, LIN1_LIE, address 0xE008 A018) …continued * = reset value Symbol Access Value Description WPIE Wake-up and LIN protocol error-interrupt...
Page 373: Lin Master-Controller Time-Out Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 to the CPU as read-only memory. By setting the software checksum bit the checksum register appears to the CPU as read/write memory. In this case, and before a transmission is initiated, the software has to provide the checksum to the checksum register.
Page 374 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Header Response data field(s) + checksum field minimum frame length data field(s) + checksum field maximum frame length expected message complete time frame time-out period Slave is sending and Master is receiving 001aaa220 Fig 91.
Page 375 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 314. LIN master-controller time-out register bit description (LIN0_LTO, address 0xE008 9024, LIN1_LTO, address 0xE008 A024) * = reset value Symbol Access Value Description 31 to 8 reserved Reserved; do not modify. Read as logic 0 7 to 0 LIN message time-out.
Page 376 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 315. LIN message-identifier register bit description (LIN0_LID, address 0xE008 9028, LIN1_LID, address 0xE008 A028) …continued * = reset value Symbol Access Value Description CSID Checksum ID inclusion The identifier field is included in the checksum...
Page 377 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 317. LDATB register bit description (LIN0_LDATB, address 0xE008 9030, LIN1_LDATB, address 0xE008 A030) * = reset value Symbol Access Value Description 31 to 24 DF8[7:0] LIN message-data field 8 0x00* 23 to 16 DF7[7:0]...
Page 378: Lin/Uart Registers (Lin In Uart Mode)
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 7.3 LIN/UART registers (LIN in UART mode) 7.3.1 LIN/UARTn Receiver Buffer Register The LU0/1RBR is the top byte of the LIN/UARTn RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest”...
Page 379 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 322. LIN/UARTn Interrupt Enable Register (LU0IER - address 0xE008 9014, LU1IER - 0xE008 A014) bit description Symbol Value Description Reset Value THRE enables the THRE interrupt for LIN/UARTn. The status of Interrupt this can be read from LU0/1LSR[5].
Page 380 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The LU0/1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine.
Page 381: Lin/Uartn Interrupt Identification Register 379 Lin/Uartn Fifo Control Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 For details see Section 22–7.3.7 “LIN/UARTn Line Status Register” For details see Section 22–7.3.1 “LIN/UARTn Receiver Buffer Register” For details see Section 22–7.3.4 “LIN/UARTn Interrupt Identification Register” Section 22–7.3.2 “LIN/UARTn Transmit Holding Register”...
Page 382: Lin/Uartn Line Control Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 7.3.6 LIN/UARTn Line Control Register The LU0/1LCR determines the format of the data character that is to be transmitted or received. Table 326. LIN/UARTn Line Control Register (LU0LCR - address 0xE008 901C,...
Page 383 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 327. LIN/UARTn Line Status Register (LU0LSR - address 0xE008 9024, LU1LSR - 0xE008 A024, Read Only) bit description Bit Symbol Value Description Reset Value Transmitter TEMT is set when both LU0/1THR and LU0/1TSR are empty;...
Page 384: Lin/Uartn Scratch Pad Register
UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 Table 327. LIN/UARTn Line Status Register (LU0LSR - address 0xE008 9024, LU1LSR - 0xE008 A024, Read Only) bit description Bit Symbol Value Description Reset Value Receiver LU0/1LSR0 is set when the LU0/1RBR holds an unread Data Ready character and is cleared when the RBR FIFO is empty.
Page 385 UM10316 NXP Semiconductors Chapter 22: LPC29xx LIN/UART 0/1 The example uses hardware support from the LIN master, so the software ID parity (SWPA) and the checksum (SWCS) are generated automatically. LIN master interrupts are used for message reception and transmission.
Page 386: Chapter 23: Lpc29Xx I2C-Interface
UM10316 Chapter 23: LPC29xx I2C-interface Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Features • C0 and I C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I C-bus) and do not support powering off of individual devices connected to the same bus lines.
Page 387: Pin Description
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I C bus will not be released. Each of the two I...
Page 388: Master Transmitter Mode
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the master mode, the I C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer.
Page 389: Master Receiver Mode
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 6.2 Master Receiver mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition...
Page 390: Slave Transmitter Mode
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 333. I2CnCONSET used to configure Slave mode Symbol I2EN Value I2EN must be set to 1 to enable the I C function. AA bit must be set to 1 to acknowledge its own slave address or the general call address. The STA, STO and SI bits are set to 0.
Page 391: C Implementation And Operation
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface SLAVE ADDRESS DATA DATA “0” - write “1” - read data transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) from Master to Slave A = Not acknowledge (SDA high) from Slave to Master...
Page 392: Address Registers, Addr0 To Addr3
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface ADDRESS REGISTERS I2CnADDR0 to I2CnADDR3 MATCHALL I2CnMMCTRL[3] MASK REGISTERS MASK and COMPARE I2CnMASK0 to I2CnMASK3 INPUT FILTER I2CnDATABUFFER SHIFT REGISTER OUTPUT I2CnDAT STAGE MONITOR MODE REGISTER I2CnMMCTRL BIT COUNTER/ PCLK ARBITRATION and INPUT...
Page 393: Address Mask Registers, Mask0 To Mask3
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 7.3 Address mask registers, MASK0 to MASK3 The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause an automatic compare on the corresponding bit of the received address when it is compared to the ADDRn register associated with that mask register.
Page 394: Serial Clock Generator
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface SDA line SCL line (1) A device transmits serial data. (2) Another device overrules a logic 1 (dotted line), transmitted by this I C master, by pulling the SDA line low. Arbitration is lost, and this I C enters Slave Receiver mode.
Page 395: Timing And Control
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface via the I C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.
Page 396: C Control Set Register (I2C[0/1]Conset: 0Xe008 2000, 0Xe008 3000)
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 334. Register overview: I2C (base address 0xE008 2000 (I2C0) and 0xE008 3000 (I2C1)) Name Access Address Description Reset offset value 0x0C I2C Slave Address Register. Contains the 7 bit slave address for operation of...
Page 397 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 335. I C Control Set Register (I2C[0/1]CONSET - addresses: 0xE008 2000, 0xE008 3000) bit description Bit Symbol Description Reset Value Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 398: C Status Register (I2C[0/1]Stat - 0Xe008 2004, 0Xe008 3004)
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface SI is the I C Interrupt Flag. This bit is set when the I C state changes. However, entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case.
Page 399: C Slave Address Register (I2C[0/1]Adr - 0Xe008 200C, 0Xe008 300C)
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 337. I C Data Register ( I2C[0/1]DAT - addresses 0xE008 2008, 0xE008 3008) bit description Bit Symbol Description Reset Value 7:0 Data This register holds data values that have been received, or are to be transmitted.
Page 400: I 2 C Control Clear Register (I2C[0/1]Conclr: 0Xe008 2018, 0Xe008 3018)
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I C bus specification defines the SCL low time and high time at different values for a 400 kHz I rate.
Page 401: C Monitor Mode Control Register (I2C[0/1]Mmctrl: 0Xe008 201C, 0Xe008 301C)
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET register. Writing 0 has no effect. I2ENC is the I C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the I2CONSET register.
Page 402: Interrupt In Monitor Mode
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode). 8.8.1 Interrupt in Monitor mode All interrupts will occur as normal when the module is in monitor mode. This means that...
Page 403: C Slave Address Registers (I2C[0/1]Adr0 To 3: 0Xe008 20[0C, 20, 24, 28], 0Xe008 30[0C, 20, 24, 28])
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 344. I C Data buffer register (I2C[0/1]DATA_BUFFER addresses - 0xE008 202C, 0xE008 302C) bit description Bit Symbol Description Reset value 7:0 Data This register holds contents of the 8 msb’s of the I2DAT shift register.
Page 404: Details Of I C Operating Modes
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 9. Details of I C operating modes The four operating modes are: • Master Transmitter • Master Receiver • Slave Receiver • Slave Transmitter Data transfers in each mode of operation are shown in Figures to 106.
Page 405: Master Receiver Mode
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface The master transmitter mode may now be entered by setting the STA bit. The I C logic will now test the I C bus and generate a start condition as soon as the bus becomes free.
Page 406 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface The I C bus rate settings do not affect the I C block in the slave mode. I2EN must be set to logic 1 to enable the I C block. The AA bit must be set to enable the I C block to acknowledge its own slave address or the general call address.
Page 407 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR Data byte...
Page 408 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
Page 409 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
Page 410: Slave Transmitter Mode
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface reception of the own Slave address and one or more Data DATA DATA P OR S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched...
Page 411 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 351. Master Transmitter mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 412 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 352. Master Receiver mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 413 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 353. Slave Receiver Mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 414 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 353. Slave Receiver Mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 415 UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 354. Tad_105: Slave Transmitter mode Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
Page 416: Miscellaneous States
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 9.5 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I C hardware state (see Table 23–355). These are discussed below. 23.9.5.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set.
Page 417: Some Special Cases
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface Table 355. Miscellaneous states Status Status of the I C bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI 0xF8...
Page 418: C Bus Obstructed By A Low Level On Scl Or Sda
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I C bus is possible.
Page 419: C State Service Routines
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface time limit STA flag STO flag SDA line SCL line start condition Fig 107. Forced access to a busy I C bus STA flag SDA line SCL line start condition (1) Unsuccessful attempt to send a start condition.
Page 420: I 2 C Interrupt Service
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface The I C hardware now begins checking the I C bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information.
Page 421: I 2 C Interrupt Routine
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up the Master Receive buffer.
Page 422: Master Transmitter States
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 10.7 Master Transmitter states 10.7.1 State : 0x18 Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK has been received.
Page 423: State : 0X38
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 10.7.5 State : 0x38 Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new Start condition will be transmitted when the bus is free again.
Page 424: Slave Receiver States
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 1. Read data byte from I2DAT into Master Receive buffer. 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit 10.9 Slave Receiver states...
Page 425: State : 0X80
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit 10.9.5 State : 0x80 Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read.
Page 426: Slave Transmitter States
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.10 Slave Transmitter States 10.10.1 State : 0xA8 Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received.
Page 427: State : 0Xc8
UM10316 NXP Semiconductors Chapter 23: LPC29xx I2C-interface 3. Exit 10.10.5 State : 0xC8 The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit.
Page 428: Chapter 24: Lpc29Xx Modulation And Sampling Control Subsystem (Mscss)
UM10316 Chapter 24: LPC29xx Modulation and Sampling Control Subsystem (MSCSS) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. Note that the ADC0 is available on LPC2926/27/29, LPC2930, and LPC2939 only.
Page 429 UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of MSCSS timer 0 to start the PWM after a pre-programmed delay. This sync signal is cascaded through all PWMs, allowing a programmable delay offset between subsequent PWMs.
Page 430: Mscss Miscellaneous Operations
UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem ADC2_EXT_START ADC1_EXT_START ADC0_EXT_START pause_0 ADC0 pause ADC1 MSCSS TIMER 0 ADC2 pause_0 PWM0 MSCSS PWM1 TE_i TIMER 1 PWM2 TE_o TE_i trap PWM3 TE_o TE_i trap TE_o TE_i trap...
Page 431: Continuous Level Measurement
UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem • Capture inputs to measure time between events • Synchronization between several PWM signals • Synchronization between ADCs • Synchronization between PWMs and ADCs • Timed and synchronized renewal of settings •...
Page 432: Register Overview
UM10316 NXP Semiconductors Chapter 24: LPC29xx Modulation and Sampling Control Subsystem To generate a sine wave, the sine period can be divided into N periods. In each of these a fixed voltage is generated via PWM0, having a much shorter period compared to the sine itself.
Page 433: Chapter 25: Lpc29Xx Pulse Width Modulator (Pwm)
UM10316 Chapter 25: LPC29xx Pulse Width Modulator (PWM) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The MSCSS contains four PWM blocks to allow generation and capture of all kinds of square waveforms.
Page 434: Functional Description
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) the TRANS_ENA bit is not taken into account and shadowing occurs only if TRANS_EN_IN pin is high (update triggered by MSCSS Timer0 match3 output of TRANS_EN_OUT of previous PWM block). If TRANS_ENA_SEL is low shadowing is controlled via software.
Page 435: Pwm Counter Synchronization
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) MTCHDEACT 16-bit internal counter PWM0 MTCHACT PWM0 output Sync_in_0 Sync_out_0 Global programmable sync_delay PWM1 output Sync_in_1 Sync_out_1 Sync_out_0 Fig 111.PWM operation 4.1 PWM counter synchronization Several PWMs can be synchronized using TRANS_ENABLE_IN and TRANS_ENABLE_OUT (see Section 25–5.1...
Page 436: Center-Aligned Pwm
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) PWM in continuous mode, sync_out Write first configuration Configure PWM0 output 0, activated, sync_in to PWM, duty cycle 25% disable trap and carrier and shadow-register update triggered by timer match...
Page 437: Register Overview
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Timer1 output Internal PWM output Fig 113.Modulation of PWM and timer carrier Figure 25–113 illustrates the carrier signal (Timer1, 50% duty cycle) the internal PWM signal and the modulated output signal of the PWM. The flowchart below shows how to...
Page 438 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 357. Register overview: PWM (base address: 0xE00C 5000 (PWM0), 0xE00C 6000 (PWM1), 0xE00C 7000 (PWM2), 0xE00C 8000 (PWM3)) …continued Name Access Address Description Reset Value Reference PRSC 0x018 The prescale register defines the number 0x0000 FFFF Table 25–365...
Page 439 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 357. Register overview: PWM (base address: 0xE00C 5000 (PWM0), 0xE00C 6000 (PWM1), 0xE00C 7000 (PWM2), 0xE00C 8000 (PWM3)) …continued Name Access Address Description Reset Value Reference TRPCTLS 0x804 Mirror the synchronized TRPCTL register 0x0000 0000 Table 25–372...
Page 440: Pwm Shadow Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 357. Register overview: PWM (base address: 0xE00C 5000 (PWM0), 0xE00C 6000 (PWM1), 0xE00C 7000 (PWM2), 0xE00C 8000 (PWM3)) …continued Name Access Address Description Reset Value Reference INT_STATUS 0xF98 PWM interrupt status register 0x0000 0000 Table 10–93...
Page 441 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) active HIGH-level on the trans_enable_in pin of the PWM. If TRANS_ENA_SEL is cleared, the trans_enable_in pin is ignored and update of the shadow registers takes place when the TRANS_ENA bit is set AND the PWM counter starts a new cycle. This happens when the counter overflows, or on an active HIGH signal on the sync_in input pin (if enabled via the SYNC_SEL bit of the MODECTL register).
Page 442: Pwm Trap Control Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 359. Bits involved in shadow register update SYNC_SEL TRANS_ENA_SEL Update of registers TRANS_ENA bit TRANS_ENA bit (master mode) trans_enable_in signal (slave mode) 5.3 PWM trap control register The APB PWM has an external asynchronous input which is used to switch the selected PWM outputs to the not-active level.
Page 443: Pwm Capture Source Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 361. CAPCTL register bit description (0xE00C 5008 (PWM0), 0xE00C 6008 (PWM1), 0xE00C 7008 (PWM2), 0xE00C 8008 (PWM3)) * = reset value Symbol Access Value Description 31 to 8 reserved Reserved;...
Page 444: Pwm Control Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.6 PWM control register The CTRL register selects the active level for each output. It also allows mixing of the external carrier signal with the internal PWM generated signals. Table 25–363 shows the bit assignment of the CTRL register.
Page 445: Pwm Prescale Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.8 PWM prescale register The PWM has a prescale register. The PWM counter increments after ‘PRSC + 1’ PWM clock cycles are counted. Table 25–365 shows the bit assignment of the PRSC register.
Page 446: Pwm Match Active Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.11 PWM match active registers There are six MTCHACT registers per PWM; one for each PWM output. Each MTCHACT register can be programmed to contain the first value which is compared with the PWM counter to generate the corresponding PWM output and interrupt.
Page 447: Pwm Mode Control Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 370. CAPT0 - 3 register bit description (0xE00C 5300 - 30C (PWM0), 0xE00C 6300 - 30C (PWM1), 0xE00C 7300 - 30C (PWM2), 0xE00C 8300 - 30C (PWM3)) * = reset value...
Page 448: Pwm Capture Control Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 372. TRPCTLS register bit description (0xE00C 5804 (PWM0), 0xE00C 6804 (PWM1), 0xE00C 7804 (PWM2), 0xE00C 8804 (PWM3)) * = reset value Symbol Access Value Description 30 to 17 reserved Reserved;...
Page 449: Pwm Control Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 374. CAPTSRCS register bit description (0xE00C 580C (PWM0), 0xE00C 680C (PWM1), 0xE00C 780C (PWM2), 0xE00C 880C (PWM3)) * = reset value Symbol Access Value Description 30 to 6 reserved reserved;...
Page 450: Pwm Prescale Shadow Register
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.20 PWM prescale shadow register The PRSCS register is the shadow register of the PRSC register. It mirrors the values used in the PWM domain. See Section 25–5.1 for more information on the principle of shadow registers.
Page 451: Pwm Match Deactive Shadow Registers
UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) 5.23 PWM match deactive shadow registers The MTCHDEACTS registers are the shadow registers of the MTCHDEACT registers. They mirror the values used in the PWM domain. See Section 25–5.1 for more information about the principle of the shadow registers.
Page 452 UM10316 NXP Semiconductors Chapter 25: LPC29xx Pulse Width Modulator (PWM) Table 382. PWM Match interrupt sources Register Interrupt source Description 31 to 12 unused Unused MTCHDEACT5 PWM counter value matching MTCHDEACT5 MTCHDEACT0 PWM counter value matching MTCHDEACT0 MTCHACT5 PWM counter value matching MTCHACT5...
Page 453: Chapter 26: Lpc29Xx Analog-To-Digital Converter (Adc)
UM10316 Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. ADC0 is available in LPC2926/27/29, LPC2930, and LPC2939 only. 2.
Page 454: Clock Distribution
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) running or finished. The channel configuration register (ACC) is used to define the resolution of the individual channels and to enable them. Once the conversion scan is finished the resulting conversion data can be read from the ACD registers.
Page 455: Pin Description
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) 3. Pin description Table 384. ADC pins Symbol Pin name Direction Description ADC0 IN[7:0] IN0[7:0] analog input for 5.0 V ADC0, channel 7 to channel 0. ADC1/2 IN[7:0] IN1/2[7:0] analog input for 3.3 V ADC1/2, channel 7 to channel 0.
Page 456 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 385. Register overview: ADC (base address: 0xE00C 2000 (ADC0), 0xE00C 3000 (ADC1), 0xE00C 4000 (ADC2)) …continued Name Access Address Description Reset Reference offset value ACC8 0x020 ADC channel 8 configuration register 0x0000 Table 26–386...
Page 457: Adc Channel Configuration Register
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 385. Register overview: ADC (base address: 0xE00C 2000 (ADC0), 0xE00C 3000 (ADC1), 0xE00C 4000 (ADC2)) …continued Name Access Address Description Reset Reference offset value ACD15 0x23C ADC channel 15 conversion data register 0x0000 Table 26–388...
Page 458: Adc Channel-Compare Register
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 386. ACCn register bit description (ACC0 to 15, addresses 0xE00C 2000 to 0xE00C203C (ADC0), 0xE00C 3000 to 0xE00C303C (ADC1), 0xE00C 4000 to 0xE00C403C (ADC2)) …continued * = reset value Symbol...
Page 459: Adc Channel Conversion Data Register
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 387. COMPn register bit description (COMP0 to 15, addresses 0xE00C 2100 to 0xE00C213C (ADC0), 0xE00C 3100 to 0xE00C313C (ADC1), 0xE00C 4100 to 0xE00C413C (ADC2)) * = reset value Symbol Access Value...
Page 460: Compare-Status Clear Register
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 389. COMP_STATUS register bit description (COMP_STATUS addresses 0xE00C 2300 (ADC0), 0xE00C 3300 (ADC1), 0xE00C 4300 (ADC2)) …continued * = reset value Symbol Access Value Description COMP_STATUS_0 Compare match of channel 0 No compare match of channel 0 4.5 Compare-status clear register...
Page 461 UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 391. ADC_CONFIG register bit description (ADC_CONFIG addresses, 0xE00C 2400 (ADC0), 0xE00C 3400 (ADC1), 0xE00C 4400 (ADC2) * = reset value Symbol Access Value Description 31 to 16 reserved Reserved; do not modify. Read as logic 0...
Page 462: Adc Control Register
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) 4.7 ADC control register The ADC_CONTROL register controls the ADC operation modes. It contains three bits. • The start bit (0): when set to 1 the ADC conversion is started. •...
Page 463: Adc Interrupt Bit Description
UM10316 NXP Semiconductors Chapter 26: LPC29xx Analog-to-Digital Converter (ADC) Table 393. ADC_STATUS register bit description (ADC_STATUS addresses, 0xE00C 2408 (ADC0), 0xE00C 3408 (ADC1), 0xE00C 4408 (ADC2) * = reset value Symbol Access Value Description 31 to 2 reserved Reserved; do not modify. Read as logic 0...
Page 464: Chapter 27: Lpc29Xx Quadrature Encoder Interface (Qei)
UM10316 Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The MSCSS includes a quadrature encoder interface (QEI) with the following features: •...
Page 465 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) VELOCITY velocity interrupt TIMER (TIM_Int) VELOCITY RELOAD low velocity interrupt VELOCITY (LVEL_Int) COMPARE VELOCITY CAPTURE index Ph A DIGITAL VELOCITY QUAD FILTER COUNTER Ph B DECODER BASE_MSCSS_CLK encoder clock interrupt...
Page 466: Functional Description
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 4. Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel.
Page 467: Digital Input Filtering
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 397. Encoder direction DIR bit DIRINV bit direction forward reverse reverse forward 4.1.2 Digital input filtering All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of sample clocks is user programmable from 1 to 4,294,967,295.
Page 468: Velocity Compare
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Fig 117.Encoder and velcoity divider operation The following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges) where: •...
Page 469: Pin Description
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 5. Pin description Table 398. QEI pin description Pin name Description 6. Register overview Table 399. Register overview: QEI (base address 0xE00C 9000) Symbol Access Address offset Description Control registers...
Page 470: Qei Configuration (Qeiconf)
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 400. QEI Control Register (QEICON - address 0xE00C 9000) Symbol Description Reset value 4:31 reserved RESI Reset index counter. When set = 1, resets the index counter to all zeros.
Page 471: Qei Maximum Position (Qeimaxpos)
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 403. QEI Position Register (QEIPOS - address 0xE00C 900C) Symbol Description Reset value 0:31 Current position value. 6.5 QEI Maximum Position (QEIMAXPOS) This register contains the maximum value of the encoder position. In forward rotation the position register resets to zero when the position register exceeds this value.
Page 472: Qei Index Count (Inxcnt)
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) 6.9 QEI Index Count (INXCNT) This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation. Table 408. QEI Index Count Register (CMPOS - address 0xE00C 9020)
Page 473: Qei Velocity Capture (Qeicap)
UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 412. QEI Velocity Register (QEIVEL - address 0xE00C 9030) Symbol Description Reset value 0:31 Current velocity pulse count. 6.14 QEI Velocity Capture (QEICAP) This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer...
Page 474 UM10316 NXP Semiconductors Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) Table 416. QEI Interrupt bits Symbol Description 13:31 reserved POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.
Page 475: Chapter 28: Lpc29Xx Flash/Eeprom
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM UM10316 Chapter 28: LPC29xx Flash/EEPROM Rev. 3 — 19 October 2010 User manual 1. How to read this chapter Flash configurations vary for the different LPC29xx parts. Table 417. Feature overview Part Flash size...
Page 476: Flash Memory Layout
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM The flash memory consists of the embedded flash memory (flash), EEPROM, and a controller (the FMC) to control access to both. The EEPROM for the LPC29xx contains one 16 kB EEPROM block. The controller can be accessed in two ways: either by register...
Page 477: Flash Memory Reading
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 419. Flash sector overview Sector Sector Sector base number size address (kB) 0x2000 0000 0x2000 2000 0x2000 4000 0x2000 6000 0x2000 8000 0x2000 A000 0x2000 C000 0x2000 E000 0x2001 0000 0x2002 0000...
Page 478: Erase Sequence (For One Or More Sectors)
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Normally the sectors are protected against write actions. Before a write is started, the corresponding sector(s) must be unprotected, after which protection can be enabled again. Protection is automatically enabled on a reset. During a write (erase/burn) operation the internal clock of the flash must be enabled.
Page 479: Flash Signature Generation
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Enable flash clock Unprotect sectors Write data to page for each page to be programmed Wait for burning Start burning page Disable flash clock to finish Fig 120. Flash-memory burn sequence 2.4 Flash signature generation The flash module contains a built-in signature generator.
Page 480: Flash Memory Index-Sector Features
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Generation of an interrupt can be enabled (INT_SET_ENABLE register) or disabled (INT_CLR_ENABLE register) for each of these interrupt sources. The interrupt status is always available even if the corresponding interrupt is disabled. INT_STATUS indicates the raw, unmasked interrupt status.
Page 481: Index Sector Programming
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Flash index sector (FS_ISS bit set) 0x2000 1000 reserved page 7 0x2000 0E30 sector security: flash sectors 16-18 0x2000 0E00 sector security: flash sectors 11-15 0x2000 0CB0 page 6 sector security: flash sectors 0-10...
Page 482: Index Sector Customer Info
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM #define PROTECT 0xFFFF FFFF /* unprotect index sector */ FMC_INX_SECTOR = UNPROTECT; FCTR = (FS_ISS| FS_LOADREQ | FS_WPB | FS_WEB | FS_WRE | FS_CS); FTCTR=(FTCTR |(1<<29)|(1<<28)); /* disable error correction! */ ... /* program the index sector */ /* re enable ECC */ FTCTR=(FTCTR &...
Page 483: Eeprom Functional Description
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM For every sector in flash memory there is a corresponding flash-word in the index sector that defines whether it is secured or not. Table 28–421 shows the link between index sector flash-words and sectors in flash memory.
Page 484: Addressing
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM really updating the memory, but only updating the temporary data register called the “page register”. The page register needs to be written with minimum 1 byte and maximum 8 bytes before the second operation which is called “erase/program” in this document can be used to actually update the non-volatile memory.
Page 485: Eeprom Operations
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM After the reset period the EEPROM devices will initialize themselves. Therefore the first 2 bytes (containing trimming information) of the last (protected) page of every EEPROM device will be read. The information that is read will be used as input values of the EEPROM devices, it will be ignored by the controller and is not visible on the AHB/VPB bus.
Page 486: Programming
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM A write operation causes an automatic post-increment of the address. This allows consecutive writes to the page register without the need of writing a new address for every write operation. Of course the address register could be written with another address value to write to another location.
Page 487: Reading
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Programming the page into memory takes a long time, therefore the corresponding interrupt can be enabled or the interrupt status bit can be polled to avoid stalling of the system bus. An erase/program operation starts by providing the MSBs of the address that selects the page in memory of a device.
Page 488: Error Responses
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM first read operation is started as result of writing the command register. The following read operations are started as result of reading the read data register to obtain the result of the previous read operations.
Page 489: Register Overview
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Polling is the easiest way to detect completion of an operation. This method is also used in the previous examples. 3. Register overview Table 423. Register overview: FMC (base address 0x2020 0000) Name...
Page 490: Flash Memory Control Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.1 Flash memory control register The flash memory control register (FCTR) is used to select read modes and to control the programming of flash memory. Flash memory has data latches to store the data that is to be programmed into it, so that the data-latch contents can be read instead of reading the flash memory contents.
Page 491: Unprotect Sector
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 424. FCTR register bit description (FTCR, address: 0x2020 0000) …continued * = reset value Symbol Access Value Description FS_WPB Program and erase protection. Program and erase enabled. Program and erase disabled. FS_ISS Index-sector selection.
Page 492: Flash Memory Program-Time Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.2 Flash memory program-time register The flash memory program-time register (FPTR) controls the timer for burning and erasing the flash memory. It also allows reading of the remaining burn or erase time. A built-in timer is used to control the burn time or erase time. The timer is started by writing the burn or erase time to the timer register FPTR.TR, and by enabling it through...
Page 493: Flash-Memory Clock Divider Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM To eliminate the delay associated with synchronizing flash-read data, a predefined number of wait-states must be programmed. These depend on flash-memory response time and system clock period. The minimum wait-states value can be calculated with the...
Page 494: Flash-Memory Bist Control Registers
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 28–428 shows the bit assignment of the FCRA register. Table 428. FCRA register bit description (FCRA, address: 0x2020 001C) * = reset value Symbol Access Value Description 31 to 12 reserved Reserved; do not modify. Read as logic 0...
Page 495: Flash-Memory Bist Signature Registers
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.7 Flash-memory BIST signature registers The flash-memory BIST signature registers return signatures as produced by the embedded signature generator. There is a 128-bit signature reflected by the four registers FMSW0, FMSW1, FMSW2 and FMSW3. The 16-bit signature is reflected by the FMS16 register.
Page 496: Eeprom Address Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 436. EEPROM command register bit description (EECMD - address 0x2020 0080) Bits Access Reset Field name Description value 31:5 reserved PAR_ACCESS Parallel access 0: no parallel access 1: the selected write or erase/program operation (no read!) is performed in parallel on all devices.
Page 497: Eeprom Write Data Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.10 EEPROM write data register The EEPROM write data register is used to write data into the page register (write operations). Writing this register will start the write operation as side-effect. If the post-increment bit in the command register is set, consecutive writes to this register can be done to write a burst of data.
Page 498: Eeprom Wait State Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM 3.12 EEPROM wait state register The EEPROM controller has no awareness of absolute time, while for EEPROM operations several minimum absolute timing constraints have to be met. Therefore it can only derive time from its clock by frequency division. The user must program the wait state fields to appropriate values in this wait state register.
Page 499: Eeprom Clock Divider Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM wait state 1 wait state 2 wait state 3 su_a_we_n VALID DATA VALID DATA VALID DATA su_di_we_n VALID DATA VALID DATA VALID DATA BE_N su_be_n_we_n BE_N WE_N hw_we_n WE_N h_i_we_n Fig 127. Wait states in a write operation 3.13 EEPROM clock divider register...
Page 500: Eeprom Power-Down Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Fclk ≈ ± ---------------------------------------------- - 375kH 6.67% divisionfactor Table 441. EEPROM clock divider register bit description (EECLKDIV - address 0x2020 0094) Bits Access Reset Field name Description value 31:16 - Reserved 15:0 CLKDIV Division factor (minus 1 encoded) 3.14 EEPROM power-down register...
Page 501: Eeprom Signature Register
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 444. EEPROM BIST stop address register bit description (EEMSSTOP - address 0x2020 00A0) Bits Access Reset Field name Description value STRTBIST BIST start bit Setting this bit will start the BIST. This bit is self-clearing.
Page 502: Flash And Eeprom Programming Details
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 446. FMC interrupt sources Register Interrupt source Description END_OF_MISR BIST signature generation has finished (flash) END_OF_BURN Page burning has finished (flash) END_OF_ERASE Erasing of one or more sectors has finished (flash) 4. Flash and EEPROM programming details 4.1 AHB programming...
Page 503: Un)Protecting Sectors
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM UNPROTECT sector(s) ERASE sector(s) PRESET data latches WRITE Word by hardware FlashWord complete? (auto) LOAD FlashWord Page complete? last FlashWord incomplete? LOAD FlashWord BURN page Sector(s) complete? PROTECT sector(s) Fig 128. Flash (AHB/APB) programming 4.1.1 (Un)protecting sectors...
Page 504: Erasing A Single Sector
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Table 447. Un(protect) trigger LOADREQ PROGREQ (un)protect A sector gets protected by writing an odd value to its base address, followed by the same trigger as for unprotecting. Although the flash module does not need the CRA clock to select a sector for (un)protecting, the CRA clock must already be enabled to ensure an active APB clock.
Page 505: Presetting Data Latches
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM Although the flash module does not need the CRA clock to select a sector for erasure, the CRA clock must already be enabled to ensure an active APB clock. 4.1.4 Presetting data latches When only a part of a page has to be programmed, the data latches for the rest of the page must be preset to logical 1’s.
Page 506: Index Sector Programming
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM ⋅ ⋅ ≥ 512 FPTR.TR tlw_web_write which is true for: tlw_web_write FPTR.TR ----------------------------------- - ⋅ 512 t The burning is started by writing a trigger value to the FCTR register. Table 452. Burn trigger value...
Page 507: Content Verification
UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM tp_cl_ry_rr × MISR duration ----------------------------- FMSSTOP - FMSSTART + 1 clock period When signature generation is triggered via AHB or VPB, the duration is expressed in ahb_clk cycles. Polling the INT_STATUS.END_OF_MISR bit can also be used to check the completion of the signature generation.
Page 508 UM10316 NXP Semiconductors Chapter 28: LPC29xx Flash/EEPROM sign = 0 FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP FOR i = 0 TO 126 nextSign[i] = f_Q[address][i] XOR sign[i+1] nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR sign[27] XOR sign[29] sign = nextSign signature128 = sign Fig 130.
Page 509: How To Read This Chapter
UM10316 Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Introduction The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions.
Page 510: Functional Description
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 4. Functional description This section describes the major functional blocks of the DMA Controller.
Page 511: Channel Logic And Channel Register Bank
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 4.1.4 Channel logic and channel register bank The channel logic and channel register bank contains registers and logic required for each DMA channel. 4.1.5 Interrupt request The interrupt request generates the interrupt to the ARM processor.
Page 512 UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 453. Endian behavior Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[7:0] 21212121...
Page 513: Error Conditions
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 453. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane 1/[31:24] 1/[15:0] 12341234 2/[23:16]...
Page 514: Channel Hardware
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 4.1.7 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic.
Page 515: Dma Request Signals
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 4.2.1 DMA request signals The DMA request signals are used by peripherals to request a data transfer. The DMA request signals indicate whether a single or burst transfer of data is required and whether the transfer is the last in the data packet.
Page 516 UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 455. Register overview: GPDMA (base address 0xE014 0000) …continued Name Access Address Description Reset state offset DMACSoftLSReq 0x02C DMA Software Last Single Request Register DMACConfig 0x030 DMA Configuration Register...
Page 517: Dma Interrupt Status Register (Dmacintstat - 0Xe014 0000)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 455. Register overview: GPDMA (base address 0xE014 0000) …continued Name Access Address Description Reset state offset DMACC6SrcAddr 0x1C0 DMA Channel 6 Source Address Register DMACC6DestAddr 0x1C4 DMA Channel 6 Destination Address Register...
Page 518: Dma Interrupt Terminal Count Request Clear
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 5.3 DMA Interrupt Terminal Count Request Clear Register (DMACIntTCClear - 0xE014 0008) The DMACIntTCClear Register is write-only and clears one or more terminal count interrupt requests. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the status register (DMACIntTCStat) to be cleared.
Page 519: Dma Raw Interrupt Terminal Count Status Register (Dmacrawinttcstat - 0Xe014 0014)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 5.6 DMA Raw Interrupt Terminal Count Status Register (DMACRawIntTCStat - 0xE014 0014) The DMACRawIntTCStat Register is read-only and indicates which DMA channel is requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the DMACIntTCStat Register contains the same information after masking.) A HIGH bit...
Page 520: Dma Software Burst Request Register 6.2.3 (Dmacsoftbreq - 0Xe014 0020)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 5.9 DMA Software Burst Request Register (DMACSoftBReq - 0xE014 0020) The DMACSoftBReq Register is read/write and enables DMA burst requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit.
Page 521: Dma Software Last Single Request Register (Dmacsoftlsreq - 0Xe014 002C)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 466. DMA Software Last Burst Request Register (DMACSoftLBReq - 0xE014 0028) Name Function 31:16 Reserved. Read undefined. Write reserved bits as zero. 15:0 SoftLBReq Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect.
Page 522: Dma Synchronization Register (Dmacsync - 0Xe014 0034)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 5.14 DMA Synchronization Register (DMACSync - 0xE014 0034) The DMACSync Register is read/write and enables or disables synchronization logic for the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0], DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0].
Page 523: Dma Channel Destination Address Registers (Dmaccxdestaddr - 0Xe014 01X4)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 470. DMA Channel Source Address Registers (DMACCxSrcAddr - 0xE014 01x0) Name Function 31:0 SrcAddr DMA source address. Reading this register will return the current source address. 5.17 DMA Channel Destination Address registers (DMACCxDestAddr -...
Page 524: Protection And Access Information
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 5.19.1 Protection and access information AHB access information is provided to the source and destination peripherals when a transfer occurs. The transfer information is provided by programming the DMA channel (the Prot bits of the DMACCxControl Register, and the Lock bit of the DMACCxConfig Register).
Page 525: Channel Configuration Registers (Dmaccxconfig - 0Xe014 01X0)
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 473. DMA channel control registers (DMACCxControl - 0xE014 01xC) …continued Name Function 20:18 SWidth Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other.
Page 526 UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Table 474. Channel Configuration registers (DMACCxConfig - 0xE014 01x0) Name Function 31:19 Reserved Reserved, do not modify, masked on read. Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests.
Page 527: Lock Control
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 5.20.1 Lock control The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig Register. When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock is deasserted.
Page 528: Disabling A Dma Channel
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 6.1.4 Disabling a DMA channel A DMA channel can be disabled in three ways: • By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used.
Page 529: Flow Control
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 7. Write the channel configuration information into the DMACCxConfig register. If the enable bit is set then the DMA channel is automatically enabled. 6.2 Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMA Controller where the packet length is programmed by software before the DMA channel is enabled.
Page 530: Peripheral-To-Memory Or Memory-To-Peripheral Dma Flow
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence occurs: 1. Program and enable the DMA channel. 2. Wait for a DMA request.
Page 531: Memory-To-Memory Dma Flow
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 9. If the transfer has completed it is indicated by the transfer count reaching 0 if the DMA Controller is performing flow control, or by the sending a DMA request if the peripheral is performing flow control.
Page 532: Address Generation
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller 1. Read the DMACIntTCStat Register to determine whether the interrupt was generated due to the end of the transfer (terminal count). A HIGH bit indicates that the transfer completed. If more than one request is active, it is recommended that the highest priority channels be checked first.
Page 533: Linked List Items
UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller The data to be transferred described by a LLI (referred to as the packet of data) usually requires one or more DMA bursts (to each of the source and destination).
Page 534 UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Fig 132. LLI example The first LLI, stored at 0x20000, defines the first block of data to be transferred, which is the data stored between addresses 0x0A200 and 0x0AE00: •...
Page 535 UM10316 NXP Semiconductors Chapter 29: LPC29xx General Purpose DMA (GPDMA) controller Because the next LLI address is set to zero, this is the last descriptor, and the DMA channel is disabled after transferring the last item of data. The channel is probably set to generate an interrupt at this point to indicate to the ARM processor that the channel can be reprogrammed.
Page 536: Chapter 30: Lpc29Xx Etm/Etb Interface
UM10316 Chapter 30: LPC29xx ETM/ETB interface Rev. 3 — 19 October 2010 User manual 1. How to read this chapter The contents of this chapter apply to all LPC29xx parts. 2. Features • Closely tracks the instructions that the ARM core is executing. •...
Page 537: Etb Configuration
UM10316 NXP Semiconductors Chapter 30: LPC29xx ETM/ETB interface Table 477. ETM configuration Resource description Qty. Pairs of address comparators Data Comparators Memory Map Decoders Counters Sequencer Present External Inputs 4 (Not brought out) External Outputs 4 (Not brought out) FIFOFULL Present...
Page 538: Register Description
UM10316 NXP Semiconductors Chapter 30: LPC29xx ETM/ETB interface 6. Register description 6.1 ETM registers Please refer to ARM9 Embedded Trace Macrocell (ETM9) Technical Reference manual published by ARM 6.2 ETB registers Please refer to Embedded Trace Buffer Technical Reference manual published by ARM.
Page 539: Abbreviations
UM10316 Chapter 31: Supplementary information Rev. 3 — 19 October 2010 User manual 31.1 Abbreviations Table 478. Abbreviations Acronym Description Analog to Digital Converter BEMF Back Electromotive Force BIST Built-In Self Test BLDCM Brushless Direct Current Motor BSDL Boundary-Scan Description Language Controller Area Network, see Ref.
Page 540: Glossary
UM10316 NXP Semiconductors Chapter 31: Supplementary information 31.2 Glossary ADC — Analog to Digital Converter; converts an analog input value to a discrete integer value. Atomic action — A number of software instructions executed without the possibility to interrupt them. A common solution is to disable the interrupts before this instruction sequence, and to restore the interrupt allowance afterwards.
Page 541: References
[10] Maxon EC-max Datasheet, Maxon Motor AG 2005 [11] TrenchMos transistor BUK7528-55A Datasheet, NXP 2000 [12] MSCSS Requirement Specification v0.1, Rolf van de Burgt, NXP Semiconductors - ABL 2005 [13] OsCan performance measurements on SJA2510 and SJA2020, Janett Honko, NXP...
Page 542: Legal Information
In no event shall NXP Semiconductors be liable for any indirect, incidental, NXP Semiconductors does not accept any liability related to any default, punitive, special or consequential damages (including - without limitation - lost...
Page 543: Tables
UM10316 NXP Semiconductors Chapter 31: Supplementary information 31.5 Tables Table 1. Ordering information .....5 ADC (address 0xFFFF 80AC)) ... . 44 Table 2.
Page 544 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 49. Branch clocks implemented in LPC29xx (x = Table 76. MASK_CLR register bit description (address CLK_CFG_ or CLK_STAT_) ....62 0xE000 2C80) .
Page 545 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 108.SMBWST2Rn register bit description Table 128.USB Device Interrupt Priority register (SMBWRST1R0 to SMBWRST1R7, addresses (USBDevIntPri - address 0xE010 022C) bit 0x6000 0008, 0x6000 0024, 0x6000 0040, description ......166 0x6000 005C, 0x6000 0078, 0x6000 0094, Table 129.USB Endpoint Interrupt Status register...
Page 546 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 152.USB DMA Request Clear register (USBDMARClr Table 182.Register overview: USB Host (base address - address 0xE010 0254) bit description ..177 0xE010 0000) ......214 Table 153.USB DMA Request Set register (USBDMARSet -...
Page 547 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 204.TC register description (addresses: 0xE004 1004 (SPI2)) ......262 (timer 0), 0xE004 2004 (timer 1), 0xE004 3004 Table 218.RX_FIFO_READMODE register bit description...
Page 548 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 238.UARTn Line Status Register (U0LSR - address 0xE008 0000 (CAN0) , 0xE008 1000 (CAN1)) . . 0xE004 5014, U1LSR - 0xE004 6014, Read Only) bit description ......280 Table 265.Register overview: CANAFM Look-up table...
Page 549 UM10316 NXP Semiconductors Chapter 31: Supplementary information addresses 0xE008 0038, 0xE008 0048, 0xE008 description (LIN0_LCFG, address 0xE008 9004, 0058 (CAN0), and 0xE008 1038, 0xE008 1048, LIN1_LCFG, address 0xE008 A004) ..365 0xE008 1058 (CAN1)) ....333 Table 308.LIN master-controller command register bit...
Page 550 UM10316 NXP Semiconductors Chapter 31: Supplementary information address 0xE008 901C, LU1LCR - 0xE008 Table 351.Master Transmitter mode ....411 A01C) bit description ....382 Table 352.Master Receiver mode.
Page 551 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 374.CAPTSRCS register bit description (0xE00C Table 393.ADC_STATUS register bit description 580C (PWM0), 0xE00C 680C (PWM1), 0xE00C (ADC_STATUS addresses, 0xE00C 2408 780C (PWM2), 0xE00C 880C (PWM3)) ..449 (ADC0), 0xE00C 3408 (ADC1), 0xE00C 4408 Table 375.CTRLS register bit description (0xE00C 5810...
Page 552 UM10316 NXP Semiconductors Chapter 31: Supplementary information Table 427.FBWST register bit description (FBWST, address: Register (DMACIntTCClear - 0xE014 0008) . 518 0x2020 0010) ......493 Table 459.DMA Interrupt Error Status Register...
Page 553 UM10316 NXP Semiconductors Chapter 31: Supplementary information 31.6 Figures Fig 1. LPC2917/19/01 block diagram ....8 Fig 49. LPC29xx USB OTG port configuration: USB port 1 Fig 2.
Page 554 UM10316 NXP Semiconductors Chapter 31: Supplementary information Fig 93. I C bus configuration .....387 Fig 94. Format in the Master Transmitter mode..388 Fig 95.
Page 555: Table Of Contents
UM10316 NXP Semiconductors Chapter 31: Supplementary information 31.7 Contents Chapter 1: LPC29xx Introductory information Introduction ......3 Block diagram .
Page 556 UM10316 NXP Semiconductors Chapter 31: Supplementary information Chapter 5: LPC29xx Power Management Unit (PMU) How to read this chapter ....62 Register overview ..... . 65 Power mode register (PM) .
Page 557 UM10316 NXP Semiconductors Chapter 31: Supplementary information Chapter 12: LPC29xx external Static Memory Controller (SMC) How to read this chapter ....140 Bank output enable assertion-delay control register .
Page 558 UM10316 NXP Semiconductors Chapter 31: Supplementary information 9.7.9 USB DMA Interrupt Enable register 13.3 Data transfer for IN endpoints ... 197 (USBDMAIntEn - 0xE010 0294) ..179 DMA operation.
Page 559 UM10316 NXP Semiconductors Chapter 31: Supplementary information Chapter 14: LPC29xx USB Host controller How to read this chapter ....212 Pin description ..... . . 213 3.1.1...
Page 560 UM10316 NXP Semiconductors Chapter 31: Supplementary information Chapter 18: LPC29xx SPI0/1/2 How to read this chapter ....255 SPI FIFO data register ....261 SPI receive FIFO POP register .
Page 561 UM10316 NXP Semiconductors Chapter 31: Supplementary information Extended frame-format explicit identifier 10.8 CAN acceptance-filter look-up table error section ......308 register .
Page 562 UM10316 NXP Semiconductors Chapter 31: Supplementary information 5.1.5 Wake-up interrupt handling....363 7.2.4 LIN master-controller checksum register . . . 372 5.1.6 Slave-not-responding error and the LIN master 7.2.5...
Page 563 UM10316 NXP Semiconductors Chapter 31: Supplementary information 10.2 Start master transmit function ... . 420 10.8.4 State : 0x58 ......423 10.3...
Page 564 UM10316 NXP Semiconductors Chapter 31: Supplementary information ADC interrupt bit description... . . 463 Chapter 27: LPC29xx Quadrature Encoder Interface (QEI) How to read this chapter ....464 QEI Position (QEIPOS) .
Page 565: Chapter 31: Supplementary Information
UM10316 NXP Semiconductors Chapter 31: Supplementary information 4.1.1 AHB slave interface ....510 5.14 DMA Synchronization Register (DMACSync - 4.1.2 Control logic and register bank ... 510 0xE014 0034).
Page 566 UM10316 NXP Semiconductors Chapter 31: Supplementary information 31.6 Figures ......553 31.7...

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