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NXP Semiconductors LPC824M201JHI33 User Manual

NXP Semiconductors LPC824M201JHI33 User Manual

Lpc82 series
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Table of Contents

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UM10800
LPC82x User manual
Rev. 1.2 — 5 October 2016
Document information
Info
Content
Keywords
LPC82x, LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20,
LPC822M101JDH20, LPC82x UM, LPC82x user manual, LPC820
Abstract
LPC82x User manual
User manual

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Summary of Contents for NXP Semiconductors LPC824M201JHI33

  • Page 1 UM10800 LPC82x User manual Rev. 1.2 — 5 October 2016 User manual Document information Info Content Keywords LPC82x, LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20, LPC822M101JDH20, LPC82x UM, LPC82x user manual, LPC820 Abstract LPC82x User manual...
  • Page 2 For sales office addresses, please send an email to: salesaddresses@nxp.com UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 2 of 487...
  • Page 3 – High-current sink driver (20 mA) on two true open-drain pins. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 3 of 487...
  • Page 4 – Timer-controlled self-wake-up from Deep power-down mode. – Power-On Reset (POR). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 4 of 487...
  • Page 5 The core includes a single-cycle multiplier and a system tick timer (SysTick). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 6 DMA request lines. Fig 1. LPC82x block diagram UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 6 of 487...
  • Page 7 The GPIO port and pin interrupt/pattern match registers are accessed by the ARM Cortex-M0+ single-cycle I/O enabled port (IOP). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 7 of 487...

  • Page 8: Table Of Contents

    The LPC82x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 31.5.4. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 8 of 487...
  • Page 9 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 9 of 487...
  • Page 10 The structure of the boot ROM APIs is shown in Figure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 10 of 487...
  • Page 11 Ptr to Function n Fig 3. Boot ROM structure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 11 of 487...
  • Page 12 8 locations in sector 0 of the flash. If the result is 0, then execution control is transferred to the user code. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 12 of 487...
  • Page 13 ISP session. The Unlock command is explained in Table 313 “UART ISP Unlock command”. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 13 of 487...
  • Page 14 (2) This step is included for backward compatibility and the response is ignored by the bootloader. Fig 4. Boot process flowchart UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 14 of 487...
  • Page 15 (INTENSET, address 0x4006 400C (USART0), 0x4006 800C (USART1), 0x4006C00C (USART2)) bit description” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 15 of 487...
  • Page 16 PSTAT - pin interrupt status match engine slice 1 interrupt UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 16 of 487...
  • Page 17 VTOR register, see the ARM Cortex-M0+ documentation (Ref. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 17 of 487...

  • Page 18: Xe000

    This register contains the 2-bit priority fields for interrupts 28 to 31. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 18 of 487...
  • Page 19 ISE_PININT5 Interrupt enable. ISE_PININT6 Interrupt enable. ISE_PININT7 Interrupt enable. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 19 of 487...
  • Page 20 ICE_PININT5 Interrupt disable. ICE_PININT6 Interrupt disable. ICE_PININT7 Interrupt disable. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 20 of 487...
  • Page 21 Interrupt pending set. ISP_PININT3 Interrupt pending set. ISP_PININT4 Interrupt pending set. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 21 of 487...
  • Page 22 ISP_I2C2 Interrupt pending clear. ISP_I2C3 Interrupt pending clear. Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 22 of 487...
  • Page 23 ISP_ADC_THCMP Interrupt active. ISP_ADC_OVR Interrupt active. ISP_SDMA Interrupt active. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 23 of 487...
  • Page 24 Interrupt Priority. 0 = highest priority. 3 = lowest priority. 31:30 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 24 of 487...
  • Page 25 Interrupt Priority. 0 = highest priority. 3 = lowest priority. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 25 of 487...
  • Page 26 Interrupt Priority. 0 = highest priority. 3 = lowest priority. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 26 of 487...
  • Page 27 2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input options: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 27 of 487...
  • Page 28 Table 96 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 28 of 487...
  • Page 29 Remark: The main clock frequency is limited to 100 MHz. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 29 of 487...
  • Page 30 Section 5.6.6 “Watchdog oscillator control register” Section 5.6.5 “System oscillator control register” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 30 of 487...
  • Page 31 Table 35 UARTCLKDIV 0x094 USART clock divider Table 36 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 31 of 487...
  • Page 32 0x190 GPIO Pin Interrupt Select register 6 Table 49 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 32 of 487...
  • Page 33 SPI0 reset control Assert the SPI0 reset. Clear the SPI0 reset. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 33 of 487...
  • Page 34 Assert the analog comparator reset. Clear the analog comparator controller reset. Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 34 of 487...
  • Page 35 00000: Division ratio M = 1 11111: Division ratio M = 32 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 35 of 487...
  • Page 36 (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 37 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 38 Trim value 0x80, then flash will reprogram 31:8 Reserved 0x00 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 38 of 487...
  • Page 39 Crystal Oscillator (SYSOSC) Reserved. CLKIN. External clock input. 31:2 Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 39 of 487...
  • Page 40 Enable main clock source update No change Update clock source 31:1 Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 40 of 487...
  • Page 41 Enables clock for GPIO port registers and GPIO pin interrupt registers. Disable Enable UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 41 of 487...
  • Page 42 Enable ACMP Enables clock to analog comparator. Disable Enable UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 42 of 487...
  • Page 43 1: Divide by 1. 255: Divide by 255. 31:8 Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 43 of 487...
  • Page 44 All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 44 of 487...
  • Page 45 Section 13.3.1 “Configure the USART clock and baud rate” Section 13.7.1 “Clocking and baud rates” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 45 of 487...
  • Page 46 (IOCONFILTR_PCLK) to the IOCON programmable glitch filter. The clocks can be shut down by setting the DIV bits to 0x0. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 46 of 487...
  • Page 47 25:0 System tick timer calibration value 31:26 - Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 47 of 487...
  • Page 48 Non-Maskable and a normal interrupt. This can be avoided by disabling the normal interrupt in the NVIC. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 48 of 487...
  • Page 49 Enabled PINT3 GPIO pin interrupt 3 wake-up Disabled Enabled UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 49 of 487...
  • Page 50 USART1 interrupt wake-up. Configure USART in synchronous slave mode. Disabled Enabled UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 50 of 487...
  • Page 51 Table 253) is set. See Section 17.5.3 for details. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 51 of 487...
  • Page 52 Powered down SYSOSC_PD Crystal oscillator wake-up configuration Powered Powered down UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 52 of 487...
  • Page 53 Powered down FLASH_PD Flash power down Powered Powered down UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 53 of 487...
  • Page 54 0x0000 8221 = LPC822M101JHI33 0x0000 8242 = LPC824M201JDH20 0x0000 8222 = LPC822M101JDH20 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 54 of 487...
  • Page 55 1.8 V. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 55 of 487...
  • Page 56 The LPC82X uses the system PLL to create the clocks for the core and peripherals. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 57 Power-down configuration register (Table 54). In this mode, the internal current UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 57 of 487...
  • Page 58       Fclkout Fclkin FCCO UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 58 of 487...
  • Page 59 24 MHz 00001(binary) 10 (binary) 192 MHz 24 MHz UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 59 of 487...
  • Page 60 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 61 SLEEPDEEP = 1 to either deep-sleep or power-down or to enter the Deep power-down mode, use the PCON register (Table 61). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 61 of 487...
  • Page 62 WAKEUP pin to hold it HIGH. In addition, pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 62 of 487...
  • Page 63 Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 63 of 487...
  • Page 64 For a list of all wake-up sources: Table 59 “Wake-up sources for reduced power modes” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 64 of 487...
  • Page 65 Table 63 register. Also includes bits for general purpose storage. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 65 of 487...
  • Page 66 Only a cold boot - when all power has been completely removed from the chip - will reset the general purpose registers. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 66 of 487...
  • Page 67 IRC or the external clock input. Disabled. Enabled. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 67 of 487...
  • Page 68 SysOsc software configurable UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 68 of 487...
  • Page 69 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 69 of 487...
  • Page 70 The watchdog oscillator can be left running in Deep-sleep mode if required for the WWDT. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 70 of 487...
  • Page 71 Power-down mode in the PDSLEEPCFG UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 72 WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 73 (POR) trip point, a system reset will be triggered and the chip re-boots. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 73 of 487...
  • Page 74 Remark: The RESET pin has no functionality in Deep power-down mode. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 74 of 487...
  • Page 75 Remark: The switch matrix is reset by a system reset from the RESET pin as well as all other resets. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 75 of 487...
  • Page 76 GPIO pins, and the debug SWD pins. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 76 of 487...
  • Page 77 For fixed-pin analog functions, the switch matrix enables the analog input or output and disables the digital pad. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 77 of 487...
  • Page 78 It is not allowed to connect more than one output or bidirectional function to a pin. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 79 Table 74 SCT_OUT1 SCT output 1. PINASSIGN8 Table 75 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 79 of 487...
  • Page 80 – If a fixed-pin function is deselected, any movable function can be assigned to its port and pin. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 80 of 487...
  • Page 81 0xFFFF FFFF Table 76 functions SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 81 of 487...
  • Page 82 The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 82 of 487...
  • Page 83 The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 83 of 487...
  • Page 84 The following pins are available: PIO0_0 (= 0) to PIO0_28 (= 0x1C). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 84 of 487...
  • Page 85 PIO0_0 (= 0) to PIO0_28 (= 0x1C). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 85 of 487...
  • Page 86 PIO0_0 (= 0) to PIO0_28 (= 0x1C). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 86 of 487...
  • Page 87 I2C0_SCL function select. I2C0_SCL enabled on pin PIO0_10. I2C0_SCL disabled. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 87 of 487...
  • Page 88 ADC_11 enabled on pin PIO0_4. ADC_11 disabled. 31:25 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 88 of 487...
  • Page 89 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 89 of 487...
  • Page 90 PIO0_10 and PIO0_11, which do not have a programmable pull-up resistor. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 91 (S_MODE) to minimize the effect of the potential extra clock cycle. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 92 I/O configuration for pin 0x0000 0090 Table 99 PIO0_0/ACMP_I0 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 92 of 487...
  • Page 93 Table 93 PIO0_16 0x024 Table 92 PIO0_17 0x000 Table 83 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 93 of 487...
  • Page 94 Open-drain mode enabled. Remark: This is not a true open-drain mode. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 94 of 487...
  • Page 95 Input inverted (HIGH on pin reads as 0, LOW on pin reads as Reserved. 0b001 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 95 of 487...
  • Page 96 Input inverted (HIGH on pin reads as 0, LOW on pin reads as UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 97 Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. Hysteresis. Disable. Enable. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 97 of 487...
  • Page 98 Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 98 of 487...
  • Page 99 PIO0_3 register (PIO0_3, address 0x4004 4014) bit description Symbol Value Description Reset value Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 99 of 487...
  • Page 100 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 100 of 487...
  • Page 101 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 101 of 487...
  • Page 102 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 102 of 487...
  • Page 103 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 103 of 487...
  • Page 104 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 104 of 487...
  • Page 105 IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 105 of 487...
  • Page 106 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 106 of 487...
  • Page 107 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 107 of 487...
  • Page 108 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 108 of 487...
  • Page 109 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 109 of 487...
  • Page 110 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 110 of 487...
  • Page 111 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 111 of 487...
  • Page 112 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 112 of 487...
  • Page 113 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 113 of 487...
  • Page 114 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 114 of 487...
  • Page 115 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 115 of 487...
  • Page 116 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 116 of 487...
  • Page 117 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 117 of 487...
  • Page 118 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 118 of 487...
  • Page 119 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 119 of 487...
  • Page 120 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 120 of 487...
  • Page 121 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 121 of 487...
  • Page 122 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 122 of 487...
  • Page 123 IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 123 of 487...
  • Page 124 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...

  • Page 125: Xa000

    Any write will clear the pin’s output bit if the value written is all zeros, else it will set the pin’s output bit. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 125 of 487...
  • Page 126 0s. Writing these registers loads the output bits of the pins written to, regardless of the Mask register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 126 of 487...
  • Page 127 Output bits can be cleared by writing ones to these write-only registers, regardless of MASK registers. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 127 of 487...
  • Page 128 Direction bits can be set by writing ones to these write-only registers. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 129 Writing ones to a port’s SET register sets output bits. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 129 of 487...
  • Page 130 To make a decision based on multiple pins, read and mask a PORT register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 131 49). The pin selection process is the same for pin interrupts and the pattern match engine. The two features are mutually exclusive. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 131 of 487...
  • Page 132 You can configure up to eight pins total using the PINTSEL registers in the SYSCON block for these features. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 132 of 487...
  • Page 133 A pin interrupt for this slice is asserted when the minterm evaluates as true. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 133 of 487...
  • Page 134 Fig 12. Pattern match engine connections UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 134 of 487...
  • Page 135 GPIO port pins or another pin function depending on the switch matrix configuration. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 136 If this combination is detected, the interrupt associated with bit slice 7(PININT7_IRQ) will be asserted. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 136 of 487...
  • Page 137 0 = Edge sensitive 1 = Level sensitive 31:8 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 137 of 487...
  • Page 138 If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 139 If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is selected. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 139 of 487...
  • Page 140 Write 1: clear rising edge detection for this pin. 31:8 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 140 of 487...
  • Page 141 SEL_PMATCH and ENA_RXEV of this register should be left at 0 to conserve power. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 141 of 487...
  • Page 142 Reserved Software should not write 1s to unused bits. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 142 of 487...
  • Page 143 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 143 of 487...
  • Page 144 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 144 of 487...
  • Page 145 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 145 of 487...
  • Page 146 Two types of edge detection on each input are possible: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 146 of 487...
  • Page 147 NVIC is raised if the minterm evaluates as true. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 147 of 487...
  • Page 148 0x3). This bit is cleared after one clock cycle. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 149 0x3). This bit is cleared after one clock cycle. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 150 0x3). This bit is cleared after one clock cycle. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 151 0x3). This bit is cleared after one clock cycle. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 152 Write to disable falling-edge interrupts. Write to select low-active. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 152 of 487...
  • Page 153 – CFG7: 111 - event (any edge, non-sticky) on the selected input (input 7) for bit slice 7 • PMCTRL register (Table 138): UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 153 of 487...
  • Page 154 Fig 14. Pattern match engine examples: sticky edge detect UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 154 of 487...
  • Page 155 Fig 16. Pattern match engine examples: Windowed non-sticky edge detect evaluates as false UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 156 The DMA can use trigger input multiplexing to sequence DMA transactions without the use of interrupt service routines. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 156 of 487...
  • Page 157 DMA channel 17 INP_N Fig 18. DMA trigger multiplexing UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 157 of 487...
  • Page 158 DMA channel 0. Selects from ADC, SCT, ACMP, pin interrupts, and DMA requests. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 158 of 487...
  • Page 159 (n = 0 to 8). All other values are reserved. ADC_SEQA_IRQ ADC_SEQB_IRQ SCT_DMA0 SCT_DMA1 ACMP_O PININT0 PININT1 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 159 of 487...
  • Page 160 SCT_PIN3. Assign to pin using the switch matrix. ADC_THCMP_IRQ ACMP_O UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 160 of 487...
  • Page 161 Symbol Value Description Reset value ARM_TXEV DEBUG_HALTED 31:4 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 161 of 487...
  • Page 162 Table 145 for a list of possible trigger input sources. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 162 of 487...
  • Page 163 DMA_ITRIG_INMUX13 I2C2_SLV_DMA DMA_ITRIG_INMUX14 I2C2_MST_DMA DMA_ITRIG_INMUX15 I2C3_SLV_DMA DMA_ITRIG_INMUX16 I2C3_MST_DMA DMA_ITRIG_INMUX17 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 163 of 487...
  • Page 164 UART, SPI, and I2C peripherals. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 164 of 487...
  • Page 165 This process repeats as each descriptor is exhausted as long as reload is selected in the transfer configuration for each new descriptor. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 165 of 487...
  • Page 166 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 166 of 487...
  • Page 167 To use channel chaining, first configure DMA channels x and y as if no channel chaining would be used. Then: • For channel x: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 167 of 487...

  • Page 168: X5000

    SRAM address of the channel configuration table. Table 156 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 168 of 487...

  • Page 169: X4008

    Control and status register for DMA channel 6. Table 172 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 169 of 487...
  • Page 170 Control and status register for DMA channel 16. Table 172 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 170 of 487...
  • Page 171 Transfer configuration register for DMA channel 17. Table 173 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 171 of 487...
  • Page 172 18 channels, the table must begin on a 512 byte boundary. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 172 of 487...
  • Page 173 0 = disabled. 1 = enabled. 31:18 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 173 of 487...
  • Page 174 0 = not busy. 1 = busy. 31:18 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 174 of 487...
  • Page 175 INTENSET0. Bit n corresponds to DMA channel n. 31:18 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 175 of 487...
  • Page 176 If, during DMA transmission, a Channel Descriptor is found with CFGVALID UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 177 1 = aborts DMA operations on channel n. 31:18 - Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 177 of 487...
  • Page 178 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 178 of 487...
  • Page 179 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 179 of 487...
  • Page 180 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 180 of 487...
  • Page 181 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 181 of 487...
  • Page 182 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 183 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 183 of 487...
  • Page 184 Send and receive lines are connected to DMA request lines. See Table 148. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 184 of 487...
  • Page 185 4. In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 185 of 487...
  • Page 186 Configure the USART in either asynchronous mode or synchronous mode. See Table 176. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 186 of 487...
  • Page 187 USART RTS signal is configured to appear on a device pin. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 187 of 487...
  • Page 188 Un_TXD. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 188 of 487...
  • Page 189 USART2 block U_PCLK = FRGCLKDIV/(1+MULT/DIV) Fig 21. USART block diagram UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 189 of 487...
  • Page 190 0x02C Address register for automatic address matching. Table 187 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 190 of 487...
  • Page 191 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 191 of 487...
  • Page 192 OE will also remain asserted if another transmit begins before it is de-asserted. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 192 of 487...
  • Page 193 The CTL register controls aspects of USART operation that are more likely to change during operation. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 193 of 487...
  • Page 194 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 194 of 487...
  • Page 195 This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 195 of 487...
  • Page 196 The INTENCLR register is used to clear bits in this register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 196 of 487...
  • Page 197 The INTENCLR register is used to clear bits in the INTENSET register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 198 Remark: Reading this register changes the status flags in the RXDATSTAT register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 199 TXDAT. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 199 of 487...
  • Page 200 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 200 of 487...
  • Page 201 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 201 of 487...
  • Page 202 FRG. See Figure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 202 of 487...
  • Page 203 The receiver DMA request is asserted when received data is available to be read. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 203 of 487...
  • Page 204 The UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 205 At 16x oversampling, there are several UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 206 Generally speaking, it is recommended to use the highest oversampling where the rate error is acceptable in the system. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 206 of 487...
  • Page 207 (slave mode) (SPI0/1 clock enable) Fig 23. SPI clocking UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 207 of 487...
  • Page 208 SPI functions to pins on the part. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 208 of 487...
  • Page 209 PINASSIGN6 Table 73 Slave Select 1. to pin UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 209 of 487...
  • Page 210 1 to that bit position UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 210 of 487...
  • Page 211 Reverse. Data is transmitted and received in reverse order (LSB first). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 211 of 487...
  • Page 212 Timing details are shown in: Section 14.7.2.1 “Pre_delay and Post_delay” Section 14.7.2.2 “Frame_delay” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 212 of 487...
  • Page 213 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 213 of 487...
  • Page 214 Stalled status flag. This indicates whether the SPI is currently in a stall condition. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 214 of 487...
  • Page 215 An interrupt will be generated if the transmitter underruns. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 215 of 487...
  • Page 216 For details on the slave select process, see Section 14.7.4. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 216 of 487...
  • Page 217 Reserved, the value read from a reserved bit is not defined. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 217 of 487...
  • Page 218 Remark: The active state of the SSEL3 pin is configured by bits in the CFG register. SSEL3 asserted. SSEL3 not asserted. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 218 of 487...
  • Page 219 TXDAT. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 219 of 487...
  • Page 220 For details on clocking, see Section 14.7.3 “Clocking and data rates”. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 220 of 487...
  • Page 221 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 221 of 487...
  • Page 222 MISO Data frame Fig 25. Basic SPI operating modes UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 222 of 487...
  • Page 223 Pre_delay Data frame Post_delay Fig 26. Pre_delay and Post_delay UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 223 of 487...
  • Page 224 First data frame Frame_delay Second data frame Fig 27. Frame_delay UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 224 of 487...
  • Page 225 First data frame Transfer _delay Second data frame Fig 28. Transfer_delay UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 225 of 487...
  • Page 226 RXSSEL_N field of the RXDAT register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 226 of 487...
  • Page 227 Stalls are reflected in the STAT register by the Stalled status flag, which indicates the current SPI status. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 227 of 487...
  • Page 228 Second data frame Fig 29. Examples of data stalls UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 228 of 487...
  • Page 229 The peripheral clock for the I2C is the system clock (see Figure 30). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 229 of 487...
  • Page 230 The result is an SCL clock of 375 kHz. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 230 of 487...
  • Page 231 See Table 202. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 231 of 487...
  • Page 232 5. Acknowledge (“ack”) the data by setting SLVCONTINUE = 1 in the slave control register. See Table 216. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 232 of 487...
  • Page 233 Table 51 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 233 of 487...
  • Page 234 The architecture of the I2C-bus interface is shown in Figure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 234 of 487...
  • Page 235 4028 (I2C1), 0x4007 0028 (I2C2), 0x4007 4028 (I2C3)) bit description” • Slave function registers: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 235 of 487...
  • Page 236 0x4005 0080 (I2C0), 0x4005 4080 (I2C1), 0x4007 0080 (I2C2), 0x4007 4080 (I2C3)) bit description” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 236 of 487...
  • Page 237 C slave function is disabled. Enabled. The I C slave function is enabled. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 237 of 487...
  • Page 238 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 238 of 487...
  • Page 239 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 239 of 487...
  • Page 240 Deep-sleep or Power-down mode could be entered at this time. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 240 of 487...
  • Page 241 Active. The Monitor function considers the I C bus to be active. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 241 of 487...
  • Page 242 Slave NACKed transmitted data. Send a Stop or Repeated Start. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 242 of 487...
  • Page 243 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 243 of 487...
  • Page 244 Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 244 of 487...
  • Page 245 EVENTTIMEOUTEN bit in the INTENSET register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 246 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 246 of 487...
  • Page 247 MSTSTART and MSTSTOP are not self-clearing flags. ORing in new data following a Start or Stop may cause undesirable side effects. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 247 of 487...
  • Page 248 Master function. These include the clock (SCL) high and low times, repeated Start setup time, and transmitted data setup time. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 248 of 487...
  • Page 249 9 clocks. Minimum SCL low time is 9 clocks of the I clock pre-divider. Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 249 of 487...
  • Page 250 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 250 of 487...
  • Page 251 Reserved. Read value is undefined, only zero should be written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 251 of 487...
  • Page 252 The SLVQUAL0 register can alter how Slave Address 0 is interpreted. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 252 of 487...
  • Page 253 C pins, and adds indication of Start, Repeated Start, and data NACK. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 253 of 487...
  • Page 254 C function clock rate / (SCL high time + SCL low time) UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 255 10-bit address is a complete match to the previous address before acknowledging the address. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 255 of 487...
  • Page 256 DMA. The DMA supports three DMA requests: data transfer in master mode, slave mode, and monitor mode. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 256 of 487...
  • Page 257 – Match events can be held until another qualifying event occurs. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 257 of 487...
  • Page 258 CLOCK PROCESSING SYSAHBCLKCTRL[8] Fig 32. SCT clocking UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 258 of 487...
  • Page 259 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 259 of 487...
  • Page 260 Capability of selecting a “greater-than-or-equal-to” match condition for the purpose of UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 260 of 487...
  • Page 261 SCT registers, the register function depends on the setting of certain other register bits: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 261 of 487...
  • Page 262 SCT match/capture mode register low counter 0x0000 0000 Table 232 16-bit UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 262 of 487...
  • Page 263 16-bit; REGMOD0 = 1 to REGMODE7 = 1 CAPCTRL7_H UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 263 of 487...
  • Page 264 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 264 of 487...
  • Page 265 CAPCTRL[7:0] Fig 36. SCT event configuration and selection registers UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 265 of 487...
  • Page 266 In the dual-counter mode, the events can be selected independently for each counter. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 267 The SCT output register to set or clear any of the SCT outputs or to read the state of the outputs. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 267 of 487...
  • Page 268 This bit is not used when the UNIFY bit is set. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 269 This is true regardless of what triggered the event. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 269 of 487...
  • Page 270 Writing a 1 to this bit clears the H counter. This bit always reads as 0. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 271 (event 0 = bit 16, event 1 = bit 17, event 7 = bit 23). 31:24 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 271 of 487...
  • Page 272 STOPT_L and STOP_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 272 of 487...
  • Page 273 32-bit read or write operation. In this case, the L and H registers count independently under the control of the other registers. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 273 of 487...
  • Page 274 If UNIFY = 1 in the CONFIG register, only the _L bits are used. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 275 If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. In this case, REGMODE_H is not used. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 275 of 487...
  • Page 276 1,..., output 5 = bit 5). 31:6 Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 276 of 487...
  • Page 277 (or even the same event) dictate that a given output should be both set and cleared at the same time. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 277 of 487...
  • Page 278 Clear output (or set based on the SETCLR5 field). Toggle output. 31:12 - Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 278 of 487...
  • Page 279 (event 0 = bit 0, event 1 = bit 1,..., event 7 = bit 7). 31:8 Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 279 of 487...
  • Page 280 H, STATE H, MATCH H, or the Output register when the H counter was not halted. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 280 of 487...
  • Page 281 BIDIR = 0 and the counter is cleared to zero upon reaching it limit condition. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 282 HEVENT bit in the corresponding EVn_CTRL register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 282 of 487...
  • Page 283 Selects the inputs elected by IOSEL. Selects the outputs selected by IOSEL. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 283 of 487...
  • Page 284 Based on a selected event, each SCT output can be set. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 284 of 487...
  • Page 285 See the OUTPUTCTRL register. 31:8 Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 285 of 487...
  • Page 286 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 286 of 487...
  • Page 287 Software must interfere to change out of this state. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 287 of 487...
  • Page 288 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 288 of 487...
  • Page 289 RISE or FALL Event can occur whenever HALT = 0 (A). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 289 of 487...
  • Page 290 0. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 291 – Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 291 of 487...
  • Page 292 – When the counters are halted, software can set any SCT output HIGH or LOW directly by writing to the OUT register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 292 of 487...
  • Page 293 6 events and match 0 used with autolimit function • 2 states UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 293 of 487...
  • Page 294 MAT2 is associated with event 1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 294 of 487...
  • Page 295 Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled event 5 is enabled in state 1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 295 of 487...
  • Page 296 For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in the STARTERP1 register (Table 51). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 296 of 487...
  • Page 297 If a window value is programmed, the feed must also occur after the watchdog counter passes that value. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 297 of 487...
  • Page 298 WDCLK and then synchronize it with PCLK, so that the CPU can read the WDTV register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 298 of 487...
  • Page 299 MOD register. The length of the delay depends on the selected watchdog clock WDCLK. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 299 of 487...
  • Page 300 The reload overwrite lock mechanism can only be disabled by a reset of any type. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 301 WDPROTECT. Cleared by software. Causes a chip external reset if WDRESET = 1. reset) UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 301 of 487...
  • Page 302 Table 51 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 302 of 487...
  • Page 303 WDT before control is returned to the interrupted task. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 303 of 487...
  • Page 304 WINDOW resets to the maximum possible WDTV value, so windowing is not in effect. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 305 = 0x3FF = 0x2000 Fig 47. Watchdog warning interrupt UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 305 of 487...
  • Page 306 Section 6.7.1 to enable the various power down modes. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 306 of 487...
  • Page 307 The self-wake-up timer can be clocked from two alternative clock sources: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 307 of 487...
  • Page 308 The oscillator must also be set to remain active in Deep power-down if needed. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 308 of 487...
  • Page 309 A read reflects the current value of the timer. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 309 of 487...
  • Page 310 Each channel operates independently from the other channels in one of the following modes: • Repeat interrupt mode. See Section 19.5.1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 310 of 487...
  • Page 311 LOAD bit to 1. No interrupt is generated when the INTVALn register is written. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 312 The reset values shown in Table 263 are POR reset values. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 312 of 487...
  • Page 313 This register contains the MRT load value and controls how the timer is reloaded. The load value is IVALUE -1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 313 of 487...
  • Page 314 The control register configures the mode for each MRT and enables the interrupt. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 315 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 315 of 487...
  • Page 316 Writing a 1 to this bit clears the interrupt request. 31:4 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 316 of 487...
  • Page 317 System Tick interrupt Fig 51. System tick timer block diagram UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 317 of 487...
  • Page 318 This register determines the clock source for the system tick timer. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 318 of 487...
  • Page 319 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 319 of 487...
  • Page 320 RELOAD = (system tick clock frequency  10 ms) 1 = (20 MHz  10 ms) 1 = 2000001 = 199999 = 0x00030D3F. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 320 of 487...
  • Page 321 Calibration is required after every power-up or wake-up from Deep power-down mode. See Section 21.3.4 “Hardware self-calibration”. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 321 of 487...
  • Page 322 6. Read the RESULT bits in the DAT1 register for the conversion result. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 323 Table 282 “A/D Conversion Sequence A Control Register (SEQA_CTRL, address 0x4001 C008) bit description” UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 323 of 487...
  • Page 324 ADC inputs can be configured as digital I/O pins and are 5 V tolerant. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 324 of 487...
  • Page 325 ADC hardware from the associated pin whenever a digital function is selected on that pin. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 325 of 487...
  • Page 326 The reset value reflects the data stored in used bits only. It does not include reserved bits content. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 326 of 487...
  • Page 327 1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 327 of 487...
  • Page 328 Reserved.Do not write a one to these bits. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 328 of 487...
  • Page 329 Remark: Set the BURST and SEQU_ENA bits at the same time. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 329 of 487...
  • Page 330 It will consequently always read-back as a zero. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 330 of 487...
  • Page 331 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 331 of 487...
  • Page 332 Remark: Set the BURST and SEQU_ENA bits at the same time. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 332 of 487...
  • Page 333 Bypass synchronization. The hardware trigger bypass is enabled. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 333 of 487...
  • Page 334 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 334 of 487...
  • Page 335 MODE bit in the corresponding ADSEQn_CTRL register since this will impact interrupt and overrun flag generation. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 335 of 487...
  • Page 336 MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 336 of 487...
  • Page 337 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 337 of 487...
  • Page 338 The OVERRUN fields for each channel are also replicated in the FLAGS register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 339 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 339 of 487...
  • Page 340 ADCMPINTEN bits associated with each channel in the INTEN register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 340 of 487...
  • Page 341 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 341 of 487...
  • Page 342 Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 342 of 487...
  • Page 343 In this register, threshold events selected in the ADCMPINTENn bits are described as follows: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 343 of 487...
  • Page 344 Threshold comparison interrupt enable. Disabled. Outside threshold. Crossing threshold. Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 344 of 487...
  • Page 345 Threshold comparison interrupt enable. Disabled. Outside threshold. Crossing threshold. Reserved UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 345 of 487...
  • Page 346 INTEN register. This bit is cleared by writing a 1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 346 of 487...
  • Page 347 This interrupt must be enabled in the INTEN register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 347 of 487...
  • Page 348 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 349 SEQn_ENA bit itself should only be set when the selected trigger input is in its INACTIVE UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 350 DMA engine). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 350 of 487...
  • Page 351 DMA using the scatter/gather linked lists. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 351 of 487...
  • Page 352 TRIGGER fields in the two SEQn_CTRL registers. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 352 of 487...
  • Page 353 Table 147 “SCT input mux registers 0 to 3 (SCT0_INMUX[0:3], address 0x4002 C020 (SCT0_INMUX0) to 0x4002 C02C (SCT0_INMUX3)) bit description”. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 353 of 487...
  • Page 354 Input 6 of the multiplexer connects the ADC channel 0 input. Input 7 is tied to ground. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 354 of 487...
  • Page 355 COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 355 of 487...
  • Page 356 Reserved. Write as 0. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 356 of 487...
  • Page 357 1/31. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 357 of 487...
  • Page 358 Selects the reference voltage Vref for the voltage ladder: Supply pin VDD VDDCMP pin 31:7 Reserved. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 358 of 487...
  • Page 359 The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 359 of 487...
  • Page 360 CR C CRC SUM Fig 55. CRC block diagram UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 360 of 487...
  • Page 361 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 361 of 487...
  • Page 362 1's complement for CRC sum: NO CRC_MODE = 0x0000 0015 CRC_SEED = 0x0000 0000 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 362 of 487...
  • Page 363 1's complement for CRC sum: YES CRC_MODE = 0x0000 0036 CRC_SEED = 0xFFFF FFFF UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 363 of 487...
  • Page 364 Bits 31:2 must be written back exactly as read. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 364 of 487...
  • Page 365 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 366 FOR i = 0 TO 30 nextSign[i] = f_Q[address][i] XOR sign[i + 1] UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 366 of 487...
  • Page 367 = f_Q[address][31] XOR sign[0] XOR sign[10] XOR sign[30] XOR sign[31] sign = nextSign signature32 = sign UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 367 of 487...
  • Page 368 The size of a sector is 1 KB and the size of a page is 64 Byte. One sector contains 16 pages. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 368 of 487...
  • Page 369 Hamming code. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 369 of 487...
  • Page 370 Important: any CRP change becomes effective only after the device has gone through a power cycle. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 370 of 487...
  • Page 371 High CRP1 CRP2 High CRP2 CRP3 CRP1 CRP2 CRP3 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 371 of 487...
  • Page 372 Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go" commands. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 372 of 487...
  • Page 373 "B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 374 Reads the plain binary code of the data stream, followed by the CMD_SUCCESS return code. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 374 of 487...
  • Page 375 (assuming that those pages have been erased previously). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 375 of 487...
  • Page 376 ISP, the RESET handler should do the following: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...

  • Page 377: Return Code Cmd_Success

    "I 2 3<CR><LF>" blank checks the flash sectors 2 and 3. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 377 of 487...

  • Page 378: Return Code Cmd_Success

    0x1000 8000 to the 4 bytes from the flash address 0x2000. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 378 of 487...

  • Page 379: Code_Read_Protection_Enabled

    If checksum value is 0xCBF43926, then the host will receive: "3421780262 <CR><LF>" UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 379 of 487...
  • Page 380 FLASH" command (IAP_CMD_CODE and four parameters for a total of five items in the UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 381 IAP command execution. The user should not use this space if IAP flash programming is used in the application. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 381 of 487...
  • Page 382 This command makes flash write/erase operation a two step process. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 382 of 487...
  • Page 383 Param3 is overwritten by the fixed value of 12 MHz, which is the IRC reference clock used by the flash controller. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 383 of 487...
  • Page 384 This command is used to read the part identification number. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 384 of 487...
  • Page 385 This command is used to compare the memory contents at two locations. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 386 Param2 is overwritten by the fixed value of 12 MHz, which is the IRC reference clock used by the flash controller. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 386 of 487...
  • Page 387 25.7.1.3 UART ISP data format The data stream is in plain binary format. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 387 of 487...
  • Page 388 Debug tools can write parts of the flash image to RAM and then execute the IAP call "Copy RAM to flash" repeatedly with proper offset. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 388 of 487...
  • Page 389 Power Profiles API. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 389 of 487...
  • Page 390 The power profile API provides functions to configure the system clock and optimize the system setting for lowest power consumption. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 390 of 487...
  • Page 391 The following definitions are needed when making set_pll power routine calls: /* set_pll mode options */ UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 391 of 487...
  • Page 392 PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and Param0 is returned as Result1. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 392 of 487...
  • Page 393 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 393 of 487...
  • Page 394 /* set_power result0 options */ #define PWR_CMD_SUCCESS #define PWR_INVALID_FREQ #define PWR_INVALID_MODE UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 394 of 487...
  • Page 395 PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 395 of 487...
  • Page 396 PLL_CMD_SUCCESS in result[0] and 24000 in result[1]. The new system clock is 24 MHz. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 396 of 487...
  • Page 397 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 397 of 487...

  • Page 398: X1400

    Ptr to Device Table n Fig 60. USART driver routines pointer structure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 398 of 487...
  • Page 399 Get the memory size needed by one UART instance. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 399 of 487...
  • Page 400 Send one Char through uart. This function is only returned after data is sent. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 401 0x0008 0004 ERR_UART_UNDERRUN Underrun error 0x0008 0005 ERR_UART_PARAM Parameter error UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 401 of 487...
  • Page 402 // reaching \0. A <LF> character is sent out after that. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 402 of 487...
  • Page 403 //0x02: RESERVED UART_CALLBK_T callback_func_pt; // callback function } UART_PARAM_T ; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 403 of 487...
  • Page 404 Ptr to Device Table n Fig 61. SPI driver routines pointer structure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 404 of 487...
  • Page 405 Set up SPI instance with provided memory and return the handle to this instance. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 405 of 487...
  • Page 406 This function is invoked by the user ISR. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 407 SPI CFG register. See Table 190. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 407 of 487...

  • Page 408: X4008

    To perform a DMA transfer for receive data, also enable the SPI transmit DMA channel, so that a SPI clock is generated. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 408 of 487...
  • Page 409 SPID_API_T * pSpiApi ; //define pointer to type API function addr table SPI_HANDLE_T* spi_handle; //handle to SPI API SPI_PARAM_T param; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 409 of 487...
  • Page 410 = 0; pSpiApi->spi_master_transfer(spi_handle, &param); while(!receivetag); //wait until receivetag is set UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 410 of 487...
  • Page 411 9. Set up the SPI parameter structure SPI_PARAM_T for the SPI: UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 411 of 487...
  • Page 412 = DMA_SW_ON | DMA_INT_A; //enable trigger for peripheral request and // DMA interrupt tsk.data_length = driver->buffer_size - 1; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 412 of 487...
  • Page 413 &param); while(!receivetag); //wait for receive tag to be set UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 413 of 487...
  • Page 414 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 414 of 487...
  • Page 415 Table 371 ErrorCode_t i2c_master_tx_rx_intr(I2C_HANDLE_T* , I2C_PARAM* , Interrupt I2C_RESULT*); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 415 of 487...
  • Page 416 (*i2c_get_mem_size)(void) ; //ramsize_in_bytes memory needed by I2C drivers UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 416 of 487...
  • Page 417 I2C Master Receive Polling Prototype ErrorCode_t i2c_master_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 417 of 487...
  • Page 418 When task is completed, the callback function is called. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 418 of 487...
  • Page 419 Receives data from master. When the task is completed, the function returns to the line after the call. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 419 of 487...
  • Page 420 When task is completed, the callback function is called. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 420 of 487...
  • Page 421 Description Configures the I2C duty-cycle registers (SCLH and SCLL). UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 421 of 487...
  • Page 422 ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT - 0x0006 0007 ERR_I2C_GENERAL_FAILURE Failure detected on I2C bus. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 422 of 487...
  • Page 423 ; uint8_t *buffer_ptr_send ; uint8_t *buffer_ptr_rec ; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 423 of 487...
  • Page 424 1. Enable the clock to the I2C peripheral. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 424 of 487...
  • Page 425 32 bit variable. When in slave UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 426 I2C_RESULT* is a containing the results after the function executes. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 426 of 487...
  • Page 427 PARAM structure, the callback functions will be invoked. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 427 of 487...
  • Page 428 If the amount of data exceed the receive buffer size, an error code will be returned. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 428 of 487...
  • Page 429 // disable timeout feature h->i2c_base->CFG &= ~BI2C_TIMEOUT_EN; return(LPC_OK) ; }//i2c_set_timeout UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 429 of 487...
  • Page 430 Ptr to Device Table n Fig 64. ADC driver routines pointer structure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 430 of 487...
  • Page 431 Memory size in bytes. Description The memory size for one ADC instance. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 431 of 487...
  • Page 432 Description Setup operation mode for ADC, then enable ADC. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 432 of 487...
  • Page 433 ADC interrupt must be enabled. This function is invoked by the user ISR. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 433 of 487...
  • Page 434 /*0x000F0004*/ ERR_ADC_INVALID_SETUP, /*0x000F0005*/ ERR_ADC_PARAM, /*0x000F0006*/ ERR_ADC_INVALID_LENGTH, /*0x000F0007*/ ERR_ADC_NO_POWER } ErrorCode_t; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 434 of 487...
  • Page 435 Low threshold 0 value. thr0_high: High threshold 0 value. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 435 of 487...
  • Page 436 //total number ADC channels, DMA req function is called for ADC DMA channel setup, then SEQx UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 436 of 487...
  • Page 437 The following callback function is invoked in the ADC sequence interrupt handler: typedef void (*ADC_CALLBK_T) (ErrorCode_t error_code, uint32_t num_channel ); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 437 of 487...
  • Page 438 4. Initialize ADC0: size_in_bytes = pAdcApi->adc_get_mem_size() ; //size_in_bytes/4 must be UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 438 of 487...
  • Page 439 // stop ADC SEQA now. adcr->INTEN &= ~SEQA_ENA; completiona_tag = 1; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 439 of 487...
  • Page 440 (!completiona_tag); // wait until ADC conversion is complete UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 440 of 487...
  • Page 441 LPC800. This pin is pulled up internally. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 441 of 487...
  • Page 442 GPIO, but it should not be held LOW on power-up or reset. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 443 MTB POSITION register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 443 of 487...
  • Page 444 0x0 independently of the SRAM memory area configured for trace. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 444 of 487...
  • Page 445 Ptr to Device Table n Fig 66. ROM pointer structure UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 445 of 487...
  • Page 446 Table 400. sidiv Routine sidiv Prototype int(*sidiv) (int32_t numerator, int32_t denominator); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 446 of 487...
  • Page 447 Unsigned division result with remainder. Description Unsigned integer division UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 447 of 487...
  • Page 448 /* result.div contains (+24) */ /* result.mod contains (+3) */ UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 448 of 487...
  • Page 449 In boundary scan mode: TMS (Test Mode Select). PIO0_2 — General purpose port 0 input/output 2. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 449 of 487...
  • Page 450 C Fast-mode Plus is selected in the I/O configuration register. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 450 of 487...
  • Page 451 IA = inactive, no pull-up/down enabled; F = floating. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 451 of 487...
  • Page 452 When configured as an analog input, the digital section of the pin is disabled. UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 452 of 487...
  • Page 453 #define I2C_MSTCTL_MSTSTOP (0x4) #define I2C_SLVCTL_SLVCONTINUE (0x1) #define I2C_SLVCTL_SLVNACK (0x2) UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 453 of 487...
  • Page 454 & I2C_STAT_MSTPENDING)); if((LPC_I2C->STAT & I2C_STAT_MSTSTATE) != I2C_STAT_MSTST_IDLE) abort(); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 454 of 487...
  • Page 455 & I2C_STAT_MSTPENDING)); if((LPC_I2C->STAT & I2C_STAT_MSTSTATE) != I2C_STAT_MSTST_IDLE) abort(); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 455 of 487...
  • Page 456 & I2C_STAT_MSTPENDING)); if((LPC_I2C->STAT & I2C_STAT_MSTSTATE) != I2C_STAT_MSTST_IDLE) abort(); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 456 of 487...
  • Page 457 & I2C_STAT_MSTPENDING)); if((LPC_I2C->STAT & I2C_STAT_MSTSTATE) != I2C_STAT_MSTST_IDLE) abort(); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 457 of 487...
  • Page 458 != 0xdd) abort(); LPC_I2C->SLVCTL = I2C_SLVCTL_SLVCONTINUE; // ack data UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 458 of 487...
  • Page 459 != 0xdd) abort(); LPC_I2C->SLVCTL = I2C_SLVCTL_SLVCONTINUE; // ack data UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 459 of 487...
  • Page 460 != 0xdd) abort(); LPC_I2C->SLVCTL = I2C_SLVCTL_SLVNACK; // nack data UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 460 of 487...
  • Page 461 = LPC_SPI->RXDAT; if(data != 0xdd) abort(); LPC_SPI->INTENCLR = SPI_STAT_RXRDY; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 461 of 487...
  • Page 462 = LPC_SPI->RXDAT; if(data != 0xdd) abort(); while(~LPC_SPI->STAT & SPI_STAT_MSTIDLE); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 462 of 487...
  • Page 463 & SPI_STAT_RXRDY); data = LPC_SPI->RXDAT; if(data != 0xdd) abort(); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 463 of 487...
  • Page 464 & UART_STAT_TXRDY) { if(tx_rdy_flag) abort(); tx_rdy_flag = 1; LPC_USART->INTENCLR = UART_STAT_TXRDY; UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 464 of 487...
  • Page 465 LPC_USART->INTENCLR = UART_STAT_TXRDY | UART_STAT_RXRDY; while(~LPC_USART->STAT & UART_STAT_TXIDLE); NVIC_DisableIRQ(Usart_IRQn); UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 465 of 487...
  • Page 466 AN11538 application note and code bundle (SCT cookbook) ARMv6-M Architecture Reference Manual UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 466 of 487...
  • Page 467 NXP Semiconductors. applications and products. In no event shall NXP Semiconductors be liable for any indirect, incidental, NXP Semiconductors does not accept any liability related to any default, punitive, special or consequential damages (including - without limitation - lost...
  • Page 468 ......49 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 469 0x4000 C1C0) bit description ....87 Table 109. PIO0_20 register (PIO0_20, address 0x4004 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 469 of 487...
  • Page 470 8038) bit description....174 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 471 (USART2)) bit description....199 0000 (I2C0), 0x4005 4000 (I2C1), 0x4007 0000 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 471 of 487...
  • Page 472 0x4005 0080 (I2C0), 0x4005 4080 (I2C1), 0x4007 (CAPCTRL0) to 0x5000 421C (CAPCTRL7)) bit UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 472 of 487...
  • Page 473 Table 271. SysTick Timer Control and status register Table 298. Register overview: CRC engine (base address UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 473 of 487...
  • Page 474 Table 398. JTAG boundary scan pin description..442 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 475 Table 439. Abbreviations ......466 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 476 Fig 50. MRT block diagram ..... . 311 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 477 0 ....... . 46 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 478 General description ....90 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 479 ......138 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 480 Features ......207 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 481 16.6.13 SCT bi-directional output control register. . . 277 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 481 of 487...
  • Page 482 Pin description ......317 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 483 Flash signature start address register ..365 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 483 of 487...
  • Page 484 Features ......398 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 485 30.4.12.6 ADC_DMA_SETUP_T ....438 UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016...
  • Page 486 Code examples SPI ....461 continued >> UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. User manual Rev. 1.2 — 5 October 2016 486 of 487...
  • Page 487 Disclaimers ......467 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com...

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