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(2) How to access PCI configuration register
• Write access
Set the access target register address to the PCI_CONFIG_ADD register
Write the access target register setting value to the PCI_CONFIG_DATA register
• Read access
Set the access target register address to the PCI_CONFIG_ADD register
Read the PCI_CONFIG_DATA register
3.4.3 PCI_CONTROL register
After reset: 07000100H
R/W
31
24 23
PCI_PARKCNT
Bit Name
R/W
PCI_PARKCNT
R/W
PCI_BPMODE
R/W
PCI_REQ
R/W
PCI_RESET
R/W
TARGET_EN
R/W
MEM_EN
R/W
IO_EN
R/W
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
↓
↓
Offset address: 08H
17 16 15
0
0
0
0
0
0
0
Sets the time for shifting to bus parking.
At the default value, bus parking is performed seven clocks after the bus status becomes IDLE.
The counter is started when FRAME# = High and IRDY# = High.
Sets the bus parking master.
0: Limited to this macro
1: Master accessed last
Enables/disables the REQ# signal (I_REQ_B1 to I_REQ_B7 pins) from the bus master.
Bit 0 of this field (bit 8 of the PCI_CONTROL register) is assigned to the PCI host bridge macro,
and is always 1.
0: Disabled
1: Enabled
Sets the reset status of the PCI bus.
0: Reset status
1: Reset released
Sets the operation of the PCI bus target of the PCI host bridge macro.
0: Do not respond to main memory (SDRAM) access from the PCI device
1: Respond to main memory (SDRAM) access from the PCI device
Enables/disables access from the CPU to the PCI memory area.
0: Access disabled
1: Access enabled
Enables/disables access from the CPU to the PCI I/O area.
0: Access disabled
1: Access enabled
Application Note U17121EJ1V1AN
8
7
PCI_REQ
0
0
Function
5
4
3
2
1
0
0
0
37
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