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The correspondence between the output address signals when the main memory (SDRAM) is accessed and the
PCI bus address signals is shown below.
COLUMN_SIZE
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
Field Setting Value
25 to 18
00 (8 bits)
25 to 18
01 (9 bits)
25 to 18
10 (10 bits)
25 to 18
11 (11 bits)
25 to 18
BUS_SIZE
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
Bit Setting Value
25 to 18
0 (16 bits)
25 to 18
1 (32 bits)
25 to 18
Remark H: High level
BUS_SIZE
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
Bit Setting Value
25 to 18
0 (16 bits)
25 to 18
1 (32 bits)
25 to 18
Remark L: Low level
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Table 3-1. Row Address Output
(O_SD_ADR1 to O_SD_ADR25)
17
16
15
14
25
24
23
22
17
25
24
23
17
16
25
24
17
16
15
25
Table 3-2. Column Address Output (Precharge Command)
(O_SD_ADR1 to O_SD_ADR25)
17
16
15
14
17
16
15
14
17
16
15
14
Table 3-3. Column Address Output (Read/Write Command)
(O_SD_ADR1 to O_SD_ADR25)
17
16
15
14
17
16
15
14
17
16
15
14
Application Note U17121EJ1V1AN
13
12
11
10
9
8
21
20
19
18
17
16
22
21
20
19
18
17
23
22
21
20
19
18
24
23
22
21
20
19
13
12
11
10
9
8
12
11
H
10
9
8
12
H
11
10
9
8
13
12
11
10
9
8
12
11
L
10
9
8
12
L
11
10
9
8
7
6
5
4
3
2
15
14
13
12
11
10
16
15
14
13
12
11
17
16
15
14
13
12
18
17
16
15
14
13
7
6
5
4
3
2
7
6
5
4
3
2
7
6
5
4
3
2
7
6
5
4
3
2
7
6
5
4
3
2
7
6
5
4
3
2
1
9
10
11
12
1
1
1
1
1
1
43
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