Cautions On Designing Fpga; Fpga Fitting Design; Pci Bus Interface Timing Parameters (As Constraint Of Pci Clk = 33 Mhz) - NEC V850E/MA1 Application Note

CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION

4.6 Cautions on Designing FPGA

Cautions when fitting an FPGA using Altera's "Quartusll Design Software" are shown below.

4.6.1 FPGA fitting design

(1) Set the "I/O Standard" buffer type to "3.3-V PCI" for the following PCI bus interface pins.
Pin Name/Usage
INTA
INTB
FRAME
DEVSEL
REQ1
REQ2
GNT1
GNT2
IRDY
TRDY
STOP
PCIRST
AD0 to AD31
CBE0 to CBE3
PAR
PERR
SERR
(2) Determine the pin assignment taking equal length wiring into consideration for the PCI bus interface pins.
(3) Specify the "PCLK" and "SDCLK" signals as Global CLK.

4.6.2 PCI bus interface timing parameters (as constraint of PCI CLK = 33 MHz)

Adjust the timing so that the following PCI specification values are satisfied.
(1) Input setup time to CLK point to point
REQ1, REQ2
Other PCI pins
Dir
input
input
bidir
bidir
input
input
output
output
bidir
bidir
bidir
output
bidir
bidir
bidir
bidir
input
Pin Setup
10 ns
7 ns
Application Note U17121EJ1V1AN
I/O Standard
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
Hold
0 ns
0 ns
65