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CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.5.2 Internal connection diagram of PCI bus interface
PCI host
bridge macro
O_PCIRST_B
I_AD0 to I_AD31
O_AD0 to O_AD31
I_CBE0 to I_CBE3
O_CBE0 to O_CBE3
O_FRAME_B
I_DEVSEL_B
O_DEVSEL_B
EN_DEVSEL
I_REQ_B1, I_REQ_B2
I_REQ_B3 to I_REQ_B7
O_GNT_B1, O_GNT_B2
O_GNT_B3 to O_GNT_B7
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FPGA top
I_PCLK
EN_AD
EN_CBE
I_FRAME_B
EN_FRAME
I_IRDY_B
O_IRDY_B
EN_IRDY
I_TRDY_B
O_TRDY_B
EN_TRDY
I_STOP_B
O_STOP_B
EN_STOP
I_PAR
O_PAR
EN_PAR
I_PERR_B
O_PERR_B
EN_PERR
I_SERR_B
H fixed
Open
Application Note U17121EJ1V1AN
PCLK
PCIRST
AD0 to AD31
CBE0 to CBE3
FRAME
IRDY
DEVSEL
TRDY
STOP
PAR
PERR
SERR
REQ1, REQ2
GNT1, GNT2
I/O buffer
CLK
RST#
AD0 to AD31
C/BE0# to C/BE3#
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
PERR#
SERR#
REQ1#, REQ2#
GNT1#, GNT2#
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