Table of Contents
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SRAM data bank A,
1-12
startup, of this EZ-KIT Lite,
CCES,
1-4
SW10-11 (test) DIP switches,
SW12 (audio enable) switch,
SW13 (SPIS1/SPISS select) switch,
SW1 (reset) push button,
SW2 (video config) DIP switch, 1-16, 2-6,
2-7, 2-8,
2-11
SW3 (boot mode) switch,
SW4 (push button enable) DIP switch,
1-15, 2-12,
2-16
SW5 (PPI clock select) switch, 1-16, 2-6,
2-13
SW6-9 (general input) push buttons, 1-14,
2-4, 2-12,
2-16
synchronous dynamic random access
memory, See SDRAM
system
architecture, of EZ-KIT Lite,
clock (SCLK),
1-13
T
technical support,
xv
test DIP switches (SW10-11),
TFS0 signal, 1-15,
2-12
time-division multiplexed (TDM) mode,
1-15
timers11-8,
2-6
timers7-0,
2-4
TSCLK0 signal, 1-15,
U
UART
loop jumper (P1),
2-15
port, xii,
2-8
transmit/receive pins (PF26-27),
universal asynchronous
receiver/transmitter, See UART port
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-8
2-13
2-13
2-14
2-16
2-11
2-2
2-13
2-12
2-5
USB
cable,
1-2
connector (ZJ1,
1-5
debug agent connector (ZJ1),
interface, 2-9, 2-16,
monitor LED (ZLED3),
user LEDs (LED5-12, LED13-20),
V
VDDINT signal,
2-14
very-long instruction word (VLIW),
video
channels,
2-7
configuration switch (SW2),
connector (J6),
2-20
control signals, 2-7,
decoders, See ADV7183A
encoders, See ADV7179
input (PPI0),
2-7
interface,
1-16
output (PPI1),
2-7
VisualDSP++
environment,
1-8
VROUT pins,
2-14
VSYNC signals, 2-6,
2-7
Index
2-21
2-22
2-17
2-17
ix
2-10
2-8
I-5
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