Disabling Of Link-Up And Update - Siemens SIMATIC PCS 7 System Manual

Supplementary information
16.12 Link-up and update sequence
Work memory
The following components are transferred from the work memory of the master CPU to the
standby CPU:
● Contents of all data blocks assigned the same interface time stamp in both load
memories and whose attributes "read only" and "unlinked" are not set.
● Data blocks generated in the master CPU by SFCs.
The DBs generated in the standby CPU by means of SFC are deleted.
If a data block with the same number is also contained in the load memory of the standby
CPU, the link-up operation is cancelled with an entry in the diagnostics buffer.
● Process images, timers, counters, and bit memories
The status of SFB instances of S7 communication contained in modified data blocks is
restored to the status prior to their initial call.
16.12.4

Disabling of link-up and update

Link-up and update entails a cycle time extension. This includes a period during which no I/O
updates are performed; see Chapter Time monitoring (Page 117). You must pay special
attention to this if you are using distributed I/O and a master/standby changeover occurs
after the update (thus, when the configuration is modified during operation).
Always perform link-up and update operations when the process is not in a critical state.
You can set specific start times for link-up and update operations at SFC 90 "H_CTRL". For
detailed information on this SFC, refer to Manual
and Standard Functions
Note
If the process tolerates cycle time extensions at any time, you do not need to call SFC 90
"H_CTRL".
The CPU does not perform a self-test during link-up and updating. If you use a fail-safe user
program, you should avoid any excessive delay for the update operation. For more details,
refer to Manual
Example of a time-critical process
A slide block with a 50 mm cam moves on an axis at a constant velocity
v = 10 km/h = 2.78 m/s = 2.78 mm/ms. A switch is located on the axis. So the switch is
actuated by the cam for the duration of ∆t = 18 ms.
For the CPU to detect the actuation of the switch, the inhibit time for priority classes > 15
(see below for definition) must be significantly below 18 ms.
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CAUTION
.
S7-400F and S7-400FH Automation Systems
System Software for S7-300/400, System
.
CPU 410-5H Process Automation/CPU 410 SMART
System Manual, 09/2014, A5E32631667-AB