5. SEQUENCE INSTRUCTIONS
5.3.4 Bit device output reverse (CHK)
CPU
An
AnN, AnS, AnSH, A1FX,
A0J2H, A73, A3N board
A3H, A3M
A3V, AnA,
A2C, A52G, AnU, A2AS,
QCPU-A (A Mode),
A2USH board
Bit device
X
Y
M
O
O
(D1)
*1
*1
*1
(D2)
*1: Device used for D2 is a dummy data which has nothing to do with program processing.
The CHK instruction varies in function with I/0 control mode as shown below.
Direct mode
Failure check
Failure check
Failure check
For failure check, refer to Section 7.10.2.
Available Device
L
S
B
F
T
C
O
O
O
O
*1
*1
*1
*1
*1
Output reverse command
CHK
AnS
AnN
An
A1FX
Applicable
AnSH
CPU
*
x
Remark
* Valid only when the input/output control method is refresh method.
I/O control mode
(when either or both of input and output are in refresh mode)
Word (16-bit) device
D
W
R
A0
A1
Z
*1
*1
*1
*1
*1
*1
(D1)
(D2)
5 − 26
AnU, A2AS
A2USH-S1
A3H
A3V
AnA
A2USH board
A3M
QCPU-A
(A Mode)
O
x
x
x
x
Refresh mode
Bit device output reverse
Failure check
Failure check
Constant Pointer
Level
V
K
H
P
I
N
K1
*1
to
K4
Setting data
(D1)
Required device number
Dummy data
(D2)
Any device number
indicated by
MELSEC-A
A2C
A3N
A0J2H
A73
A52G
boad
*
*
*
x
M9012 (M9010, M9011)