Mitsubishi MELSEC-A Series Programming Manual page 28

2. INSTRUCTIONS
Classi- Instruction
fication Symbol
∗
B
BCD
∗
B P
4-digit
multipli-
cation,
B/
division
B/P
∗
DB
BCD ∗
DB P
8-digit
multipli-
cation,
DB/
division
DB/P
INC
INCP
BIN
data
incre-
ment
DINC
DINCP
DEC
DECP
BIN
data
decre-
ment
DDEC
DDECP
Table 2.11 Arithmetic Operation Instructions
Symbol Contents of Processing
(S1) × (S2) → (D+1, D)
(S1) / (S2) → Quotient (D)
|Remainder (D+1)
(S1+1, S1) × (S2+1, S2)
→ (D+3, D+2, D+1, D)
(S1+1, S1) / (S2+1, S2)→
Quotient (D+1, D),
Remainder (D+3, D+2)
(D) +1 → (D)
(D+1, D) +1 → (D+1, D)
(D) -1 → (D)
(D+1, D) -1 → (D+1, D)
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1
Execu-
tion Con-
dition
9
9
9
9
11
11
11
11
3
3
3
3
3
3
3
3
2 − 12
MELSEC-A
Applicable CPU
*3
!
*3
!
*3
!
*3
!
!
!
!
!
!
!
!
!
!
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