Mitsubishi MELSEC-A Series Programming Manual page 26

2. INSTRUCTIONS
Classi- Instruction
fication Symbol
+
+P
+
BIN
+P
16-bit
addition/
subtrac-
-
tion
-P
-
-P
D+
D+P
D+
BIN
D+P
32bit
addition/
subtrac-
D-
tion
D-P
D-
D-P
∗
BIN ∗
P
16bit
multipli-
cation/
/
division
/P
(2) Arithmetic operation instruction
Table 2.11 Arithmetic Operation Instruction (Continue)
Symbol Contents of Processing
(D) + (S) → (D)
(S1) + (S2) → (D)
(D) - (S) → (D)
(S1) - (S2) → (D)
(D+1, D) + (S+1, S)
→ (D+1, D)
(S1+1, S1) + (S2+1, S2)
→ (D+1, D)
(D+1, D) - (S+1, S) → (D+1, D)
(S1+1, S1) - (S2+1, S2)
→ (D+1, D)
(S1) × (S2) → (D+1, D)
(S1) / (S2) → Quotient (D),
Remainder (D+1)
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1
Execu-
tion Con-
dition
5
5
7
7
5
5
7
7
9
9
11
11
9
9
11
11
7
7
7
7
2 − 10
MELSEC-A
Applicable CPU
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
Page
6-10
6-10
6-10
6-10
6-10
6-10
6-10
6-10
6-13
6-13
6-13
6-13
6-13
6-13
6-13
6-13
6-16
6-16
6-16
6-16