Mitsubishi MELSEC-A Series Programming Manual page 35

2. INSTRUCTIONS
Classi- Instruction
fication Symbol
SFR
SFRP
n bit
shift
SFL
SFLP
BSFR
BSFRP
1 bit
shift
BSFL
BSFLP
DSFR
DSFRP
1 ward
shift
DSFL
DSFLP
(3) Shift instructions
Table 2.19 Shift Instructions
Symbol Contents of Processing
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1
Execu-
tion Con-
dition
5
5
5
5
7
7
7
7
7
7
7
7
2 − 19
MELSEC-A
Applicable CPU
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*3
Not applicable to A73
*3
Not applicable to A73
*3
Not applicable to A73
*3
Not applicable to A73
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