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Programming the Status Registers
Status register programming lets you determine the operating condition of the dc source at any time. For
example, you may program the dc source to generate an interrupt (SRQ) when an event such as a current
limit occurs. When the interrupt occurs, your program can act on the event in the appropriate fashion.
Figure 5-5 shows the status register structure of the dc source. Table 5-1 defines the status bits. The
Standard Event, Status Byte, and Service Request Enable registers and the Output Queue perform
standard GPIB functions as defined in the IEEE 488.2 Standard Digital Interface for Programmable
Instrumentation. The Operation Status and Questionable Status registers implement functions that are
specific to the dc source.
QUESTIONABLE STATUS
(IDENTICAL REGISTERS FOR EACH CHANNEL)
CONDITION
PTR/NTR
0
1
1
OV+
1
2
2
OV -
2
4
4
PCLR
4
16
16
OT
10
UNR
1024
1024
OSC 12 4096
4096
Meas Ovld 14
16384
16384
STANDARD EVENT
STATUS
EVENT
ENABLE
0
OPC
1
1
2
QYE
4
4
3
DDE
8
8
4
EXE
16
16
5
CME
32
32
7
PON
128
128
OPERATION STATUS
(IDENTICAL REGISTERS FOR EACH CHANNEL)
CONDITION
PTR/NTR
EVENT
0
1
1
1
CV
2
1
2
2
CL+
4
2
4
4
CL -
3
8
8
8
CC
4
16
16
16
VL+
5
32
32
32
VL -
6
64
64
64
OFF
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EVENT
ENABLE
1
1
2
2
4
4
16
16
LOGICAL
OR
1024
1024
CHAN 1
4096
4096
16384
16384
OUTPUT QUEUE
DATA
QUEUE
NOT
DATA
EMPTY
DATA
LOGICAL
OR
ENABLE
1
2
CHAN 1
LOGICAL
4
OR
8
CHAN 2
16
32
CHAN 3
64
CHAN 4
SAME
AS
CHAN 1
Figure 5-5. DC Source Status Model
Programming the DC Source - 5
CHAN 1
QSUM
QSUM
LOGICAL
CHAN 2
OR
SAME
QSUM
CHAN 3
AS
QSUM
CHAN 4
STATUS BYTE
2
WTG
QUES
3
8
4
MAV
16
ESB
5
32
MSS
6
RQS
OPER
7
128
SERVICE
REQUEST
GENERATION
OSUM
OSUM
LOGICAL
OR
OSUM
OSUM
SERVICE
REQUEST
ENABLE
8
16
LOGICAL
OR
32
128
49
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