Push-Button Switches With Selectable Jumpers For Gclr And Oe1 Pins - Atmel ATF15 DK3-U Series User Manual

Push-button Switches with Selectable Jumpers for GCLR and OE1 Pins

The CPLD Development/Programmer Board contains two push-button switches for the Global Clear
(GCLR) and Output Enable (OE1) pins of the CPLD. The switches control the logic states of the OE1
and GCLR inputs of the ATF15xx devices. These switches are labeled SW-GCLR and SW-GOE1 on
the board. One end of the SW-GCLR input push-button switch is connected to GND. The other end of
the push-button switch is connected to a pull-up resistor to V
dedicated input pin of the ATF15xx device. It is intended to be used as an active-low reset signal to
reset the registers in the ATF15xx device with the JPGCLR selectable jumper set. Similarly, one end of
the SW-GOE1 input push-button switch is connected to GND. The other end of the push-button switch
is connected to a pull-up resistor to V
ATF15xx device. It is intended to be used as an active-low output enable signal to control the
enabling/disabling of the tri-state output buffers in the ATF15xx with the JPGOE selectable jumper set.
Figure 5
pins.
If any of these push-button switches is pressed and the corresponding jumper is set, the specific I/O of
the CPLD will be driven to a logic low state. Since each push-button is also connected to a pull-up
resistor, the corresponding CPLD input will have a logic high state if the push-button switch is not
pressed with the corresponding selectable jumper set. If the selectable jumper is not set, the
corresponding dedicated input pin of the CPLD can be considered a No Connect (NC) pin.
shows the pin numbers of the GCLR and OE1 dedicated input pins of the ATF15xx devices in all
available package types.
Figure 5.
GCLR
Table 5.
GCLR
OE1
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is the circuit diagram of the push-button switches and the jumpers for the GCLR and OE1
Circuit Diagram of Push-button Switches and Selectable Jumpers for GCLR and OE1
VccIO
R15
1K
R37 JPGCLR
1K
C7
0.001uF
SW-GCLR
SW-GCLR
Pin Numbers of GCLR and OE1
44-pin TQFP
39
38
IO, and then connected to the OE1 dedicated input pin of the
CC
R16
1K
JPGOE
C8
0.001uF
SW-GOE
SW-GOE
44-pin PLCC
1
44
ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015
IO, and then connected to the GCLR
CC
R38
GOE
1K
84-pin PLCC 100-pin TQFP
1
84
Table 5
89
88
9