Uart Interfaces - Quectel EG91 Series Hardware Design

A common mode choke L1 is recommended to be added in series between the module and customer's
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be
added in series between the module and the test points so as to facilitate debugging, and the resistors are
not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
 It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
 Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
Pay attention to the influence of junction capacitance of ESD protection components on USB data

lines. Typically, the capacitance value should be less than 2pF.
 Junction capacitance of the ESD protection device might cause influences on USB data line, so
please pay attention to the selection of the device. Typically, the stray capacitance should be less
than 2pF.
 Keep the ESD protection components to the USB connector as close as possible.

3.11. UART Interfaces

The module provides two UART interfaces: the main UART interface and the debug UART interface. The
following shows their features.
EG91_Series_Hardware_Design
Figure 19: Reference Circuit of USB Interface
LTE Standard Module Series
EG91 Series Hardware Design
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