Quectel EG91 Series Hardware Design page 51

Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No.
PCM_DIN 6
PCM_DOUT 7
PCM_SYNC 5
PCM_CLK 4
I2C_SCL 40
I2C_SDA 41
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to
document [2] about AT+QDAI command for details.
The following figure shows a reference design of PCM interface with external codec IC.
Figure 24: Reference Circuit of PCM Application with Audio Codec
NOTES
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. EG91 series module works as a master device pertaining to I2C interface.
EG91_Series_Hardware_Design
I/O Description
DI PCM data input
DO PCM data output
PCM data frame
IO
synchronization signal
IO PCM data bit clock
OD I2C serial clock
OD I2C serial data
LTE Standard Module Series
EG91 Series Hardware Design
Comment
1.8V power domain
1.8V power domain
1.8V power domain
1.8V power domain
Require an external pull-up to 1.8V
Require an external pull-up to 1.8V
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