Quectel EG91 Series Hardware Design page 47
Lte standard module
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Also See for EG91 Series:
- Hardware design (98 pages) ,
- Hardware design (94 pages) ,
- Hardware design (108 pages)
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The main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps,
230400bps, 460800bps, 921600bps and 3000000bps baud rates, and the default is 115200bps. It
supports RTS and CTS hardware flow control, and is used for AT command communication only.
The debug UART interface supports 115200bps baud rate. It is used for Linux console and log
output.
The following tables show the pin definition of the two UART interfaces.
Table 11: Pin Definition of Main UART Interfaces
Pin Name
Pin No.
RI
39
DCD
38
CTS
36
RTS
37
DTR
30
TXD
35
RXD
34
Table 12: Pin Definition of Debug UART Interface
Pin Name
Pin No.
DBG_TXD
23
DBG_RXD
22
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
EG91_Series_Hardware_Design
I/O
Description
DO
Ring indicator
DO
Data carrier detection
DO
Clear to send
DI
Request to send
DI
Sleep mode control
DO
Transmit data
DI
Receive data
I/O
Description
DO
Transmit data
DI
Receive data
Min.
-0.3
1.2
LTE Standard Module Series
EG91 Series Hardware Design
Comment
1.8V power domain
Comment
1.8V power domain
1.8V power domain
Max.
0.6
2.0
Unit
V
V
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