NXP Semiconductors LPC2926FBD144 Manuals

Manuals and User Guides for NXP Semiconductors LPC2926FBD144. We have 1 NXP Semiconductors LPC2926FBD144 manual available for free PDF download: User Manual

NXP Semiconductors LPC2926FBD144 User Manual (566 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Chapter 1: Lpc29Xx Introductory Information

3
Introduction

3
About this User Manual

3
General Features

3
Ordering Information

5
Block Diagram

8
Functional Blocks

13
Architectural Overview

14
ARM968E-S Processor

14
On-Chip Flash Memory System

15
On-Chip Static RAM

15
Chapter 2: Lpc29Xx Memory Mapping

16
How to Read this Chapter

16
Memory-Map View of the AHB

16
Memory-Map Regions

17
Memory-Map Operating Concepts

21
Chapter 3: Lpc29Xx Clock Generation Unit (CGU)

24
How to Read this Chapter

24
Introduction

24
CGU0 Functional Description

25
- Controlling the XO50M Oscillator (External Oscillator)
  28
- Controlling the PL160M PLL
  28
- Controlling the Frequency Dividers
  30
- Controlling the Clock Output
  30
- Reading the Control Settings
  30
- Frequency Monitor
  30
- Clock Detection
  31
- Bus Disable
  31
- Clock-Path Programming
  31
CGU1 Functional Description

31
Register Overview

32
Chapter 4 : Lpc29Xx Reset Generation Unit (RGU)

48
How to Read this Chapter

48
Introduction

48
RGU Functional Description

48
- Reset Hierarchy
  49
Register Overview

50
- RGU Reset Control Register
  51
- RGU Reset Status Register
  52
- RGU Reset Active Status Register
  58
- RGU Reset Source Registers
  59
  - POR Reset
    59
  - RGU Reset
    59
  - PCR Reset
    59
  - Cold Reset
    60
  - Peripherals Activated by Cold Reset
    60
  - Peripherals Activated by Warm Reset
    60
- RGU Bus-Disable Register
  61
Chapter 5: Lpc29Xx Power Management Unit (PMU)

62
How to Read this Chapter

62
Introduction

62
PMU Functional Description

62
- PMU Clock-Branch Run Mode
  64
- PMU Clock Branch Overview
  65
Register Overview

65
Chapter 6: Lpc29Xx System Control Unit (SCU)

73
How to Read this Chapter

73
Introduction

73
Register Overview

73
Chapter 7: Lpc29Xx Chip Feature ID (CFID)

81
Introduction

81
Register Overview

81
Chapter 8: Lpc29Xx Event Router

83
How to Read this Chapter

83
Event Router Functional Description

83
- Event Router Pin Connections
  84
Register Overview

85
- Event Status Register
  85
- Event-Status Clear Register
  86
- Event-Status Set Register
  86
- Event Enable Register
  86
- Event-Enable Clear Register
  87
- Event-Enable Set Register
  87
- Activation Polarity Register
  88
- Activation Type Register
  88
- Raw Status Register
  88
Chapter 9: Lpc29Xx Vectored Interrupt Controller (VIC)

90
How to Read this Chapter

90
VIC Functional Description

90
- Non-Nested Interrupt Service Routine
  92
- Nested Interrupt Service Routine
  92
VIC Programming Example

92
Register Overview

93
Chapter 10: Lpc29Xx General System Control

103
How to Read this Chapter

103
Introduction

103
Power Modes

103
Reset and Power-Up Behavior

104
Functional Description of the Interrupt and Wake-Up Structure

104
Interrupt Device Architecture

105
- Interrupt Registers
  106
- Interrupt Clear-Enable Register
  107
- Interrupt Set-Enable Register
  107
- Interrupt Status Register
  107
- Interrupt Enable Register
  107
- Interrupt Clear-Status Register
  107
- Interrupt Set-Status Register
  108
ISR Functional Description

108
- ESR Functional Description
  108
Wake-Up

109
Chapter 11 : Lpc29Xx Pin Configuration

111
How to Read this Chapter

111
LPC2917/19/01 Pinning Information

111
LPC2921/23/25 Pin Configuration

118
LPC2927/29 Pin Configuration

122
LPC2930/30 Pin Configuration

129
LPC2930 Boot Control

137
Chapter 12: Lpc29Xx External Static Memory Controller (SMC)

140
How to Read this Chapter

140
SMC Functional Description

140
External Memory Interface

141
Register Overview

146
Chapter 13: Lpc29Xx USB Device

154
How to Read this Chapter

154
Introduction

154
Features

155
Fixed Endpoint Configuration

155
Functional Description

156
- Analog Transceiver
  157
- Serial Interface Engine (SIE)
  157
- Endpoint RAM (EP_RAM)
  157
- EP_RAM Access Control
  157
- DMA Engine and Bus Master Interface
  157
- Register Interface
  157
- Softconnect
  157
- Goodlink
  158
Operational Overview

158
Pin Description

158
Clocking and Power Management

159
- Power Requirements
  159
- Clocks
  159
- Power Management Support
  159
- Remote Wake-Up
  160
Register Overview

160
Interrupt Handling

183
- Slave Mode
  183
- DMA Mode
  183
Serial Interface Engine Command Description

186
USB Device Controller Initialization

195
Slave Mode Operation

196
- Interrupt Generation
  196
- Data Transfer for out Endpoints
  197
- Data Transfer for in Endpoints
  197
DMA Operation

197
- Transfer Terminology
  197
- USB Device Communication Area
  198
- Triggering the DMA Engine
  199
- The DMA Descriptor
  199
- Next_Dd_Pointer
  200
- Dma_Mode
  200
- Next_Dd_Valid
  200
- Isochronous_Endpoint
  201
- Max_Packet_Size
  201
- Dma_Buffer_Length
  201
- Dma_Buffer_Start_Addr
  201
- Dd_Retired
  201
- Dd_Status
  201
- Packet_Valid
  202
- Ls_Byte_Extracted
  202
- Ms_Byte_Extracted
  202
- Present_Dma_Count
  202
- Message_Length_Position
  202
- Isochronous_Packetsize_Memory_Address
  202
- Non-Isochronous Endpoint Operation
  202
- Setting up DMA Transfers
  202
- Finding DMA Descriptor
  203
- Transferring the Data
  203
  - Optimizing Descriptor Fetch
    203
- Ending the Packet Transfer
  203
- Packet DD
  204
- Isochronous Endpoint Operation
  204
- Setting up DMA Transfers
  204
- Finding the DMA Descriptor
  204
  - Transferring the Data
    205
  - OUT Endpoints
    205
  - IN Endpoints
    205
- DMA Descriptor Completion
  205
- Isochronous out Endpoint Operation Example
  205
- Auto Length Transfer Extraction (ATLE) Mode Operation
  206
  - OUT Transfers in ATLE Mode
    207
  - IN Transfers in ATLE Mode
    208
- Setting up the DMA Transfer
  208
- Finding the DMA Descriptor
  208
- Transferring the Data
  208
  - OUT Endpoints
    208
  - IN Endpoints
    208
- Ending the Packet Transfer
  209
  - OUT Endpoints
    209
  - IN Endpoints
    209
Double Buffered Endpoint Operation

209
- Bulk Endpoints
  209
- Isochronous Endpoints
  211
Chapter 14: Lpc29Xx USB Host Controller

212
How to Read this Chapter

212
Introduction

212
- Features
  212
- Architecture
  213
Interfaces

213
- Pin Description
  213
- USB Host Usage Note
  214
- Software Interface
  214
Register Overview

214
- USB Host Register Definitions
  215
Chapter 15: Lpc29Xx USB OTG Interface

216
How to Read this Chapter

216
Introduction

216
Features

216
Architecture

216
Pin Configuration

217
- Suggested USB Interface Solutions
  219
Register Overview

221
HNP Support

230
- B-Device: Peripheral to Host Switching
  231
- Remove D+ Pull-Up
  233
- Add D+ Pull-Up
  234
- A-Device: Host to Peripheral HNP Switching
  234
  - Set BDIS_ACON_EN in External OTG Transceiver
    237
  - Ceiver
    237
  - Discharge VBUS
    237
  - Load and Enable OTG Timer
    238
  - Stop OTG Timer
    238
  - Suspend Host on Port 1
    238
Clocking and Power Management

239
- Device Clock Request Signals
  240
- Host Clock Request Signals
  240
- Power-Down Mode Support
  240
USB OTG Controller Initialization

241
Chapter 16: Lpc29Xx General Purpose Input/Output (GPIO)

242
How to Read this Chapter

242
GPIO Functional Description

242
Register Overview

243
- GPIO Port Input Register
  243
- GPIO Port Output Register
  244
- GPIO Port Direction Register
  244
Chapter 17: Lpc29Xx Timer 0/1/2/3

245
How to Read this Chapter

245
Timer Functional Description

245
Timer Counter and Interrupt Timing

246
Timer Match Functionality

247
- Timer Capture Functionality
  247
- Timer Interrupt Handling
  247
Register Overview

248
- Timer Control Register (TCR)
  248
- Timer Counter
  249
- Timer Prescale Register
  249
- Timer Match-Control Register
  250
- Timer External-Match Register
  251
- Timer Match Register
  252
- Timer Capture-Control Register
  252
- Timer Capture Register
  253
- Timer Interrupt Bit Description
  254
Chapter 18: Lpc29Xx SPI0/1/2

255
How to Read this Chapter

255
Introduction

255
- SPI Functional Description
  255
- Modes of Operation
  255
- Slave Mode
  257
Register Overview

258
- SPI Configuration Register
  258
- SPI Slave-Enable Register
  260
- SPI Transmit-FIFO Flush Register
  261
- SPI FIFO Data Register
  261
- SPI Receive FIFO POP Register
  262
- SPI Receive-FIFO Read-Mode Register
  262
- SPI DMA Settings Register
  263
- SPI Status Register (Status)
  264
- SPI Slave-Settings 1 Register
  265
- SPI Slave-Settings 2 Register
  266
- SPI FIFO Interrupt Threshold Register
  267
- SPI Interrupt Bit Description
  268
Chapter 19: Lpc29Xx Universal Asynchronous Receiver/Transmitter (UART)

269
How to Read this Chapter

269
Features

269
Pin Description

269
Register Overview

271
- Uartn Receiver Buffer Register
  271
- Uartn Transmit Holding Register
  272
- Uartn Divisor Latch Registers
  272
- Uartn Interrupt Enable Register
  273
- Uartn Interrupt Identification Register
  273
- Uartn FIFO Control Register
  275
- Uartn Line Control Register
  276
- UART0/1 Modem Control Register
  277
- Auto-Flow Control
  278
- Auto-RTS
  278
- Auto-CTS
  279
- Uartn Line Status Register
  280
- UART0/1 Modem Status Register
  281
- Uartn Scratch Pad Register
  282
- Uartn Auto-Baud Control Register
  282
- Auto-Baud
  283
- Auto-Baud Modes
  284
- Uartn Fractional Divider Register
  285
- Baudrate Calculation
  286
- Example 1: BASE_UART_CLK = 14.7456 Mhz, BR = 9600
  288
- Example 2: BASE_UART_CLK = 12 Mhz, BR = 115200
  288
- Uartn Transmit Enable Register
  288
- Uartn RS485 Control Register
  289
- Uartn RS485 Address Match Register
  290
- Uartn RS-485 Delay Value Register
  290
- Modes of Operation
  290
Architecture

291
Chapter 20: Lpc29Xx Watchdog Timer (WDT)

294
How to Read this Chapter

294
Introduction

294
Watchdog Programming Example

294
Register Overview

295
- Watchdog Timer-Control Register
  295
- Watchdog Timer Counter
  296
- Watchdog Prescale Register
  296
- Watchdog Timer Key Register
  297
- Watchdog Time-Out Register
  297
- Watchdog Debug Register
  297
- Watchdog Interrupt Bit Description
  298
Chapter 21: Lpc29Xx CAN 0/1

299
How to Read this Chapter

299
CAN Functional Description

299
CAN Controller 0

299
CAN Bus Timing

300
- Baud-Rate Prescaler
  300
- Synchronization Jump Width
  300
- Time Segments 1 and 2
  300
CAN Transmit Buffers

301
- Transmit Buffer Layout
  301
- Automatic Transmit-Priority Protection
  302
CAN Receive Buffer

302
- Receive Buffer Layout
  302
CAN Controller Self-Test

303
- Global Self-Test
  303
- Local Self-Test
  303
CAN Global Acceptance Filter

304
Register Overview

312
CAN Acceptance-Filter Register Overview

334
Fullcan Mode

342
CAN Configuration Example 1

353
CAN Configuration Example 2

355
CAN Look-Up Table Programming Guidelines

357
Chapter 22 : Lpc29Xx LIN/UART 0/1

359
How to Read this Chapter

359
Introduction

359
LIN Features

359
UART Features

360
LIN Functional Description

360
- LIN Master
  361
- LIN Sync-Break Generation
  361
- Registers and Mapping
  362
- Error Detection
  362
- Line-Clamped Detection Versus Bit-Error Detection
  362
- Wake-Up Interrupt Handling
  363
- Slave-Not-Responding Error and the LIN Master Time-Out Register
  363
Pin Description

363
Register Overview

363
Chapter 23: Lpc29Xx I2C-Interface

386
How to Read this Chapter

386
Features

386
Applications

386
Description

386
Pin Description

387
C Operating Modes

387
- Master Transmitter Mode
  388
- Master Receiver Mode
  389
- Slave Receiver Mode
  389
- Slave Transmitter Mode
  390
C Implementation and Operation

391
- Input Filters and Output Stages
  391
- Address Registers, ADDR0 to ADDR3
  392
- Address Mask Registers, MASK0 to MASK3
  393
- Comparator
  393
- Shift Register DAT
  393
- Arbitration and Synchronization Logic
  393
- Serial Clock Generator
  394
- Timing and Control
  395
- Control Register CONSET and CONCLR
  395
- Status Decoder and Status Register
  395
Register Overview

395
Details of I C Operating Modes

404
- Master Transmitter Mode
  404
- Master Receiver Mode
  405
- Slave Receiver Mode
  405
- Slave Transmitter Mode
  410
- Miscellaneous States
  416
- I2STAT = 0Xf8
  416
- I2STAT = 0X00
  416
- Some Special Cases
  417
- Simultaneous Repeated START Conditions from Two Masters
  417
- Data Transfer after Loss of Arbitration
  417
- Forced Access to the I C Bus
  417
- C Bus Obstructed by a LOW Level on SCL or SDA
  418
- Bus Error
  418
- C State Service Routines
  419
- Initialization
  419
  - I 2 C Interrupt Service
    420
- The State Service Routines
  420
- Adapting State Services to an Application
  420
Software Example

420
- Initialization Routine
  420
- Start Master Transmit Function
  420
- Start Master Receive Function
  420
- I 2 C Interrupt Routine
  421
- Non Mode Specific States
  421
- State : 0X00
  421
- Master States
  421
- State : 0X08
  421
- State : 0X10
  421
- Master Transmitter States
  422
- State : 0X18
  422
- State : 0X20
  422
- State : 0X28
  422
- State : 0X30
  422
- State : 0X38
  423
- Master Receive States
  423
- State : 0X40
  423
- State : 0X48
  423
- State : 0X50
  423
- State : 0X58
  423
- Slave Receiver States
  424
- State : 0X60
  424
- State : 0X68
  424
- State : 0X70
  424
- State : 0X78
  424
- State : 0X80
  425
- State : 0X88
  425
- State : 0X90
  425
- State : 0X98
  425
- State : 0Xa0
  425
- Slave Transmitter States
  426
- State : 0Xa8
  426
- State : 0Xb0
  426
- State : 0Xb8
  426
- State : 0Xc0
  426
- State : 0Xc8
  427
Chapter 24: Lpc29Xx Modulation and Sampling Control Subsystem (MSCSS)

428
How to Read this Chapter

428
MSCSS Functional Description

428
- Synchronization and Trigger Features of the MSCSS
  428
MSCSS Miscellaneous Operations

430
- Continuous Level Measurement
  431
- Comparator Functionality
  431
- Dimmer Using Pwms
  431
- Generating Sine Waves
  431
Register Overview

432
Chapter 25: Lpc29Xx Pulse Width Modulator (PWM)

433
How to Read this Chapter

433
Introduction

433
Shadow Registers and Related Update Mechanism

433
Functional Description

434
- PWM Counter Synchronization
  435
- Delayed Register Update Triggered by Timer 0
  435
- Center-Aligned PWM
  436
- Input Capturing
  436
- Modulation of PWM and Timer Carrier
  436
Register Overview

437
- PWM Shadow Registers
  440
- PWM Mode Control Register
  440
- PWM Trap Control Register
  442
- PWM Capture Control Register
  442
- PWM Capture Source Register
  443
- PWM Control Register
  444
- PWM Period Register
  444
- PWM Prescale Register
  445
- PWM Synchronization Delay Register
  445
- PWM Count Register
  445
- PWM Match Active Registers
  446
- PWM Match Deactive Registers
  446
- PWM Capture Registers
  446
- PWM Mode Control Shadow Register
  447
- PWM Trap Control Shadow Register
  447
- PWM Capture Control Shadow Register
  448
- PWM Capture Source Shadow Register
  448
- PWM Control Shadow Register
  449
- PWM Period Shadow Register
  449
- PWM Prescale Shadow Register
  450
- PWM Synchronization Delay Shadow Register 450 PWM Match Active Shadow Registers
  450
- PWM Match Deactive Shadow Registers
  451
- PWM Interrupt Bit Description
  451
Chapter 26: Lpc29Xx Analog-To-Digital Converter (ADC)

453
How to Read this Chapter

453
ADC Functional Description

453
Pin Description

455
Register Overview

455
- ADC Channel Configuration Register
  457
- ADC Channel-Compare Register
  458
- ADC Channel Conversion Data Register
  459
- Compare Status Register
  459
- Compare-Status Clear Register
  460
- ADC Configuration Register
  460
- ADC Control Register
  462
- ADC Status Register
  462
- ADC Interrupt Bit Description
  463
Chapter 27: Lpc29Xx Quadrature Encoder Interface (QEI)

464
How to Read this Chapter

464
Introduction

464
Functional Description

466
- Input Signals
  466
- Quadrature Input Signals
  466
- Digital Input Filtering
  467
- Position Capture
  467
- Velocity Capture
  467
- Velocity Compare
  468
Pin Description

469
Register Overview

469
- QEI Control (QEICON)
  469
- QEI Configuration (QEICONF)
  470
- QEI Status (QEISTAT)
  470
- QEI Position (QEIPOS)
  470
- QEI Maximum Position (QEIMAXPOS)
  471
- QEI Position Compare 0 (CMPOS0)
  471
- QEI Position Compare 1 (CMPOS1)
  471
- QEI Position Compare 2 (CMPOS2)
  471
- QEI Index Count (INXCNT)
  472
- QEI Index Compare (INXCMP)
  472
- QEI Timer Reload (QEILOAD)
  472
- QEI Timer (QEITIME)
  472
- QEI Velocity (QEIVEL)
  472
- QEI Velocity Capture (QEICAP)
  473
- QEI Velocity Compare (VELCOMP)
  473
- QEI Digital Filter (FILTER)
  473
- Interrupt Registers
  473
- QEI Interrupt Bit Description
  473
Chapter 28: Lpc29Xx Flash/Eeprom

475
How to Read this Chapter

475
Flash Memory/Eeprom Controller Functional Description

475
- Flash Memory Layout
  476
- Flash Memory Reading
  477
- Flash Memory Writing
  477
- Erase Sequence (for One or more Sectors)
  478
- Burn Sequence (for One or more
  478
- Flash Signature Generation
  479
- Flash Interrupts
  479
- Flash Memory Index-Sector Features
  480
- Index Sector Programming
  481
- Index Sector Customer Info
  482
- JTAG Security
  482
- Flash Memory Sector Protection
  482
- EEPROM Functional Description
  483
- Addressing
  484
- Initialization
  484
- EEPROM Operations
  485
- Writing
  485
- Programming
  486
- Reading
  487
- Error Responses
  488
- EEPROM Usage Note
  488
- EEPROM Interrupts
  488
Register Overview

489
- Flash Memory Control Register
  490
  - Unprotect Sector
    491
  - Erase Sector
    491
  - Burn Page
    491
  - Preset Data Latches
    491
- Flash Memory Program-Time Register
  492
- Flash Test Control Register
  492
- Flash Bridge Wait-States Register
  492
- Flash-Memory Clock Divider Register
  493
- Flash-Memory bist Control Registers
  494
- Flash-Memory bist Signature Registers
  495
- EEPROM Command Register
  495
- EEPROM Address Register
  496
- EEPROM Write Data Register
  497
- EEPROM Read Data Register
  497
- EEPROM Wait State Register
  498
- EEPROM Clock Divider Register
  499
- EEPROM Power-Down Register
  500
- EEPROM bist Start Address Register
  500
- EEPROM bist Stop Address Register
  500
- EEPROM Signature Register
  501
- FMC Interrupt Bit Description
  501
Flash and EEPROM Programming Details

502
- AHB Programming
  502
- Un)Protecting Sectors
  503
- Erasing a Single Sector
  504
- Erasing Multiple Sectors
  504
- Presetting Data Latches
  505
- Writing and Loading
  505
- Burning
  505
- Index Sector Programming
  506
- Algorithm for Signature Generation
  506
  - Signature Generation
    506
  - Content Verification
    507
Chapter 29 : Lpc29Xx General Purpose DMA (GPDMA) Controller

509
How to Read this Chapter

509
Introduction

509
Features

509
Functional Description

510
- DMA Controller Functional Description
  510
- AHB Slave Interface
  510
- Control Logic and Register Bank
  510
- DMA Request and Response Interface
  510
- Channel Logic and Channel Register Bank
  511
- Interrupt Request
  511
- AHB Master Interface
  511
- Bus and Transfer Widths
  511
- Endian Behavior
  511
- Error Conditions
  513
- Channel Hardware
  514
- DMA Request Priority
  514
- Interrupt Generation
  514
- DMA System Connections
  514
- DMA Request Signals
  515
- DMA Response Signals
  515
Register Overview

515
Using the DMA Controller

527
- Programming the DMA Controller
  527
- Enabling the DMA Controller
  527
- Disabling the DMA Controller
  527
  - Enabling a DMA Channel
    527
- Disabling a DMA Channel
  528
  - Fifo
    528
  - Disabling the DMA Channel Without Losing Data in the FIFO
    528
- Setting up a New DMA Transfer
  528
- Halting a DMA Channel
  528
- Programming a DMA Channel
  528
  - Flow Control
    529
- Peripheral-To-Memory or Memory-To-Peripheral DMA Flow
  530
- Peripheral-To-Peripheral DMA Flow
  530
  - Memory-To-Memory DMA Flow
    531
- Interrupt Requests
  531
  - Hardware Interrupt Sequence Flow
    531
- Address Generation
  532
  - Word-Aligned Transfers Across a Boundary . 532 Scatter/Gather
    532
- Linked List Items
  533
- Programming the DMA Controller for Scatter/Gather DMA
  533
- Example of Scatter/Gather DMA
  533
Chapter 30: Lpc29Xx ETM/ETB Interface

536
How to Read this Chapter

536
Features

536
Introduction

536
Description

536
- ETM9 Configuration
  536
- ETB Configuration
  537
Block Diagram

537
Register Description

538
- ETM Registers
  538
- ETB Registers
  538
Abbreviations

539
Glossary

540
References

541
Legal Information

542
- Definitions
  542
- Disclaimers
  542
- Trademarks
  542
Tables

543
- Table of Contents
  555
Chapter 31: Supplementary Information

565

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors LPC2926FBD144 Manuals

NXP Semiconductors LPC2926FBD144 User Manual (566 pages)

Table of Contents

Chapter 1: Lpc29Xx Introductory Information

Introduction

About this User Manual

General Features

Ordering Information

Block Diagram

Functional Blocks

Architectural Overview

ARM968E-S Processor

On-Chip Flash Memory System

On-Chip Static RAM

Chapter 2: Lpc29Xx Memory Mapping

How to Read this Chapter

Memory-Map View of the AHB

Memory-Map Regions

Memory-Map Operating Concepts

Chapter 3: Lpc29Xx Clock Generation Unit (CGU)

How to Read this Chapter

Introduction

CGU0 Functional Description

CGU1 Functional Description

Register Overview

Chapter 4 : Lpc29Xx Reset Generation Unit (RGU)

How to Read this Chapter

Introduction

RGU Functional Description

Register Overview

Chapter 5: Lpc29Xx Power Management Unit (PMU)

How to Read this Chapter

Introduction

PMU Functional Description

Register Overview

Chapter 6: Lpc29Xx System Control Unit (SCU)

How to Read this Chapter

Introduction

Register Overview

Chapter 7: Lpc29Xx Chip Feature ID (CFID)

Introduction

Register Overview

Chapter 8: Lpc29Xx Event Router

How to Read this Chapter

Event Router Functional Description

Register Overview

Chapter 9: Lpc29Xx Vectored Interrupt Controller (VIC)

How to Read this Chapter

VIC Functional Description

VIC Programming Example

Register Overview

Chapter 10: Lpc29Xx General System Control

How to Read this Chapter

Introduction

Power Modes

Reset and Power-Up Behavior

Functional Description of the Interrupt and Wake-Up Structure

Interrupt Device Architecture

ISR Functional Description

Wake-Up

Chapter 11 : Lpc29Xx Pin Configuration

How to Read this Chapter

LPC2917/19/01 Pinning Information

LPC2921/23/25 Pin Configuration

LPC2927/29 Pin Configuration

LPC2930/30 Pin Configuration

LPC2930 Boot Control

Chapter 12: Lpc29Xx External Static Memory Controller (SMC)

How to Read this Chapter

SMC Functional Description

External Memory Interface

Register Overview

Chapter 13: Lpc29Xx USB Device

How to Read this Chapter

Introduction

Features

Fixed Endpoint Configuration

Functional Description

Operational Overview

Pin Description