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NXP Semiconductors LPC546 Series User Manual
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NXP Semiconductors LPC546 Series User Manual

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UM10912
LPC546xx User manual
Rev. 1.7 — 14 April 2017
Document information
Info
Content
Keywords
LPC546xx, ARM Cortex-M4, 32-bit microcontroller, LCD, Ethernet AVB,
SPIFI, SCT/PWM, USB Host, USB device, CAN FD, I2C, I2S, EEPROM,
Flash, EMC, SDRAM controller, DMIC, SDIO interface, SD card interface,
LCD controller, eCRP
Abstract
LPC546xx User Manual
User manual

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Summary of Contents for NXP Semiconductors LPC546 Series

  • Page 1 UM10912 LPC546xx User manual Rev. 1.7 — 14 April 2017 User manual Document information Info Content Keywords LPC546xx, ARM Cortex-M4, 32-bit microcontroller, LCD, Ethernet AVB, SPIFI, SCT/PWM, USB Host, USB device, CAN FD, I2C, I2S, EEPROM, Flash, EMC, SDRAM controller, DMIC, SDIO interface, SD card interface, LCD controller, eCRP Abstract LPC546xx User Manual...
  • Page 2 POR or a BOD event will reset it to its default value. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 3 32 kHz oscillator, or the watchdog oscillator (see Figure 4 and related registers). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 4 For sales office addresses, please send an email to: salesaddresses@nxp.com UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 4 of 1149...
  • Page 5 32 kB SRAM on the I&D buses. 8 kB of SRAM bank intended for USB traffic. – 16 kB of EEPROM. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 5 of 1152...
  • Page 6 – Two CAN FD modules with dedicated DMA controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 6 of 1152...
  • Page 7 – 24-bit Multi-Rate Timer (MRT) module with four channels each capable of generating repetitive interrupts at different, programmable frequencies. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 7 of 1152...
  • Page 8 Operating temperature range 40 °C to +105 °C. • • Available in TFBGA180 and LQFP208 packages. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 8 of 1152...
  • Page 9 - Yellow shaded blocks include dedicated DMA Ctrl. aaa-026740 Fig 1. Block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 9 of 1152...
  • Page 10 It also allows separation of data for different peripherals functions, in UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 11 The LPC546xx contains up to 16 kB of on-chip EEPROM memory. The EEPROM is accessible only by the CPU. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 11 of 1152...
  • Page 12 LPC54606 devices (HS/FS USB, Ethernet, CAN 2.0) LPC54606J256ET180 TFBGA180 LPC54606J512BD208 LQFP208 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 12 of 1152...
  • Page 13 …continued LPC54605 devices (HS/FS USB) LPC54605J256ET180 TFBGA180 LPC54605J512ET180 TFBGA180 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 13 of 1152...
  • Page 14 Peripheral bit band alias addressing band alias (32 MB) addressing UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 14 of 1152...
  • Page 15 SRAM when not used for USB. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 15 of 1152...
  • Page 16 AHB/APB peripheral base address = 0x4000 0000 • RAM bit-band base address = 0x2200 0000 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 16 of 1152...
  • Page 17 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 17 of 1152...
  • Page 18 The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers. Fig 2. Main memory map UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 18 of 1152...
  • Page 19 The MPU register interface is located on the private peripheral bus and is described in detail in Ref. 1 “Cortex-M4 TRM”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 19 of 1152...
  • Page 20 Pin interrupt 2 or pattern match engine slice 2 PSTAT - pin interrupt status UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 21 Flexcomm Interface 9 (USART, SPI, I2C) Same as Flexcomm0. SDIO SD/MMC interrupt UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 21 of 1152...
  • Page 22 Smart card 0 interrupt SMARCARD1_IRQ Smart card 1 interrupt UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 22 of 1152...
  • Page 23 Interrupt priority register 11. This register contains the 3-bit priority fields for 3.4.20 interrupts 44 to 47. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 23 of 1152...
  • Page 24 Software trigger interrupt register, allows software to generate interrupts. 3.4.26 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 24 of 1152...
  • Page 25 Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 26 3.4.4). Enabling interrupts is done through the ISER0 and ISER1 registers (Section 3.4.1 Section 3.4.2). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 26 of 1152...
  • Page 27 ISPR0 and ISPR1 registers (Section 3.4.5 Section 3.4.6). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 27 of 1152...
  • Page 28 7 priorities, where 0 is the highest priority. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 28 of 1152...
  • Page 29 7 priorities, where 0 is the highest priority. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 30 31:29 IP_ADC0SEQB ADC 0 sequence B interrupt priority. 0 = highest priority. 7 = lowest priority. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 31 Pin interrupt / pattern match engine slice 7 priority. 0 = highest priority. 7 = lowest priority. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 32 USB1 interface interrupt priority. 0 = highest priority. 7 = lowest priority. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 33 23:21 - Reserved. 28:24 - Unused. 31:29 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 33 of 1152...
  • Page 34 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 34 of 1152...
  • Page 35 1. Select the main clock. The following options are available: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 35 of 1152...
  • Page 36 PIO2_29 Chapter 7 PIO3_12 Chapter 7 PIO3_20 Chapter 7 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 36 of 1152...
  • Page 37 The output of the USB PLL. The USB PLL and its source selection are shown in Figure 4 “Clock generation”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 37 of 1152...
  • Page 38 Output of the main oscillator. If used, this is connected to an external crystal and load capacitor. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 39 SDIO clock select SDIOCLKSEL[2:0] aaa-023922 Fig 4. Clock generation UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 39 of 1152...
  • Page 40 CLKOUT select SPIFICLKSEL[2:0] aaa-023923 CLKOUTSEL[2:0] Fig 5. Clock generation (continued) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 40 of 1152...
  • Page 41 4.5.26 AHBCLKCTRLCLR2 WO 0x248 Clear bits in AHBCLKCTRL2. 4.5.27 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 41 of 1152...
  • Page 42 4.5.57 DMICCLKDIV 0x3A8 DMIC clock divider. 0x4000 0000 4.5.58 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 42 of 1152...
  • Page 43 0x2000008F 4.5.85 PDRUNCFGSET0 0x620 Set bits in PDRUNCFG0. 4.5.86 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 43 of 1152...
  • Page 44 Reset Value reflects the data stored in defined bits only. Reserved bits assumed to be 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 45 0 to the NMIEN bit. Then change the source by updating the IRQN bits and re-enable the NMI source by setting NMIEN. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 45 of 1152...
  • Page 46 Each bit represents the reset state of one GPIO pin. This register is a read-only register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 46 of 1152...
  • Page 47 0 = Clear reset to this function. 1 = Assert reset to this function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 48 0 = Clear reset to this function. 1 = Assert reset to this function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 49 0 = Clear reset to this function. 1 = Assert reset to this function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 50 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 50 of 1152...
  • Page 51 PRESETCTRL1. This is a write-only register. For bit assignments, see Table UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 51 of 1152...
  • Page 52 WDT reset detected. Writing a one clears this flag. This bit is cleared by software writing a one to this bit, and by POR. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 52 of 1152...
  • Page 53 System reset detected. Writing a one clears this flag. 31:5 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 53 of 1152...
  • Page 54 Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable. 31:28 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 54 of 1152...
  • Page 55 Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable. 31:28 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 55 of 1152...
  • Page 56 AHBCLKCTRL1. This is a write-only register. For bit assignments, see Table UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 56 of 1152...
  • Page 57 AHBCLKCTRL2. This is a write-only register. For bit assignments, see Table UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 57 of 1152...
  • Page 58 System PLL output (pll_clk). RTC oscillator 32 kHz output (32k_clk). 31:2 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 58 of 1152...
  • Page 59 This register configures the peripheral clock for the SPI Flash Interface. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 59 of 1152...
  • Page 60 This register selects a clock source for the USB1 high-speed controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 60 of 1152...
  • Page 61 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 61 of 1152...
  • Page 62 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 62 of 1152...
  • Page 63 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 63 of 1152...
  • Page 64 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 64 of 1152...
  • Page 65 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 65 of 1152...
  • Page 66 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 66 of 1152...
  • Page 67 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 67 of 1152...
  • Page 68 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 68 of 1152...
  • Page 69 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 69 of 1152...
  • Page 70 The clock used by the fractional rate generator is selected via the FRGSEL register (see Section 4.5.39). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 70 of 1152...
  • Page 71 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 71 of 1152...
  • Page 72 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 72 of 1152...
  • Page 73 Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 73 of 1152...
  • Page 74 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 74 of 1152...
  • Page 75 Rising edge of device USB0_NEEDCLK triggers wake-up. PU_DISABLE Internal pull-up disable control. 31:5 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 75 of 1152...
  • Page 76 Frequency target clock select register (FREQMEAS_TARGET) - Section 8.6.6 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 76 of 1152...
  • Page 77 Forces PHY to wake-up. Normal PHY behavior. 31:5 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 77 of 1152...
  • Page 78 USB1 Device host USB1_NEEDCLK signal status. Low. High. 31:2 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 78 of 1152...
  • Page 79 SDRAM memories. See the LPC546xx data sheet for details on clock delay times. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 79 of 1152...
  • Page 80 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 80 of 1152...
  • Page 81 Select MII PHY Interface. Select RMII PHY Interface. 31:3 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 81 of 1152...
  • Page 82 Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. 15:8 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 82 of 1152...
  • Page 83 3. Set bit 30 (HSPDCLK) in FROCTRL register to 1. 4. Switch the main clock to fro_hf clock. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 83 of 1152...
  • Page 84 The selected high-speed FRO output (48 MHz or 96 MHz) is enabled. Reserved, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 84 of 1152...
  • Page 85 The actual frequency may be measured using the frequency measure block. See Section 4.2.3. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 85 of 1152...
  • Page 86 0x1E = 3.0 MHz 0x1F = 3.05 MHz 31:6 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 86 of 1152...
  • Page 87 Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO input. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 87 of 1152...
  • Page 88 = (((x ^ (x>>2) ^ (x>>3) ^ (x>>4)) & 1) << 7) | ((x>>1) & 0x7F); } NENC[9:0] = x; UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 88 of 1152...
  • Page 89 Reserved. Read value is undefined, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 89 of 1152...
  • Page 90 The USBPLLCTRL register provides control of the USB PLL. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 90 of 1152...
  • Page 91 Description Reset value LOCK USBPLL lock indicator. 31:1 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 91 of 1152...
  • Page 92 Description Reset value LOCK PLL lock indicator. 31:1 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 92 of 1152...
  • Page 93 = (((x ^ (x>>2)) & 1) << 4) | ((x>>1) & 0xF); } PDEC[6:0] = x; UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 93 of 1152...
  • Page 94 Reserved. Read value is undefined, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 94 of 1152...
  • Page 95 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 95 of 1152...
  • Page 96 See bit descriptions in the PDRUNCFG1 register. 0x1000 0000 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 96 of 1152...
  • Page 97 PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27). Powered. Powered down. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 97 of 1152...
  • Page 98 Power control for EEPROM. Also, see bit 5 in PDRUNCFG1 register. Powered. Powered down. 31:30 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 98 of 1152...
  • Page 99 PDEN_RNG Random Number Generator Power. Powered. Powered-down. 31:8 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 99 of 1152...
  • Page 100 Bits that do not correspond to defined bits in PDRUNCFG1 are reserved and only zeroes should be written to them. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 100 of 1152...
  • Page 101 USB0_NEEDCLK USB activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 102 STARTER0. This is a write-only register. For bit assignments, see Table 139. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 102 of 1152...
  • Page 103 These wake-ups are based on peripheral FIFO levels, not directly related to peripheral DMA requests and interrupts, and can UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 103 of 1152...
  • Page 104 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 104 of 1152...
  • Page 105 0xFFF54608 LPC54616J256ET180 0x7F954616 LPC54616J512BD208 0xFFF54616 LPC54618J512ET180 0xFFF54618 LPC54618J512BD208 0xFFF54618 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 105 of 1152...
  • Page 106 Table 150. Device ID1 register (DEVICE_ID1, main syscon: offset 0xFFC) bit description Symbol Description Value 31:0 REVID Revision 0x08410CAA UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 106 of 1152...
  • Page 107 Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 107 of 1152...
  • Page 108 This register selects a potential clock for the asynchronous APB peripherals from among several clock sources. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 108 of 1152...
  • Page 109 BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit. 31:8 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 109 of 1152...
  • Page 110 If the BOD reset is enabled, the forced BOD reset can wake up the chip from reduced power modes, not including deep power-down. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 110 of 1152...
  • Page 111 Application code, especially interrupts, can continue to run from other memories during flash erase/write operations. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 111 of 1152...
  • Page 112 – Post-divider. Divide by 1 or 2 x P, where P = 1 to 32 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 113 PLL is not in lock. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 114 In the equations, use N = 1 when the pre-divider is not used: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 115 – Fout is in the range of 4.3 MHz to 550 MHz. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 116 USB1 in high speed mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 116 of 1152...
  • Page 117 1 to 32. For PLL register descriptions, see Section 4.5.81. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 117 of 1152...
  • Page 118 – Pre-divider. Divide by N, where N = 1 to 256 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 118 of 1152...
  • Page 119 PDRUNCFG0 (Section 4.5.84). In this mode, the UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 119 of 1152...
  • Page 120 MHz. Fig 12. Frequency measure block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 120 of 1152...
  • Page 121 If the target and reference clocks are different by more than a factor of approximately 500, then the accuracy decreases to ±4%. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 121 of 1152...
  • Page 122 USART, WWDT, RTC, Micro-tick Timer, and BOD can be left running in deep-sleep mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 122 of 1152...
  • Page 123 Certain Flexcomm Interface and DMIC subsystem activity. See Section 4.5.96 “Hardware Wake-up control register”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 123 of 1152...
  • Page 124 Certain Flexcomm Interface and DMIC subsystem activity. See Section 4.5.96 “Hardware Wake-up control register”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 124 of 1152...
  • Page 125 PLL, the system oscillator, 32 kHz oscillator, or the watchdog oscillator (see Figure 4 and related registers). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 125 of 1152...
  • Page 126 1. In the NVIC, enable all interrupts that are needed to wake up the part. 2. Call power API (see Section 40.4.2). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 126 of 1152...
  • Page 127 The peripheral parameter is a 64-bit value that corresponds to bits in the PDRUNCFG0 and PDRUNCFG1 registers. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 127 of 1152...
  • Page 128 The part goes through the entire reset process when the RTC times out: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 129 • All registers will be in their reset state. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 129 of 1152...
  • Page 130 PIO0_4 ISP_1 PIO0_5 ISP_2 PIO0_6 USART mode FC0_TXD PIO0_30 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 130 of 1152...
  • Page 131 Chapter 41 “LPC546xx Flash API” for ISP and IAP commands. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 131 of 1152...
  • Page 132 6.3.1 Boot process flowchart Fig 13. Legacy image boot process flowchart UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 132 of 1152...
  • Page 133 1. ECRP is checked using most restrictive combination of OTP and flash feature bits. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 134 0. If 2 images exist, the version number is UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 135 OTP and the ECRP of the images found and then the code locks in UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 136 __Vectors DCD __initial_sp ; Top of Stack Reset_Handler ; Reset Handler NMI_Handler HardFault_Handler MemManage_Handler UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 136 of 1152...
  • Page 137 If the value is 0, then the fourth entry is used as the length to UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 138 ECRP) automatically enters the ISP mode by selecting USART/ I2C/ SPI as the mode UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 139 Chapter 6: LPC546xx Boot process (see Chapter 41 “LPC546xx Flash API”). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 139 of 1152...
  • Page 140 IOCON clock can be disabled in order to conserve power. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 141 7.5. The following sections describe specific characteristics of pins. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 141 of 1152...
  • Page 142 = 0) and disable the digital pin function (DIGIMODE = 0). The MODE field should also be set to 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 142 of 1152...
  • Page 143 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 143 of 1152...
  • Page 144 Digital I/O control for port 5 pins. 0x0320 7.5.1 0x2A8] UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 144 of 1152...
  • Page 145 For PIO0_11 and PIO0_12, the reset value is 0x5. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 145 of 1152...
  • Page 146 The input may be turned off by clearing DIGIMODE if it is not needed. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 147 DIGIMODE bit in the related IOCON register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 148 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 173. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name/ FUNC = 1 FUNC = 2...
  • Page 149 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 173. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name/ FUNC = 1 FUNC = 2...
  • Page 150 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 173. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name/ FUNC = 1 FUNC = 2...
  • Page 151 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 173. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name/ FUNC = 1 FUNC = 2...
  • Page 152 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 173. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name/ FUNC = 1 FUNC = 2...
  • Page 153 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 173. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name/ FUNC = 1 FUNC = 2...
  • Page 154 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 175. Type A I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Reg name FUNC = 0 FUNC = 1 FUNC = 2...
  • Page 155 ADC and the SCTimer/PWM. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 155 of 1152...
  • Page 156 The input mux for the pin interrupts and pattern match engine multiplexes all existing pins from ports 0 and 1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 156 of 1152...
  • Page 157 Chapter 8: LPC546xx Input multiplexing (INPUT MUX) Fig 17. Pin interrupt multiplexing UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 157 of 1152...
  • Page 158 8.5.3 DMA trigger input multiplexing Fig 18. DMA trigger multiplexing UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 158 of 1152...
  • Page 159 Trigger select register for DMA channel 17. 0x1F 8.6.3 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 159 of 1152...
  • Page 160 Input mux register 6, which selects the input for SCT0 input 6. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 161 To use the selected pins for pin interrupts or the pattern match engine, see Section 10.5.2 “Pattern match engine”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 161 of 1152...
  • Page 162 21 = DMA output trigger mux 3 31:5 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 162 of 1152...
  • Page 163 5 = Main clock (main_clk) 6 = FREQME_GPIO_CLK_A 7 = FREQME_GPIO_CLK_B 31:5 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 163 of 1152...
  • Page 164 4.5.29) 6 = FREQME_GPIO_CLK_A 7 = FREQME_GPIO_CLK_B 31:5 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 164 of 1152...
  • Page 165 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 165 of 1152...
  • Page 166 Write: Set register for port 3. 9.5.7 Read: output bits for port 3. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 166 of 1152...
  • Page 167 0x2494 Toggle pin direction bits for port 5. 9.5.12 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 167 of 1152...
  • Page 168 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 168 of 1152...
  • Page 169 1 = Read: output bit; write: set output bit. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 169 of 1152...
  • Page 170 0 = No operation. 1 = Clear direction bit. 31:29 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 170 of 1152...
  • Page 171 0 = no operation. 1 = Toggle direction bit. 31:29 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 171 of 1152...
  • Page 172 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 172 of 1152...
  • Page 173 To make a decision based on multiple pins, read and mask a PORT register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 174 – Pattern match can be used, in conjunction with software, to create complex state machines based on pin inputs. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 174 of 1152...
  • Page 175 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 176 (the detect logic output remains HIGH) until the pattern match engine detect logic is cleared again. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 176 of 1152...
  • Page 177 Fig 20. Pattern match engine connections UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 177 of 1152...
  • Page 178 Fig 21. Pattern match bit slice with detect logic UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 178 of 1152...
  • Page 179 Related links: Section 10.7.2 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 179 of 1152...
  • Page 180 PMCFG 0x030 Pattern match interrupt bit slice configuration. 10.6.13 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 180 of 1152...
  • Page 181 1 = Enable rising edge or level interrupt. 31:8 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 181 of 1152...
  • Page 182 1 = Select HIGH-active interrupt or enable falling edge interrupt. 31:8 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 182 of 1152...
  • Page 183 All edges are detected for all pins selected by the PINTSELn registers, regardless of whether they are interrupt-enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 183 of 1152...
  • Page 184 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 184 of 1152...
  • Page 185 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 186 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 187 (the detect logic output remains HIGH) until the pattern match engine detect logic is cleared again. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 187 of 1152...
  • Page 188 Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 188 of 1152...
  • Page 189 0x3). This bit is cleared after one clock cycle. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 189 of 1152...
  • Page 190 0x3). This bit is cleared after one clock cycle. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 190 of 1152...
  • Page 191 0x3). This bit is cleared after one clock cycle. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 191 of 1152...
  • Page 192 0x3). This bit is cleared after one clock cycle. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 192 of 1152...
  • Page 193 – SRC6: 101 - select input 5 for bit slice 6 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 193 of 1152...
  • Page 194 – The remaining bits will always be low. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 194 of 1152...
  • Page 195 Fig 23. Pattern match engine examples: Windowed non-sticky edge detect evaluates as true UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 196 Fig 24. Pattern match engine examples: Windowed non-sticky edge detect evaluates as false UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 197 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 197 of 1152...
  • Page 198 PORT_ENA1 0x044 GPIO grouped interrupt port 1 enable. 11.4.3 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 198 of 1152...
  • Page 199 1 = the port 0 pin is enabled and contributes to the grouped interrupt. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 200 (see Table 139). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 200 of 1152...
  • Page 201 For details on the trigger input and output multiplexing, see Section 8.5.3 “DMA trigger input multiplexing”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 201 of 1152...
  • Page 202 A sequence complete DMA UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 202 of 1152...
  • Page 203 DMA_ITRIG_INMUX16 Yes DMIC1 DMA_ITRIG_INMUX17 Yes SPIFI DMA_ITRIG_INMUX18 Yes Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 203 of 1152...
  • Page 204 Pin interrupt 3 Timer CTIMER0 Match 0 DMA request UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 204 of 1152...
  • Page 205 DMA controller that have commonly used terminology in the industry. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 206 Table 222: Channel descriptor for a single transfer Offset Description + 0x0 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 206 of 1152...
  • Page 207 The DMA will place data for each successive value at the next location for that peripheral. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 207 of 1152...
  • Page 208 To use channel chaining, first configure DMA channels x and y as if no channel chaining would be used. Then: • For channel x: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 208 of 1152...
  • Page 209 In sleep mode, the DMA can operate and access all enabled SRAM blocks, without waking up the CPU. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 209 of 1152...
  • Page 210 DMA requests and interrupts. See Section 4.5.96 for more information. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 210 of 1152...
  • Page 211 0x438 Transfer configuration register for DMA channel 3. 12.6.18 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 211 of 1152...
  • Page 212 Transfer configuration register for DMA channel 13. 12.6.18 Channel 14 registers UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 212 of 1152...
  • Page 213 0x568 Transfer configuration register for DMA channel 23. 12.6.18 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 213 of 1152...
  • Page 214 0x5B0 Transfer configuration register for DMA channel 29. 12.6.18 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 214 of 1152...
  • Page 215 The contents of each channel descriptor are described in Table 220. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 215 of 1152...
  • Page 216 Enables are cleared by writing to ENABLECLR0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 217 DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 217 of 1152...
  • Page 218 DMA interrupt output if it is enabled in the related INTENSET register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 219 This register is write-only. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 219 of 1152...
  • Page 220 0 = no effect. 1 = aborts DMA operations on channel n. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 220 of 1152...
  • Page 221 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 221 of 1152...
  • Page 222 Hardware DMA trigger is low level sensitive. The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 222 of 1152...
  • Page 223 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 223 of 1152...
  • Page 224 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 224 of 1152...
  • Page 225 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 225 of 1152...
  • Page 226 – Selected events can limit, halt, start, or stop a counter or change its direction. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 227 DIVIDER audio_pll_clk “none” SCTCLKDIV SCTCLKSEL[2:0] Fig 27. SCTimer/PWM clocking UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 227 of 1152...
  • Page 228 Chapter 13: LPC546xx SCTimer/PWM (SCT) Fig 28. SCTimer/PWM connections UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 228 of 1152...
  • Page 229 T4_OUT0, GPIOINT_BMATCH, USB0_FRAME_TOGGLE, USB1_FRAME_TOGGLE, ARM_TXEV, SMARTCARD0_TX_ACTIVE, SMARTCARD0_RX_ACTIVE, SMARTCARD1_TX_ACTIVE, SMARTCARD1_RX_ACTIVE, I2S6_SCLK, I2S7_SCLK. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 229 of 1152...
  • Page 230 Not used, set to 0. Same as type D. I2CSLEW: Set to 1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 230 of 1152...
  • Page 231 Any event can be enabled to: • Start, stop, or halt the counter. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 231 of 1152...
  • Page 232 Capability of selecting a “greater-than-or-equal-to” match condition for the purpose of event generation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 232 of 1152...
  • Page 233 L and H. The setting of the UNIFY bit is reflected in the register map: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 233 of 1152...
  • Page 234 0x060 SCT DMA request 1 register 0x0000 0000 13.6.15 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 234 of 1152...

  • Page 235: Name

    0x33C SCT event control register 7 0x0000 0000 13.6.25 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 235 of 1152...
  • Page 236 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 236 of 1152...
  • Page 237 = match/captures, j = events, k = states, p = outputs, q = inputs Fig 32. SCT event configuration and selection registers UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 237 of 1152...
  • Page 238 In the dual-counter mode, the events can be selected independently for each counter. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 239 The SCT output register to set or clear any of the SCT outputs or to read the state of the outputs. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 239 of 1152...
  • Page 240 Rising edges on input 7. Falling edges on input 7. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 240 of 1152...
  • Page 241 If bit UNIFY = 1 in the CONFIG register, only the _L bits are used. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 242 Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 242 of 1152...
  • Page 243 LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 243 of 1152...
  • Page 244 STOPT_L and STOP_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 244 of 1152...
  • Page 245 16 bits of the 32-bit unified counter. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 245 of 1152...
  • Page 246 Software can read the state of the SCT inputs in this read-only register in slightly different forms. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 246 of 1152...
  • Page 247 13.6.23). REGMODE_H is used only when the UNIFY bit is 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 247 of 1152...
  • Page 248 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 249 Clear output n (or set based on the SETCLR2 field). Toggle output. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 249 of 1152...
  • Page 250 DMA setup. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 250 of 1152...
  • Page 251 Output register when the H counter was not halted. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 251 of 1152...
  • Page 252 BIDIR = 1 and the counter counts down to 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 252 of 1152...
  • Page 253 0), setting bit 0 permanently enables this event. Conversely, clearing bit 0 will disable the event. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 253 of 1152...
  • Page 254 CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 254 of 1152...
  • Page 255 Each bit of an output set register is associated with a different event (bit 0 with event 0, etc.). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 255 of 1152...
  • Page 256 See the OUTPUTCTRL register. 31:16 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 256 of 1152...
  • Page 257 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 257 of 1152...
  • Page 258 Software must intervene to change out of this state. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 258 of 1152...
  • Page 259 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 259 of 1152...
  • Page 260 To configure the SCT as simple event controlled counter/timer, see Section 13.7.12. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 260 of 1152...
  • Page 261 3. Define how each event affects the counter: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 261 of 1152...
  • Page 262 2. Write to the STATE register to define the initial state. By default the initial state is state UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 263 1, and EV3/4 are enabled, which create the UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 264 0,1, 2, 3, 4 to 0. This is the default. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 264 of 1152...
  • Page 265 Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled in state 1. event 5 is enabled UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 265 of 1152...
  • Page 266 4.5.20), CTIMER3 and CTIMER4 in the ASYNCAPBCLKCTRL register (Section 4.5.104). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 266 of 1152...
  • Page 267 Pulse Width Demodulator via capture input • Free running timer UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 267 of 1152...
  • Page 268 TIMER CONTROL REGISTER PRESCALE REGISTER Fig 39. 32-bit counter/timer block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 268 of 1152...
  • Page 269 7. Note that match conditions may be used internally without the use of a device pin. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 269 of 1152...
  • Page 270 TC is reset to zero. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 270 of 1152...
  • Page 271 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 272 Symbol Description Reset value 31:0 TCVAL Timer counter value. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 272 of 1152...
  • Page 273 Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 273 of 1152...
  • Page 274 000, but capture and/or interrupt can be selected for the other 3 CAP inputs. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 274 of 1152...
  • Page 275 (Section 14.7.1 “Rules for single edge controlled PWM outputs” on page 280). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 275 of 1152...
  • Page 276 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 276 of 1152...
  • Page 277 Channel 2. CAPn.2 for CTIMERn Channel 3. CAPn.3 for CTIMERn UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 277 of 1152...
  • Page 278 Match. CTIMERn_MAT01 is controlled by EM1. PWM. PWM mode is enabled for CTIMERn_MAT1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 278 of 1152...
  • Page 279 Reset value 31:0 SHADOW Timer counter match shadow value. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 279 of 1152...
  • Page 280 PWM signal is HIGH already, then the PWM signal will be cleared with the start of the next PWM cycle. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 280 of 1152...
  • Page 281 DMA requests. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 281 of 1152...
  • Page 282 The Watchdog timer can be configured to run in deep-sleep mode. • Debug mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 282 of 1152...
  • Page 283 Set the Watchdog timer constant reload value in the TC register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 283 of 1152...
  • Page 284 (APB bus clock to WDCLK) is not shown in the block diagram. Fig 44. Windowed Watchdog timer block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 284 of 1152...
  • Page 285 The reload overwrite lock mechanism can only be disabled by a reset of any type. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 286 This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 286 of 1152...
  • Page 287 A watchdog feed prior to reaching the value of WDWINDOW will also cause a watchdog reset. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 287 of 1152...
  • Page 288 Reserved. Read value is undefined, only zero should be written. - UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 288 of 1152...
  • Page 289 0xFF FFFF 31:24 Reserved, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 289 of 1152...
  • Page 290 Fig 46. Correct watchdog feed with windowed mode enabled Fig 47. Watchdog warning interrupt UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 290 of 1152...
  • Page 291 1 kHz output for the high-resolution wake-up timer can be enabled in the RTC CTRL register (RTC1KHZ_EN bit). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 291 of 1152...
  • Page 292 The high-resolution wake-up timer can be disabled to conserve power if not used. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 292 of 1152...
  • Page 293 ) or a software reset of the RTC can clear the general purpose registers. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 293 of 1152...
  • Page 294 Input RTC oscillator input. RTCXOUT Output RTC oscillator output. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 294 of 1152...
  • Page 295 Writing a 1 clears this bit. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 296 RTC_ALARM and generate an alarm interrupt/wake-up if enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 296 of 1152...
  • Page 297 GPDATA Data retained during deep power-down mode or loss of main power as long as V supplied. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 297 of 1152...
  • Page 298 The modes for each timer are set in the timer’s control register. See Table 314. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 298 of 1152...
  • Page 299 While the timer is running in the one-shot interrupt mode, the following actions can be performed: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 299 of 1152...
  • Page 300 MRT resides, can cause the delay to be longer. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 300 of 1152...
  • Page 301 This register contains the MRT load value and controls how the timer is reloaded. The load value is IVALUE -1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 301 of 1152...
  • Page 302 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 302 of 1152...
  • Page 303 This channel is not in use. This channel is in use. 31:2 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 303 of 1152...
  • Page 304 If all timer channels are running, CHAN = 0xF. See text above for more details. 31:8 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 304 of 1152...
  • Page 305 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 305 of 1152...
  • Page 306 UM10912 Chapter 18: LPC546xx Repetitive Interrupt Timer (RIT) Rev. 1.7 — 14 April 2017 User manual 18.1 How to read this chapter This timer is available on all LPC546xx devices. 18.2 Features • 48-bit counter running from the main clock. Counter can be free-running or be reset by a generated interrupt.
  • Page 307 UM10912 NXP Semiconductors Chapter 18: LPC546xx Repetitive Interrupt Timer (RIT) Fig 50. Repetitive Interrupt Timer (RI Timer) block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved. User manual Rev.
  • Page 308 UM10912 NXP Semiconductors Chapter 18: LPC546xx Repetitive Interrupt Timer (RIT) 18.5 Register description Table 319. Register overview: Repetitive Interrupt Timer (RIT) (base address 0x4002 D000) Name Access Address Description Reset value Reference COMPVAL 0x000 Compare value LSB register. Holds the 32 LSBs of the 0xFFFF FFFF 18.5.1...
  • Page 309 UM10912 NXP Semiconductors Chapter 18: LPC546xx Repetitive Interrupt Timer (RIT) Table 322. RI Control register (CTRL, address 0x4002 D008) bit description Symbol Value Description Reset value RITENCLR Timer enable clear The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers.
  • Page 310 UM10912 NXP Semiconductors Chapter 18: LPC546xx Repetitive Interrupt Timer (RIT) Table 326. RI Counter MSB register (COUNTER_H, address 0x4002 D01C) bit description Symbol Description Reset value 15:0 RICOUNTER 16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL).
  • Page 311 UM10912 NXP Semiconductors Chapter 18: LPC546xx Repetitive Interrupt Timer (RIT) 18.6 RI timer operation Following reset, the counter begins counting up from 0. (The RIT bit must be set in the AHBCLKCTRL1 register to enable the clock to the RIT.) Whenever the counter value equals the 48-bit value programmed into the COMPVAL and COMPVAL_H registers, the interrupt flag will be set.
  • Page 312 The block diagram of the SysTick timer is shown below in the Figure Fig 51. System tick timer block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 312 of 1152...
  • Page 313 Refer to the appropriate ARM Cortex User Guide for details. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 313 of 1152...
  • Page 314 SYST_RVR register if the CPU is running at the frequency intended for use with the SYST_CALIB value. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 314 of 1152...
  • Page 315 When 0, a separate reference clock is available. When 1, a separate reference clock is not available. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 315 of 1152...
  • Page 316 SYST_RVR = (system clock frequency  10 ms) 1 = (12 MHz  10 ms) 1 = 120000 1 = 119999 = 0x0001 D4BF UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 316 of 1152...
  • Page 317 Power API. See Chapter 40 “LPC546xx Power profiles/Power control API”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 317 of 1152...
  • Page 318 CAP register with the value of counter. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 318 of 1152...
  • Page 319 This register allows enabling Micro-tick capture functions and selects the polarity of the capture triggers. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 319 of 1152...
  • Page 320 UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 321 Remark: The Flexcomm Interface function clock frequency should not be higher than 48 MHz. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 321 of 1152...
  • Page 322 Software may use this information to confirm the selection before proceeding. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 322 of 1152...
  • Page 323 Slave Select 3 input or output for the SPI function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 323 of 1152...
  • Page 324 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 325 Reserved. Read value is undefined, only zero should be written. 31:12 Flexcomm Interface ID. 0x00101 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 325 of 1152...
  • Page 326 Module identifier for the selected function. See specific device chapter UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 326 of 1152...
  • Page 327 Loopback mode for testing of data and flow control. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 327 of 1152...
  • Page 328 With specific register values: baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 329 – A start bit has been received. – Received data becomes available. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 329 of 1152...
  • Page 330 – Remark: By enabling or disabling specific USART interrupts, you can customize when the wake-up occurs. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 330 of 1152...
  • Page 331 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 331 of 1152...
  • Page 332 INTSTAT register provides a view of all interrupts that are both enabled and pending. Fig 54. USART block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 332 of 1152...
  • Page 333 Flexcomm Interface peripheral ID register when USART is selected. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 333 of 1152...
  • Page 334 Enabled. Break detect and generate is configured for LIN bus operation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 334 of 1152...
  • Page 335 High. If selected by OESEL, the output enable is active high. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 335 of 1152...
  • Page 336 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 336 of 1152...
  • Page 337 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 337 of 1152...
  • Page 338 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 338 of 1152...
  • Page 339 PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a R/W1C received character. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 339 of 1152...
  • Page 340 The INTENCLR register is used to clear bits in the INTENSET register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 341 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 341 of 1152...
  • Page 342 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 342 of 1152...
  • Page 343 The ADDR register holds the address for hardware address matching in address detect mode with automatic address matching enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 343 of 1152...
  • Page 344 Reserved, the value read from a reserved bit is not defined. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 344 of 1152...
  • Page 345 RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 345 of 1152...
  • Page 346 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 346 of 1152...
  • Page 347 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 347 of 1152...
  • Page 348 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 348 of 1152...
  • Page 349 This could be used to allow system software to observe incoming data without interfering with the peripheral driver. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 349 of 1152...
  • Page 350 31:16 ID Unique module identifier for this IP block. 0xE010 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 350 of 1152...
  • Page 351 For the same reason, multiple samples of each UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 352 RTS and CTS within the USART. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 352 of 1152...
  • Page 353 GPIO pin. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 353 of 1152...
  • Page 354 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 355 USART RX pin can be programmed to wake up the device. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 356 Configure the SPI function to wake up the part from low power modes. See Section 23.3.1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 356 of 1152...
  • Page 357 – Data available to be received. – Receive FIFO overflow. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 357 of 1152...
  • Page 358 Slave Select 3 for SPI on Flexcomm Interface n. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 358 of 1152...
  • Page 359 RXIGNORE, individual interrupt enables. Fig 56. SPI block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 359 of 1152...
  • Page 360 Flexcomm Interface peripheral ID register when SPI is selected. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 360 of 1152...
  • Page 361 Disabled. Enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 361 of 1152...
  • Page 362 Section 23.7.3.1 “Pre_delay and Post_delay”, Section 23.7.3.2 “Frame_delay”, and Section 23.7.3.3 “Transfer_delay”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 362 of 1152...
  • Page 363 In this register, the following notation is used: RO = read-only, W1C = write 1 to clear. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 364 Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 364 of 1152...
  • Page 365 Reserved. Read value is undefined, only zero should be written. - Slave Select Assert. Slave Select Deassert. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 365 of 1152...
  • Page 366 Reserved. Read value is undefined, only zero should be written. - UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 366 of 1152...
  • Page 367 RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 367 of 1152...
  • Page 368 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 368 of 1152...
  • Page 369 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 369 of 1152...
  • Page 370 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 370 of 1152...
  • Page 371 Remark: The active state of the SSEL1 pin is configured by bits in the CFG register. SSEL1 asserted. SSEL1 not asserted. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 371 of 1152...
  • Page 372 The FIFORD register is used to read values that have been received by the FIFO. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 373 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 373 of 1152...
  • Page 374 31:16 ID Unique module identifier for this IP block. 0xE020 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 374 of 1152...
  • Page 375 Same as mode 1 with SCK inverted. high falling rising UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 375 of 1152...
  • Page 376 Chapter 23: LPC546xx Serial Peripheral Interfaces (SPI) Fig 57. Basic SPI operating modes UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 376 of 1152...
  • Page 377 SSEL. Fig 58. Pre_delay and Post_delay UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 377 of 1152...
  • Page 378 See Section 23.7.7 for more information. Fig 59. Frame_delay UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 378 of 1152...
  • Page 379 SPI clock time. Transfer_delay is illustrated by the examples in Figure Fig 60. Transfer_delay UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 379 of 1152...
  • Page 380 SSELs is saved along with received data in the RXSSEL_N field of the FIFORD register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 380 of 1152...
  • Page 381 TRANSFER control bit. This may terminate the transfer while the FIFO still has data to send. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 381 of 1152...
  • Page 382 Use the RXIGNORE control bit setting to avoid the need to read the received data. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 383 Chapter 23: LPC546xx Serial Peripheral Interfaces (SPI) Fig 61. Examples of data stalls UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 383 of 1152...
  • Page 384 FCn_RTS_SCL_SSEL1 FCn_RXD_SDA_MOSI, C serial data. FCn_RXD_SDA_MOSI_DATA, or FCn_CTS_SDA_SSEL0 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 384 of 1152...
  • Page 385 C function is incorporated into the Flexcomm Interface, it does not make use of the Flexcomm Interface FIFO. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 385 of 1152...
  • Page 386 7. Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register. Table 403. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 386 of 1152...
  • Page 387 5. Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register. Table 403. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 387 of 1152...
  • Page 388 5. Acknowledge (“ack”) the data by setting SLVCONTINUE = 1 in the slave control register. See Table 406. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 388 of 1152...
  • Page 389 I2C->SLVDAT = 0xdd; // write data I2C->SLVCTL = I2C_SLVCTL_SLVCONTINUE; // continue transaction UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 389 of 1152...
  • Page 390 – Address match – Data available/ready for the Monitor function UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 390 of 1152...
  • Page 391 C-bus interface is shown in Figure Fig 62. I C block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 391 of 1152...
  • Page 392 Flexcomm Interface peripheral ID register when I2C is selected. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 392 of 1152...
  • Page 393 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 393 of 1152...
  • Page 394 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 394 of 1152...
  • Page 395 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 395 of 1152...
  • Page 396 Active. The Monitor function considers the I C bus to be active. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 396 of 1152...
  • Page 397 Slave NACKed transmitted data. Send a Stop or Repeated Start. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 397 of 1152...
  • Page 398 (Slave Transmitter mode). the slave, the slave becomes de-selected. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 398 of 1152...
  • Page 399 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 399 of 1152...
  • Page 400 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 400 of 1152...
  • Page 401 Section 24.7.2.1 “Rate calculations” for details on bus rate setup. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 401 of 1152...
  • Page 402 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 402 of 1152...
  • Page 403 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 403 of 1152...
  • Page 404 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 404 of 1152...
  • Page 405 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 405 of 1152...
  • Page 406 Section 24.7.8 “Automatic operation” for details of AUTONACK and related settings. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 406 of 1152...
  • Page 407 The SLVQUAL0 register can alter how Slave Address 0 (specified by the SLVADR0 register) is interpreted. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 407 of 1152...
  • Page 408 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 408 of 1152...
  • Page 409 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 409 of 1152...
  • Page 410 31:16 ID Unique module identifier for this IP block. 0xE030 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 410 of 1152...
  • Page 411 C bus specification for the I C mode that is being used. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 411 of 1152...
  • Page 412 – address is sent and the acknowledge bit has been received UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 412 of 1152...
  • Page 413 I C address. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 413 of 1152...
  • Page 414 DMA channels are used with the Monitor function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 414 of 1152...
  • Page 415 Software sets SLVNACK prior to receiving the final data byte. • Software receives the final data byte. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 415 of 1152...
  • Page 416 NACK Bus is ignored until software changes the setup. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 416 of 1152...
  • Page 417 (e.g. system clock frequency, PLL availability, etc.) but generally supports standard audio data rates. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 417 of 1152...
  • Page 418 FIFOCFG register (Section 25.7.5). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 418 of 1152...
  • Page 419 DSP and TDM modes. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 419 of 1152...
  • Page 420 MCLK can also be routed to the I S block and used to operate its functions. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 420 of 1152...
  • Page 421 0xC64 Configuration register 2 for channel pair 3. 25.7.17 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 421 of 1152...
  • Page 422 Offset is within the related Flexcomm Interface address space. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 422 of 1152...
  • Page 423 Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 423 of 1152...
  • Page 424 In other modes, data for the single channel of data is placed at the clock defined by POSITION. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 424 of 1152...
  • Page 425 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 425 of 1152...
  • Page 426 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 426 of 1152...
  • Page 427 MSTSLVCFG field in the CFG1 register = 0 or 2. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 428 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 428 of 1152...
  • Page 429 Generally, data interrupts would be disabled if DMA is enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 429 of 1152...
  • Page 430 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 430 of 1152...
  • Page 431 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 431 of 1152...
  • Page 432 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 432 of 1152...
  • Page 433 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 433 of 1152...
  • Page 434 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 434 of 1152...
  • Page 435 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 435 of 1152...
  • Page 436 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 436 of 1152...
  • Page 437 31:16 ID Unique module identifier for this IP block. 0xE090 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 437 of 1152...
  • Page 438 3) When MODE = 0x3, determines the duration of the WS pulse. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 439 Fig 67. DSP mode with 1 slot pulsed WS UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 439 of 1152...
  • Page 440 Fig 71. TDM and DSP modes with 1 slot pulsed WS UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 440 of 1152...
  • Page 441 Fig 74. TDM and DSP modes, mono, with WS pulsed for one SCK time UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 442 The function clock divider output rate would be 96,000 * (2 * 32) = 6.144 MHz. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 443 – Each data transfer between the bus and the FIFO will be a single value, starting with left, then right. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 443 of 1152...
  • Page 444 CPU when data is needed or available. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 444 of 1152...
  • Page 445 Wake-up: Enable interrupts for waking up from deep-sleep and deep-sleep 2 modes, enable the interrupts in the STARTER0 register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 445 of 1152...
  • Page 446 – Restart the HWVAD with step 6. A precedent reset of the filters in step 3 is optional. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 446 of 1152...
  • Page 447 76. Specific use examples are shown in Figure 77 through Figure UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 447 of 1152...
  • Page 448 Fig 78. Typical connection to two microphones sharing a data line UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 448 of 1152...
  • Page 449 Fig 80. Bypass mode with an external device taking over microphone access UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 450 Section 26.7 “Functional description”. Fig 81. DMIC subsystem block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 450 of 1152...
  • Page 451 Noise envelope estimator register. 26.6.20 ID register: 0xFFC Module ID. 26.6.21 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 451 of 1152...
  • Page 452 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 452 of 1152...
  • Page 453 This register adjust the gain of the 4FS PCM data from the input filter. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 454 This register provides status information for the FIFO and also indicates an interrupt from the peripheral function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 454 of 1152...
  • Page 455 2. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 455 of 1152...
  • Page 456 This register allows selecting 2FS output rather than 1FS output. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 456 of 1152...
  • Page 457 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 457 of 1152...
  • Page 458 * (THGS+1) > z7 * (THGN+1) HWVAD_RESULT = 1; else HWVAD_RESULT = 0; UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 458 of 1152...
  • Page 459 Indicates module ID and the number of channels in this DMIC interface. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 460 NVIC level is not affected by this bit setting UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 460 of 1152...
  • Page 461 There is also an intermediate filter result value available, which can be used for proprietary software-based analysis. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 461 of 1152...
  • Page 462 A block diagram of one DMIC channel is shown in Figure UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 462 of 1152...
  • Page 463 For the DMIC clock, the base clock divider values can be set in registers DIVHFCLK[0:1]. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 464 A final DC filter removes any unwanted DC component in the audio signal. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 465 FIFO trigger level event the DMA performs a copy of the data from the FIFO into SRAM. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 466 MCLK, can be used. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 466 of 1152...
  • Page 467 In average the system can stay longer in power save mode if spurious events can be filtered out. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 467 of 1152...
  • Page 468 UM10912 Chapter 27: LPC546xx SD/MMC and SDIO interface Rev. 1.7 — 14 April 2017 User manual 27.1 How to read this chapter The SD/MMC card interface is available on all LPC546xx devices. 27.2 Features The SD/MMC card interface supports the following features: •...
  • Page 469 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface • Pins: Configure pins that will be used for this peripheral in the IOCON register block. Chapter 7 for IOCON details, and Section 27.5 for recommended IOCON settings for the SDIO.
  • Page 470 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.5 Pin description Table 462. SD/MMC pin description Pin function Type Description SD_CLK SD/SDIO/MMC clock. SD_CARD_DET_N SDIO card detect for single slot. A 0 represents the presence of a card.
  • Page 471 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6 Register description Figure 91 shows the memory map of the SDIO peripheral. Fig 91. SDIO memory map Table 464. Register overview: SDMMC (base address: 0x4009 B000) Name Access Offset...
  • Page 472 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 464. Register overview: SDMMC (base address: 0x4009 B000) Name Access Offset Description Reset value Section WRTPRT 0x054 Write protect. 27.6.21 TCBCNT 0x05C Transferred CIU card byte count. 27.6.22 TBBCNT 0x060 Transferred host to BIU-FIFO byte count.
  • Page 473 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 465. Control register (CTRL, offset 0x000) bit description Symbol Value Description Reset value DMA_RESET DMA reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.
  • Page 474 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 465. Control register (CTRL, offset 0x000) bit description Symbol Value Description Reset value SEND_AUTO_STOP_CCSD Send auto stop ccsd. NOTE: Always set SEND_AUTO_STOP_CCSD and SEND_CCSD bits together; SEND_AUTO_STOP_CCSD should not be set independent of SEND_CCSD.
  • Page 475 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.3 Clock Divider register Table 467. Clock Divider register (CLKDIV, offset 0x008) bit description Symbol Description Reset value CLK_DIVIDER0 Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2 * 0 = 0 (no division, bypass), value of 1 means divide by 2 * 1 = 2, value of “FF”...
  • Page 476 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.7 Block Size register Table 471. Block Size register (BLKSIZ, offset 0x01C) bit description Symbol Description Reset value 15:0 BLOCK_SIZE Block size 0x200 31:16 Reserved 27.6.8 Byte Count register Table 472. Byte Count register (BYTCNT, offset 0x020) bit description...
  • Page 477 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 473. Interrupt Mask register (INTMASK, offset 0x024) bit description Symbol Description Reset value Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.
  • Page 478 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 475. Command register (CMD, offset 0x02C) bit description Symbol Value Description Reset value SEND_AUTO_STOP Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer.
  • Page 479 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 475. Command register (CMD, offset 0x02C) bit description Symbol Value Description Reset value UPDATE_CLOCK_REGISTERS_ Update clock registers only. Following register values transferred ONLY into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode);...
  • Page 480 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 475. Command register (CMD, offset 0x02C) bit description Symbol Value Description Reset value BOOT_MODE Boot Mode Mandatory Boot operation Alternate Boot operation VOLT_SWITCH Voltage switch bit Disabled. No voltage switching Enabled.
  • Page 481 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.15 Response register 3 Table 479. Response register 3 (RESP3, offset 0x03C) bit description Symbol Description Reset value 31:0 RESPONSE3 Bit[127:96] of long response 27.6.16 Masked Interrupt Status register Table 480. Masked Interrupt Status register (MINTSTS, offset 0x040) bit description...
  • Page 482 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.17 Raw Interrupt Status register Table 481. Raw Interrupt Status register (RINTSTS, offset 0x044) bit description Symbol Description Reset value CDET Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact.
  • Page 483 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.18 Status register Table 482. Status register (STATUS, offset 0x048) bit description Symbol Description Reset value FIFO_RX_WATERMARK FIFO reached Receive watermark level; not qualified with data transfer. FIFO_TX_WATERMARK FIFO reached Transmit watermark level; not qualified with data transfer.
  • Page 484 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.19 FIFO Threshold Watermark register Table 483. FIFO Threshold Watermark register (FIFOTH, offset 0x04C) bit description Symbol Value Description Reset value 11:0 TX_WMARK - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised.
  • Page 485 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 483. FIFO Threshold Watermark register (FIFOTH, offset 0x04C) bit description Symbol Value Description Reset value 30:28 DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the...
  • Page 486 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.6.22 Transferred CIU Card Byte Count register Table 486. Transferred CIU Card Byte Count register (TCBCNT, offset 0x05C) bit description Symbol Description Reset value 31:0 TRANS_CARD_BYTE_COUNT Number of bytes transferred by CIU unit to card.
  • Page 487 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 490. Bus Mode register (BMOD, offset 0x080) bit description Symbol Value Description Reset value 10:8 Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus.
  • Page 488 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 493. Internal DMAC Status register (IDSTS, offset 0x08C) bit description Symbol Description Reset value Card error summary. Indicates the status of the transaction to/from the card; also present in RINTSTS.
  • Page 489 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 494. Internal DMAC Interrupt Enable register (IDINTEN, offset 0x090) bit description Symbol Description Reset value Card error summary interrupt enable. When set, it enables the Card Interrupt summary. Reserved Normal interrupt summary enable.
  • Page 490 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 497. Card Threshold Control register (CARDTHRCTL, offset 0x100) bit description Symbol Value Description Reset value 15:2 Reserved 23:16 CARDTHRESHOLD - Card threshold size. Sets the read and/or write threshold within the 32-entry FIFOs.
  • Page 491 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.7 Functional description 27.7.1 Power/pull-up control and card detection unit Signal pull-up resistors can be enabled for the SD pins in IOCON by enabling the pull-up for the pads. The approximate pull-up value for a pin is about 50 kOhm. For designs that need to support legacy MMC cards in open-drain mode, an external pull-up controlled with a general purpose output and FET will be needed for the CMD line.
  • Page 492 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 499. SEND_AUTO_STOP bit Card Type Transfer Type Byte Count SEND_AUTO_STOP bit set Comments SDMEM Multiple-block write >0 Auto-stop after all bytes transfer SDIO Single-block read >0 Byte count = 0 is illegal...
  • Page 493 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface CPU wants to terminate the data transfer before the data transfer is complete, it can issue a stop or abort command, in which case the Module does not generate an auto-stop command.
  • Page 494 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface If the software issues a CONTROLLER_RESET command by setting control register (CTRL) bit[0] to 1, all the CIU state machines are reset; the FIFO is not cleared. The DMA sends all remaining bytes to the CPU. In addition to a card-reset, if a FIFO reset is also issued, then: •...
  • Page 495 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface ResponseTimeOut = 0x40 DataTimeOut = highest of one of the following: – (10  ((TAAC Fop) + (100 NSAC)) – CPU FIFO read/write latency from FIFO empty/full FIFO threshold value in bytes in the FIFOTH register. Typically, the threshold value can be set to half the FIFO depth (= 32/2);...
  • Page 496 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface – If ATA mode is supported, the CPU should select the ATA mode by setting the ATA bit (bit 4) of the EXT_CSD register slice 191(CMD_SET) to activate the ATA command set for use.
  • Page 497 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 3. Wait for command acceptance by CPU. The following happens when the command is loaded into the Module: – Module accepts the command for execution and clears the START_CMD bit in the CMD register, unless one command is in process, at which point the Module can load and keep the second command in the buffer.
  • Page 498 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.8.2.5 Data transfer commands Data transfer commands transfer data between the memory card and the Module. To send a data command, the Module needs a command argument, total data size, and block size.

  • Page 499: Start_Cmd

    UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 4. Software should look for data error interrupts; that is, bits 7, 9, 13, and 15 of the RINTSTS register. If required, software can terminate the data transfer by sending a STOP command.
  • Page 500 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 5. Program the Command register with the parameters listed in Table 502. For SD and MMC cards, use CMD24 for a single-block write and CMD25 for a multiple-block write. For SDIO cards, use CMD53 for both single-block and multiple-block transfers.
  • Page 501 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.8.2.8 Stream read A stream read is like the block read mentioned in "Single-Block or Multiple-Block Read", except for the following bits in the Command register (CMD): TRANSFER_MODE = 1; //Stream transfer CMD_INDEX = CMD20;...
  • Page 502 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface – Send ABORT command - Can be used with only an SDIO_IOONLY or SDIO_COMBO card. To abort the function that is transferring data, program the function number in ASx bits (CCCR register of card, address 0x06, bits (0-2) using CMD52.
  • Page 503 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface To suspend the transfer, set BR (bit 2) of the CCCR register. Poll for clear status of bits BR (bit 1) and BS (bit 0) of the CCCR. The BS (Bus Status) bit is 1 when the currently-selected function is using the data bus;...
  • Page 504 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 504. Parameters for CMDARG register Bits Contents Value 25-9 Register address 0x0D Don’t care Write data Function number to be aborted 27.8.2.13 Read_Wait Sequence Read_wait is used with only the SDIO card and can temporarily stall the data transfer-either from function or memory-and allow the CPU to send commands to any function within the SDIO device.

  • Page 505: Table Of Contents

    UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface The CPU software stack should write the task file image to the FIFO before setting the CMDARG and CMD registers. The CPU processor then sets the address and byte count in the CMDARG-offset 0x28 in the BIU register space-before setting the CMD (offset 0x2C) register bits.
  • Page 506 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 506. CMD register settings Name Value Comment CMD_INDEX Command index RESPONSE_LENGTH RESPONSE_EXPECT User-selectable USE_HOLD_REG CMD and DATA sent to card bypassing HOLD register. CMD and DATA sent to card through the HOLD register. Hold settings applied through the SDIOCLKCTRL register in Syscon.
  • Page 507 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 509. Parameters for CMDARG register Bits Contents Value 23:16 Reserved 15:8 Data Count Unit [15:8] Data count Data Count Unit [7:0] Data count • Program the Command (CMD) register as shown below.
  • Page 508 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface • Send CCSD - Module sends CCSD to the CE-ATA device if the SEND_CCSD bit is set in the CTRL register; this bit is set only after a response is received for the RW_BLK.
  • Page 509 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface • CMD register settings: – ccs_expect set to 1 – DATA_EXPECTED set to 1 • CMDARG register settings: – Bit [31] set to 0 (Read operation) Data Count set to 1 (16'h0001) •...
  • Page 510 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface • BLKSIZ register bits [15:0] and BYTCNT register - Set to 16 27.8.2.15 Controller/DMA/FIFO reset usage Communication with the card involves the following: • Controller - Controls all functions of the Module.
  • Page 511 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 513. Card Read Threshold for Round Trip Delay Model Round Trip Delay Is Stopping of Card Card Read Threshold (Delay_R = Delay_O + tODLY + Delay_I) Clock Allowed? Required? SDR25 Delay_R >...
  • Page 512 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 1. Choose Block Size The block size must be based on the following: – Rule 1 – DWORD-aligned Block Size The block size requested by the application from the card for the read transfer card must be DWORD-aligned.
  • Page 513 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface – Internal DMA (IDMAC) mode The size of the data buffer (BuffSize in bytes) for each descriptor must be a multiple of MSIZE * H_DATA_WIDTH / 8. For example, BuffSize = n * MSIZE * H_DATA_WIDTH / 8, where n = 1, 2, 3…...
  • Page 514 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface The following shows how to program the CardRdThreshold when BlkSize is greater than ½ FifoDepth. 1. Choose a DWORD-aligned BlkSize less than FifoDepth. If Block Size is 192 bytes, then BlkSize = 192 * 8/F_DATA_WIDTH = 48 FIFO locations 2.
  • Page 515 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface For example, RX_WMARK = 16 - 1 = 15 FIFO locations. 4. Since BlkSize < ½ FifoDepth, choose CardRdThreshold = Block Size. CardRdThreshold = 64 bytes. Fig 93. FIFO contents when BlkSize < ½ FifoDepth 27.8.2.17 Back-end power...
  • Page 516 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Fig 95. Flowchart for card power requirements 1. The driver reads the SMPC register. 2. If the value is 0, then the total power requirement is less than or equal to 720 mW.
  • Page 517 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 514. FBR registers for power tuning Addr: Field Type Description Support Power Selection • SPS = 0: Has no Power Selection; EPS is zero. • SPS = 1: Has two power modes selected by EPS.
  • Page 518 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface – If the value of SPS is 0, the function does not support power selection. – If the value of SPS is 1, the driver reads the EPS register. If the value of EPS is 0, the function is set to High Current Mode.
  • Page 519 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface • Write operation - Any MMC Transport layer error known to the device causes an outstanding ATA command to be terminated. The ERR bits are set in the ATA status registers and the appropriate error code is sent to the ATA Error register.
  • Page 520 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Fig 98. Dual buffer descriptor structure Fig 99. Chain descriptor structure 27.8.3.1 SD/MMC DMA descriptors 27.8.3.1.1 SD/MMC DMA descriptor DESC0 The DES0 descriptor contains control and status information. Table 515. SD/MMC DMA DESC0 descriptor...
  • Page 521 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 515. SD/MMC DMA DESC0 descriptor Symbol Description First Descriptor When set, this bit indicates that this descriptor contains the first buffer of the data. If the size of the first buffer is 0, next Descriptor contains the beginning of the data.
  • Page 522 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 517. SD/MMC DMA DESC2 descriptor Symbol Description 31:0 BAP1 Buffer Address Pointer 1 These bits indicate the physical address of the first data buffer. The SD/MMC DMA ignores DES2 [1:0], corresponding to the bus width of 64/32/16, internally.
  • Page 523 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.8.3.2.3 Buffer size calculations The driver knows the amount of data to transmit or receive. For transmitting to the card, the IDMAC transfers the exact number of bytes to the FIFO, indicated by the buffer size field of DES1.
  • Page 524 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 3. The Host will program the required receive threshold level (RX_WMARK field in FIFOTH register). 4. The SD/MMC DMA determines that a read data transfer needs to be done as a consequence of step 2.
  • Page 525 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 1. When the host issues CMD12 when a data transfer on the card data lines is in progress, the FSM closes the present descriptor after completing the transfer of data until a DTO interrupt is asserted.
  • Page 526 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 519. PBL and watermark levels PBL (number of transfers) Transmit/receive watermark value greater than or equal to 1 greater than or equal to 4 greater than or equal to 8...
  • Page 527 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface is inserted, the card-detect pin is shorted to ground, which makes card_detect_n go to 0. Similarly in SD cards, when the write-protect switch is toward the left, it shorts the SD_WR_PRT port to ground.
  • Page 528 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 2.2 RC = rise-time = 1/400 kHz R = 1/(2.2 * C * 100 kHz = 1/(2.2 x 20 x 10**-12 x 400 x 10**3 = 1/(1.76 x 10**-5 = 56.8K The Rod and Rcmd should be adjusted in such a way that the effective pull-up is at the maximum 5.68K during enumeration.
  • Page 529 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.9 Clocking and timing guidelines The SDMMC/SDIO interface (also referred to as the host controller) has four input clocks and one output clock. 27.9.1 Clock domains The SDMMC/SDIO interface has the following clocks: Table 520.
  • Page 530 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface – During data transfers, in order to avoid data loss when the host does not push or pop data to or from the FIFO at the rate the data is sent or received from the cards;...
  • Page 531 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface • tODLY = cclk_out to card output delay (varies across card manufactures and speed modes) • Delay_S = Delay by which cclk_in_sample is phase-shifted with regard to cclk_in • Delay_D = Delay by which cclk_in_drv is phase-shifted with regard to cclk_in •...
  • Page 532 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Table 521. Timing requirements Speed Mode Max cclk_out Frequency Min Hold Min Setup Max tODLY Time Time tODLY SDR12 14.0 0.35 Identification Mode 2500 50.0 0.02 MMC High Speed (DAT and CMD) 50 13.7...
  • Page 533 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface Fig 107. Timing diagram for phase-shifted clocks 27.9.2.3 SDIOCLKCTRL register The SDIOCLKCTRL is a 32-bit SYSCON register that allows delay the SD/MMC internal input clock for both sampling of input data from the SD card and delay of data output (drive) from the LPC54xxx to the SD card.
  • Page 534 UM10912 NXP Semiconductors Chapter 27: LPC546xx SD/MMC and SDIO interface 27.9.3 Stop clock Alternatively, you can avoid a stop-clock scenario by correctly enabling the Card Read Threshold feature and programming the Card Read Threshold Size—RX_WMARK and MSIZE; for details, refer to “Card Read Threshold Programming Sequence” on page 227.
  • Page 535 SCI0_SCLK, SCI1_SCLK Output Serial Clock. Smart Card clock output. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 535 of 1152...
  • Page 536 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 537 Reserved. Read value is undefined, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 537 of 1152...
  • Page 538 Reserved. Read value is undefined, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 538 of 1152...
  • Page 539 Reserved. Read value is undefined, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 539 of 1152...
  • Page 540 105 character message and the trigger level was 10 characters, the CPU would UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 541 SCInIIR occurs and the THRE is the highest interrupt (SCInIIR[3:1] = 001). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 541 of 1152...
  • Page 542 FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 542 of 1152...
  • Page 543 Reserved. Read value is undefined, only 0 should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 543 of 1152...
  • Page 544 Reserved. The value read from a reserved bit is not defined. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 544 of 1152...
  • Page 545 Smart Card interface disabled. Asynchronous half duplex Smart Card interface is enabled. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 545 of 1152...
  • Page 546 Fig 108. Typical Smart Card application UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 546 of 1152...
  • Page 547 • Poll GPIO attached to Smart Card insert signal. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 547 of 1152...
  • Page 548 Reset HIGH GPIO attached to Smart Card reset. • Capture Answer-to-Reset response from Smart Card. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 548 of 1152...
  • Page 549 3. Pins: Select SPIFI pins and pin modes through the relevant IOCON registers (see Chapter 7 “LPC546xx I/O pin configuration (IOCON)”). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 549 of 1152...
  • Page 550 If the flash memory does not have quad capability, these pins can be assigned to GPIO or other functions. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 550 of 1152...
  • Page 551 This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 551 of 1152...
  • Page 552 SPIFI memory area. DMAEN should only be used in Command mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 552 of 1152...
  • Page 553 The opcode of the command (not used for some FRAMEFORM values). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 553 of 1152...
  • Page 554 Load Halfword instructions deliver two bytes, and Load Word UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 555 All quad/dual. All fields of the command are in quad/dual format. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 555 of 1152...
  • Page 556 SPIFI. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 556 of 1152...
  • Page 557 SPI mode, and the most significant 4 bits first in quad mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 557 of 1152...
  • Page 558 3 bytes from the slave with the opcode and input data fields both in quad mode. Fig 111. Read commands UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 558 of 1152...
  • Page 559 DATALEN field of the Command register or reads or writes when no command was issued, the SPIFI hardware issues an abort exception. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 559 of 1152...
  • Page 560 There are at least 4 bytes in the FIFO for a read operation, or at least 4 empty byte locations in the FIFO for a write/program operation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 560 of 1152...
  • Page 561 In addition to the EMCStaticExtendedWait register which applies to all static chip selects. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 562 SDRAM. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 562 of 1152...
  • Page 563 3. Pins: Select EMC pins and pin modes through the relevant IOCON registers (Section 7.4.2). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 563 of 1152...
  • Page 564 7. To calibrate the EMC clock, see Section 4.5.73. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 564 of 1152...
  • Page 565 SDRAM bursts of four. For 16 bit wide chip selects, SDRAM bursts of eight are used. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 566 Registers. 30.5.4.1 Write buffers Write buffers are used to: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 566 of 1152...
  • Page 567 AHB transfer performs a write that hits the buffer. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 567 of 1152...
  • Page 568 112). See descriptions of the EMCDLYCTL and EMCCAL registers for more information. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 568 of 1152...
  • Page 569 The memory banks that are not refreshed lose their data contents. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 570 If the EMC is configured correctly, auto-refresh can be maintained through a warm reset. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 570 of 1152...
  • Page 571 Burst Control, and is found in the EMCSYSCTRL register (see Section 4.5.71 “EMC system control register”). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 571 of 1152...
  • Page 572 Single location access 120515 Fig 113. SDRAM mode register UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 572 of 1152...
  • Page 573 0xA000 0000 + (0x23 << (2 + 9 + 1)) = 0xA000 0000 + 0x23000 = 0xA002 3000 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 574 EMC_FBCK Feedback clock to sample SDRAM data. Input UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 574 of 1152...
  • Page 575 Delay for asynchronous page mode sequential 0x1F 30.13.25 accesses for EMC_CS0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 575 of 1152...
  • Page 576 POR reset value. Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 577 The EMC registers can be programmed in low-power and/or disabled state. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 578 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 578 of 1152...
  • Page 579 All data in the memory is lost. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 579 of 1152...
  • Page 580 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 580 of 1152...
  • Page 581 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 581 of 1152...
  • Page 582 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 582 of 1152...
  • Page 583 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 583 of 1152...
  • Page 584 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 584 of 1152...
  • Page 585 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 585 of 1152...
  • Page 586 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 586 of 1152...
  • Page 587 50 x 10 ) / 16 - 1 = 24 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 587 of 1152...
  • Page 588 The buffers must be disabled during SDRAM initialization. The buffers must be enabled during normal operation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 588 of 1152...
  • Page 589 512 Mbits (64M x 8) 512 Mbits (32M x 16) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 589 of 1152...
  • Page 590 Note: The values programmed into these registers must be consistent with the values used to initialize the SDRAM memory device. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 590 of 1152...
  • Page 591 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 591 of 1152...
  • Page 592 For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 592 of 1152...
  • Page 593 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 593 of 1152...
  • Page 594 The reset value depends on the boot mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 594 of 1152...
  • Page 595 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 595 of 1152...
  • Page 596 The WAITTURN field also controls the number of turnaround cycles between static memory and dynamic memory accesses. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 596 of 1152...
  • Page 597 32 bit wide memory bank interfaced to two 16 bit memory chips UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 598 Fig 115. 16 bit bank external memory interfaces (bits MW = 01) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 599 Fig 116. 8 bit bank external memory interface (bits MW = 00) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 600 128Kx8 SRAM , four o Fig 117. Typical memory configuration diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 600 of 1152...
  • Page 601 CGU from a variety of sources, including an LCD clock input pin. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 602 The LCD controller supports the following types of LCD panel: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 602 of 1152...
  • Page 603 4 bpp, palettized, 16 gray scales selected from 15. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 603 of 1152...
  • Page 604 CLKSEL bit in the LCD_POL register (Section 31.7.3). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 604 of 1152...
  • Page 605 LD refers to lower panel data. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 605 of 1152...
  • Page 606 LCD_VD[19] BLUE[0] BLUE[0] BLUE[3] LCD_VD[23:20] BLUE[3:0] BLUE[4:1] BLUE[4:1] BLUE[7:4] UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 606 of 1152...
  • Page 607 LCD controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 607 of 1152...
  • Page 608 The inherent AHB master interface state machine performs the following functions: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 608 of 1152...
  • Page 609 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 609 of 1152...
  • Page 610 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 610 of 1152...
  • Page 611 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 611 of 1152...
  • Page 612 Red 4 p0, Red 4 p0, Green 0 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 612 of 1152...
  • Page 613 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 613 of 1152...
  • Page 614 Blue palette data R[3:0] Red palette data Unused Unused UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 614 of 1152...
  • Page 615 Bits per pixel Words per line Words in cursor image UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 615 of 1152...
  • Page 616 120). The checked pattern shows the visible portion of the cursor. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 616 of 1152...
  • Page 617 32 x 32 format shown in Figure 121. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 617 of 1152...
  • Page 618 (16, 0) (0, y) (16, y) (0, 31) (16, 31) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 618 of 1152...
  • Page 619 (44, y) (60, y) (60, 63) Cursor pixel encoding UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 619 of 1152...
  • Page 620 FIFO, which has enough space to store eight color pixels. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 620 of 1152...
  • Page 621 The status of the individual interrupt sources can be read from the LCD_INTRAW register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 622 LCD_DCLK • LCD_FP • LCD_AC • LCD_VD[23:0] • LCD_LE UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 622 of 1152...
  • Page 623 Fig 122. Power-up and power-down sequences UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 623 of 1152...
  • Page 624 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 625 PCD = 4, the minimum value. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 625 of 1152...
  • Page 626 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 627 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 627 of 1152...
  • Page 628 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 628 of 1152...
  • Page 629 LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 629 of 1152...
  • Page 630 0 = little-endian byte order. 1 = big-endian byte order. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 630 of 1152...
  • Page 631 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 631 of 1152...
  • Page 632 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 632 of 1152...
  • Page 633 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 633 of 1152...
  • Page 634 LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 634 of 1152...
  • Page 635 Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 635 of 1152...
  • Page 636 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 636 of 1152...
  • Page 637 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 637 of 1152...
  • Page 638 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 638 of 1152...
  • Page 639 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 639 of 1152...
  • Page 640 Reserved. Read value is undefined, only zero should be written. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 640 of 1152...
  • Page 641 (1) Signal polarities may vary for some displays. Fig 124. Vertical timing for STN displays UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 641 of 1152...
  • Page 642 (1) Polarities may vary for some displays. Fig 126. Vertical timing for TFT displays UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 642 of 1152...
  • Page 643 P2[0] LCD_PWR LCD_CLKIN P2[11] LCD_CLKIN P2[11] LCD_CLKIN P2[0] LCD_PWR UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 643 of 1152...
  • Page 644 P2[0] LCD-PWR LCD_CLKIN P2[11] LCD_CLKIN P2[11] LCD_CLKIN P2[11] LCD_CLKIN UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 644 of 1152...
  • Page 645 LCD_CLKIN P2[11] LCD_CLKIN P2[11] LCD_CLKIN P2[11] LCD_CLKIN P2[11] LCD_CLKIN UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 645 of 1152...
  • Page 646 Pins: Select the MCAN pins and pin modes through the relevant IOCON registers (See Section 7.4.2). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 646 of 1152...
  • Page 647 Fig 127. MCAN IP block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 647 of 1152...
  • Page 648 MCAN0 receive input CAN1_TD MCAN1 transmit output CAN1_RD MCAN1 receive input UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 648 of 1152...
  • Page 649 32.8.34 TXBAR RW 0x0D0 Tx buffer add request. 32.8.35 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 649 of 1152...
  • Page 650 32.8.45 ETSCV RW 0x600 External timestamp counter value. 32.8.46 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 650 of 1152...
  • Page 651 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 651 of 1152...
  • Page 652 Low. CAN_TXD pin is driven LOW/dominant. High. CAN_TXD is driven HIGH/recessive. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 652 of 1152...
  • Page 653 CAN FD operation is disabled CAN FD operation is enabled UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 653 of 1152...
  • Page 654 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 654 of 1152...
  • Page 655 Symbol Description Reset value 15:0 Timestamp counter. 31:16 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 655 of 1152...
  • Page 656 ELO interrupt flag in the IR register. This counter is reset whenever a read access to these bits is made. 31:24 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 656 of 1152...
  • Page 657 At least one of error counter has reached the Error_Warning limit of 96 Bus off status. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 657 of 1152...
  • Page 658 The REC bits in the ECR register is used to count these sequences. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 659 Rx FIFO 1 not full Rx FIFO 1 full. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 659 of 1152...
  • Page 660 Timestamp wraparound. No timestamp counter wraparound Timestamp counter wrapped around UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 660 of 1152...
  • Page 661 Error_Passive status changed Warning status. Error_Warning status unchanged. Error_Warning status changed. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 661 of 1152...
  • Page 662 Rx FIFO 1 watermark reached interrupt enable. Interrupt disabled Interrupt enabled UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 662 of 1152...
  • Page 663 TOOE Timeout occurred interrupt enable. Interrupt disabled Interrupt enabled UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 663 of 1152...
  • Page 664 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 664 of 1152...
  • Page 665 Interrupt assigned to interrupt line MCANx_INT0 Interrupt assigned to interrupt line MCANx_INT1 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 665 of 1152...
  • Page 666 Interrupt assigned to interrupt line MCANx_INT0 Interrupt assigned to interrupt line MCANx_INT1 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 666 of 1152...
  • Page 667 Filter remote frames with 11-bit standard IDs Reject all remote frames with 11-bit standard IDs UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 667 of 1152...
  • Page 668 >64 = Values of greater than 64 are interpreted as 64 31:24 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 668 of 1152...
  • Page 669 A flag is cleared by writing a 1 to the corresponding bit position. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 670 1 will not set this flag. 31:26 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 670 of 1152...
  • Page 671 FIFO 1 operation mode. The FIFO can be operated in block or overwrite mode. FIFO 1 blocking mode FIFO 1 overwrite mode UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 671 of 1152...
  • Page 672 Reset value F1AI Rx FIFO 1 acknowledge index. 31:6 Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 672 of 1152...
  • Page 673 RXESC register are stored to the Rx buffer resp. Rx FIFO element. The data field of the rest of the frame is ignored. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 673 of 1152...
  • Page 674 15 points to the fourth buffer of the Tx FIFO. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 675 TXBCF bit is set for all unsuccessful transmissions. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 675 of 1152...
  • Page 676 1 to the corresponding bit in the TXBAR register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 676 of 1152...
  • Page 677 Cancellation finished interrupt disabled Cancellation finished interrupt enabled UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 677 of 1152...
  • Page 678 EFAI +1 and update the event FIFO fill level. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 678 of 1152...
  • Page 679 16-bit value. 31:16 - Reserved. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 679 of 1152...
  • Page 680 Transmitting node is error active Transmitting node is error passive UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 680 of 1152...
  • Page 681 32-bit words are used for storage of a CAN message’s data field. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 682 Transmit remote frame Extended identifier. 11-bit standard identifier 29-bit extended identifier UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 682 of 1152...
  • Page 683 32-bit words are used to store the data field of a CAN message. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 684 Standard frame format CAN FD frame format (new DLC-coding and CRC) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 684 of 1152...
  • Page 685 Message Marker. Copied from Tx buffer into Tx event FIFO element for identification of Tx message status. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 685 of 1152...
  • Page 686 Store into Rx buffer or as debug message, configuration of the SFT bit field is ignored UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 687 Classic filter: SFID1 = filter, SFID2 = mask Filter element disabled UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 687 of 1152...
  • Page 688 Store into Rx buffer or as debug message, configuration of the EFT bit field is ignored UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 689 Range filter from EFID1 to EFID2 (EFID2  EFID1), the mask in the XIDAM register is not applied UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 690 Both bits may be reset at any time. The DAR bit can only be set or reset while the INIT and CCE bit are set. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 690 of 1152...
  • Page 691 Afterwards, all nodes switch back to classic CAN communication. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 691 of 1152...
  • Page 692 Remark: The restricted operation mode must not be combined with the loop back mode, whether internal or external. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 692 of 1152...
  • Page 693 Fig 134. Pin control in bus monitoring mode UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 693 of 1152...
  • Page 694 MCAN can be tested without affecting a running CAN system connected to the pins UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 695 FD frame while TDC bit is set in the DBTP register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 696 By default automatic UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 696 of 1152...
  • Page 697 It is stopped when the INIT bit is set. For example, when the M_CAN enters a buf_off state. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 697 of 1152...
  • Page 698 Extended ID filter configuration (XIDFC. • Extended ID AND mask (XIDAM). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 698 of 1152...
  • Page 699 ID, the filter element has to be configured with SFID1= SFID2 resp. EFID1= EFID2. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 699 of 1152...
  • Page 700 (RTR), and the identifier extension bit (IDE) of received frames are compared against the list of configured filter elements. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 700 of 1152...
  • Page 701 The XIDAM register is ANDed with the received identifier before the filter list is execute. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 702 FIFO full interrupt flag in the IR register is set. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 702 of 1152...
  • Page 703 The Rx FIFO overwrite mode is configured in the Rx FIFO configuration register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 704 ID message 2 00 0001 ID message 3 00 0010 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 704 of 1152...
  • Page 705 (Tx buffer with lowest message ID) when the TXBRP register is updated, or when a transmission has been started. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 705 of 1152...
  • Page 706 Table 690. Tx buffer / FIFO / queue element size TXESC.TBDS[2:0] Data Field (bytes) Element size (RAM words) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 706 of 1152...
  • Page 707 Tx buffer start address stored in the TBSA bit field in the TXBC register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 708 Tx buffer with lowest message ID gets highest priority and is transmitted next. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 709 EFSA bit field in the TXEFC register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 710 The MCAN does not check for erroneous values. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 710 of 1152...
  • Page 711 UM10912 Chapter 33: LPC546xx Ethernet Rev. 1.7 — 14 April 2017 User manual 33.1 How to read this chapter The Ethernet controller is available on all LPC546xx devices. 33.2 Features • 10/100 Mbit/s. • Ethernet MAC IEEE 802.3-2008. • DMA support. •...
  • Page 712 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet • Set the Ethernet mode to RMII or MII in the ETHPHYSEL register (see Table 111). • Set the sideband flow control for each channel. See Section 4.5.75. 33.4 General description The Ethernet block enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2008 standard.
  • Page 713 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Tx MEMORY Tx DMA MTL Tx FIFO CONTROLLER CHANNEL MASTER INTERFACE Rx DMA MTL Rx FIFO INTERFACE CHANNEL CONTROLLER (RMII) SLAVE INTERFACE CHANNEL MTL CSR CORE Rx MEMORY aaa-021827 Fig 143. Ethernet block diagram 33.5 Pin description...
  • Page 714 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6 Register description Table 692. Register overview: Ethernet MAC and DMA (base address 0x4009 2000) Name Access Offset Description Reset value Section MAC_CONFIG 0x0000 MAC configuration. 0x8000 33.6.1 MAC_EXT_CONFIG 0x0004 MAC extended configuration.
  • Page 715 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 692. Register overview: Ethernet MAC and DMA (base address 0x4009 2000) …continued Name Access Offset Description Reset value Section MAC_Tx_TIMESTAMP_STATUS_ 0x0B30 Tx timestamp status nanoseconds. 33.6.39 NANOSECONDS MAC_Tx_TIMESTAMP_STATUS_ 0x0B34 Tx timestamp status seconds.
  • Page 716 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 692. Register overview: Ethernet MAC and DMA (base address 0x4009 2000) …continued Name Access Offset Description Reset value Section DMA_CH0_TX_CTRL 0x1104 DMA channel 0 transmit control. 33.6.66 DMA_CH0_RX_CTRL 0x1108 DMA channel 0 receive control.
  • Page 717 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 692. Register overview: Ethernet MAC and DMA (base address 0x4009 2000) …continued Name Access Offset Description Reset value Section DMA_CH1_CUR_HST_TXBUF 0x11D4 The channel 1 current host transmit 33.6.79 buffer address. DMA_CH1_CUR_HST_RXBUF 0x11DC The channel 1 current host receive 33.6.80...
  • Page 718 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.1 MAC configuration register The MAC configuration register establishes receive and transmit operating modes of the MAC. Table 693. MAC configuration register (MAC_CONFIG, offset 0x0000) bit description Symbol Value Description Reset value Receiver enable.
  • Page 719 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 693. MAC configuration register (MAC_CONFIG, offset 0x0000) bit description …continued Symbol Value Description Reset value Back-off limit. The back-off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision.
  • Page 720 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 693. MAC configuration register (MAC_CONFIG, offset 0x0000) bit description …continued Symbol Value Description Reset value Loopback mode. When this bit is set, the MAC operates in loopback mode at MII. The MII receive clock input is required for the loopback to work properly, as the transmit clock is not looped-back internally.
  • Page 721 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 693. MAC configuration register (MAC_CONFIG, offset 0x0000) bit description …continued Symbol Value Description Reset value Watchdog disable. When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.
  • Page 722 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 693. MAC configuration register (MAC_CONFIG, offset 0x0000) bit description …continued Symbol Value Description Reset value GPSLCE Giant packet size limit control enable. When this bit is set, the MAC considers the value in GPSL field in MAC extended configuration register to declare a received packet as giant packet.
  • Page 723 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 694. MAC extended configuration register (MAC_EXT_CONFIG, offset 0x0004) bit description Symbol Value Description Reset value 13:0 GPSL Giant packet size limit. If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as giant packet.
  • Page 724 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 695. MAC frame filter register (MAC_FRAME_FILTER, offset 0x0008) bit description Symbol Value Description Reset value Access Promiscuous mode. When this bit is set, the address filter module passes all incoming frames regardless of its destination or source address. The SA/DA filter fails status bits of the receive status word will always be cleared when PR is set.
  • Page 725 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 695. MAC frame filter register (MAC_FRAME_FILTER, offset 0x0008) bit description …continued Symbol Value Description Reset value Access Source address filter enable. When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers.
  • Page 726 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 696. MAC watchdog timeout register (MAC_WD_TIMEROUT, offset 0x000C) bit description Symbol Value Description Reset value Watchdog timeout. When the PWE bit is set and the WD bit of the MAC configuration register Table 693 is reset, this field is used as watchdog timeout for a received packet.
  • Page 727 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.5 MAC VLAN tag register The VLAN tag register identifies the IEEE 802.1Q VLAN type packets. Table 697. MAC VLAN tag register (MAC_VLAN_TAG, offset 0x0050) bit description Symbol Description Reset value 15:0 VLAN tag identifier for receive packets.
  • Page 728 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 697. MAC VLAN tag register (MAC_VLAN_TAG, offset 0x0050) bit description …continued Symbol Description Reset value VTHM VLAN tag hash table match enable. When this bit is set, the most significant four bits of CRC of VLAN tag are used to index the content of the MAC_VLAN_Hash_Table register.
  • Page 729 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 698. MAC transmit flow control register (MAC_TX_FLOW_CTRL_Q0, offset 0x0070 and MAC_TX_FLOW_CTRL_Q1, offset 0x0074) bit description Symbol Value Description Reset value Flow control busy/backpressure activate. This register field can be read by the application (read), can be set to 1 by the application with a register write of 1 (write set), and is cleared to 0 by the core (self clear).
  • Page 730 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 698. MAC transmit flow control register (MAC_TX_FLOW_CTRL_Q0, offset 0x0070 and MAC_TX_FLOW_CTRL_Q1, offset 0x0074) bit description …continued Symbol Value Description Reset value DZPQ Disable zero-quanta pause. When set, this bit disables the automatic generation of zero-quanta pause control frames on the deassertion of the flow-control signal from the FIFO layer.
  • Page 731 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 700. MAC Tx Queue priority mapping register (MAC_TXQ_PRIO_MAP, offset 0x0098) bit description Symbol Description Reset value PSTQ0 Priorities selected in Tx Queue 0. This field holds the priorities assigned to Tx Queue 0 by the software. This field determines if Tx Queue 0 should be blocked from transmitting specified pause time when a PFC packet is received with priorities matching the priorities programmed in this field.
  • Page 732 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 702. MAC Rx Queue control 1 register (MAC_RXQ_CTRL1, offset 0x00A4) bit description …continued Symbol Value Description Reset value AVPTPQ AV PTP packets queue. This field specifies the Rx Queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed.
  • Page 733 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.11 MAC Rx Queue control 2 register The Rx Queue control 2 register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx Queues 0 to 3. This register is present when multiple Rx Queues are selected while configuring the core.
  • Page 734 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 704. MAC interrupt status register (MAC_INTR_STAT, offset 0x00B0) bit description Symbol Value Description Reset value Reserved. PHYIS PHY interrupt. This bit is set when rising edge is detected on the PHY interrupt input signal. This bit is cleared when this register is read.
  • Page 735 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 704. MAC interrupt status register (MAC_INTR_STAT, offset 0x00B0) bit description …continued Symbol Value Description Reset value TXSTSIS Transmit status interrupt. This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the MAC receive transmit status register.
  • Page 736 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 705. MAC interrupt enable register (MAC_INTR_EN, offset 0x00B4) bit description …continued Symbol Value Description Reset value TXSTSIE Transmit status interrupt enable. When this bit is set, it enables the assertion of the interrupt signal because of the...
  • Page 737 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 706. MAC receive transmit status register (MAC_RXTX_STAT, offset 0x00B8) bit description …continued Symbol Description Reset value Reserved. Receive watchdog timeout. This bit is set when a packet with length greater than 2,048 bytes is received (10,240 bytes...
  • Page 738 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 707. MAC PMT control status register (MAC_PMT_CTRL_STAT, offset 0x00C0) bit description Symbol Description Reset Access value RWKPFE Remote wake-up packet forwarding enable. When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected wake-up frame.
  • Page 739 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.17 MAC LPI control status register The LPI control and status register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. This register is present only when you select the energy efficient Ethernet feature while configuring the core.
  • Page 740 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 709. MAC LPI control status register (MAC_LPI_CTRL_STAT, offset 0x00D0) bit description …continued Symbol Description Reset Access value LPITXA LPI Tx automate. This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.
  • Page 741 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 710. MAC LPI timer control register (MAC_LPI_TIMER_CTRL, offset 0x00D4) bit description Symbol Description Reset value 15:0 LPI TW timer. This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission.
  • Page 742 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 713. MAC Version register (MAC_VERSION, offset 0x0110) bit description Symbol Description Reset value SNPVER NXP defined version. 0x10 15:8 USERVER User defined version. 31:16 - Reserved. 33.6.22 MAC debug register The debug register provides the debug status of various MAC blocks.
  • Page 743 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 715. MAC HW Feature0 register (MAC_HW_FEAT0, offset 0x011C) bit description …continued Symbol Value Description Reset value VLHASH Hash table based filtering option. Disabled Enabled SMASEL SMA (MDIO) interface. Disable station management (MDIO interface)
  • Page 744 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 715. MAC HW Feature0 register (MAC_HW_FEAT0, offset 0x011C) bit description …continued Symbol Value Description Reset value 30:28 ACTPHYSEL Active PHY selected. 0x00 RMII. All other values reserved. Reserved. 33.6.24 MAC HW feature1 register The MAC HW feature1 register indicates the presence of the optional features or functions.
  • Page 745 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 716. MAC HW Feature1 register (MAC_HW_FEAT1, offset 0x0120) bit description …continued Symbol Value Description Reset value DBGMEMA DMA debug register feature. Disable Enable AVSEL Audio video bridging feature. Disable Enable 23:21 - Reserved.
  • Page 746 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.26 MAC MDIO address register The MDIO address register controls the management cycles to external PHY through a management interface. Table 718. MAC MDIO address register (MAC_MDIO_ADDR, offset 0x0200) bit description Symbol Value Description Reset value MII busy.
  • Page 747 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 718. MAC MDIO address register (MAC_MDIO_ADDR, offset 0x0200) bit description …continued Symbol Value Description Reset value Back to back transactions. When this bit is set and the NTC has value greater than 0, then the MAC will inform the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted).
  • Page 748 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 720. MAC address high register (MAC_ADDR_HIGH, offset 0x0300) bit description Symbol Description Reset value Access 15:0 A47_32 MAC address0[47:32]. 0xFFFF This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the transmit flow control (PAUSE) frames.
  • Page 749 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 722. MAC timestamp control register (MAC_TIMESTAMP_CTRL, offset 0x0B00) bit description …continued Symbol Description Reset value TSUPDT Update timestamp. When this bit is set, the system time is updated (added or subtracted) with the...
  • Page 750 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 722. MAC timestamp control register (MAC_TIMESTAMP_CTRL, offset 0x0B00) bit description …continued Symbol Description Reset value TSEVTENA Enable timestamp snapshot for event messages. When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
  • Page 751 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 723. Timestamp snapshot dependency on register bits SNAPTYPSEL TSMSTRENA TSEVNTENA PTP Messages SYNC, Follow_Up, Delay_Req, Delay_Resp SYNC Delay_Req SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up SYNC, Pdelay_Req, Pdelay_Resp Delay_Req, Pdelay_Req, Pdelay_Resp SYNC,Pdelay_Req, Pdelay_Resp Delay_Req 33.6.31 Sub-second increment register...
  • Page 752 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 726. System time nanoseconds register (MAC_SYS_TIME_NCND, offset 0x0B0C) bit description Symbol Description Reset value 30:0 TSSS Timestamp sub seconds. The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second.
  • Page 753 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.37 System time higher words seconds register This register contains the most significant 16-bits of the timestamp seconds value. Table 730. System time higher words seconds register (MAC_SYS_TIME_HWORD_SCND, offset 0x0B1C) bit description Symbol Description...
  • Page 754 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 733. Tx timestamp status seconds register (MAC_Tx_TIMESTMP_STAT_SECONDS, offset 0x0B34) bit description Symbol Description Reset value 31:0 TXTSSTSHI Transmit timestamp status high. This field contains the lower 32 bits of the seconds field of transmit packet's captured timestamp.
  • Page 755 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 736. MTL operation mode register (MTL_OP_MODE, offset 0x0C00) bit description …continued Symbol Description Reset value Access SCHALG Tx scheduling algorithm. This field indicates the algorithm for Tx scheduling: 0x00: WRR algorithm 0x1: Reserved...
  • Page 756 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.45 MTL Rx Queue and DMA channel mapping register Table 738. MTL Rx Queue and DMA channel mapping register (MTL_RXQ_DMA_MAP, offset 0x0C30) bit description Symbol Description Reset value Q0MDMACH Queue 0 mapped to DMA channel.
  • Page 757 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 739. MTL TxQ operation mode register (MTL_TXQ0_OP_MODE, offset 0x0D00) and MTL_TXQ1_OP_MODE, offset 0x0D40 bit description Symbol Description Reset value Flush Tx Queue. When this bit is set, the Tx Queue controller logic is reset to its default values. Therefore, all the data in the Tx Queue is lost or flushed.
  • Page 758 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 740. MTL TxQ Underflow register (MTL_TXQ0_UNDRFLW, offset 0x0D04 and MTL_TXQ1_UNDRFLW, offset 0x0D44) bit description Symbol Description Reset value 10:0 UFFRMCNT Underflow packet counter. This field indicates the number of packets aborted by the controller because of Tx Queue underflow.
  • Page 759 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 741. MTL TxQ debug register (MTL_TXQ0_DBG, offset 0x0D08 and MTL_TXQ1_DBG, offset 0x0D48) bit description …continued Symbol Description Reset value Reserved. 22:20 STSXSTSF Number of status words in Tx status FIFO of queue.
  • Page 760 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 743. MTL TxQ ETS status register (MTL_TXQ0_ETS_STAT, offset 0x0D14 and MTL_TXQ1_ETS_STAT, offset 0x0D54) bit description Symbol Description Reset value 23:0 Average bits per slot. This field contains the average transmitted bits per slot.
  • Page 761 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.53 MTL TxQ1 SendSlopeCredit register The SendSlopeCredit register contains the SendSlope credit value required for the credit-based shaper algorithm for the queue. Table 746. MTL TxQ1 SendSlopCredit register (MTL_TXQ1_SNDSLP_CRDT, offset 0x0D5C) bit description...
  • Page 762 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.56 MTL TxQ interrupt control status register This register contains the interrupt enable and status bits for the queue interrupts. Table 749. MTL TxQ interrupt control status register (MTL_TXQ0_INTCTRL_STAT, offset 0x0D2C and MTL_TXQ1_INTCTRL_STAT, offset 0x0D6C) bit description...
  • Page 763 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 750. MTL RxQ operation mode register (MTL_RXQ0_OP_MODE, offset 0x0D30 and MTL_RXQ1_OP_MODE, offset 0x0D70) bit description Symbol Description Reset value Access Rx Queue threshold control. These bits control the threshold level of the MTL Rx Queue (in bytes):...
  • Page 764 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.58 MTL RxQ missed packet overflow counter register The queue missed packet and overflow counter register contains the counter for packets missed because of Rx Queue packet flush and packets discarded because of Rx Queue overflow.
  • Page 765 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.60 MTL RxQ control register The queue receive control register controls the receive arbitration and passing of received packets to the application. Table 753. MTL RxQ control register (MTL_RXQ0_CTRL, offset 0x0D3C and MTL_RXQ1_CTRL, offset 0x0D7C) bit...
  • Page 766 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 754. DMA mode register (DMA_MODE, offset 0x1000) bit description Symbol Description Reset value Software reset. When this bit is set, the MAC and the OMA controller reset the logic and all internal registers of the OMA, MTL, and MAC.
  • Page 767 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 755. DMA system bus mode register (DMA_SYSBUS_MODE, offset 0x1004) bit description Symbol Description Reset value Access Fixed burst length. When this bit is set to 1, the AHB master will initiate burst transfers of specified length (INCRx or SINGLE).
  • Page 768 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 756. DMA interrupt status register (DMA_INTR_STAT, offset 0x1008) bit description …continued Symbol Description Reset value MTLIS MTL interrupt status. This bit indicates an interrupt event in the MTL. To reset this bit to 0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source.
  • Page 769 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 757. DMA debug status register (DMA_DBG_STAT, offset 0x100C) bit description …continued Symbol Description Reset value 19:16 RPS1 DMA channel 1 receive process state. This field indicates the Rx DMA FSM state for channel 1. This field is similar to the RPS0 field.
  • Page 770 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 759. DMA channel transmit control register (DMA_CH0_TX_CTRL, offset 0x1104 and DMA_CH1_TX_CTRL, offset 0x1184) bit description Symbol Description Reset value Start or stop transmission command. When this bit is set, transmission is placed in the running state. The DMA checks the transmit list at the current position for a packet to be transmitted.
  • Page 771 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 760. DMA channel receive control register (DMA_CH0_RX_CTRL, offset 0x1108 and DMA_CH1_RX_CTRL, offset 0x1188) bit description Symbol Description Reset value Start or stop receive. When this bit is set, the DMA tries to acquire the from the receive list and processes the incoming packets.
  • Page 772 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 760. DMA channel receive control register (DMA_CH0_RX_CTRL, offset 0x1108 and DMA_CH1_RX_CTRL, offset 0x1188) bit description …continued Symbol Description Reset value 21:16 RxPBL Receive programmable burst length. These bits indicate the maximum number of beats to be transferred in one DMA data transfer.
  • Page 773 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.70 DMA channel transmit tail pointer register The channel Tx tail pointer register points to an offset from the base and indicates the location of the last valid. When this register is read, it always returns zero.
  • Page 774 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.74 DMA channel interrupt enable register The channel interrupt enable register enables the interrupts reported by the status register. Table 767. DMA interrupt enable register (DMA_CH0_INT_EN, offset 0x1134 and DMA_CH1_INT_EN, offset 0x11B4) bit description...
  • Page 775 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 767. DMA interrupt enable register (DMA_CH0_INT_EN, offset 0x1134 and DMA_CH1_INT_EN, offset 0x11B4) bit description …continued Symbol Description Reset value Abnormal interrupt summary enable. When this bit is set, an abnormal interrupt summary is enabled. When this bit is reset, an abnormal interrupt is disabled.
  • Page 776 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 769. DMA slot function control register (DMA_CH_SLOT_FUNC_CTRL_STAT, CH0 offset 0x113C,CH1 offset 0x11BC) bit description Symbol Description Reset value Access Enable slot comparison. When set, this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field.
  • Page 777 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.6.79 DMA channel current host transmit buffer address register The current host transmit buffer address register points to the current transmit buffer address being read by the DMA. Table 772. DMA current host transmit buffer address register (DMA_CH_CUR_HST_TXBUF, CH0 offset 0x1154 and...
  • Page 778 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 774. DMA channel status register (DMA_CH_STAT, CH0 offset 0x1160 and CH1 offset 0x11E0) bit description Symbol Description Reset value Receive buffer unavailable. This bit indicates that the application owns the next in the receive list, and the DMA cannot acquire it.
  • Page 779 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 774. DMA channel status register (DMA_CH_STAT, CH0 offset 0x1160 and CH1 offset 0x11E0) bit description Symbol Description Reset value Normal interrupt summary. Normal interrupt summary bit value is the logical OR of the following bits when the...
  • Page 780 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 775. DMA channel miss frame count (DMA_CH0_MISS_FRAME_CNT, offset 0x116C and DMA_CH1_MISS_FRAME_CNT, offset 0x11EC) bit description …continued Symbol Description Reset value 14:11 - Reserved. MFCO Overflow status of the MFC counter. When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read.
  • Page 781 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7 Functional description 33.7.1 Power management block and low power modes This section describes the power management (PMT) mechanisms supported by the MAC. PMT supports the reception of network (remote) wake-up frames and magic packet frames.
  • Page 782 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 4. Updates the status (TLPIEN bit of MAC LPI control status register Table 709) and generates an interrupt. To bring the PHY out of the LPI state, that is, when the software resets the LPIEN bit, the MAC performs the following tasks: a.
  • Page 783 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.1.1.4 LPI Timers The transmitter maintains the following two timers that are loaded with the respective values from the MAC_LPI_Timers_Control register: • LPI LS Timer – The LPI LS TIMER counts, in milliseconds, the time expired since the link status is up.
  • Page 784 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Only magic packets that are addressed to the device or a broadcast address will be checked to determine whether they meet the wake-up requirements. Magic packets that pass the address filtering (unicast or broadcast) will be checked to determine whether they meet the remote wake-on-LAN data format of 6 bytes of all ones followed by a MAC address appearing 16 times.
  • Page 785 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 144. Wake-up frame filter register Filter i byte mask This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in order to determine whether or not the frame is a wake-up frame. The MSB (thirty-first bit) must be zero.
  • Page 786 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet When the MAC is in sleep mode and the remote wake-up bit is enabled in PMT control and status register (0x00C0), normal operation is resumed after receiving a remote wake-up frame. The application writes all eight wake-up filter registers by performing a sequential write to address (0x00C4).
  • Page 787 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 3. Wait until the receive DMA empties all the frames from the Rx FIFO.This can be done by reading the appropriate bits of Debug registers in the DMA and MTL CSR space. 4. Enable power-down mode by appropriately configuring the PMT registers.
  • Page 788 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet When the FCB bit is set, the MAC generates and transmits a single pause packet. If the FCB bit is set again after the pause packet transmission is complete, the MAC sends another pause packet irrespective of whether the pause time is complete or not. To...
  • Page 789 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 777. Tx MAC flow control EFC TFE DM Description The MAC transmitter performs backpressure when bit 0 of MAC_Q0_Tx_Flow_Ctrl register is set or the sideband signal sbd_flowctrl_i is 1. In addition, the MAC Tx performs backpressure when Rx Queue level crosses the threshold set by bits 10:8 of MTL_RxQ0_Operation_Mode register.
  • Page 790 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 145. Multiple channels and queues 33.7.4.1 Support in the transmit path Ethernet block supports up to two Tx Queues. The fixed priority scheme is the default priority scheme for the DMA channels. In fixed priority scheme, the channel with highest priority always wins the arbitration when it requests the bus.
  • Page 791 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Each Rx DMA indicates when it is ready to transfer data and the size of the burst-length (number of beats) that it has to transfer. The scheduler checks whether sufficient data (of requested burst length) is available to be transferred to these DMAs and then selects the Rx DMA that gets serviced using the programmed priorities.
  • Page 792 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.4.5 Rx Queue to DMA mapping The packets in the MTL Rx Queues can be routed to any one of the two DMA channels by programming the MTL RxQ DMA map registers for queues 0, 1. The following types of Rx Queue to DMA mapping is possible through programming: 1.
  • Page 793 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet and the weights programmed in the corresponding queue receive control register. The arbitration is done among queues for which DMA is ready to service. After the Rx Queue is selected, PBL (Programmable Burst Length) amount of data is read out from that queue and is routed to the Rx DMA channel based on the Rx channel selection criteria.
  • Page 794 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet The transmit paths of additional queues support traffic management by using the credit-based shaper algorithm. For a queue, the credit-based shaper algorithm determines that a queue is available for transmission if the following conditions are true: 1.
  • Page 795 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet control1 register Table 701. 33.7.4.9.3 Credit based shaper algorithm The MTL queue scheduler uses the credit-based shaper algorithm to arbitrate the AV traffic in all queues and the legacy Ethernet traffic in Queue 0. You can program the additional queues to use the credit-based shaper algorithm.The following sections provide...
  • Page 796 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet loCredit values are 12,000 bits and 3,036 bits respectively, the values to be programmed in the hiCredit and loCredit registers of the corresponding channel are 12,000 x 1,024 bits and two's complement of 3,036 x1,024, respectively.
  • Page 797 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Check the following sections for AV programming: Programming guidelines for initializing the DMA Section 33.7.11.9.1. Programming guidelines for enabling slot number checking Section 33.7.11.9.2. Programming guidelines for enabling average bits per slot reporting Section 33.7.11.9.3.
  • Page 798 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet The checksum for TCP, UDP, or ICMP is calculated over a complete packet, and then inserted into its corresponding header field.It must be made sure that the Tx FIFO is deep enough to store a complete packet before that packet is transferred to the MAC transmitter.
  • Page 799 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 780. Transmit checksum offload engine functions for different frame types Frame type Hardware IP header Hardware TCP/UDP checksum insertion checksum insertion Non-IPv4 or IPv6 frame IPv4 frame is greater than 1,522 bytes (2,000 bytes when IEEE 802.3ad Support for 2K frames is enabled in MAC) but less than or...
  • Page 800 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet version, or when the received packet does not have enough bytes, as indicated by the Length field of the IPv4 header (or when fewer than 20 bytes are available in an IPv4 or IPv6 header).
  • Page 801 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.6 Loopback mode The MAC supports loopback of transmitted packets to its receiver. To enable this feature, program the LM bit of the MAC configuration register.Lopback mode can be enabled for all PHY interfaces. The data is always looped back on the MII interface irrespective of which PHY interface is selected.
  • Page 802 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.8 IEEE 1588 timestamps The IEEE 1588 standard defines a protocol, Precision Time Protocol (PTP), that enables precise synchronization of clocks in measurement and control systems implemented with technologies such as network communication, local computing, and distributed objects.
  • Page 803 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 782. Ordinary clock: PTP messages for snapshot Master Slave Delay_Req SYNC For an ordinary clock, you can take the snapshot of either one of the following PTP message types: version 1 or version 2. You cannot take the snapshots for both PTP message types.
  • Page 804 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 784. End-to-end transparent clock: PTP messages for which a snapshot is taken for transparent clock implementation SYNC Pdelay_Req Pdelay_Resp The transparent clock corrects only the sync and follow-up message. As discussed earlier this can be achieved using the message status provided.
  • Page 805 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 1. The master broadcasts the PTP sync messages to all its nodes. The sync message contains the master.s reference time information. The time at which this message leaves the master.s system is t1. This time must be captured, for Ethernet ports, at MII.
  • Page 806 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 147. Propagation delay calculation in clocks supporting peer-to-peer path correction The propagation delay is calculated in the following way: 1. Port-1 issues a Pdelay_Req message and generates a timestamp, t1, for the Pdelay_Req message.
  • Page 807 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.8.4 Frequency range of the reference timing clock The timestamp information is transferred across asynchronous clock domains, that is, from MAC clock domain to application clock domain. Therefore, a minimum delay is required between two consecutive timestamp captures. This delay is 4 clock cycles of II and 3 clock cycles of PTP clocks.
  • Page 808 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet • PTP Frames Over IPv6 • PTP Frames Over Ethernet 33.7.8.5.1 PTP frames over IPv4 Table 4-6 provides information about the fields that are matched to control snapshot for the PTP packets sent over UDP over IPv4 for IEEE 1588 version 1 and 2. The octet positions for the tagged frames are offset by 4.
  • Page 809 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 788. IPv6-UDP PTP frame fields required for control and status Field Matched Octet Position Matched Value Description MAC Frame Type 12, 13 0x86DD IP datagram IP version 14(bits 7:4) IP version is IPv6...
  • Page 810 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 789. Ethernet PTP frame fields required for control and status Field Matched Octet Position Matched Value Description PTP Control Field 0x00/0x01/0x02/ 0x00 – SYNC (IEEE version 1) 0x03/0x04 0x01 – Delay_Req 0x02 – Follow_Up 0x03 –...
  • Page 811 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet • Enable snapshot for IEEE 1588 version 1 or version 2 timestamp. • Enable snapshot for PTP packets transmitted directly over Ethernet or UDP-IP-Ethernet. • Enable timestamp snapshot for the received packet for IPv4 or IPv6.
  • Page 812 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet – Digital rollover mode: In digital rollover mode, the maximum value in the nanoseconds field is 0x3B9A_C9FF, that is, (10e9-1) nanoseconds. – Binary rollover mode: In binary rollover mode, the nanoseconds field rolls over and increments the seconds field after value 0x7FFF_FFFF.
  • Page 813 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 148. System update using fine method The system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy. The frequency division is the ratio of the reference clock frequency to the required clock frequency.
  • Page 814 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet The frequency division (FreqDivisionRatio) is the ratio of the reference clock frequency to the required clock frequency. If MasterToSlaveDelay is initially assumed to be the same for consecutive sync messages, the algorithm described below must be applied. After a few sync cycles, frequency lock occurs.
  • Page 815 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet memory, and transmit data frames from the transmit buffer in the system memory. Descriptors that reside in the system memory act as pointers to these buffers. There are two descriptor lists; one for reception, and one for transmission.The DMA supports up to two Tx and two Rx descriptor lists (or DMA channels).
  • Page 816 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.9.1 Host bus burst access The DMA attempts to execute fixed-length Burst transfers on the AHB master interface if configured to do so (FB bit of DMA system bus mode register 0). The maximum burst length is indicated and limited by the PBL field (DMA register 0[13:8]).
  • Page 817 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet If the receive buffer address is 0x0000 0FF2 (for 64-bit data bus) and 16 bytes of a received frame need to be transferred, then the DMA writes 3 full words from address 0x0000 0FF0. But the first 2 bytes of first transfer and the last 6 bytes of the third transfer have dummy data.
  • Page 818 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.9.5 Transmission 33.7.9.5.1 TxDMA operation: Default (non-OSF) mode The transmit DMA engine in default mode proceeds as follows: 1. The host sets up the transmit descriptor (TDES0-TDES3) and sets the OWN bit (TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet frame data.
  • Page 819 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 150. Transmit DMA operation in default mode 33.7.9.5.2 TxDMA operation: OSF mode In the run state, if bit 4 is set in the transmit control register of corresponding DMA channel, the transmit process can simultaneously acquire two packets without closing the status descriptor of the first frame.
  • Page 820 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet frame, it immediately polls the transmit descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. In OSF mode, the run state transmit DMA operates in the following sequence: 1.
  • Page 821 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 151. Transmit DMA operation in OSF mode UM10912 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 822 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.9.5.3 Timestamp Correction According to the IEEE 1588 specification, a timestamp must be captured when the message timestamp point (leading edge of the first bit of the octet immediately following the Start Frame Delimiter octet) crosses the boundary between the node and the network.
  • Page 823 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet The egress latency correction between the recommended capture point and the internal timestamp snapshot point is done by adding the latency value (EGRESS_LATENCY) with the captured timestamp as follows: Egress Correction = EGRESS_SYNC_CORR + EGRESS_LATENCY Egress correction is performed by programming the TSEC field in the MAC timestamp egress correction register.
  • Page 824 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet The actual frame transmission begins after the MTL Tx Queue has reached either a programmable transmit threshold (DMA operation mode register, bits 6:4), or a full frame is contained in the FIFO. There is also an option for store and forward mode (MTL operation mode register, bit 1).
  • Page 825 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 152. DMA transmit channel arbitration process When there is any request in the Tx Queue, the DMA arbiter checks the type of the request: packet buffer fetch or descriptor fetch request. The descriptor fetch requests have higher priority than the buffer requests.
  • Page 826 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet • Fixed priority (FP): In fixed priority mode, channel 0 has the lowest priority and the last selected channel has the highest priority. The weight programmed in the transmit control register of a channel is ignored.
  • Page 827 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 153. Receive DMA operation 33.7.9.5.8 Receive descriptor acquisition The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is satisfied: •...
  • Page 828 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet • The controller has completed frame reception, but the current receive descriptor is not yet closed. • A receive poll demand has been issued. 33.7.9.5.9 Receive frame processing The MAC transfers the received frames to the host memory only when the frame passes...
  • Page 829 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Remark: The DMA interrupt status register (Table 756) is the (interrupt) status register. The interrupt pin is asserted because of any event in this status register only if the corresponding interrupt enable bit is set in DMA interrupt enable register (Table 767).
  • Page 830 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet The DMA goes into the suspend mode when this condition occurs. The application must perform a write to the descriptor tail pointer register and update the tail pointer so that the following condition is true: Current descriptor pointer <...
  • Page 831 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 155. Descriptor structure 33.7.10.2 Descriptor endianness The data bus can be configured for little-endian format. 33.7.10.3 Transmit descriptor The DMA in Ethernet core requires at least one descriptor for a transmit packet. In...
  • Page 832 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 790. Transmit descriptor word 0(TDES0) Symbol Description 31:0 BUF1AP Buffer 1 address pointer or TSO header address pointer. These bits indicate the physical address of buffer 1. These bits indicate the TSO header address pointer...
  • Page 833 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 793. Transmit descriptor word 3 (TDES3) Symbol Description 22:19 SLOTNUM Slot number control bits in AV mode. These bits indicate the slot interval in which the data should be fetched from the corresponding buffers addressed by TDES0 or TDES1.
  • Page 834 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 157. Transmitter descriptor write-back Format 33.7.10.3.3 TDES0 normal descriptor (write-back format) This format is only applicable to the last descriptor of a packet. Table 794. TDES0 normal descriptor (write-back Format) Symbol Description 31:0 TTSL Transmit packet timestamp low.
  • Page 835 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 797. TDES3 normal descriptor (write-back format) Symbol Description IP header error. When IP header error is set, this bit indicates that the checksum offload engine detected an IP header error. If COE detects an IP header error, it still inserts an IPv4 header checksum if the Ethernet type field indicates an IPv4 payload.
  • Page 836 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 797. TDES3 normal descriptor (write-back format) Symbol Description Error summary. This bit indicates the logical OR of the following bits: • TDES3[0]: IP header error • TDES3[14]: jabber timeout • TDES3[13]: packet flush •...
  • Page 837 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet In the receive descriptor (read format), if the buffer address field is all 0s, Ethernet does not transfer data to that buffer and skips to the next buffer or next descriptor. Fig 158. Receive normal descriptor (read format) 33.7.10.4.1 Receive normal descriptor (read format)
  • Page 838 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 801. RDES3 normal descriptor (read format) Symbol Description 23:0 Reserved. BUF1V Buffer 1 address valid. When set, this indicates to the DMA that the buffer 1 address specified in RDES1 is valid.
  • Page 839 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 803. RDES1 normal descriptor (write-back format) Symbol Description Payload type. These bits indicate the type of payload encapsulated in the IP datagram processed by the receive checksum offload engine (COE): • 0x0: Unknown type or IP/AV payload not processed •...
  • Page 840 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 803. RDES1 normal descriptor (write-back format) …continued Symbol Description 11:8 PTP message type. These bits are encoded to give the type of the message received: • 0x0: No PTP message received •...
  • Page 841 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.10.4.6 RDES3 normal descriptor (write-back format) Table 805. RDES3 normal descriptor (write-back format) Symbol Description 14:0 Packet length. These bits indicate the byte length of the received packet that was transferred to system memory (including CRC).
  • Page 842 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Table 805. RDES3 normal descriptor (write-back format) Symbol Description Giant packet. When this bit is set, it indicates that the packet length exceeds the specified maximum Ethernet size of 1518, 1522, or 2000 bytes (9,018 or 9,022 bytes if jumbo packet enable is set).
  • Page 843 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet • Programming guidelines for AV feature • Programming guidelines for energy efficient Ethernet 33.7.11.1 Initializing DMA Follow these steps to initialize the DMA controller: 1. Assert a software reset by setting bit 0 of DMA mode register Table 754.
  • Page 844 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 3. Program the following fields to initialize the mode of operation in the MTL TxQ0 operation mode register Table 739 a. Transmit store and forward (TSF) or transmit threshold control (TTC) in case of threshold mode b.
  • Page 845 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 33.7.11.3.1 Host bus burst access The DMA attempts to execute fixed-length burst transfers on the AHB master interface if configured to do so (FB bit of DMA register 0). The maximum burst length is indicated and limited by the PBL field (DMA register 0[13:8]).
  • Page 846 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet If the receive buffer address is 0x0000 0FF2 (for 64-bit data bus) and 16 bytes of a received frame need to be transferred, then the DMA writes 3 full words from address 0x0000 0FF0. But the first 2 bytes of first transfer and the last 6 bytes of the third transfer have dummy data.
  • Page 847 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 1. For normal transmit and receive interrupts, read the interrupt status. Then, poll the descriptors, reading the status of the descriptor owned by the host (either transmit or receive). 2. If the descriptors are not owned by the DMA (or no descriptor is available), the DMA goes into SUSPEND state.
  • Page 848 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 1. Program the Tx Queue size in the TQS field of MTL TxQ0 operation mode register Table 739 if queue 0 is used or MTL TxQ1 operation mode register Table 739 queue1 is used. Based on the value programmed in TQS field, the size of the queue is determined.
  • Page 849 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 3. Wait for any previous frame transmissions to complete. It can be checked this by reading the appropriate bits of MTL_TXQ0_DBG register (TRCSTS is not 01). or Flush the Tx FIFO for faster empty operation.
  • Page 850 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Fig 160. Transmit DMA operation in OSF mode UM10912 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 851 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet Programming guidelines for IEEE 1588 timestamping 33.7.11.8 33.7.11.8.1 Initialization guideline for system time generation The timestamp feature can be enabled by setting bit 0 of the MAC timestamp control register Table 722. However, it is essential that the timestamp counter should be initialized after this bit is set.
  • Page 852 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 5. Set bit 4 in MAC timestamp control register Table 722. 6. When this trigger causes an interrupt, read MAC interrupt status register Table 704. 7. Reprogram MAC timestamp addend register with the old value and set bit 5 again Table 729.
  • Page 853 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 12. Start the receive and transmit DMA by setting bit 0 of the DMA channel 0, channel 1 transmit control register and bit 0 of DMA channel 0, channel 1 receive control register.
  • Page 854 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 2. Program the PHY registers through the MDIO interface (including the RX CLK stoppable bit that indicates to the PHY whether to stop Rx clock in LPI mode.) 3. Program bits 25:16 and bits 15:0 in MAC LPI Timer control register Table 710.
  • Page 855 UM10912 NXP Semiconductors Chapter 33: LPC546xx Ethernet 3. Set bit 0 (ESC) of the slot function control and status register of a channel to enable the slot number checking Table 769. Gating off the CSR clock in the Rx LPI mode:...
  • Page 856 Configure the USB0 wake-up signal (see Section 34.7.6) if needed. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 856 of 1152...
  • Page 857 USB0 device controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 857 of 1152...
  • Page 858 Fig 161. USB Full-speed host/device controller block diagram UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 858 of 1152...
  • Page 859 VDD through an internal 1.5 KOhm pull-up resistor. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 859 of 1152...
  • Page 860 The USB0 device controller has the following clock connections: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 860 of 1152...
  • Page 861 USB0_PORTPWRN Host only function. USB0_OVERCURRENTN - Host only function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 861 of 1152...
  • Page 862 Reserved. LPM_SUP LPM Supported: LPM not supported. LPM supported. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 862 of 1152...
  • Page 863 VBUS disappeared. The bit is reset by writing a 1 to it. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 863 of 1152...
  • Page 864 VBUS disappeared. The bit is reset by writing a 1 to it. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 864 of 1152...
  • Page 865 Sent empty packet Bitstuff error Sync error Wrong data toggle UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 865 of 1152...
  • Page 866 Programmable portion of the data buffer start 31:22 DA_BUF address. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 866 of 1152...
  • Page 867 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. 31:10 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 867 of 1152...
  • Page 868 Software can clear this bit by writing a 1 to it. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 868 of 1152...
  • Page 869 Device Status Change register are set. Software can clear this bit by writing a 1 to UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 870 Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 31:10 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 870 of 1152...
  • Page 871 Fig 163. Endpoint command/status list (see also Table 821) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 871 of 1152...
  • Page 872 When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 873 Figure 164 “Flowchart of control endpoint 0 - OUT direction”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 873 of 1152...
  • Page 874 Fig 164. Flowchart of control endpoint 0 - OUT direction UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 874 of 1152...
  • Page 875 Fig 165. Flowchart of control endpoint 0 - IN direction UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 875 of 1152...
  • Page 876 The stall bit of the endpoint is set to 1. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 876 of 1152...
  • Page 877 The chip will automatically wake up and resume execution on USB activity. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 878 34.6.1, bit 0) in the DEVCMDSTAT to enable automatic USB clock control. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 878 of 1152...
  • Page 879 UM10912 Chapter 35: LPC546xx USB0 Full-speed Host controller Rev. 1.7 — 14 April 2017 User manual 35.1 How to read this chapter The USB full-speed controller is available on all LPC546xx devices. This chapter describes the host functionality of the controller. 35.2 Introduction This section describes the host portion of the USB0 Full-speed controllerUSB 2.0 The USB is a four-wire bus that supports communication between a host and a number...
  • Page 880 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller USB Full-speed controller USB0HSL_CLK USB0 Host registers slave interface HOST USB0 Host CONTROLLER master interface USB0HMR_CLK USB0_DP PORT USB 2.0 USB0_DM USB0D_CLK USB0 Device registers slave interface DEVICE USB0 Device...
  • Page 881 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller • Wake-up: Activity on the USB bus port can wake up the microcontroller from deep-sleep mode. See Section 35.6.2.1. • Interrupts: The USB0_IRQ interrupt is connected to interrupt slot # 28 in the NVIC.
  • Page 882 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.6 Interfaces 35.6.1 Pin description Table 823. USB Host pin description Pin name Port pin IOCON function, Mode Direction Description USB0_DP PIO5_25 Function 0 Positive differential data. Mode: pull-up USB0_DM...
  • Page 883 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 6. Enable the wake-up from deep-sleep mode on the USB activity interrupt by enabling the USB0_NEEDCLK signal in the STARTER0 register (Section 4.5.90). 7. Clear pending USB0 Activity Interrupt, USB0_NEEDCLK (Section 3.3.1) before...
  • Page 884 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 824. Register overview: USB Host register address definitions (base address 0x400A 2000) Name Access Offset Description Reset value Section HCFMREMAINING 0x38 A 14-bit counter showing the bit time remaining in 35.7.15...
  • Page 885 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.1 Host controller revision register Table 825. Host controller revision register (HCREVISION, offset 0x00) bit description Symbol Description Reset value Revision. This read-only field contains the BCD representation of the 0x10 version of the HCI specification that is implemented by this HC.
  • Page 886 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 826. Host controller control register (HCCONTROL, offset 0x04) bit description Symbol Description Reset value BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. If cleared by HCD, processing of the Bulk list does not occur after the next SOF.
  • Page 887 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.3 Host controller command status register Table 827. Host controller command status register (HCCOMMANDSTATUS, offset 0x08) bit description Symbol Description Reset value HostControllerReset This bit is set by HCD to initiate a software reset of HC. Regardless of the functional state of HC, it moves to the USBSUSPEND state in which most of the operational registers are reset except those stated otherwise;...
  • Page 888 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller enabled in the HcInterruptEnable register (see Section 7.1.5) and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing 1 to bit positions to be cleared. The Host Controller Driver may not set any of these bits.
  • Page 889 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit unchanged. On read, the current value of this register is returned.
  • Page 890 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 830. Host controller interrupt disable register (HCINTERRUPTDISABLE, offset 0x14) bit description Symbol Value Description Reset value Scheduling Overrun interrupt. No effect. Disables interrupt. HcDoneHead Writeback interrupt. No effect. Disables interrupt.
  • Page 891 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.7 Host controller communication area register Table 831. Host controller communication area register (HCHCCA, offset 0x18) bit description Symbol Description Reset value Reserved 31:8 HCCA Base address of the Host Controller Communication Area.
  • Page 892 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.11 Host controller bulk head ED register Table 835. Host controller bulk head ED register (HCBULKHEADED, offset 0x28) bit description Symbol Description Reset value Reserved 31:4 BHED BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. The content is loaded from HCCA during the initialization of HC.
  • Page 893 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.14 Host controller frame interval register Table 838. Host controller frame interval register (HCFMINTERVAL, offset 0x34) bit description Symbol Description Reset value 13:0 FrameInterval 0x2EDF This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11,999.
  • Page 894 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.15 Host controller frame remaining register The Host controller frame remaining register is a 14-bit down counter showing the bit time remaining in the current frame. Table 839. Host controller frame remaining register (HCFMREMAINING, offset 0x38) bit description...
  • Page 895 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.17 Host controller periodic start register The Host controller periodic start register has a 14-bit programmable value that determines the earliest time when HC should start processing the periodic list.
  • Page 896 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 843. Host controller root hub descriptor register (HCRHDESCRIPTORA offset 0x48) bit description Symbol Description Reset value NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
  • Page 897 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller 35.7.20 Host controller root hub descriptor B register The host controller root hub descriptor B register is the second register describing the characteristics of the root hub. These fields are written during initialization to correspond with the system implementation.
  • Page 898 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 845. Host controller root hub status register (HCRHSTATUS register offset 0x50) bit description Symbol Description Reset value DRWE (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt.
  • Page 899 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 846. Host controller root hub port status register (HCRHPORTSTATUS[1:NDP] register offset 0x54) bit description Symbol Description Reset value (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
  • Page 900 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 846. Host controller root hub port status register (HCRHPORTSTATUS[1:NDP] register offset 0x54) bit description …continued Symbol Description Reset value POCI (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis.
  • Page 901 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 846. Host controller root hub port status register (HCRHPORTSTATUS[1:NDP] register offset 0x54) bit description …continued Symbol Description Reset value LSDA (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. When set, a Low Speed device is attached to this port.
  • Page 902 UM10912 NXP Semiconductors Chapter 35: LPC546xx USB0 Full-speed Host controller Table 846. Host controller root hub port status register (HCRHPORTSTATUS[1:NDP] register offset 0x54) bit description …continued Symbol Description Reset value OCIC PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
  • Page 903 – Enable port control configuration by setting the USB1 host clock control in AHBCLKCTRL2 register. See Section 4.5.21. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 903 of 1152...
  • Page 904 (USB1RAM_RST5) in PRESETCTRL2. See Section 4.5.11 for more details. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 904 of 1152...
  • Page 905 USB device controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 905 of 1152...
  • Page 906 CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 906 of 1152...
  • Page 907 1024/512/1024 Interrupt/Bulk/Isochronous 1024/512/1024 Interrupt/Bulk/Isochronous 1024/512/1024 Interrupt/Bulk/Isochronous 1024/512/1024 Interrupt/Bulk/Isochronous 1024/512/1024 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 907 of 1152...
  • Page 908 AHB clock: The AHB system bus clock controls the USB device registers. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 909 USB1_OVERCURRENTN - Host only function. USB1_PORTPWRN Host only function. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 909 of 1152...
  • Page 910 LPM_SUP LPM Supported: LPM not supported. LPM supported. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 910 of 1152...
  • Page 911 VBUS disappeared. The bit is reset by writing a 1 to it. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 911 of 1152...
  • Page 912 CRC error, the frame number returned will be the corrupted frame number as received by the device. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 912 of 1152...
  • Page 913 RAM, and should not be changed. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 914 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. 31:12 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 914 of 1152...
  • Page 915 Software can clear this bit by writing a one to it. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 915 of 1152...
  • Page 916 Status Change register are set. Software can clear this bit by writing a one to it. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 917 Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 31:30 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 917 of 1152...
  • Page 918 Fig 169. Endpoint command/status list (see also Table 863) UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 918 of 1152...
  • Page 919 1: Interrupt endpoint (Max Packet Size is determined by the smallest value when comparing NBytes field with 1024). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 919 of 1152...
  • Page 920 Figure 170 “Flowchart of control endpoint 0 - OUT direction”. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 920 of 1152...
  • Page 921 Fig 170. Flowchart of control endpoint 0 - OUT direction UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 921 of 1152...
  • Page 922 When NBytes goes to 0, hardware clears the Active bit and sets the corresponding endpoint interrupt status bit in INTSTAT. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 922 of 1152...
  • Page 923 If the endpoint is used in double buffer mode, program the following: UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 924 PDEN_USB1PHY are left ON before going to deep-sleep mode. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 924 of 1152...
  • Page 925 5. Wait until the USB device leaves the suspend state by polling the DSUS bit in the DEVCMDSTAT register (DSUS =0). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 925 of 1152...
  • Page 926 Figure 172 shows the architecture of the USB host controller. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 926 of 1152...
  • Page 927 48 MHz (USB clock input). See Section 4.5.35 Section 4.5.56 for more details. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 927 of 1152...
  • Page 928 USB1_AVDDTX3V3 USB1 analog 3.3 V supply for line drivers. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 928 of 1152...
  • Page 929 USB RAM. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 930 Rsvd 0x00 aaa-021247 Fig 173. USB host software interface UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 930 of 1152...
  • Page 931 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 932 The FLADJ register controls the SOF frame length timing and the frame index. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 933 Base address to be used by the hardware to find the start of the INT list. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 934 INT List enabled. When this bit is set, the hardware will process the INT list. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 935 Software must write a one to clear the bit. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 935 of 1152...
  • Page 936 SOF Interrupt Enable bit: 1: enable 0: disable 31:20 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 936 of 1152...
  • Page 937 This field is 0 if Port Power is 0. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 937 of 1152...
  • Page 938 Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 938 of 1152...
  • Page 939 V bit setting. The information in that PTD is not processed. Hardware will go automatically to the next PTD. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 939 of 1152...
  • Page 940 This indicates the last PTD in the ISO list. If hardware has reached this PTD, it will continue with processing the INT list UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 940 of 1152...
  • Page 941 This indicates the last PTD in the INT list. If hardware has reached this PTD, it will continue with processing the ATL list. 31:21 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 941 of 1152...
  • Page 942 0b: PHY operational. 1b: PHY in power-down mode. 31:20 Reserved UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 942 of 1152...
  • Page 943 These channels are allocated and de-allocated on receiving the transfer from the core USB driver. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 943 of 1152...
  • Page 944 Figure 174 shows the flowchart of the PTD scheduler. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 944 of 1152...
  • Page 945 DT Cerr NakCnt[3:0 Token NrBytesToTransferred[14:0] [1:0] Type [1:0] [1:0] UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 945 of 1152...
  • Page 946 [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 946 of 1152...
  • Page 947 01 – IN 10 – SETUP 11 – Undefined UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 947 of 1152...
  • Page 948 11 — The transaction will retry three times. The hardware will decrement these values. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 948 of 1152...
  • Page 949 HW - writes Isochronous IN or OUT status at uSOF4. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 949 of 1152...
  • Page 950 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 950 of 1152...
  • Page 951 Bits[4:0] are compared with FRINDEX[7:3] Any 1 bit set UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 951 of 1152...
  • Page 952 UM10912 Chapter 38: LPC546xx USB ROM API Rev. 1.7 — 14 April 2017 User manual 38.1 How to read this chapter The USB ROM driver routines are available on all LPC546xx devices. USB on-chip drivers are provided via the USB Stack in SDK and LPCOpen software packages.
  • Page 953 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API • Communication Device Class (CDC) function driver. This module contains an internal implementation of the USB CDC Class. User applications can use this class driver instead of implementing the CDC-ACM class manually via the low-level USBD_HW and USBD_Core APIs.
  • Page 954 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API – HID class API functions structure. This structure contains pointers to all the functions exposed by the HID function driver module (Table 924 “USBD_HW_API class structure”). • USB device controller driver –...
  • Page 955 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4 USB API 38.4.1 __WORD_BYTE Table 891. __WORD_BYTE class structure Member Description uint16_t __WORD_BYTE::W data member to do 16 bit access WB_TWB_T __WORD_BYTE::WB data member to do 8 bit access 38.4.2 _BM_T Table 892.
  • Page 956 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.5 _CDC_HEADER_DESCRIPTOR Table 895. _CDC_HEADER_DESCRIPTOR class structure Member Description bFunctionLength uint8_t _CDC_HEADER_DESCRIPTOR::bFunctionLength bDescriptorType uint8_t _CDC_HEADER_DESCRIPTOR::bDescriptorType bDescriptorSubtype uint8_t _CDC_HEADER_DESCRIPTOR::bDescriptorSubtype bcdCDC uint16_t _CDC_HEADER_DESCRIPTOR::bcdCDC 38.4.6 _CDC_LINE_CODING Table 896. _CDC_LINE_CODING class structure Member Description dwDTERate...
  • Page 957 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.10 _HID_DESCRIPTOR HID class-specific HID Descriptor. Table 900. _HID_DESCRIPTOR class structure Member Description bLength uint8_t _HID_DESCRIPTOR::bLength Size of the descriptor, in bytes. bDescriptorType uint8_t _HID_DESCRIPTOR::bDescriptorType Type of HID descriptor. bcdHID uint16_t _HID_DESCRIPTOR::bcdHID BCD encoded version that the HID descriptor and device complies to.
  • Page 958 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.13 _MSC_CBW Table 903. _MSC_CBW class structure Member Description dSignature uint32_t _MSC_CBW::dSignature dTag uint32_t _MSC_CBW::dTag dDataLength uint32_t _MSC_CBW::dDataLength bmFlags uint8_t _MSC_CBW::bmFlags bLUN uint8_t _MSC_CBW::bLUN bCBLength uint8_t _MSC_CBW::bCBLength uint8_t _MSC_CBW::CB[16][16] 38.4.14 _MSC_CSW Table 904.
  • Page 959 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.17 _USB_CORE_DESCS_T USB descriptors data structure. Table 907. _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t * _USB_CORE_DESCS_T::device_desc Pointer to USB device descriptor string_desc uint8_t * _USB_CORE_DESCS_T::string_desc Pointer to array of USB string descriptors...
  • Page 960 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.19 _USB_DFU_FUNC_DESCRIPTOR Table 909. _USB_DFU_FUNC_DESCRIPTOR class structure Member Description bLength uint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength bDescriptorType uint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType bmAttributes uint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes wDetachTimeOut uint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut wTransferSize uint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize bcdDFUVersion uint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion 38.4.20 _USB_INTERFACE_DESCRIPTOR Table 910. _USB_INTERFACE_DESCRIPTOR class structure...
  • Page 961 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.21 _USB_OTHER_SPEED_CONFIGURATION Table 911. _USB_OTHER_SPEED_CONFIGURATION class structure Member Description bLength uint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength Size of descriptor bDescriptorType uint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType Other_speed_Configuration Type wTotalLength uint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength Total length of data returned bNumInterfaces uint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces...
  • Page 962 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.23 _USB_STRING_DESCRIPTOR Table 913. _USB_STRING_DESCRIPTOR class structure Member Description bLength uint8_t _USB_STRING_DESCRIPTOR::bLength Size of this descriptor in bytes bDescriptorType uint8_t _USB_STRING_DESCRIPTOR::bDescriptorType STRING Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR::bString UNICODE encoded string 38.4.24 _WB_T Table 914.
  • Page 963 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 915. USBD_API class structure Member Description const USBD_CDC_API_T* USBD_API::cdc Pointer to function table which exposes functions provided by CDC-ACM function driver module. reserved6 const uint32_t* USBD_API::reserved6 Reserved for future function driver module.
  • Page 964 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 916. USBD_API_INIT_PARAM class structure Member Description USB_Resume_Event USB_CB_T USBD_API_INIT_PARAM::USB_Resume_Event Event for USB wake up or resume. This event fires when a the USB device interface is suspended and the host wakes up the device by supplying Start Of Frame pulses. This is generally hooked to pull the user application out of a low power state and back into normal operating mode.
  • Page 965 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 916. USBD_API_INIT_PARAM class structure Member Description USB_Configure_Event USB_CB_T USBD_API_INIT_PARAM::USB_Configure_Event Event for USB configuration number changed. This event fires when a the USB host changes the selected configuration number. On receiving configuration change request from host, the stack enables/configures the endpoints needed by the new configuration before calling this callback function.
  • Page 966 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 917. USBD_CDC_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param, USBD_HANDLE_T *phCDC) Function to initialize CDC function driver module. This function is called by application layer to initialize CDC function driver module.
  • Page 967 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.28 USBD_CDC_INIT_PARAM Communication Device Class function driver initialization parameter data structure. Table 918. USBD_CDC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_CDC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers.
  • Page 968 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 918. USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) Communication Interface Class specific set request call-back function. This function is provided by the application software. This function gets called when host sends a CIC management element requests.
  • Page 969 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 918. USBD_CDC_INIT_PARAM class structure Member Description CDC_BulkOUT_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkOUT_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Communication Device Class specific BULK OUT endpoint handler. The application software should provide the BULK OUT endpoint handler. Applications should transfer data depending on the communication protocol type set in descriptors.
  • Page 970 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 918. USBD_CDC_INIT_PARAM class structure Member Description SetCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t *buffer, uint16_t len) Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a SET_COMM_FEATURE set request.
  • Page 971 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 918. USBD_CDC_INIT_PARAM class structure Member Description ClrCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature) Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a CLEAR_COMM_FEATURE request.
  • Page 972 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 918. USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding) Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. This function is provided by the application software. This function gets called when host sends a SET_LINE_CODING request.
  • Page 973 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.29 USBD_CORE_API USBD stack Core API functions structure. Table 919. USBD_CORE_API class structure Member Description RegisterClassHandler ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterClassHandler)(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void *data) Function to register class specific EP0 event handler with USB device stack.
  • Page 974 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 919. USBD_CORE_API class structure Member Description SetupStage void(*void USBD_CORE_API::SetupStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in setup state. This function is called by USB stack and the application layer to set the EP0 state machine in setup state.
  • Page 975 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 919. USBD_CORE_API class structure Member Description StatusOutStage void(*void USBD_CORE_API::StatusOutStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in status_out state. This function is called by USB stack and the application layer to set the EP0 state machine in status_out state.
  • Page 976 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 920. USBD_DFU_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_DFU_API::init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T *param, uint32_t init_state) Function to initialize DFU function driver module. This function is called by application layer to initialize DFU function driver module.
  • Page 977 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 921. USBD_DFU_INIT_PARAM class structure Member Description DFU_Write uint8_t(*uint8_t(* USBD_DFU_INIT_PARAM::DFU_Write)(uint32_t block_num, uint8_t **src, uint32_t length, uint8_t *bwPollTimeout))(uint32_t block_num, uint8_t **src, uint32_t length, uint8_t *bwPollTimeout) DFU Write callback function. This function is provided by the application software. This function gets called when host sends a write command.
  • Page 978 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 921. USBD_DFU_INIT_PARAM class structure Member Description DFU_Ep0_Hdlr ErrorCode_t(* USBD_DFU_INIT_PARAM::DFU_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default DFU class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
  • Page 979 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 922. USBD_HID_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_HID_API::init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T *param) Function to initialize HID function driver module. This function is called by application layer to initialize HID function driver module. On successful initialization the function returns a handle to HID function driver module in passed param structure.
  • Page 980 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 923. USBD_HID_INIT_PARAM class structure Member Description HID_GetReport ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t *length) HID get report callback function. This function is provided by the application software. This function gets called when host sends a HID_REQUEST_GET_REPORT request.
  • Page 981 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 923. USBD_HID_INIT_PARAM class structure Member Description HID_GetPhysDesc ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetPhysDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuf, uint16_t *length) Optional callback function to handle HID_GetPhysDesc request. The application software could provide this callback HID_GetPhysDesc handler to handle get physical descriptor requests sent by the host.
  • Page 982 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 923. USBD_HID_INIT_PARAM class structure Member Description HID_SetProtocol ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetProtocol)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t protocol) Optional callback function to handle HID_REQUEST_SET_PROTOCOL request. The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL requests sent by the host.
  • Page 983 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 923. USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt OUT endpoint event handler. The application software could provide Interrupt OUT endpoint event handler. Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member.
  • Page 984 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 923. USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default HID class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
  • Page 985 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 924. USBD_HW_API class structure Member Description Connect void(*void USBD_HW_API::Connect)(USBD_HANDLE_T hUsb, uint32_t con) Function to make USB device visible/invisible on the USB bus. This function is called after the USB initialization. This function uses the soft connect feature to make the device visible on the USB bus.
  • Page 986 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 924. USBD_HW_API class structure Member Description WakeUpCfg void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg) Function to configure USB device controller to walk-up host on remote events. This function is called by application layer to configure the USB device controller to wake up on remote events.
  • Page 987 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 924. USBD_HW_API class structure Member Description ConfigEP void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) Function to configure USB Endpoint according to descriptor. This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received by the stack from USB host.
  • Page 988 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 924. USBD_HW_API class structure Member Description DisableEP void(*void USBD_HW_API::DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to disable selected USB endpoint. This function disables interrupts on selected endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
  • Page 989 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 924. USBD_HW_API class structure Member Description ReadEP uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) Function to read data received on the requested endpoint. This function is called by USB stack and the application layer to read the data received on the requested endpoint.
  • Page 990 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 924. USBD_HW_API class structure Member Description WakeUp void(*void USBD_HW_API::WakeUp)(USBD_HANDLE_T hUsb) Function to generate resume signaling on bus for remote host wake-up. This function is called by application layer to remotely wake up host controller when system is in suspend state.
  • Page 991 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API 38.4.36 USBD_MSC_INIT_PARAM Mass Storage class function driver initialization parameter data structure. Table 926. USBD_MSC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_MSC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers.
  • Page 992 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 926. USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t offset, uint8_t **dst, uint32_t length) MSC Read callback function. This function is provided by the application software. This function gets called when host sends a read command.
  • Page 993 UM10912 NXP Semiconductors Chapter 38: LPC546xx USB ROM API Table 926. USBD_MSC_INIT_PARAM class structure Member Description MSC_Ep0_Hdlr ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default MSC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
  • Page 994 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 994 of 1152...
  • Page 995 0x05 31:8 - Reserved: leave existing value unchanged. 0xC0 UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 995 of 1152...
  • Page 996 Word 2 of 128-bit signature (bits 95 to 64). UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 996 of 1152...
  • Page 997 STOP bits of the same register. UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017...
  • Page 998 = f_Q[address][127] XOR sign[0] XOR sign[2] XOR sign[27] XOR sign[29] sign = nextSign signature128 = sign UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 998 of 1152...
  • Page 999 FRO operation. CLOCK_SetupFROClocking(uin t32_t iFreq); UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 999 of 1152...
  • Page 1000 POWER_EnterPowerMode API. For details, see Section 22.3.2 “Configure the USART for UM10912 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.7 — 14 April 2017 1000 of 1152...

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