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NXP Semiconductors LPC800 User Manual

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UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012
Document information
Info
Content
ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
Keywords
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
LPC800 Preliminary user manual
Abstract
Preliminary user manual

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Summary of Contents for NXP Semiconductors LPC800

  • Page 1 UM10601 LPC800 User manual Rev. 1.0 — 7 November 2012 Preliminary user manual Document information Info Content ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8, Keywords LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20, LPC812M101FDH20 LPC800 Preliminary user manual Abstract...
  • Page 2 UM10601 NXP Semiconductors LPC800 User manual Revision history Date Description 20121107 Preliminary LPC800 user manual Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10601 All information provided in this document is subject to legal disclaimers.

  • Page 3: Chapter 1: Lpc800 Introductory Information

    Preliminary user manual 1.1 Introduction The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory and 4 kB of SRAM.
  • Page 4 UM10601 NXP Semiconductors Chapter 1: LPC800 Introductory information – CRC engine. – Windowed Watchdog timer Analog peripherals: • – Comparator with external voltage reference with pin functions assigned through the switch matrix. – Internal reference voltage. Serial interfaces: • – Three UART interfaces with pin functions assigned through the switch matrix.

  • Page 5: Ordering Information

    UM10601 NXP Semiconductors Chapter 1: LPC800 Introductory information 1.3 Ordering information Table 1. Ordering information Type number Package Name Description Version LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2 LPC811M001FDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm...

  • Page 6: Block Diagram

    UM10601 NXP Semiconductors Chapter 1: LPC800 Introductory information 1.4 Block diagram /3& 6:&/. 6:' 7(67'(%8* ,17(5)$&(  [ 3,2 +,*+63((' *3,2 &257(;0 )/$6+ 65$0 3,1 ,17(558376  N%  N%  N% 3$77(51 0$7&+ VODYH VODYH VODYH &7287B>@ $+%/,7( %86 &7,1B>@...

  • Page 7: General Description

    UM10601 NXP Semiconductors Chapter 1: LPC800 Introductory information 1.5 General description 1.5.1 ARM Cortex-M0+ core configuration The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints.

  • Page 8: Chapter 2: Lpc800 Memory Mapping

    Rev. 1.0 — 7 November 2012 Preliminary user manual 2.1 How to read this chapter The memory mapping is identical for all LPC800 parts. Different LPC800 parts support different flash memory sizes. 2.2 General description The LPC800 incorporates several distinct memory regions.

  • Page 9: Memory Mapping

    The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers. Fig 2. LPC800 Memory mapping 2.2.2 Micro Trace Buffer (MTB) The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer. UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

  • Page 10: Chapter 3: Lpc800 Nested Vectored Interrupt Controller (Nvic)

    (NVIC) Rev. 1.0 — 7 November 2012 Preliminary user manual 3.1 How to read this chapter The NVIC is identical on all LPC800 parts. The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and LPC812M101FDH16 only. 3.2 Features Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.
  • Page 11 UM10601 NXP Semiconductors Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) Table 3. Connection of interrupt sources to the NVIC Interrupt Name Description Flags number UART0_IRQ USART0 interrupt Table 161 “USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description”...
  • Page 12 UM10601 NXP Semiconductors Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) Table 3. Connection of interrupt sources to the NVIC Interrupt Name Description Flags number PININT5_IRQ Pin interrupt 5 or pattern PSTAT - pin interrupt status match engine slice 5...

  • Page 13: Chapter 4: Lpc800 System Configuration (Syscon)

    Rev. 1.0 — 7 November 2012 Preliminary user manual 4.1 How to read this chapter The system configuration block is identical for all LPC800 parts. USART2 and SPI1 are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding clocks, reset, and wake-up control bits are reserved for all other parts.

  • Page 14: Configure The Main Clock And System Clock

    4.3.3 Set up the system oscillator using XTALIN and XTALOUT If you want to use the system oscillator with the LPC800, you need to assign the XTALIN and XTALOUT pins, which connect to the external crystal, through the fixed-pin function in the switch matrix.

  • Page 15: Pin Description

    The system control block facilitates the clock generation. Except for the USART clock and the clock to configure the glitch filters of the digital I/O pins, the clocks to the core and peripherals run at the same frequency. The maximum clock frequency for LPC800 is 30 MHz. See...

  • Page 16: Power Control Of Analog Components

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 6<6&21 $+% FORFN  FRUH V\VWHP PDLQ FORFN V\VWHP FORFN DOZD\VRQ &/2&. ',9,'(5 6<6$+%&/.',9 PHPRULHV DQG SHULSKHUDOV SHULSKHUDO FORFNV 6<6$+%&/.&75/>@ V\VWHP FORFN HQDEOH 86$57 )5$&7,21$/ 5$7( &/2&. ',9,'(5 86$57 *(1(5$725 8$57&/.',9 86$57 ,5&...

  • Page 17: Configuration Of Reduced Power-Modes

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.5.3 Configuration of reduced power-modes The system control block configures analog blocks that can remain running in the reduced power modes (the BOD and the watchdog oscillator for safe operation) and enables various interrupts to wake up the chip when the internal clocks are shut down in Deep-sleep and Power-down modes.
  • Page 18 UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 5. Register overview: System configuration (base address 0x4004 8000) …continued Name Access Offset Description Reset value Reference 0x09C Reserved 0x0A0 - Reserved 0x0BC 0x0CC Reserved CLKOUTSEL 0x0E0 CLKOUT clock source select...

  • Page 19: System Memory Remap Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 5. Register overview: System configuration (base address 0x4004 8000) …continued Name Access Offset Description Reset value Reference PDSLEEPCFG 0x230 Power-down states in deep-sleep mode 0xFFFF Table 35 PDAWAKECFG 0x234 Power-down states for wake-up from...

  • Page 20: System Pll Control Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 7. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description Symbol Value Description Reset value USART0_RST_N USART0 reset control Assert the USART0 reset. Clear the USART0 reset. UART1_RST_N USART1 reset control Assert the USART reset.

  • Page 21: System Pll Status Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 8. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Symbol Value Description Reset value MSEL Feedback divider value. The division value M is the programmed MSEL value + 1.

  • Page 22: Watchdog Oscillator Control Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.6.6 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana).

  • Page 23: System Reset Status Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.6.7 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register.

  • Page 24: System Pll Clock Source Update Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.6.9 System PLL clock source update register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

  • Page 25: System Clock Divider Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.6.12 System clock divider register This register controls how the main clock is divided to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV field to zero.
  • Page 26 UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 18. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Symbol Value Description Reset value GPIO Enables clock for GPIO port registers and GPIO pin interrupt registers. Disable Enable Enables clock for switch matrix.

  • Page 27: Usart Clock Divider Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 18. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Symbol Value Description Reset value ACMP Enables clock to analog comparator. Disable Enable 31:20 Reserved 4.6.14 USART clock divider register This register configures the clock for the fractional baud rate generator and all USARTs.

  • Page 28: Clkout Clock Divider Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 21. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004 80E4) bit description Symbol Value Description Reset value Enable CLKOUT clock source update No change Update clock source 31:1 Reserved 4.6.17 CLKOUT clock divider register...

  • Page 29: Usart Fractional Generator Multiplier Value Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 23. USART fractional generator divider value register (UARTFRGDIV, address 0x4004 80F0) bit description Symbol Description Reset value Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.

  • Page 30: Por Captured Pio Status Register 0

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.6.21 POR captured PIO status register 0 The PIOPORCAP0 register captures the state of GPIO port 0 at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register.

  • Page 31: System Tick Counter Calibration Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 28. BOD control register (BODCTRL, address 0x4004 8150) bit description Symbol Value Description Reset value BODINTVAL BOD interrupt level Level 0: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>...

  • Page 32: Nmi Source Selection Register

    PIO0_0 to PIO0_17 to the INTPIN bits. For example, setting INTPIN to 0x5 in PINTSEL0 selects pin PIO0_5 for pin interrupt 0. To determine the GPIO port pin number on a given LPC800 package, see the pin description table in the data sheet.

  • Page 33: Start Logic 0 Pin Wake-Up Enable Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 32. Pin interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to 0x4004 8194 (PINTSEL7)) bit description Symbol Description Reset value INTPIN Pin number select for pin interrupt or pattern match engine input.

  • Page 34: Start Logic 1 Interrupt Wake-Up Enable Register

    NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.6.29 Start logic 1 interrupt wake-up enable register This register selects which interrupts wake the LPC800 from deep-sleep and power-down modes. Remark: Also enable the corresponding interrupts in the NVIC. See Table 3 “Connection of interrupt sources to the NVIC”.

  • Page 35: Deep-Sleep Mode Configuration Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 34. Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description …continued Symbol Value Description Reset value Self wake-up timer interrupt wake-up Disabled Enabled 31:16 Reserved. 4.6.30 Deep-sleep mode configuration register The bits in this register (BOD_PD and WDTOSC_OD) can be programmed to control aspects of Deep-sleep and Power-down modes.

  • Page 36: Power Configuration Register

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 36. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description Symbol Value Description Reset value IRCOUT_PD IRC oscillator output wake-up configuration Powered Powered down IRC_PD IRC oscillator power-down wake-up configuration...

  • Page 37: Device Id Register

    Powered Powered down 31:16 Reserved 4.6.33 Device ID register This device ID register is a read-only register and contains the part ID for each LPC800 part. This register is also read by the ISP/IAP commands (see Table 229). UM10601 All information provided in this document is subject to legal disclaimers.

  • Page 38: Functional Description

    0x0000 8120 = LPC812M101FDH16 0x0000 8121 = LPC812M101FD20 0x0000 8122 = LPC812M101FDH20 4.7 Functional description 4.7.1 System PLL functional description The LPC800 uses the system PLL to create the clocks for the core and peripherals. LUFBRVFBFON V\VBRVFBFON &/.,1 36(/! 6<63//&/.6(/ /2&.

  • Page 39: Lock Detector

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) 4.7.1.1 Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called “lock criterion”...

  • Page 40: Normal Mode

    UM10601 NXP Semiconductors Chapter 4: LPC800 System configuration (SYSCON) Table 39. PLL frequency parameters Parameter System PLL FCLKOUT Frequency of sys_pllclkout System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see Section 4.6.3). System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see Section 4.6.3).

  • Page 41: How To Read This Chapter

    Deep power-down mode. 5.5 General description Power on the LPC800 is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption: 1.

  • Page 42: Wake-Up Process

    The part can wake up on a pulse on the WAKEUP pin or when the self wake-up timer times out. On wake-up, the part reboots. Remark: The LPC800 is in active mode when it is fully powered and operational after booting.

  • Page 43: Register Description

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management Table 41. Wake-up sources for reduced power modes Power mode Wake-up source Conditions Sleep Any interrupt Enable interrupt in NVIC. Deep-sleep and Pin interrupts Enable pin interrupts in NVIC and STARTERP0 registers.

  • Page 44: Power Control Register

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management 5.6.1 Power control register The power control register selects whether one of the ARM Cortex-M0 controlled power-down modes (Sleep mode or Deep-sleep/Power-down mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep/Power-down modes and Deep power-down modes respectively.

  • Page 45: Deep Power-Down Control Register

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management 5.6.3 Deep power-down control register The Deep power-down control register controls the low-power oscillator that can be used by the self wake-up timer to wake up from Deep power-down mode. In addition, this register configures the functionality of the WAKEUP pin (pin PIO0_4).

  • Page 46: Functional Description

    5.7 Functional description 5.7.1 Power management The LPC800 support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are four special modes of processor power reduction with different peripherals running: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.

  • Page 47: Reduced Power Modes And Wwdt Lock Features

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management 5.7.2 Reduced power modes and WWDT lock features The WWDT clock select lock feature influences the power consumption in any of the power modes because locking the WWDT clock source forces the selected WWDT clock source to be on independently of the Deep-sleep and Power-down mode software configuration through the PDSLEEPCFG register.

  • Page 48: Power Configuration In Sleep Mode

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

  • Page 49: Programming Deep-Sleep Mode

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management 5.7.5.2 Programming Deep-sleep mode The following steps must be performed to enter Deep-sleep mode: 1. The PD bits in the PCON register must be set to 0x1 (Table 43).

  • Page 50: Power Configuration In Power-Down Mode

    UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management register. The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC itself and the flash are powered down, decreasing power consumption compared to Deep-sleep mode.

  • Page 51: Deep Power-Down Mode

    6. Use the ARM WFI instruction. 5.7.7.3 Wake-up from Deep power-down mode Pulling the WAKEUP pin LOW wakes up the LPC800 from Deep power-down, and the part goes through the entire reset process. 1. On the WAKEUP pin, transition from HIGH to LOW.
  • Page 52 UM10601 NXP Semiconductors Chapter 5: LPC800 Reduced power modes and Power Management 2. Once the chip has booted, read the deep power-down flag in the PCON register (Table 43) to verify that the reset was caused by a wake-up event from Deep power-down and was not a cold reset.

  • Page 53: Chapter 6: Lpc800 I/O Configuration (Iocon)

    Rev. 1.0 — 7 November 2012 Preliminary user manual 6.1 How to read this chapter The IOCON block is identical for all LPC800 parts. Registers for pins that are not available on a specific package are reserved. Table 47. Pinout summary...

  • Page 54: General Description

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.4 General description 6.4.1 Pin configuration RSHQGUDLQ HQDEOH VWURQJ SLQ FRQILJXUHG RXWSXW HQDEOH SXOOXS DV GLJLWDO RXWSXW GULYHU GDWD RXWSXW VWURQJ SXOOGRZQ ZHDN SXOOXS SXOOXS HQDEOH ZHDN UHSHDWHU PRGH SXOOGRZQ SLQ FRQILJXUHG...

  • Page 55: Open-Drain Mode

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) The repeater mode enables the pull-up resistor if the pin is high and enables the pull-down resistor if the pin is low. This causes the pin to retain its last known state if it is configured as an input and is not driven externally.
  • Page 56 UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) Table 27 “IOCON glitch filter clock divider registers 6 to 0 (IOCONCLKDIV[6:0], address 0x4004 8134 (IOCONCLKDIV6) to 0x004 814C (IOCONFILTCLKDIV0)) bit description” UM10601 All information provided in this document is subject to legal disclaimers.

  • Page 57: Register Description

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5 Register description Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and electrical characteristics. Table 48. Register overview: I/O configuration (base address 0x4004 4000) Name...
  • Page 58 UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) Table 49. PIO0_17 register (PIO0_17, address 0x4004 4000) bit description Symbol Value Description Reset value MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled.

  • Page 59: Pio0_13 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.2 PIO0_13 register Table 50. PIO0_13 register (PIO0_13, address 0x4004 4004) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 60: Pio0_12 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.3 PIO0_12 register Table 51. PIO0_12 register (PIO0_12, address 0x4004 4008) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 61: Pio0_5 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.4 PIO0_5 register Table 52. PIO0_5 register (PIO0_5, address 0x4004 400C) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 62: Pio0_4 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.5 PIO0_4 register Table 53. PIO0_ register (PIO0_ , address 0x4004 4010) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 63: Pio0_3 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.6 PIO0_3 register Table 54. PIO0_3 register (PIO0_3, address 0x4004 4014) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 64: Pio0_2 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.7 PIO0_2 register Table 55. PIO0_2 register (PIO0_2, address 0x4004 4018) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 65: Pio0_11 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.8 PIO0_11 register Table 56. PIO0_11 register (PIO0_11, address 0x4004 401C) bit description Symbol Value Description Reset value Reserved. Invert input Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

  • Page 66: Pio0_10 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.9 PIO0_10 register Table 57. PIO0_10 register (PIO0_10, address 0x4004 4020) bit description Symbol Value Description Reset value Reserved. Invert input Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

  • Page 67: Pio0_16 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.10 PIO0_16 register Table 58. PIO0_16 register (PIO0_16, address 0x4004 4024) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 68: Pio0_15 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.11 PIO0_15 register Table 59. PIO0_15 register (PIO0_15, address 0x4004 4028) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 69: Pio0_1 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.12 PIO0_1 register Table 60. PIO0_1 register (PIO0_1, address 0x4004 402C) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 70: Pio0_9 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.13 PIO0_9 register Table 61. PIO0_9 register (PIO0_9, address 0x4004 4034) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 71: Pio0_8 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.14 PIO0_8 register Table 62. PIO0_8 register (PIO0_8, address 0x4004 4038) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 72: Pio0_7 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.15 PIO0_7 register Table 63. PIO0_7 register (PIO0_7, address 0x4004 403C) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 73: Pio0_6 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.16 PIO0_6 register Table 64. PIO0_6 register (PIO0_6, address 0x4004 4040) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 74: Pio0_0 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.17 PIO0_0 register Table 65. PIO0_0 register (PIO0_0, address 0x4004 4044) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 75: Pio0_14 Register

    UM10601 NXP Semiconductors Chapter 6: LPC800 I/O configuration (IOCON) 6.5.18 PIO0_14 register Table 66. PIO0_14 register (PIO0_14, address 0x4004 4048) bit description Symbol Value Description Reset value Reserved. MODE Selects function mode (on-chip pull-up/pull-down resistor 0b10 control). Inactive (no pull-down/pull-up resistor enabled).

  • Page 76: Chapter 7: Lpc800 Gpio Port

    All GPIO functions are fixed-pin functions. The switch matrix assigns every GPIO port pin to one and only one pin on the LPC800 package. By default, the switch matrix connects all package pins except supply and ground pins to their GPIO port pins.

  • Page 77: Register Description

    UM10601 NXP Semiconductors Chapter 7: LPC800 GPIO port 7.6 Register description The GPIO port registers and the GPIO pin interrupt registers are located on the ARM M0+ I/O port. The I/O port supports single-cycle access. Remark: In all GPIO registers, bits that are not shown are reserved.

  • Page 78: Gpio Port Direction Registers

    UM10601 NXP Semiconductors Chapter 7: LPC800 GPIO port Table 70. GPIO port 0 word pin registers (W[0:17], addresses 0xA000 1000 (W0) to 0x5000 1048 (W17)) bit description Symbol Description Reset Access value 31:0 PWORD Read 0: pin is LOW. Write 0: clear output bit.

  • Page 79: Gpio Masked Port Pin Registers

    UM10601 NXP Semiconductors Chapter 7: LPC800 GPIO port Table 73. GPIO port 0 pin register (PIN0, address 0xA000 2100) bit description Symbol Description Reset Access value 17:0 PORT0 Reads pin states or loads output bits (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17).

  • Page 80: Gpio Port Toggle Registers

    UM10601 NXP Semiconductors Chapter 7: LPC800 GPIO port Table 76. GPIO clear port 0 register (CLR0, address 0xA000 2280) bit description Symbol Description Reset Access value 17:0 CLRP0 Clear output bits: 0 = No operation. 1 = Clear output bit.

  • Page 81: Masked I/O

    UM10601 NXP Semiconductors Chapter 7: LPC800 GPIO port Writing to a Byte Pin register loads the output bit from the least significant bit. • Writing to a Word Pin register loads the output bit with the OR of all of the bits written.

  • Page 82: How To Read This Chapter

    Chapter 8: LPC800 Pin interrupts/pattern match engine Rev. 1.0 — 7 November 2012 Preliminary user manual 8.1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all LPC800 parts. 8.2 Features •...

  • Page 83: Configure Pins As Pin Interrupts Or As Inputs To The Pattern Match Engine

    The pattern match engine output is assigned to an external pin through the switch matrix. Section 9.3.1 “Connect an internal signal to a package pin” for the steps that you need to follow to assign the GPIO pattern match function to a pin on the LPC800 package. Table 78. SCT pin description...

  • Page 84: Pin Interrupts

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine 8.5.1 Pin interrupts From all available GPIO pins, up to eight pins can be selected in the system control block to serve as external interrupt pins (see Table 32). The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin.

  • Page 85: Example

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine )URP 3UHYLRXV 6OLFH 5LVH 'HWHFW VWLFN\ ZLWK V\QFK FOHDU 30&)* )DOO 'HWHFW 3URGB(QGSWV L VWLFN\ ZLWK V\QFK FOHDU 3065& 65& L 3DWWHUQB0DWFK L ,QWUB5HT L 5LVH 'HWHFW QRQVWLFN\ )DOO 'HWHFW QRQVWLFN\ 7R 1H[W 6OLFH 30&)*...

  • Page 86: Register Description

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine 8.6 Register description Table 79. Register overview: Pin interrupts/pattern match engine (base address: 0xA000 4000) Name Access Address Description Reset Reference offset value ISEL 0x000 Pin Interrupt Mode register Table 80...

  • Page 87: Pin Interrupt Level Or Rising Edge Interrupt Set Register

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled. • The IENF register configures the active level (HIGH or LOW) for this interrupt.

  • Page 88: Pin Interrupt Active Level Or Falling Edge Interrupt Enable Register

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 83. Pin interrupt level or rising edge interrupt clear register (CIENR, address 0xA000 400C) bit description Symbol Description Reset Access value CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts.

  • Page 89: Pin Interrupt Active Level Or Falling Edge Interrupt Clear Register

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 85. Pin interrupt active level or falling edge interrupt set register (SIENF, address 0xA000 4014) bit description Symbol Description Reset Access value SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts.

  • Page 90: Pin Interrupt Falling Edge Register

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine 8.6.9 Pin interrupt falling edge register This register contains ones for pin interrupts selected in the PINTSELn registers (see Section 4.6.27) on which a falling edge has been detected. Writing ones to this register clears falling edge detection.
  • Page 91 UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Remark: Set up the pattern-match configuration in the PMSRC and PMCFG registers before writing to this register to enable (or re-enable) the pattern-match functionality. This eliminates the possibility of spurious interrupts as the feature is being enabled.
  • Page 92 UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C) bit description Symbol Value Description Reset value 10:8 SRC0 Selects the input source for bit slice 0 Input 0. Selects pin interrupt input 0 as the source to bit slice 0.
  • Page 93 UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C) bit description Symbol Value Description Reset value 22:20 SRC4 Selects the input source for bit slice 4 Input 0. Selects pin interrupt input 0 as the source to bit slice 4.

  • Page 94: Pattern Match Interrupt Bit-Slice Configuration Register

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine 8.6.13 Pattern Match Interrupt Bit-Slice Configuration register The bit-slice configuration register contains bits to select from among eight alternative conditions for each bit slice that will cause that bit slice to contribute to a pattern match.
  • Page 95 UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Symbol Value Description Reset value 13:11 CFG1 Specifies the match-contribution condition for bit slice 1.
  • Page 96 UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Symbol Value Description Reset value 19:17 CFG3 Specifies the match-contribution condition for bit slice 3.
  • Page 97 UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Symbol Value Description Reset value 25:23 CFG5 Specifies the match-contribution condition for bit slice 5.

  • Page 98: Functional Description

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Symbol Value Description Reset value 31:29 CFG7 Specifies the match-contribution condition for bit slice 7.

  • Page 99: Pattern Match Engine Example

    UM10601 NXP Semiconductors Chapter 8: LPC800 Pin interrupts/pattern match engine 8.7.2 Pattern Match engine example Suppose the desired boolean pattern to be matched is: (IN1) + (IN1 * IN2) + (~IN2 * ~IN3 * IN6fe) + (IN5 * IN7ev) with:...

  • Page 100: Chapter 9: Lpc800 Switch Matrix

    Rev. 1.0 — 7 November 2012 Preliminary user manual 9.1 How to read this chapter The switch matrix is identical for all LPC800 parts. The USART2 and SPI1 functions are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding switch matrix select bits are reserved for all other parts.

  • Page 101: Connect An Internal Signal To A Package Pin

    Table 94 or in the data sheet. 2. Use the LPC800 data sheet to decide which pin x on the LPC800 package to connect FUNC to. 3. Use the pin description table to find the default GPIO function PIO0_n assigned to package pin x.

  • Page 102: General Description

    NXP Semiconductors Chapter 9: LPC800 Switch matrix If you want to assign a GPIO pin to a pin on any LPC800 package, disable any special • function available on this pin in the PINENABLE0 register and do not assign any movable function to it.

  • Page 103: Switch Matrix Register Interface

    UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix Table 94. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description SWM Pin assign Reference register U2_RXD Receiver input for USART2. PINASSIGN2 Table 98 U2_RTS Request To Send output for USART1.

  • Page 104: Register Description

    UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix 1. Movable functions (PINASSIGN0 to 8): All movable functions are digital functions. Assign movable functions to pin numbers through the 8 bits of the PINASSIGN register associated with this function. Once the function is assigned a pin PIO0_n, it is connected through this pin to a physical pin on the package.

  • Page 105: Pin Assign Register 0

    UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix Table 95. Register overview: Switch matrix (base address 0x4000 C000) …continued Name Access Offset Description Reset value Reference PINASSIGN7 0x01C Pin assign egister 7. Assign movable 0xFFFF FFFF Table 103 functions CTOUT_1, CTOUT_2, CTOUT_3,...

  • Page 106: Pin Assign Register 2

    UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix 9.5.3 Pin assign register 2 Table 98. Pin assign register 2 (PINASSIGN2, address 0x4000 C008) bit description Symbol Description Reset value U1_CTS_I U1_CTS function assignment. The value is the pin number to be 0xFF assigned to this function.

  • Page 107: Pin Assign Register 5

    UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description Symbol Description Reset value 15:8 SPI0_MISO_IO SPI0_MISIO function assignment. The value is the pin number 0xFF to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11).

  • Page 108: Pin Assign Register 7

    UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix 9.5.8 Pin assign register 7 Table 103. Pin assign register 7 (PINASSIGN7, address 0x4000 C01C) bit description Symbol Description Reset value CTOUT_1_O CTOUT_1 function assignment. The value is the pin number to 0xFF be assigned to this function.
  • Page 109 UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description Symbol Value Description Reset value ACMP_I2_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin.
  • Page 110 UM10601 NXP Semiconductors Chapter 9: LPC800 Switch matrix Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description Symbol Value Description Reset value VDDCMP Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.

  • Page 111: Chapter 10: Lpc800 State Configurable Timer (Sct)

    (Table 18) to enable the clock to the SCT register • interface and peripheral clock. The LPC800 system clock is the input clock to the SCT clock processing and is the source of the SCT clock. • Clear the SCT peripheral reset using the PRESETCTRL register (Table •...

  • Page 112: Pin Description

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 1. Set up the SCT as one 32-bit timer or one or two 16-bit timers. See Table 108. 2. Preload the 32-bit timer or the 16-bit timers with a count value. See Table 114.
  • Page 113 UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: State variable •...

  • Page 114: Register Description

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 6&7 FORFN V\VWHP FORFN SUHVFDOHU + FRXQWHU 8QLILHG FRXQWHU SUHVFDOHU / FRXQWHU Fig 9. SCT counter and select logic 10.6 Register description The register addresses of the State Configurable Timer are shown in Table 107.
  • Page 115 UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) Name Access Address Description Reset value Reference offset CONFIG 0x000 SCT configuration register 0x0000 7E00 Table 108 CTRL 0x004...
  • Page 116 UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued Name Access Address Description Reset value Reference offset MATCH0 to MATCH4 R/W 0x100 to SCT match value register of match channels 0 to...

  • Page 117: Sct Configuration Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued Name Access Address Description Reset value Reference offset OUT1_CLR 0x50C SCT output 1 clear register 0x0000 0000 Table 132...

  • Page 118: Sct Control Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 108. SCT configuration register (CONFIG, address 0x5000 4000) bit description …continued Symbol Value Description Reset value 16:9 INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7).

  • Page 119: Sct Limit Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 109. SCT control register (CTRL, address 0x5000 4004) bit description Symbol Value Description Reset value CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.

  • Page 120: Sct Halt Condition Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Note that in addition to using this register to specify events that serve as limits, it is also possible to automatically cause a limit condition whenever a match register 0 match occurs.

  • Page 121: Sct Start Condition Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 112. SCT stop condition register (STOP, address 0x5000 4010) bit description Symbol Description Reset value STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).

  • Page 122: Sct State Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 114. SCT counter register (COUNT, address 0x5000 4040) bit description Symbol Description Reset value 15:0 CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.

  • Page 123: Sct Input Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.6.9 SCT input register Software can read the state of the SCT inputs in this read-only register in two slightly different forms. The only situation in which these values are different is if CLKMODE = 2 in the CONFIG register.

  • Page 124: Sct Output Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 117. SCT match/capture registers mode register (REGMODE, address 0x5000 404C) bit description Symbol Description Reset value REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4).

  • Page 125: Sct Conflict Resolution Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description Symbol Value Description Reset value SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.

  • Page 126: Sct Flag Enable Register

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.6.14 SCT flag enable register This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag register (Section 10.6.15) is also set. Table 121. SCT flag enable register (EVEN, address 0x5000 40F0) bit description...

  • Page 127: Sct Match Registers 0 To 4 (Regmoden Bit = 0)

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 124. SCT conflict flag register (CONFLAG, address 0x5000 40FC) bit description Symbol Description Reset value NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3).

  • Page 128: Sct Match Reload Registers 0 To 4 (Regmoden Bit = 0)

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 126. SCT capture registers 0 to 4 (CAP[0:4], address 0x5000 4100 (CAP0) to 0x5000 4110 (CAP4)) bit description (REGMODEn bit = 1) Symbol Description Reset value 15:0 VALCAP_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured.

  • Page 129: Sct Event State Mask Registers 0 To 5

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.6.22 SCT event state mask registers 0 to 5 Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter selected by the HEVENT bit in the corresponding EVn_CTRL register.
  • Page 130 UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C (EV5_CTRL)) bit description Symbol Value Description Reset value HEVENT Select L/H counter. Do not set this bit if UNIFY = 1.

  • Page 131: Sct Output Set Registers 0 To 3

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C (EV5_CTRL)) bit description Symbol Value Description Reset value 22:21 DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode.

  • Page 132: Functional Description

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.7 Functional description 10.7.1 Match logic &RXQWHU + 0DWFK 0DWFK 5HORDG 0DWFK L + 5HJ L + 81,)< 0DWFK 0DWFK 5HORDG 0DWFK L / 5HJ L / &RXQWHU / Fig 10. Match logic 10.7.2 Capture logic...

  • Page 133: Output Generation

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) + PDWFKHV VHOHFW / PDWFKHV 0$7&+6(/L LQSXWV HYHQW ³L´ VHOHFW RXWSXWV ,26(/L 2876(/L ,2&21'L &20%02'(L VHOHFW 67$7(0$6.L + 67$7( / 67$7( +(9(17L Fig 12. Event selection 10.7.4 Output generation Figure 13 shows one output slice of the SCT.

  • Page 134: Clearing The Prescaler

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.7.6 Clearing the prescaler When enabled by a non-zero PRE field in the Control register, the prescaler acts as a clock divider for the counter, like a fractional part of the counter value. The prescaler is...

  • Page 135: Sct Operation

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.7.8 SCT operation In its simplest, single-state configuration, the SCT operates as an event controlled one- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior.

  • Page 136: Configure Events And Event Responses

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.7.9.3 Configure events and event responses 1. Define when each event can occur in the following way in the EVn_CTRL registers (up to 6, one register per event): – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE.

  • Page 137: Configure Multiple States

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) 10.7.9.4 Configure multiple states 1. In the EVn_STATE register for each event (up to 6 events, one register per event), select the state or states (up to 2) in which this event is allowed to occur. Each state can be selected for more than one event.

  • Page 138: Configure The Sct Without Using States

    UM10601 NXP Semiconductors Chapter 10: LPC800 State Configurable Timer (SCT) The current state can be read at any time by reading the STATE register. To change the current state by software (that is independently of any event occurring), set the HALT bit and write to the STATE register to change the state value. Writing to the STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H bits are set) and no events can occur.

  • Page 139: How To Read This Chapter

    Chapter 11: LPC800 Multi-Rate Timer (MRT) Rev. 1.0 — 7 November 2012 Preliminary user manual 11.1 How to read this chapter The MRT is available on all LPC800 parts. 11.2 Features 24-bit interrupt timer • Four channels independently counting down from individually set values •...

  • Page 140: Repeat Interrupt Mode

    UM10601 NXP Semiconductors Chapter 11: LPC800 Multi-Rate Timer (MRT) =(526 ,54  '(& ,54B*(1 7,0(5 ,179$/ &21752/ 67$7 &+$11(/ ,54>@ &+$11(/>@ Fig 15. MRT block diagram 11.5.1 Repeat interrupt mode The repeat interrupt mode generates repeated interrupts after a selected time interval.

  • Page 141: One-Shot Interrupt Mode

    UM10601 NXP Semiconductors Chapter 11: LPC800 Multi-Rate Timer (MRT) 11.5.2 One-shot interrupt mode The one-shot interrupt generates one interrupt after a one-time count. With this mode, you can generate a single interrupt at any point. This mode can be used to introduce a specific delay in a software task.

  • Page 142: Time Interval Register

    UM10601 NXP Semiconductors Chapter 11: LPC800 Multi-Rate Timer (MRT) Table 134. Register overview: MRT (base address 0x4000 4000) Name Access Address Description Reset value Reference offset INTVAL3 0x30 MRT3 Time interval value register. This value is Table 135 loaded into the TIMER3 register.

  • Page 143: Timer Register

    UM10601 NXP Semiconductors Chapter 11: LPC800 Multi-Rate Timer (MRT) 11.6.2 Timer register The timer register holds the current timer value. This register is read-only. Table 136. Timer register (TIMER[0:3], address 0x4000 4004 (TIMER0) to 0x4000 4034 (TIMER3)) bit description Symbol Description...

  • Page 144: Status Register

    UM10601 NXP Semiconductors Chapter 11: LPC800 Multi-Rate Timer (MRT) 11.6.4 Status register This register indicates the status of each MRT. Table 138. Status register (STAT[0:3], address 0x4000 400C (STAT0) to 0x4000 403C (STAT3)) bit description Symbol Value Description Reset value INTFLAG Monitors the interrupt flag.

  • Page 145: Global Interrupt Flag Register

    UM10601 NXP Semiconductors Chapter 11: LPC800 Multi-Rate Timer (MRT) 11.6.6 Global interrupt flag register The global interrupt register combines the interrupt flags from the individual timer channels in one register. Setting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers.

  • Page 146: Chapter 12: Lpc800 Windowed Watchdog Timer (Wwdt)

    Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Rev. 1.0 — 7 November 2012 Preliminary user manual 12.1 How to read this chapter The watchdog timer is identical on all LPC800 parts. 12.2 Features Internally resets chip if not reloaded during the programmable time-out period. •...

  • Page 147: General Description

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 12.5 General description The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state. When enabled, a watchdog reset is generated if the user program fails to feed (reload) the Watchdog within a predetermined amount of time.

  • Page 148: Clocking And Power Control

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 7& IHHG RN ZGBFON HQDEOH FRXQW · ELW GRZQ FRXQWHU :'79 )((' :,1'2: UDQJH IHHG VHTXHQFH FRPSDUH GHWHFW DQG :',179$/ SURWHFWLRQ FRPSDUH FRPSDUH IHHG HUURU XQGHUIORZ LQWHUUXSW FRPSDUH VKDGRZ ELW IHHG RN :'3527(&7...

  • Page 149: Using The Wwdt Lock Features

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 12.5.3 Using the WWDT lock features The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times: • Disabling the WWDT clock source Changing the WWDT reload value •...

  • Page 150: Register Description

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 12.6 Register description The Watchdog Timer contains the registers shown in Table 141. The reset value reflects the data stored in used bits only. It does not include the content of reserved bits.
  • Page 151 UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description Symbol Value Description Reset value WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.

  • Page 152: Watchdog Timer Constant Register

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Table 143. Watchdog operating modes selection WDEN WDRESET Mode of Operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.

  • Page 153: Watchdog Timer Value Register

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Table 145. Watchdog Feed register (FEED - 0x4000 4008) bit description Symbol Description Reset Value FEED Feed value should be 0xAA followed by 0x55. 31:8 Reserved, user software should not write ones to reserved bits.

  • Page 154: Functional Description

    UM10601 NXP Semiconductors Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Table 148. Watchdog Timer Window register (WINDOW - 0x4000 4018) bit description Symbol Description Reset Value 23:0 WINDOW Watchdog window value. 0xFF FFFF 31:24 - Reserved, user software should not write ones to reserved bits.

  • Page 155: Chapter 13: Lpc800 Analog Comparator

    Rev. 1.0 — 7 November 2012 Preliminary user manual 13.1 How to read this chapter The analog comparator is available on all LPC800 parts. 13.2 Features Selectable external inputs can be used as either the positive or negative input of the •...

  • Page 156: Pin Description

    Section 9.3.1 “Connect an internal signal to a package pin” to assign the analog comparator output to any pin on the LPC800 package. Section 9.3.2 to enable the analog comparator inputs and the reference voltage input.

  • Page 157: Reference Voltages

    UM10601 NXP Semiconductors Chapter 13: LPC800 Analog comparator H[W 9''&03 /$'5() /$'(1 Q$&203B3' 92/7$*( /$''(5 287 &203B93B6(/ /$'6(/ $&203B3' &20367$7 $&03B, $&03B, QF WR $&03B2 +<6 LQWHUQDO 9 %$1'*$3 &2036$ 6<1& &203B90B6(/ &203('*( ('*(6(/ WR ,17(55837 $&203B567B1  2)  ('*(&/5 RU...

  • Page 158: Comparator Outputs

    UM10601 NXP Semiconductors Chapter 13: LPC800 Analog comparator 13.5.4 Comparator outputs The comparator output (conditioned by COMPSA bit) can be routed to an external pin. When COMPSA is 0 and the comparator interrupt is disabled, the comparator can be used with the bus clock disabled (Table 18 “System clock control register...
  • Page 159 UM10601 NXP Semiconductors Chapter 13: LPC800 Analog comparator Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description Symbol Value Description Reset value 10:8 COMP_VP_SEL Selects positive voltage input Voltage ladder output ACMP_I1 ACMP_I2 Reserved Reserved Reserved Internal reference voltage...

  • Page 160: Voltage Ladder Register

    UM10601 NXP Semiconductors Chapter 13: LPC800 Analog comparator 13.6.2 Voltage ladder register This register enables and controls the voltage ladder. The fraction of the reference voltage produced by the ladder is programmable in steps of 1/31. Table 152. Voltage ladder register (LAD, address 0x4002 4004) bit description...

  • Page 161: Chapter 14: Lpc800 Self Wake-Up Timer (Wkt)

    Chapter 14: LPC800 Self wake-up timer (WKT) Rev. 1.0 — 7 November 2012 Preliminary user manual 14.1 How to read this chapter The self wake-up timer is available on all LPC800 parts. 14.2 Features 32-bit loadable down-counter. Counter starts automatically when a count value is •...

  • Page 162: Register Description

    UM10601 NXP Semiconductors Chapter 14: LPC800 Self wake-up timer (WKT) A 10 kHz, low-power clock with a dedicated on-chip oscillator as clock source. • The IRC-derived clock is much more accurate than the alternative, low-power clock. However, the IRC is not available in most low-power modes. This clock must not be selected when the timer is being used to wake up from a power mode where the IRC is disabled.

  • Page 163: Count Register

    UM10601 NXP Semiconductors Chapter 14: LPC800 Self wake-up timer (WKT) Table 154. Control register (CTRL, address 0x4000 8000) bit description Symbol Value Description Reset value ALARMFLAG Wake-up or alarm timer flag. No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.

  • Page 164: Chapter 15: Lpc800 Usart0/1/2

    USART0 and USART1 are available on all parts. USART2 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only. Read this chapter for a description of the USART peripheral and the software interface. The LPC800 also provides an on-chip ROM-based USART API to configure and operate the USART. See Table 271.

  • Page 165: Configure The Usart Clock And Baud Rate

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Enable or disable the USART0/1/2 interrupts in slots #3 to 5 in the NVIC. • Configure the USART0/1/2 pin functions through the switch matrix. See Section 15.4. • Configure the USART clock and baud rate. See Section 15.3.1.

  • Page 166: Configure The Usart For Wake-Up

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 6<6&21 EORFN 8B3&/. 8$57&/.',9   08/7',9 PDLQ FORFN 8$57&/.',9 8$57)5*$'' 86$57 8$57)5*',9 86$57 8B6&/. %$8'6(5,$/ &/2&. *(1(5$725 86$57 86$57 8B6&/. %$8'6(5,$/ &/2&. *(1(5$725 86$57 86$57 8B6&/. %$8'6(5,$/ &/2&. *(1(5$725 Fig 21. USART clocking For details on the clock configuration see: Section 15.7.1 “Clocking and Baud rates”...

  • Page 167: Wake-Up From Deep-Sleep Or Power-Down Mode

    The USART receive, transmit, and control signals are movable functions and are assigned to external pins through the switch matrix. Section 9.3.1 “Connect an internal signal to a package pin” to assign the USART functions to pins on the LPC800 package. Table 156. USART pin description Function Direction Pin...

  • Page 168: General Description

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 156. USART pin description Function Direction Pin Description SWM register Reference U0_SCLK Serial clock input/output for USART0 in synchronous mode. PINASSIGN1 Table 97 Clock input or output in synchronous mode. If connected to a pin in asynchronous mode, will output the baud rate clock if the SYNCMST bit in CFG register is set to 1.
  • Page 169 UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 6<6&21 EORFN 7UDQVPLWWHU 7UDQVPLWWHU 7UDQVPLWWHU 8B3&/. 8B7;' PDLQ FORFN 8$57&/.',9 +ROGLQJ 6KLIW 5HJLVWHU 5HJLVWHU 6&/. 8QB6&/. 6&/. %DXG 5DWH DQG &ORFNLQJ *HQHUDWLRQ 8QB&76 ,QWHUUXSW *HQHUDWLRQ 6WDWXV 8QB576 86$57 LQWHUUXSW )ORZ &RQWURO  %UHDN SDULW\...

  • Page 170: Register Description

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 15.6 Register description The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Table 157: Register overview: USART (base address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000...

  • Page 171: Usart Configuration Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 15.6.1 USART Configuration register The CFG register contains communication and mode settings for aspects of the USART that would normally be configured once in an application. Remark: If software needs to change configuration values, the following sequence should be used: 1) Make sure the USART is not currently sending or receiving data.

  • Page 172: Usart Control Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) bit description …continued Symbol Value Description Reset Value CTSEN CTS Enable. Determines whether CTS is used for flow control.
  • Page 173 UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 159. USART Control register (CTRL, address 0x4006 4004 (USART0), 0x4006 8004 (USART1), 0x4006 C004 (USART2)) bit description Symbol Value Description Reset Value Reserved. Read value is undefined, only zero should be written.

  • Page 174: Usart Status Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 15.6.3 USART Status register The STAT register primarily provides a complete set of USART status flags for software to read. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT.

  • Page 175: Usart Interrupt Enable Read And Set Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006 C008(USART2)) bit description Symbol Description Reset Acces value FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location.

  • Page 176: Usart Interrupt Enable Clear Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description Symbol Description Reset Value 10:9 Reserved. Read value is undefined, only zero should be written.

  • Page 177: Usart Receiver Data Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006 4010(USART0), 0x4006 8010 (USART1), 0x4006 C010(USART2)) bit description Symbol Description Reset Value STARTCLR Writing 1 clears the corresponding bit in the INTENSET register.

  • Page 178: Usart Transmitter Data Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018 (USART0), 0x4006 8018 (USART1), 0x4006 C018 (USART2)) bit description Symbol Description Reset Value PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character.

  • Page 179: Usart Baud Rate Generator Register

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 15.6.9 USART Baud Rate Generator register The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register. The BRG register contains the value used to divide the base clock in order to produce the clock used for USART internal operations.

  • Page 180: Functional Description

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0), 0x4006 8024 (USART1), 0x4006 C024(USART2)) bit description Symbol Description Reset Value Reserved. Read value is undefined, only zero should be written. DELTACTS This bit is set when a change in the state of the CTS input is detected.

  • Page 181: Baud Rate Generator (Brg)

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 The base clock produced by the FRG cannot be perfectly symmetrical, so the FRG distributes the output clocks as evenly as is practical. Since the USART normally uses 16x overclocking, the jitter in the fractional rate clock in these cases tends to disappear in the ultimate USART output.

  • Page 182: Software Flow Control

    UM10601 NXP Semiconductors Chapter 15: LPC800 USART0/1/2 67$7 >&76@ FKDQJH GHWHFW 67$7 >'(/7$&76@ &)* >/223@ &)* >&76(1@ 8QB&76 7UDQVPLWWHU 8QB576 5HFHLYHU Fig 23. Hardware flow control using RTS and CTS 15.7.3.2 Software flow control Software flow control could include XON / XOFF flow control, or other mechanisms. these...

  • Page 183: How To Read This Chapter

    Read this chapter if you want to understand the I2C operation and the software interface and want to learn how to use the I2C for wake-up from reduced power modes. The LPC800 provides an on-chip ROM-based I2C API to configure and operate the I2C. Table 250 “I2C API calls”.

  • Page 184: Pin Description

    Chapter 16: LPC800 I2C-bus interface 16.4 Pin description The I2C pins are movable pin functions and are assigned to pins on the LPC800 packages through the switch matrix. You have two choices to connect the I2C pins: 1. Connect to special I2C open-drain pins (PIO0_10 and PIO0_11).

  • Page 185: Register Description

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface 0RQLWRU IXQFWLRQ 7LPLQJ & PDVWHU 6&/ JHQH UDWLRQ IXQFWLRQ RXWSXW ORJL F & VODYH IXQFWLRQ ,&B6'$ 7LPHRXW ,&B6&/ &)*>/223@ Fig 25. I2C block diagram 16.6 Register description The register functionalities can be grouped as follows: •...
  • Page 186 UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 181 “Master Data register (MSTDAT, address 0x4005 0028) bit description” – Slave function registers: • Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description” – Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description”...

  • Page 187: I2C Configuration Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 169: Register overview: I2C (base address 0x4005 0000) Name Access Offset Description Reset Reference value 0x00 Configuration for shared functions. Table 170 STAT 0x04 Status register for Master, Slave, and Monitor functions.
  • Page 188 UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description Symbol Value Description Reset Value MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.

  • Page 189: I2C Status Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface 16.6.2 I2C Status register The STAT register provides status flags and state information about all of the functions of the I C block. Some information in this register is read-only, some flags can be cleared by writing a 1 to them.
  • Page 190 UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 171. I C Status register (STAT, address 0x4005 0004) bit description …continued Symbol Value Description Reset Acce value Reserved. Read value is undefined, only zero should be written. SLVPENDING Slave Pending. Indicates whether the Slave function needs software service.
  • Page 191 UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 171. I C Status register (STAT, address 0x4005 0004) bit description …continued Symbol Value Description Reset Acce value SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET.
  • Page 192 UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 172: Master function state codes (MSTSTATE) MstState Description Actions Idle. The Master function is available to be used for a new Send a Start or disable MstPending interrupt if transaction. the Master function is not needed currently.

  • Page 193: Interrupt Enable Set And Read Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface 16.6.3 Interrupt Enable Set and read register The INTENSET register controls which I C status flags generate interrupts. Writing a 1 to a bit position in this register enables an interrupt in the corresponding position in the STAT register, if an interrupt is supported there.

  • Page 194: Interrupt Enable Clear Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit description Symbol Value Description Reset value MONIDLEEN Monitor Idle interrupt Enable. The MonIdle interrupt is disabled. The MonIdle interrupt is enabled.

  • Page 195: Time-Out Value Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 175. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description …continued Symbol Description Reset value SLVDESELCLR Slave Deselect interrupt clear. MONRDYCLR Monitor data Ready interrupt clear. MONOVCLR Monitor Overrun interrupt clear.

  • Page 196: I2C Clock Divider Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 176. time-out register (TIMEOUT, address 0x4005 0010) bit description Symbol Description Reset value TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I...

  • Page 197: Master Control Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 178. I C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description Symbol Description Reset value MSTPENDING Master Pending. Reserved. MSTARBLOSS Master Arbitration Loss flag. Reserved. Read value is undefined, only zero should be written.

  • Page 198: Master Time

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description Bit Symbol Value Description Reset value MSTSTOP Master Stop control. This bit is write-only. No effect. Stop. A Stop will be generated on the I...

  • Page 199: Master Data Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description …continued Symbol Value Description Reset value MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time.

  • Page 200: Slave Data Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 182. Slave Control register (SLVCTL, address 0x4005 0040) bit description Symbol Value Description Reset Value SlvContinue Slave Continue. No effect. Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.

  • Page 201: Slave Address Registers

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface 16.6.13 Slave Address registers The SLVADR[0:3] registers allow enabling and defining one of the addresses that can be automatically recognized by the I C slave hardware. The value in the SLVADR0 register is qualified by the setting of the SLVQUAL0 register.

  • Page 202: Monitor Data Register

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 185. Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit description Symbol Value Description Reset Value QUALMODE0 Reserved. Read value is undefined, only zero should be written. The SLVQUAL0 field is used as a logical mask for matching address 0.

  • Page 203: Functional Description

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description Symbol Value Description Reset value MONRESTART Monitor Received Repeated Start. No start detect. The monitor function has not detected a Repeated Start event on the I C bus.

  • Page 204: Ten-Bit Addressing

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface any of these events is longer than the time configured in the TIMEOUT register. This time-out could be useful in monitoring an I C bus within a system as part of a method to keep the bus running of problems occur.

  • Page 205: Lnterrupts

    UM10601 NXP Semiconductors Chapter 16: LPC800 I2C-bus interface 16.7.5 lnterrupts The I2C provides a single interrupt output that handles all interrupts for Master, Slave, and Monitor functions. UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

  • Page 206: Chapter 17: Lpc800 Spi0/1

    UM10601 Chapter 17: LPC800 SPI0/1 Rev. 1.0 — 7 November 2012 Preliminary user manual 17.1 How to read this chapter SPI0 is available on all parts. SPI1 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only. 17.2 Features • Data frames of 1 to 16 bits supported directly. Larger frames supported by software.

  • Page 207: Wake-Up From Sleep Mode

    Section 9.3.1 “Connect an internal signal to a package pin” to assign the SPI functions to pins on the LPC800 package. UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
  • Page 208 UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 Table 187: SPI Pin Description Function Direct Pin Description SWM register Reference SPI0_SCK any Serial Clock. SCK is a clock signal used to synchronize the PINASSIGN3 Table 99 transfer of data. It is driven by the master and received by the slave.

  • Page 209: General Description

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.5 General description 7[ 6KLIW 5HJL VWHU 63,QB7;'$7 6&. 6WDWH 0DFKLQH LQWHUUXSWV 026, 63, LQWHUUXSW ,QWHUUXSW FRQWURO *HQHUDO FRQWUROV 0,62 IRUPDW FRQILJXUDWLRQV LQWHUUXSWV 5[ 6KLIW 5HJL VWHU 63,QB5;'$7 6WDWH 0DFKLQH 66(/ SLQ OHYHOV...
  • Page 210 UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1)) …continued Name Access Offset Description Reset Reference value INTENSET 0x00C SPI Interrupt Enable read and Set. A Table 192 complete value may be read from this register.

  • Page 211: Spi Configuration Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.6.1 SPI Configuration register The CFG register contains information for the general configuration of the SPI. Typically, this information is not changed during operation. Some configurations, such as CPOL, CPHA, and LSBF should not be made while the SPI is not fully idle. See the description of...

  • Page 212: Spi Delay Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.6.2 SPI Delay register The DLY register controls several programmable delays related to SPI signalling. These delays apply only to master mode, and are all stated in SPI clocks. Timing details are shown in: Section 17.7.2.1 “Pre_delay and Post_delay”...

  • Page 213: Spi Status Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.6.3 SPI Status register The STAT register provides SPI status flags for software to read, and a control bit for forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT.
  • Page 214 UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 RO = Read-only, W1 = write 1 to clear. 17.6.4 SPI Interrupt Enable read and Set register The INTENSET register is used to enable various SPI interrupt sources. Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register. The complete set of interrupt enables may be read from this register.

  • Page 215: Spi Interrupt Enable Clear Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.6.5 SPI Interrupt Enable Clear register The INTENCLR register is used to clear interrupt enable bits in the INTENSET register. Table 193. SPI Interrupt Enable clear register (INTENCLR, addresses 0x4005 8010 (SPI0) ,...

  • Page 216: Spi Transmitter Data And Control Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.6.7 SPI Transmitter Data and Control register The TXDATCTL register provides a location where both transmit data and control information can be written simultaneously. This allows detailed control of the SPI without a separate write of control information for each piece of data.

  • Page 217: Spi Transmitter Data Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018 (SPI1)) bit description …continued Symbol Value Description Reset value Reserved. Read value is undefined, only zero should be written.

  • Page 218: Spi Divider Register

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 Table 197. SPI Transmitter Control register (TXCTL, addresses 0x4005 8020 (SPI0) , 0x4005 C020 (SPI1)) bit description Symbol Description Reset value 15:0 Reserved. Read value is undefined, only zero should be written. NA TX SSEL Transmit Slave Select.
  • Page 219 UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005 C028 (SPI1)) bit description Symbol Description Reset value Slave Select Assert. Slave Select Deassert. 31:6 Reserved. Read value is undefined, only zero should be written.

  • Page 220: Functional Description

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.7 Functional description 17.7.1 Operating modes: clock and phase selection SPI interfaces typically allow configuration of clock phase and polarity. These are sometimes referred to as numbered SPI modes, as described in Table 200...

  • Page 221: Operating Modes: Clock And Phase Selection 220 Frame Delays

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.7.2 Frame delays Several delays can be specified for SPI frames. These include: Pre_delay: delay after SSEL is asserted before data clocking begins • Post_delay: delay at the end of a data frame before SSEL is deasserted •...

  • Page 222: Frame_Delay

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.7.2.2 Frame_delay The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure Note that frame boundaries occur only where specified.

  • Page 223: Transfer_Delay

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.7.2.3 Transfer_delay The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be deasserted for a minimum of one SPI clock time. Transfer_delay is illustrated by the...

  • Page 224: Clocking And Data Rates

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.7.3 Clocking and data rates In order to use the SPI, clocking details must be defined. This includes configuring the system clock and selection of the clock divider value in DIV. See Figure 17.7.3.1 Data rate calculations...

  • Page 225: Data Stalls

    UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 17.7.6 Data stalls A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be returned to the rest state until the MSB of the next data frame can be driven on MOSI. In this case, the stall happens just before the final clock edge of data if the next piece of data is not yet available.
  • Page 226 UM10601 NXP Semiconductors Chapter 17: LPC800 SPI0/1 7UDQVPLWWHU VWDOO &3+$  )UDPH BGHOD\  3UHBGHOD\  3RVWBGHOD\   FORFN VWDOO 0RGH  &32/ 6&. 0RGH  &32/ 6&. 026, 0,62 )LUVW GDWD IUDPH 6HFRQG GDWD IUDPH 5HFHLYHU VWDOO &3+$...

  • Page 227: Chapter 18: Lpc800 Cyclic Redundancy Check (Crc) Engine

    Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine Rev. 1.0 — 7 November 2012 Preliminary user manual 18.1 How to read this chapter The CRC engine is available on all LPC800 parts. 18.2 Features Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. •...

  • Page 228: Description

    UM10601 NXP Semiconductors Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine 18.6 Description &5 & 02'( &5 & 6((' &&,7 7 &5& , ' 32/< 08 ; &203 5(9(56( &5&  &5 & 08 ; 32/< 08 ; &203 5(9(56( &5&...

  • Page 229: Crc Mode Register

    UM10601 NXP Semiconductors Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine 18.7.1 CRC mode register Table 202. CRC mode register (MODE, address 0x5000 0000) bit description Symbol Description Reset value CRC_POLY CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial...
  • Page 230 UM10601 NXP Semiconductors Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine Table 205. CRC data register (WR_DATA, address 0x5000 0008) bit description Symbol Description Reset value 31:0 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1’s complement pre-process.

  • Page 231: Functional Description

    UM10601 NXP Semiconductors Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine 18.8 Functional description The following sections describe the register settings for each supported CRC standard: 18.8.1 CRC-CCITT set-up Polynomial = x Seed Value = 0xFFFF Bit order reverse for data input: NO...

  • Page 232: How To Read This Chapter

    Chapter 19: LPC800 Flash controller Rev. 1.0 — 7 November 2012 Preliminary user manual 19.1 How to read this chapter The flash controller is identical on all LPC800 parts. 19.2 Features Controls flash access time. • Provides registers for flash signature generation.

  • Page 233: Flash Signature Start Address Register

    UM10601 NXP Semiconductors Chapter 19: LPC800 Flash controller Table 207. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description Symbol Value Description Reset value FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.

  • Page 234: Functional Description

    UM10601 NXP Semiconductors Chapter 19: LPC800 Flash controller Table 210. FMSW0 register bit description (FMSW0, address: 0x4003 C02C) Symbol Description Reset value 31:0 32-bit signature. 19.5 Functional description 19.5.1 Flash signature generation The flash module contains a built-in signature generator. This generator can produce a 32-bit signature from a range of flash memory.

  • Page 235: Content Verification

    UM10601 NXP Semiconductors Chapter 19: LPC800 Flash controller When signature generation is triggered via software, the duration is in AHB clock cycles, and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete.

  • Page 236: How To Read This Chapter

    Chapter 20: LPC800 Boot ROM Rev. 1.0 — 7 November 2012 Preliminary user manual 20.1 How to read this chapter The Boot ROM is identical for all LPC800 parts. 20.2 Features 8 kB on-chip boot ROM • Contains the boot loader with In-System Programming (ISP) facility and the following •...

  • Page 237: Rom-Based Apis

    UM10601 NXP Semiconductors Chapter 20: LPC800 Boot ROM 20.3.2 ROM-based APIs Once the part has booted, the user can access several APIs located in the boot ROM to access the flash memory, optimize power consumption, and operate the USART and I2C peripherals.

  • Page 238: Functional Description

    The host should respond by sending the crystal frequency (in kHz) at which the part is running. The response is required for backward compatibility of the boot loader code and, on the LPC800, is ignored. The boot loader configures the part to run at the 12 MHz IRC frequency.

  • Page 239: Boot Process Flowchart

    UM10601 NXP Semiconductors Chapter 20: LPC800 Boot ROM 20.4.4 Boot process flowchart 5(6(7 ,1,7,$/,=( &53 (1$%/('" (1$%/( '(%8* :$7&+'2* )/$* 6(7" 86(5 &2'( 9$/,'" &5312B,63 (1$%/('" (17(5 ,63 (;(&87( ,17(51$/ 02'(" 86(5 &2'( 3,2B /2: 86(5 &2'( ERRW IURP 9$/,'"...

  • Page 240: Chapter 21: Lpc800 Flash Isp And Iap Programming

    UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Rev. 1.0 — 7 November 2012 Preliminary user manual 21.1 How to read this chapter Table 212 for different flash configurations. Table 212. LPC800 flash configurations Type number Flash LPC810M021FN8 4 kB...

  • Page 241: Flash Content Protection Mechanism

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 213. LPC800 flash configuration Sector Sector Page Address range 4 kB 8 kB 16 kB number size number [kB] 96 - 111 0x0000 1800 - 0x0000 1BFF 112 - 127...
  • Page 242 UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Important: any CRP change becomes effective only after the device has gone through a power cycle. Table 214. Code Read Protection options Name Pattern Description programmed in 0x0000 02FC...

  • Page 243: Isp Entry Protection

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 216. ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 (no entry in ISP mode allowed) Unlock Set Baud Rate Echo Write to RAM yes; above 0x1000 0300...

  • Page 244: Unlock

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 217. UART ISP command summary ISP Command Usage Described in Unlock U <Unlock Code> Table 218 Set Baud Rate B <Baud Rate> <stop bit> Table 219 Echo A <setting>...

  • Page 245: Echo

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.4.1.3 Echo <setting> Table 220. UART ISP Echo command Command Input Setting: ON = 1 | OFF = 0 Return Code CMD_SUCCESS | PARAM_ERROR Description The default setting for echo command is ON. When ON the ISP command handler sends the received serial data back to the host.

  • Page 246: Prepare Sector(S) For Write Operation

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 222. UART ISP Read Memory command Command Input Start Address: Address from where data bytes are to be read. This address should be a word boundary. Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.

  • Page 247: Go

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 224. UART ISP Copy RAM to flash command Command Input Flash Address (DST): Destination flash address where data bytes are to be written. The destination address should be a 64 byte boundary.

  • Page 248: Erase Sector(S)

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.4.1.9 Erase sector(s) <start sector number> <end sector number> Table 226. UART ISP Erase sector command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.

  • Page 249: Read Boot Code Version Number

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 229. Part identification numbers Device Hex coding LPC810M021FN8 0x0000 8100 LPC811M001FDH16 0x0000 8110 LPC812M101FDH16 0x0000 8120 LPC812M101FD20 0x0000 8121 LPC812M101FDH20 0x0000 8122 21.4.1.12 Read Boot code version number Table 230.

  • Page 250: Uart Isp Return Codes

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.4.1.15 UART ISP Return Codes Table 233. UART ISP Return Codes Summary Return Mnemonic Description Code CMD_SUCCESS Command is executed successfully. Sent by ISP handler only when command given by the host has been completely and successfully executed.
  • Page 251 UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming command handler sends the status code INVALID_COMMAND when an undefined command is received. The IAP routine resides at 0x1FFF 1FF0 location and it is thumb code. The IAP function could be called in the following way using C.
  • Page 252 UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 234. IAP Command Summary IAP Command Command Code Described in Prepare sector(s) for write operation 50 (decimal) Table 235 Copy RAM to flash 51 (decimal) Table 236 Erase sector(s)

  • Page 253: Prepare Sector(S) For Write Operation (Iap) . 252 Copy Ram To Flash (Iap)

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 235. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Return Code CMD_SUCCESS | BUSY | INVALID_SECTOR Result None Description This command must be executed before executing "Copy RAM to flash" or "Erase Sector(s)"...

  • Page 254: Erase Sector(S) (Iap)

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.4.2.3 Erase Sector(s) (IAP) Table 237. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 52 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).

  • Page 255: Read Boot Code Version Number (Iap)

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.4.2.6 Read Boot code version number (IAP) Table 240. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 55 (decimal) Parameters: None...

  • Page 256: (Iap)

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.4.2.8 Reinvoke ISP (IAP) Table 242. IAP Reinvoke ISP Command Compare Input Command code: 57 (decimal) Return Code None Result None. Description This command is used to invoke the bootloader in ISP mode. It maps boot vectors, sets PCLK = CCLK, and configures USART0 pins U0_RXD and U0_TXD.

  • Page 257: Functional Description

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming Table 245. IAP Status Codes Summary Status Mnemonic Description Code SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken in to consideration where applicable.

  • Page 258: Interrupts During Iap

    UM10601 NXP Semiconductors Chapter 21: LPC800 Flash ISP and IAP programming 21.5.2.2 Interrupts during IAP The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active.

  • Page 259: How To Read This Chapter

    Chapter 22: LPC800 Power profile API ROM driver Rev. 1.0 — 7 November 2012 Preliminary user manual 22.1 How to read this chapter The power profiles are available for all LPC800 parts. 22.2 Features Includes ROM-based application services • Power Management services •...

  • Page 260: Api Description

    V\VBRVFBFON 6<6 3// V\VBSOOFONLQ &/.,1 6<63//&/.6(/ Fig 38. LPC800 clock configuration for power API use 22.4 API description The power profile API provides functions to configure the system clock and optimize the system setting for lowest power consumption. UM10601 All information provided in this document is subject to legal disclaimers.

  • Page 261: Set_Pll

    UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver Table 247. Power profile API calls API call Description Reference set_pll(command, result) Power API set pll routine Table 248 set_power(command, result) Power API set power routine Table 249 The following elements have to be defined in an application that uses the power profiles: typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]);...

  • Page 262: Param0: System Pll Input Frequency And Param1: Expected System Clock

    UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver #define CPU_FREQ_EQU #define CPU_FREQ_LTE #define CPU_FREQ_GTE #define CPU_FREQ_APPROX /* set_pll result0 options */ #define PLL_CMD_SUCCESS #define PLL_INVALID_FREQ #define PLL_INVALID_MODE #define PLL_FREQ_NOT_FOUND #define PLL_NOT_LOCKED For a simplified clock configuration scheme see Figure 38.

  • Page 263: Param3: System Pll Lock Time-Out

    UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver 22.4.1.3 Param3: system PLL lock time-out It should take no more than 100 s for the system PLL to lock if a valid configuration is selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. A non-zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL_NOT_LOCKED.
  • Page 264 UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver XVLQJ SRZHU SURILOHV DQG FKDQJLQJ V\VWHP FORFN FXUUHQWBFORFN QHZBFORFN  QHZBPRGH XVH SRZHU URXWLQH FDOO WR FKDQJH PRGH WR '()$8/7 XVH HLWKHU FORFNLQJ URXWLQH FDOO RU FXVWRP FRGH WR FKDQJH V\VWHP FORFN...

  • Page 265: Param0: Main Clock

    UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver For a simplified clock configuration scheme see Figure 38. For more details see Figure 22.4.2.1 Param0: main clock The main clock is the clock rate the microcontroller uses to source the system’s and the peripherals’...

  • Page 266: Invalid Frequency Selection (System Clock Divider Restrictions)

    UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver 22.5.1.2 Invalid frequency selection (system clock divider restrictions) command[0] = 12000; command[1] = 40; command[2] = CPU_FREQ_LTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40 kHz and no time-out while waiting for the PLL to lock.

  • Page 267: System Clock Approximately Equal To The Expected Value

    UM10601 NXP Semiconductors Chapter 22: LPC800 Power profile API ROM driver 22.5.1.6 System clock approximately equal to the expected value command[0] = 12000; command[1] = 16500; command[2] = CPU_FREQ_APPROX; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of approximately 16.5 MHz and no locking time-out.

  • Page 268: How To Read This Chapter

    Chapter 23: LPC800 I2C-bus ROM API Rev. 1.0 — 7 November 2012 Preliminary user manual 23.1 How to read this chapter The I2C-bus ROM API is available on all LPC800 parts. 23.2 Features Simple I2C drivers to send and receive data on the I2C-bus. •...

  • Page 269: Api Description

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API ,& GULYHU URXWLQHV IXQFWLRQ WDEOH LFBLVUBKDQGOHU 3WU WR 520 'ULYHU WDEOH LFBPDVWHUBWUDQVPLWBSROO [))) )) VLGLYPRG LFBJHWBVWDWXV XLGLYPRG VLGLYPRG 520 'ULYHU 7DEOH XLGLYPRG [ 3WU WR 'HYLFH 7DEOH  [ 3WU WR 'HYLFH 7DEOH ...
  • Page 270 UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API Table 250. I2C API calls API call Description Reference ErrorCode_t i2c_slave_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C Slave Receive Polling Table 258 I2C_RESULT*) ErrorCode_t i2c_slave_transmit_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C Slave Transmit Polling Table 259...

  • Page 271: Isr Handler

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API I2C_HANDLE_T* (*i2c_setup)(uint32_t i2c_base_addr, uint32_t *start_of_ram ) ; ErrorCode_t (*i2c_set_bitrate)(I2C_HANDLE_T* h_i2c, uint32_t P_clk_in_hz, uint32_t bitrate_in_bps) ; uint32_t (*i2c_get_firmware_version)() ; I2C_MODE_T (*i2c_get_status)(I2C_HANDLE_T* h_i2c ) ; } I2CD_API_T ; 23.4.1 ISR handler Table 251. ISR handler...

  • Page 272: I2C Master Transmit And Receive Polling

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API 23.4.4 I2C Master Transmit and Receive Polling Table 254. I2C Master Transmit and Receive Polling Routine I2C Master Transmit and Receive Polling Prototype ErrorCode_t i2c_master_tx_rx_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area.

  • Page 273: I2C Master Transmit Receive Interrupt

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API 23.4.7 I2C Master Transmit Receive Interrupt Table 257. I2C Master Transmit Receive Interrupt Routine I2C Master Transmit Receive Interrupt Prototype ErrorCode_t i2c_master_tx_rx_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area.

  • Page 274: I2C Slave Receive Interrupt

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API 23.4.10 I2C Slave Receive Interrupt Table 260. I2C Slave Receive Interrupt Routine I2C Slave Receive Interrupt Prototype ErrorCode_t i2c_slave_receive_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area.

  • Page 275: I2C Setup

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API Table 263. I2C Get Memory Size Routine I2C Get Memory Size Input parameter None. Return uint32. Description Returns the number of bytes in SRAM needed by the I2C driver. 23.4.14 I2C Setup Table 264.

  • Page 276: I2C Time-Out Value

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API 23.4.18 I2C time-out value Table 268. I2C time-out value Routine I2C time-out value Prototype ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. uint32_t timeout - time value is timeout*16 i2c function clock. If timeout = 0, timeout feature is disabled.

  • Page 277: Param And Result Structure

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API After the definition of the handle, the handle must be initialized with I2C base address and RAM reserved for the I2C ROM driver by making a call to the i2c_setup() function.

  • Page 278: I2C Mode

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API } ErrorCode_t; 23.4.24 I2C Mode The i2c_get_status() function returns the current status of the I2C engine. The return codes can be defined as an enum structure: typedef enum I2C_mode { IDLE,...

  • Page 279: I2C Slave Mode Set-Up

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API 1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size() function. 2. Create the I2C handle by making a call to the i2c_setup() function. 3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function.

  • Page 280: I2C Master Transmit/Receive

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API 23.5.4 I2C Master Transmit/Receive The Master mode drivers give the user the choice of either polled (wait for the message to finish) or interrupt driven routines (non-blocking). Polled routines are recommended for testing purposes or very simple I2C applications.

  • Page 281: I2C Slave Mode Transmit/Receive

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API In all the master mode routines, the transmit buffer’s first byte must be the slave address with the R/W bit set to “0”. To enable a master read, the receive buffer’s first byte must be the slave address with the R/W bit set to “1”.

  • Page 282: I2C Time-Out Feature

    UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API I2C_RESULT is a containing the results after the function executes. Section 23.4.22. • To initiate a master-mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly. The structure contains the following: Number of bytes to be transmitted.
  • Page 283 UM10601 NXP Semiconductors Chapter 23: LPC800 I2C-bus ROM API // Enable timeout feature h->i2c_base->CFG |= BI2C_TIMEOUT_EN; else // disable timeout feature h->i2c_base->CFG &= ~BI2C_TIMEOUT_EN; return(LPC_OK) ; }//i2c_set_timeout UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

  • Page 284: How To Read This Chapter

    Chapter 24: LPC800 USART API ROM driver routines Rev. 1.0 — 7 November 2012 Preliminary user manual 24.1 How to read this chapter The USART ROM driver routines are available on all LPC800 parts. 24.2 Features Send and receive characters in asynchronus UART mode •...

  • Page 285: Api Description

    UM10601 NXP Semiconductors Chapter 24: LPC800 USART API ROM driver routines 24.4 API description The UART API contains functions to send and receive characters via any of the USART blocks. Table 271. UART API calls API call Description Reference uint32_t ramsize_in_bytes uart_get_mem_size( void) ;...

  • Page 286: Uart Setup

    UM10601 NXP Semiconductors Chapter 24: LPC800 USART API ROM driver routines 24.4.2 UART setup Table 273. uart_setup Routine uart_setup Prototype UART_HANDLE_T* uart_setup(uint32_t base_addr, uint8_t *ram) ; Input parameter base_addr: Base address of register for this uart block. ram: Pointer to the memory space for uart instance. The size of the memory space can be obtained by the uart_get_mem_size function.

  • Page 287: Uart Get Line

    UM10601 NXP Semiconductors Chapter 24: LPC800 USART API ROM driver routines 24.4.6 UART get line Table 277. uart_get_line Routine uart_get_line Prototype uint32_t uart_get_line(UART_HANDLE_T* handle, UART_PARAM_T param); Input parameter handle: The handle to the uart instance. param: Refer to UART_PARAM_T definition.

  • Page 288: Uart Rom Driver Variables

    UM10601 NXP Semiconductors Chapter 24: LPC800 USART API ROM driver routines 24.4.10 UART ROM driver variables 24.4.10.1 UART_CONFIG structure Typdef struct UART_CONFIG { uint32_t sys_clk_in_hz; // Sytem clock in hz. uint32_t baudrate_in_hz; // Baudrate in hz uint8_t config; //bit1:0 // 00: 7 bits length, 01: 8 bits lenght, others: reserved...

  • Page 289: Functional Description

    UM10601 NXP Semiconductors Chapter 24: LPC800 USART API ROM driver routines // For uart_put_line function, transfer is stopped after // reaching \0. uint16_t driver_mode; //0x00: Polling mode, function is blocked until transfer is // finished. // 0x01: Intr mode, function exit immediately, callback function // is invoked when transfer is finished.

  • Page 290: How To Read This Chapter

    Chapter 25: LPC800 Debugging Rev. 1.0 — 7 November 2012 Preliminary user manual 25.1 How to read this chapter The debug functionality is identical for all LPC800 parts. 25.2 Features Supports ARM Serial Wire Debug mode. • Direct debug access to all memories, registers, and peripherals.

  • Page 291: Functional Description

    UM10601 NXP Semiconductors Chapter 25: LPC800 Debugging Table 282. JTAG boundary scan pin description Function Pin name Type Description SWCLK/PIO0_3/ JTAG Test Clock. This pin is the clock for JTAG boundary scan when the RESET pin is LOW. SWDIO/PIO0_2/ JTAG Test Mode Select. The TMS pin selects the next state in the TAP state machine.

  • Page 292: Boundary Scan

    UM10601 NXP Semiconductors Chapter 25: LPC800 Debugging /3& 975() 6:',2 6:',2 6:&/. 6:&/. 5(6(7 Q6567 3,2B ,63 HQWU\ The VTREF pin on the SWD connector enables the debug connector to match the target voltage. Fig 43. Connecting the SWD pins to a standard SWD connector 25.5.3 Boundary scan...

  • Page 293: Packages

    UM10601 Chapter 26: LPC800 Packages and pin description Rev. 1.0 — 7 November 2012 Preliminary user manual 26.1 Packages 5(6(73,2B 3,2B$&03B,7'2 3,2B:$.(837567 ',3 6:&/.3,2B7&. 6:',23,2B706 3,2B$&03B,&/.,17', DDD Fig 44. Pin configuration DIP8 package (LPC810M021FN8) 3,2B 3,2B$&03B,7'2 3,2B 3,2B9''&03 5(6(73,2B 3,2B /3&0)'+...

  • Page 294: Pin Description

    UM10601 NXP Semiconductors Chapter 26: LPC800 Packages and pin description 3,2B 3,2B 3,2B 3,2B$&03B,7'2 3,2B 3,2B9''&03 5(6(73,2B 3,2B /3&0)'+ 3,2B:$.(837567 76623 6:&/.3,2B7&. 6:',23,2B706 3,2B;7$/,1 3,2B 3,2B;7$/287 3,2B 3,2B$&03B,&/.,17', 3,2B 3,2B DDD Fig 47. Pin configuration TSSOP20 package 26.2 Pin description...
  • Page 295 UM10601 NXP Semiconductors Chapter 26: LPC800 Packages and pin description Table 283. Pin description table (fixed pins) Symbol Type Reset Description state PIO0_0/ACMP_I1/ I; PU PIO0_0 — General purpose digital input/output port 0 pin 0. In ISP mode, this is the USART0 receive pin U0_RXD.
  • Page 296 UM10601 NXP Semiconductors Chapter 26: LPC800 Packages and pin description Table 283. Pin description table (fixed pins) Symbol Type Reset Description state PIO0_11 PIO0_11 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification.
  • Page 297 UM10601 NXP Semiconductors Chapter 26: LPC800 Packages and pin description Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description U2_RXD Receiver input for USART2. U2_RTS Request To Send output for USART2. U2_CTS Clear To Send input for USART2.

  • Page 298: Abbreviations

    UM10601 Chapter 27: Supplementary information Rev. 1.0 — 7 November 2012 Preliminary user manual 27.1 Abbreviations Table 285. Abbreviations Acronym Description Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection GPIO General-Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface SMBus System Management Bus Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter...

  • Page 299: Legal Information

    NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, In no event shall NXP Semiconductors be liable for any indirect, incidental, damage, costs or problem which is based on any weakness or default in the punitive, special or consequential damages (including - without limitation - lost customer’s applications or products, or the application or use by customer’s...

  • Page 300: Tables

    UM10601 NXP Semiconductors Chapter 27: Supplementary information 27.4 Tables Table 1. Ordering information .....5 description ......29 Table 2.
  • Page 301 UM10601 NXP Semiconductors Chapter 27: Supplementary information Table 51. PIO0_12 register (PIO0_12, address 0x4004 Table 80. Pin interrupt mode register (ISEL, address 4008) bit description ....60 0xA000 4000) bit description .
  • Page 302 UM10601 NXP Semiconductors Chapter 27: Supplementary information 0x4000 C020) bit description ... . .108 (EV[0:5]_STATE, addresses 0x5000 4300 Table 105. Pin enable register 0 (PINENABLE0, address (EV0_STATE) to 0x5000 4328 (EV5_STATE)) bit 0x4000 C1C0) bit description .
  • Page 303 UM10601 NXP Semiconductors Chapter 27: Supplementary information bit description ......163 0010) bit description....196 Table 156.
  • Page 304 Table 264. I2C Setup ......275 Table 213. LPC800 flash configuration ....240 Table 265.

  • Page 305: Figures

    27.5 Figures Fig 1. LPC800 block diagram .....6 Fig 2. LPC800 Memory mapping ....9 Fig 3.

  • Page 306: Table Of Contents

    4.7.1.4.2 Power-down mode ..... 40 Chapter 5: LPC800 Reduced power modes and Power Management Unit (PMU) How to read this chapter ....41 General description .
  • Page 307 7.6.4 GPIO port mask registers ....78 Chapter 8: LPC800 Pin interrupts/pattern match engine 8.5.2.1 Example ......85 How to read this chapter .
  • Page 308 Pin enable register 0 ....108 Register description ....104 Chapter 10: LPC800 State Configurable Timer (SCT) 10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1) 10.1...
  • Page 309 11.6.2 Timer register ......143 Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 12.5.3.2 Changing the WWDT reload value ..149 12.1...
  • Page 310 17.6.6 SPI Receiver Data register ....215 Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine 18.7.1 CRC mode register ....229 18.1...
  • Page 311 Functional description ....238 Chapter 21: LPC800 Flash ISP and IAP programming 21.4.1.14 ReadUID ......249 21.1...
  • Page 312 23.4.16 I2C Get Firmware Version ....275 Chapter 24: LPC800 USART API ROM driver routines 24.4.6 UART get line......287 24.1...
  • Page 313 UM10601 NXP Semiconductors Chapter 27: Supplementary information Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com...

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