Toshiba PORTEGE R400 Maintenance Manual page 61

Table 2-4 Debug port (Boot mode) error status (3/10)
D port status
F100H
Micro code Update(
HTT Support model)
Prohibition of cache
L1/L2 Cache of Flash ROM area are
permitted.
Initialization of H/W (before DRAM
recognition)
Initialization of PIT channel 1
F101H
Check of DRAM type and size
(at cold boot)
SM-RAM stack area test
F102H
Cache configuration
Cache permission (L1/L2 Cache)
CMOS access test (at cold boot)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status
Storing DRAM size in CMOS
F103H
Resume branch (at cold boot)
PORTEGE R400 Maintenance Manual (960-623)
Inspection items
2 Troubleshooting Procedures
Details
Initialization of MCHM
I nitialization of ICH7M.D30.Func0
Initialization of ICH7M.D31.Func1
Initialization of ICH7M.D31.Func1/2
Initialization of
I USB Controller
Initialization of ICH7M.D31.Func3
Initialization of
TI Controller
(Setting the refresh interval to "30μs")
When unsupported memory is connected,
becoming HLT after beep sound (HLT when
DRAM size is 0)
HLT When it can not be used as a stack
(HLT when an error is detected)
(Setting of boot status and IRT busy flag, The rest
bits are 0)
Not resume when a CMOS error occurred
Not resume when resume status code is not set
Resume error check
S3 returning error (ICH)
Resume error F17A RSM_UNKNOWN_ERR
SM-RAM checksum check
Resume error F173H RSM_SMRAM_ERR
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