Quectel UC200T-EM Hardware Design page 38

PCM_CLK 27
I2C_SCL 41
I2C_SDA 42
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2] for more details about AT+QDAI command.
The following figure shows a reference design of PCM interface with external codec IC.
PCM_SYNC
PCM_OUT
Module
Figure 16: Reference Circuit of PCM Application with Audio Codec
NOTES
1. It is recommended to reserve an RC (R=22ohm, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. UC200T-EM works as a master device pertaining to I2C interface.
UC200T-EM_Hardware_Design
IO PCM data bit clock
OD I2C serial clock
OD I2C serial data
PCM_CLK
PCM_IN
I2C_SCL
I2C_SDA
1.8V
UMTS/HSPA(+) Module Series
UC200T-EM Hardware Design
1.8V power domain
Output when module works as
master mode
Intput when module works as
salve mode
If unused, keep it open.
Require external pull-up to 1.8V.
If unused, keep it open.
Require external pull-up to 1.8V.
If unused, keep it open.
MICBIAS
INP
BCLK
INN
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
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