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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
INTRODUCTION
This application note describes how to use the serial peripheral
interface (SPI) port on Analog Devices, Inc., high speed converters.
In addition, this application note defines the electrical, timing,
and procedural requirements for interfacing to these devices.
The implementation is compatible with industry-standard SPI
ports and employs, at minimum, a 2-wire mode and optional
chip select.
Interfacing to High Speed ADCs via SPI
by the High Speed Converter Division
CSB
SPI
SCLK
CONTROLLER
SDIO
Figure 1. Single Device Control in 2-Wire Mode
CSB 0
CSB 1
SPI
CONTROLLER
SCLK
SDIO
Figure 2. Multiple Device Control in 2-Wire Mode
Rev. B | Page 1 of 20
APPLICATION NOTE
DEFINITION
The SPI port consists of three pins: the serial clock pin (SCLK),
the serial data input/output pin (SDIO), and the chip select bar
pin (CSB). Optionally, some chips may implement a serial data
out pin (SDO), which is referred to as 3-wire mode. To minimize
pin count, most chips omit this pin. However, if it is included, it is
used only for reading data from the device.
CSB
SCLK
CONVERTER
SDIO
INTERFACE
CSB
SCLK
CONVERTER
INTERFACE
DEVICE 1
SDIO
CSB
SCLK
CONVERTER
INTERFACE
DEVICE 2
SDIO
AN-877
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Summary of Contents for Analog Devices AN-877
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Page 1: Introduction
This application note describes how to use the serial peripheral The SPI port consists of three pins: the serial clock pin (SCLK), interface (SPI) port on Analog Devices, Inc., high speed converters. the serial data input/output pin (SDIO), and the chip select bar In addition, this application note defines the electrical, timing, pin (CSB). -
Page 2: Table Of Contents
AN-877 Application Note TABLE OF CONTENTS Introduction ................... 1 Address Bits................6 Definition ..................1 Detection of SPI Mode and Pin Mode ......... 7 Revision History ................2 Hardware Interfacing ..............7 SPI Port Pins .................. 3 Chip Programming................ 8 Serial Clock (SCLK) .............. -
Page 3: Spi Port Pins
Application Note AN-877 SPI PORT PINS The following sections described the SPI port pins. CHIP SELECT BAR (CSB) Caution: Refer to specific analog-to-digital converter (ADC) CSB is an active low control that gates the read and write cycles. data sheets to determine the nominal and absolute maximum There are several modes in which the CSB can be operated. -
Page 4: Serial Data Out (Sdo)
AN-877 Application Note SERIAL DATA OUT (SDO) Table 1. Serial Timing Specifications To determine if a device supports the SDO pin, refer to the device Symbol Description data sheet. If SDO is present, it is in a high impedance state, unless Setup time between data and rising edge of SCLK. -
Page 5: Format
Application Note AN-877 FORMAT The falling edge of CSB, in conjunction with the rising edge of When the first bit in the data stream is low, a write phase is entered. SCLK, determines the start of framing. Once the beginning of the At the completion of the instruction phase, the internal state frame has been determined, timing is straightforward. -
Page 6: Streaming
AN-877 Application Note Table 2. Word Length Settings the CSB line low transfer data in 1-, 2-, or 3-byte blocks, unless they are certain that they do not wish to read data from the [W1:W0] Setting Action Stalling internal registers. Although it is not required, it is recommended that users maintain control over the CSB line so the streaming 1 byte of data can be transferred. -
Page 7: Detection Of Spi Mode And Pin Mode
Application Note AN-877 DETECTION OF SPI MODE AND PIN MODE Some users may choose not to use an SPI port to configure their The only means to accomplish this are cycling the power on the device. Where possible, devices are designed to power up using device or asserting the device pin reset, if the part is so equipped. -
Page 8: Changes To Table 3 Caption
AN-877 Application Note CHIP PROGRAMMING The SPI port is the mechanism for configuring the converter. In Bit 4—Reserved addition, a structured register space is defined for programming Bit 4 must be mirrored by the user in Bit 3. This bit defaults to 1 the device. -
Page 9: Chip Id (0X001)
Application Note AN-877 ADC channels to be written high. During a read process, only Bit 0—Software Transfer one bit at a time is recommended to be set high to prevent A software transfer is initiated by setting Bit 0 of this register confusion over which ADC is currently placed on the read bus. -
Page 10: Changes To Table 4 And Table 5
AN-877 Application Note Bit 4—Reserved Bit 3—Function Bypass MASTER SPI SLAVE SPI MEMORY MEMORY When Bit 3 is set, on-chip analog signal processing blocks are 0x0FF BIT 0 0x0FF bypassed and powered down (see the device data sheet for BIT 0... -
Page 11: Changes To Table 6 And Table 7
Application Note AN-877 PLL Control (0x00A) Table 7. Enhancement Modes, Register 0x00C, Bits[1:0] Register 0x00A is used to enable and control an on-chip PLL Bit 1 to Bit 0 Shuffle Modes that may be used to generate a sample clock. -
Page 12: Changes To Table 8
AN-877 Application Note • User Pattern 1 and User Pattern 2, on the next encode 0101, the output is set to a PN23 sequence, based on ITU cycle, are placed on the output. Further conversion cycles 0.150 using the equation x + 1. -
Page 13: Changes To Table 9
Application Note AN-877 Built-In Self Test (0x00E) Analog Input (0x00F) Register 0x00E configures and enables the built-in self test (BIST) Register 0x00F configures the analog input. functions. The BIST is a user feature that provides a high degree Bit 7 to Bit 4—Bandwidth (Low-Pass) -
Page 14: Changes To Table 10 And Table 11
AN-877 Application Note Table 11. Output Format, Register 0x014, Bits[1:0] Output Mode (0x014) Bit 1 to Bit 0 Output Data Format Bit 7 to Bit 6—Logic Type Offset binary Bit 7 to Bit 6 control the output logic type. The setting of these Twos complement bits corresponds to the type of output logic selected. -
Page 15: Changes To Table 12
Application Note AN-877 Table 12. Output Frame Length, Register 0x021, Bits[2:0] Bit 5 to Bit 0—Delay Bit 2 to Bit 0 Serial Output Frame Length Bit 5 to Bit 0 represent chip-specific offset timings, with 0x00 Native bit length being the most negative adjustment and 3F being the most Truncate/fill to 8 bits positive. -
Page 16: Changes To Table 13
AN-877 Application Note Table 13. High-Pass Filter Select, Register 0x02B, Bits[2:0] High-Pass (0x02B) Bit 2 to Bit 0 Bandwidth Mode Register 0x02B configures the high-pass filter. Default bandwidth (dc) Bit 7, Bit 5 to Bit 3—Reserved 001 through 111 Alternate high-pass choices Bit 6—Tune... -
Page 17: Change To Programming Example Section
Application Note AN-877 PROGRAMMING EXAMPLE Programming tools are available to assist in the development of This can be added to a C language project to set up the appro- code for SPI devices. A user may wish to access the features... -
Page 18: Changes To Table 14
AN-877 Application Note CONTROL REGISTER Table 14. Control Register Map Default Value Address , Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Comments Should The nibbles should be SDO active... - Page 19 Application Note AN-877 Default Value Address , Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Comments 0: Level Option 0 Output Output Output 0: Offset binary Device Configures the outputs...
- Page 20 AN-877 Application Note NOTES ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN05739-0-4/17(B) Rev. B | Page 20 of 20...
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