Thales NSS 100S-1 Component Maintenance Manual With Illustrated Parts List page 50

(b) Clock reception and generation
(c) Overflow counter
(d) Programmable local oscillator
(e) µp bus interface
(f) Generation of the AGC signal
COPYRIGHT SEXTANT Avionique 1995
c
The document reference is online, please check the correspondence between the online documentation and the printed version.
COMPONENT MAINTENANCE MANUAL
The Asic T100 receives:
- The HT100 clock (100 MHz), generated from the PLL1 circuit,
- The BT time base signal generated by the CPU PCB Z3
Based on these clocks, the Asic T100 generates the following clock
signals:
- H25T100 (25 MHz), by 4 way division of HT100,
- H2OT100 (20 MHz) by 5 way division of HT100
- H50 (50 MHz) by 2 way division of HT100
- Int BT
- The overflow counter is designed to count the number of presence
to 1 of the OVFL input bit on the HT100 clock during a period of
the int BT clock mentioned above.
This oscillator (specific to the Asic T100), is used to pre-process
the signal before a frequency change.
programmed using the µp bus interface, with 5 KHz steps; this makes
it possible to perform an infradine or supradine demodulation, de-
pending on the "frequency sign".
This interface enables the Asic T100 to communicate with the CPU
PCB using:
- Data bus D(25/31),
- Address bus A (0/3),
- Service bus SB.
This function is used to:
- Detect and compare amplitude
- Make integral proportional corrections.
Starting with AGC input and RAZCAG signals, the T100 circuit gene-
rates a AGC signal coded over 12 bits (DAC 0/11).
C17004
The oscillator frequency is
34-57-96
Page 27
MAY 30/95