Thales NSS 100S-1 Component Maintenance Manual With Illustrated Parts List page 57

D. Operation of sub-unit CPU PCB Z3 (see Figure 6)
(1) Composition
The CPU PCB includes
- A microprocessor (µp) 68020,
- A coprocessor (cp) 68882,
- An un-backed RAM memory,
- An backed RAM memory,
- An EEPROM memory,
- An Asic GLU circuit,
- An Asic COMA circuit,
- Two Asic TS25 circuits,
- An ARINC 429 input/output interface,
- A RS422 input/output interface,
- A program pin and discrete signal interface.
(2) Asic TS25 Circuits
(a) Functions
COPYRIGHT SEXTANT Avionique 1995
c
The document reference is online, please check the correspondence between the online documentation and the printed version.
COMPONENT MAINTENANCE MANUAL
The 2 TS25 circuits process GPS signals on 2 X 5 identical channels
(8 are used); the 8 channels are independently read and write acces-
sible by the 68020 microprocessor data bus.
Each circuit performs the following functions:
- Interface with the 68020 µp buses,
- Code generation and checking,
- Sequencing and time stamping,
- Satellite signal acquisition,
- Code test outputs,
- Time function.
C17004
34-57-96
Page 31
MAY 30/95