Thales NSS 100S-1 Component Maintenance Manual With Illustrated Parts List page 60

This memory comprises 2 circuits of 8 K x 8 bits that create as a whole,
a capacity of 8 Kwords of 16 bits; these 2 circuits are connected to the
16 most significant bits (D16 to D31);
They are powered by a backed-up 5 V supply (5VSPIL) which enables memo-
ryzed data saveguard, while the RPU is switched off.
(6) ROM
This memory comprises 4 EEPROM circuits of 128 K x 8 bits that provide
as a whole, a capacity of 128 Kwords of 32 bits.
(7) GLU Asic
The GLU Asic circuit is connected to:
- Data bus D (16/31): 16 most significant bits,
- Address bus A (0/24),
- Service bus SB,
- RS422 interface circuits.
This circuit performs the following functions:
- Clock generation: based on clocks CLK20 (20 MHz) and H50 (50 MHz)
it generates the µp clock: CLKMIC (20 or 25 MHz),
- "chip select" generation,
- Watch dog for monitoring bus exchanges and DMA sequences (direct access
memory),
- Interrupt encoder,
- Processing 2 RS422 lines; the data transfers are carried out in the
asynchronous mode.
(8) RS422 input/output interface
This interface is used to match:
- 2 RS422 lines: RSOPT.I (optional) and ELITE.1 (maintenance); at the
output of a buffer, these two lines are applied on inputs S11 and S12
of Asic GLU;
- 2 RS422 lines: RSOPT.O (optional) and ELITE.O (maintenance); the SO1
and SO2 outputs of Asic GLU are applied to a buffer input.
COPYRIGHT SEXTANT Avionique 1995
c
The document reference is online, please check the correspondence between the online documentation and the printed version.
COMPONENT MAINTENANCE MANUAL
C17004
1997
34-57-96
Page 34
NOV 30/97