Pci Express Root Port 1/2/3/4 Submenu - Efco SmartSL User Manual

6.5.2.4.1 PCI Express Root Port 1/2/3/4 Submenu

Feature Options
Enabled
PCI Express Root Port 1
Disabled
Disabled
ASPM
Disabled
URR
Enabled
Disabled
FER
Enabled
Disabled
NFER
Enabled
Disabled
CER
Enabled
Disabled
SEFE
Enabled
Disabled
SENFE
Enabled
Disabled
SECE
Enabled
Disabled
PME SCI
Enabled
Disabled
Ext Sync
Enabled
PCIe Spee
Disabled
Detect Non-compliant
Device
Enabled
Disabled
L1 Substates
L1.1 & L1.2
Non-Common Clock with Enabled
SSC Enabled Mode Disabled
Enabled
Transmitter Half Swing
Disabled
Description
Control the PCI Express Root Port.
Auto
PCI Express Active State Power
L0s
Management settings.
L1
L0sL1
PCI Express Unsupported Request
Reporting Enable/Disable.
Enable or disable PCI Express device Fatal
Error Reporting.
Enable or disable PCI Express device Non-
Fatal Error Reporting
Enable or disable PCI Express device
Correctable Error Reporting.
Root PCI Express System Error on Fatal
Error Enable/Disable.
Enable or disable Root PCI Express System
Error on Non-Fatal Error.
Root PCI Express System Error on
Correctable Error
Enable/Disable.
Enable or disable PCI Express PME (power
management event) SCI.
Enable Express Ext Sync Enable/Disable.
Auto
Configure PCIe Speed. CHV A1 always with
Gen 2 Gen1 Speed.
Gen 1
Try to detect also a non-compliant PCI
Express device. If enabled, it will take more
time during POST.
PCI Express L1 Substates settings.
L1.1
L1.2
Assume the root port is operating at a non-
common clock with SSC enabled.
Transmitter Half Swing Enable/Disable.
3.5dB
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