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6.4.20
PCI & PCI Express Submenu
Feature
Options
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 Bus Clocks
PCI Latency Timer
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 Bus Clocks
PCI-X Latency Timer
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Disabled
VGA Palette Snoop
Enabled
Disabled
PERR# Generation
Enabled
Disabled
SERR# Generation
Enabled
Disabled
Above 4G Decoding
Enabled
Disabled
Do not Reset VC-TC
Mapping
Enabled
Description
Value to be programmed into the PCI
latency timer register.
Value to be programmed into the PCI
latency timer register.
Enable or disable VGA palette registers
snooping.
Enable or disable a PCI device to generate
PERR#.
Enable or disable a PCI device to generate
SERR#.
Enables or disables 64bit capable Devices
to be Decoded in
Above 4G Address Space (Only if System
Supports 64bit PCI Decoding).
If the system has Virtual Channels,
Software can reset Traffic Class mapping
through Virtual Channels, to its default
state. Setting this option to Enabled will not
modify VC Resources.
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SmartSL User Manual
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