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RF: 0FH
Bit 3
0
Read/write
Initial value when reset
0
RF: 1FH
Bit 3
0
Read/write
0
Initial value when reset
148
CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Register (1/4)
Bit 2
Bit 1
Bit 0
0
0
INT
R
0
0
Note
Note Since the INT flags are not latched, they change all the
Bit 2
Bit 1
Bit 0
0
IEGMD1
IEGMD0
R/W
0
0
0
IEGMD1 IEGMD0
Read=R, write=W
INT
State of INT Pin
INT pin noise elimination circuit sets logical status
0
to 0 during PEEK instruction execution.
INT pin noise elimination circuit sets logical status
1
to 1 during PEEK instruction execution.
time in response to the logical state of the pin, However,
once the IRQ flag is set, it stays set until an interrupt is
accepted. The POKE instruction to address 0FH is invalid.
Read=R, write=W
Selection of the Interrupt Detection Edge
of the INT Pin
0
0
Interrupt at the rising edge
0
1
Interrupt at the falling edge
1
0
Interrupt at both edges
1
1
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