Quectel BG96 Series Hardware Design page 39

The logic levels are described in the following table.
Table 14: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8V UART interface. A level translator should be used if customers' application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is
recommended. The following figure shows a reference design.
VDD_EXT
RI
DCD
CTS
RTS
DTR
TXD
RXD
Please visit http://www.ti.com for more information.
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to that of solid line section, in terms of both module input and output circuit designs, but
please pay attention to the direction of connection.
BG96_Hardware_Design
Min.
-0.3
1.2
0
1.35
VCCA
0.1uF
OE
A1
A2
A3
A4
A5
A6
A7
51K
A8
Figure 15: Reference Circuit with Translator Chip
Max.
0.6
2.0
0.45
1.8
VCCB
0.1uF
GND
B1
B2
Translator
B3
B4
B5
B6
B7
B8
LTE Module Series
BG96 Hardware Design
Unit
V
V
V
V
VDD_MCU
RI_MCU
DCD_MCU
CTS_MCU
RTS_MCU
DTR_MCU
TXD_MCU
RXD_MCU
51K
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