Quectel BG96 Series Hardware Design page 33

The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.
Figure 9: Reference Circuit of RESET_N by Using Driving Circuit
Figure 10: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated in the following figure.
VBAT
RESET_N
Module
Status
BG96_Hardware_Design
150~460ms
4.7K
Reset pulse
S2
≥150ms
Running
Figure 11: Timing of Resetting Module
RESET_N
47K
RESET_N
TVS
Close to S2
≤460ms
≤0.5V
V
IL
Resetting Restart
LTE Module Series
BG96 Hardware Design
≥1.3V
V
IH
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