Advertisement
APPENDIX A – TECHNICAL REFERENCE & TROUBLESHOOTING
Pin
Board
No.
Label
Mnemonic
1
None
RST_OUT*
2
None
GND
3
None
RST_IN*
4
RST*
RST*
5
None
TGT_IRQ*
6
IRQ*
IRQ*
7
NC
None
8
NC
None
9
PTA0
TGT_PTA0
10
PTA0/KBD0
PTA0
11
PTC0, after
TGT_PTC0
reset
12
PTB0
PTC0
13
PTC1, after
TGT_PTC1
reset
A-16
Table A-3. MON08 Connector J2
MCU
Schematic
NET
RST_OUT*
GND
RST_IN*
RST*
TGT_IRQ*
IRQ*
None
None
TGT_PTA0
PTA0
TGT_PTB0
PTC0
TGT_PTC1
Direct to MCU
Dir
Sockets?
No
Out
Yes
Gnd
No
In
Yes
Bidir
No
In
Yes
Out
No
NC
No
NC
No
Bidir
(only to P7)
Yes
Bidir
Yes, after reset
Bidir
Yes
Bidir
Yes, after reset
Bidir
Signal Description
Reset signal to
target system: 0 to
+3.3 Vdc output
reflecting state of
MCU RST* signal
System ground
Reset signal from
Target System: 0 to
+3.3 Vdc input to
control state of MCU
RST* signal
External reset - Held
at +7.5 Vdc out of
reset
Reset signal from
target system: 0 to
+3.3 Vdc input to
control state of MCU
IRQ* signal
External interrupt.
Held at +7.5 Vdc in
reset and when
TGT_IRQ* not
asserted (low)
No connection
No connection
Port A I/O.
Unavailable MCU
connection
Port A I/O. Host I/O
present on this pin
Port C I/O – bit 0
Port C I/O – bit 0.
Held at +3.3 Vdc
during reset
Port C I/O – bit 1
M68ICS08ABUM/D
Advertisement
